Touch integrated circuit inspection device

Abstract

Disclosed is a touch integrated circuit inspection device, the touch integrated circuit inspection device including: an inspection board electrically connected to a touch integrated circuit; and an inspection circuit receiving an inspection result from the touch integrated circuit, in which the inspection board includes: a plurality of first electrodes, each of the plurality of first electrodes extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; and a plurality of second electrodes, each of the plurality of second electrodes extending in the second direction and being spaced apart from each other in the first direction, and wherein a number of the plurality of first electrodes is the same as a number of the plurality of second electrodes.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0111712 filed in the Korean Intellectual Property Office on August 25, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Embodiments of the present invention relate to a touch integrated circuit (IC) inspection apparatus for detecting defects in the touch IC. Background Art

[0003] Various display modules are currently being developed and used in multimedia devices such as televisions, mobile phones, tablet computers, navigation systems, or game consoles. Typically, each of the display modules includes a pixel and a drive circuit. In addition, each of the display modules is equipped with an input sensor that recognizes input from a user, such as a touch input. Summary of the invention

[0004] According to an embodiment of the present invention, a touch integrated circuit (IC) inspection device includes: an inspection board electrically connected to the touch integrated circuit; and an inspection circuit receiving an inspection result from the touch integrated circuit, wherein the inspection board includes: a plurality of first electrodes, each of the plurality of first electrodes extending in a first direction and the plurality of first electrodes being spaced apart from each other in a second direction intersecting the first direction; and a plurality of second electrodes, each of the plurality of second electrodes extending in a second direction and the plurality of second electrodes being spaced apart from each other in the first direction, and wherein the number of the plurality of first electrodes is the same as the number of the plurality of second electrodes.

[0005] In an embodiment of the present invention, each of the plurality of first electrodes and the plurality of second electrodes has a polygonal shape.

[0006] In an embodiment of the present invention, each of the plurality of first electrodes and the plurality of second electrodes has a rectangular shape.

[0007] In an embodiment of the present invention, the first portion of each of the plurality of second electrodes and the plurality of first electrodes are disposed at the same layer.

[0008] In an embodiment of the present invention, the inspection board further includes: a first resistor electrically connected to one end of each of the plurality of first electrodes; and a first capacitor connected between the first resistor and the ground electrode.

[0009] In an embodiment of the present invention, the inspection board further includes: a second resistor electrically connected to one end of each of the plurality of second electrodes; and a second capacitor connected between the second resistor and the ground electrode.

[0010] In an embodiment of the invention, the first resistor is a variable resistor, and wherein the first capacitor is a variable capacitor.

[0011] In an embodiment of the present invention, the ground electrode is disposed at the same layer as the second portion of each of the plurality of second electrodes.

[0012] In an embodiment of the present invention, the inspection board further includes: a first grounding layer disposed on the plurality of first electrodes and the plurality of second electrodes; and a second grounding layer disposed below the plurality of first electrodes and the plurality of second electrodes.

[0013] In an embodiment of the present invention, a plurality of first slits are arranged in the first ground layer, each of the plurality of first slits extends in the second direction and the plurality of first slits are spaced apart from each other in the first direction, and wherein the plurality of first slits overlap with the plurality of first electrodes and the plurality of second electrodes.

[0014] In an embodiment of the present invention, the self-capacitance of each of the plurality of first electrodes is controlled by the width of each of the plurality of first slits in the first direction.

[0015] In an embodiment of the present invention, a plurality of second slits are arranged in the second ground layer, each of the plurality of second slits extends in the first direction and the plurality of second slits are spaced apart from each other in the second direction, and wherein the plurality of second slits overlap with the plurality of first electrodes and the plurality of second electrodes.

[0016] In an embodiment of the present invention, a plurality of openings are provided in the first ground layer, each of the plurality of openings has a polygonal shape and the plurality of openings are arranged in a first direction and a second direction, and wherein the plurality of openings overlap with the plurality of first electrodes and the plurality of second electrodes.

[0017] According to an embodiment of the present invention, a touch integrated circuit (IC) inspection device includes: an inspection board electrically connected to the touch integrated circuit, wherein the inspection board includes: a plurality of first electrodes, each of the plurality of first electrodes extending in a first direction and the plurality of first electrodes being spaced apart from each other in a second direction intersecting the first direction; a plurality of second electrodes, each of the plurality of second electrodes extending in the second direction and the plurality of second electrodes being spaced apart from each other in the first direction; a first resistor electrically connected to one end of each of the plurality of first electrodes; and a first capacitor connected between the first resistor and a ground electrode.

[0018] In an embodiment of the invention, the first resistor is a variable resistor, and wherein the first capacitor is a variable capacitor.

[0019] In an embodiment of the present invention, the inspection board further includes: a second resistor electrically connected to one end of each of the plurality of second electrodes; and a second capacitor connected between the second resistor and the ground electrode.

[0020] In an embodiment of the present invention, the first portion of each of the plurality of second electrodes and the plurality of first electrodes are disposed at the same layer.

[0021] In an embodiment of the present invention, the ground electrode is disposed at the same layer as the second portion of each of the plurality of second electrodes.

[0022] In an embodiment of the present invention, at least one of the plurality of first electrodes and the plurality of second electrodes has a rhombus shape.

[0023] In an embodiment of the present invention, at least one of the plurality of first electrodes and the plurality of second electrodes has a rectangular shape. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and other features of the present invention will become apparent by describing in detail the embodiments of the present invention with reference to the attached drawings.

[0025] Figure 1 is a perspective view of a display device according to an embodiment of the present invention.

[0026] Figure 2 is an exploded perspective view of a display device according to an embodiment of the present invention.

[0027] Figure 3 is a block diagram illustrating the operation of the display device according to the embodiment of the present invention.

[0028] Figure 4A is a cross-sectional view of a display device according to an embodiment of the present invention.

[0029] Figure 4B is a cross-sectional view of a display device according to an embodiment of the present invention.

[0030] Figure 5 According to an embodiment of the present invention, Figure 1 A cross-sectional view of the display device taken along line II'.

[0031] Figure 6 is a block diagram showing a touch integrated circuit inspection apparatus according to an embodiment of the present invention.

[0032] Figure 7 is a conceptual diagram illustrating an inspection board according to an embodiment of the present invention.

[0033] Figure 8 According to an embodiment of the present invention, Figure 7 A cross-sectional view of the inspection plate taken along line II'.

[0034] Fig. 9 According to an embodiment of the present invention, by cutting and Figure 7The area AA' corresponds to a cross-sectional view of the inspection plate obtained from the portion.

[0035] Fig.10 is a plan view showing an inspection plate according to an embodiment of the present invention.

[0036] Fig.11 is a plan view showing an inspection plate according to an embodiment of the present invention.

[0037] Fig.12 is a cross-sectional view showing an inspection plate according to an embodiment of the present invention.

[0038] Fig.13 is a plan view showing a first ground layer according to an embodiment of the present invention.

[0039] Fig.14 is a plan view showing a second ground layer according to an embodiment of the present invention.

[0040] Fig.15 is a plan view showing an inspection plate according to an embodiment of the present invention.

[0041] Fig.16 An inspection result of measuring the capacitance of each channel according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0042] In the specification, the expression that a first component (or region, layer, part, portion, etc.) is "on", "connected to" or "coupled to" a second component means that the first component is directly on, directly connected to or directly coupled to the second component, or that a third component is placed between the first and second components.

[0043] Throughout the specification, the same reference numerals represent the same components. In addition, various thicknesses, lengths, and angles are shown, and although the arrangements shown do represent embodiments of the present invention, it will be understood that modifications of various thicknesses, lengths, and angles are possible within the spirit and scope of the present disclosure, and the present disclosure is not necessarily limited to the specific thicknesses, lengths, and angles shown. The term "and / or" includes one or more combinations, and the related elements are defined in each of the one or more combinations.

[0044] Although the terms "first", "second", etc. may be used to describe various components, these components should not be construed as being limited by these terms. The terms are used only to distinguish one component from another component. For example, a first component may be referred to as a second component without departing from the scope and spirit of the present invention, and similarly, a second component may be referred to as a first component without departing from the spirit and scope of the present invention. As used herein, unless the context clearly indicates otherwise, a term in the singular may include a plural form.

[0045] In addition, terms such as "below", "below", "above", and "on" may be used to describe the relationship of components shown in the drawings. These terms are used as spatially relative concepts and are described based on the directions indicated in the drawings. It will be understood that, in addition to the orientations depicted in the drawings, the spatially relative terms are intended to include different orientations of the device in use or operation. For example, if the device in the drawings is flipped, the elements described as "below" or "beneath" other elements or features will then be oriented "above" the other elements or features. Therefore, the exemplary term "below" can include both above and below orientations. The device can be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used here are interpreted accordingly.

[0046] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0047] Figure 1 is a perspective view of a display device according to an embodiment of the present invention.

[0048] Reference Figure 1 , in this specification, a display device 1000 that can be applied to a mobile phone terminal is shown; however, this is only an example, and the present invention is not limited thereto. Although not shown in the drawings, a mobile phone terminal can be implemented by positioning an electronic module, a camera module, a power module, etc. mounted on a mainboard together with the display device 1000 in a bracket or a housing. However, this is an example, and the display device 1000 according to an embodiment of the present invention is not limited thereto. For example, the display device 1000 can be applied to small and medium-sized display devices such as tablet PCs, vehicle navigation systems, game consoles, smart watches, etc., and large-sized display devices such as televisions, monitors, etc.

[0049] An active area 1000A and a peripheral area 1000NA may be defined in the display device 1000. The display device 1000 may display an image IM through the active area 1000A. An icon image is shown as an example of the image IM. The active area 1000A may be parallel to a plane defined by a first direction DR1 and a second direction DR2. A normal direction of the active area 1000A (i.e., a thickness direction of the display device 1000) may be defined as a third direction DR3. In this specification, "when viewed from above or on a plane" may mean "when viewed in the third direction DR3". The front surface (or, for example, upper surface) and the rear surface (or, for example, lower surface) of each layer or unit described later may be divided by the third direction DR3.

[0050] The peripheral area 1000NA may be adjacent to the active area 1000A. The peripheral area 1000NA may be an area in which the image IM is not displayed. However, the present invention is not limited thereto, and the peripheral area 1000NA may be adjacent to one side of the active area 1000A, or may be omitted.

[0051] Figure 2 is an exploded perspective view of a display device according to an embodiment of the present invention.

[0052] Reference Figure 2 , the display device 1000 may include a window WM, a display layer 100 , a sensor layer 200 , a data driver DIC, a circuit board PB, a touch integrated circuit 200C, and a receiving member BC.

[0053] The window WM may be provided on the sensor layer 200. The window WM may transmit an image provided from the display layer 100 to the outside. The window WM may include a transmissive area TA and a non-transmissive area NTA. The transmissive area TA may be aligned with the active area 1000A (see FIG. 1 ) of the display device 1000. Figure 1 The transmissive area TA may have a width that is substantially the same as the active area 1000A (see Figure 1 ) corresponding to the shape. Displayed in the active area 1000A of the display device 1000 (see Figure 1 ) on the image IM (see Figure 1 ) can be visible from the outside through the transmission area TA of the window WM.

[0054] The non-transmission area NTA may be aligned with the peripheral area 1000NA (see Figure 1 The non-transmission area NTA may have a width that is equal to that of the peripheral area 1000NA (see Figure 1 ) corresponding to the shape. The non-transmission area NTA may be an area having a lower transmittance than the transmittance of the transmission area TA. However, the window WM according to an embodiment of the present invention is not limited thereto, and the non-transmission area NTA may be omitted.

[0055] The window WM may be formed of, for example, glass, sapphire, plastic, etc. In addition, the window WM may include a single layer or multiple layers. The window WM may include at least one printed layer superimposed with the base layer and the non-transmissive area NTA, for example, at least one printed layer may be provided on the rear surface of the base layer. The printed layer may have a predetermined color. For example, the printed layer may be provided in black or a color other than black.

[0056] The display layer 100 and the sensor layer 200 may be interposed between the window WM and the receiving member BC. The sensor layer 200 may be provided on the display layer 100. This will be described later.

[0057] The data driver DIC may be mounted on the display layer 100. The circuit board PB may be disposed at one end of the display layer 100 and may be electrically connected to the display layer 100. The circuit board PB may be rigid or flexible. For example, when the circuit board PB is flexible, the circuit board PB may be configured as a flexible printed circuit board. The circuit board PB may include a touch integrated circuit 200C that controls the operation of the sensor layer 200. The touch integrated circuit 200C may be mounted on the circuit board PB in the form of an integrated chip. In addition, the circuit board PB may further include a circuit for controlling the display layer 100.

[0058] Figure 3 is a block diagram illustrating the operation of the display device according to the embodiment of the present invention.

[0059] Reference Figure 3 , the display device 1000 may include a display layer 100 , a sensor layer 200 , a driving controller 100C, a touch integrated circuit 200C, and a main driver 1000C.

[0060] The display layer 100 may be a component that basically generates an image. The display layer 100 may include a light-emitting display layer. For example, the display layer 100 may be an organic light-emitting display layer, a quantum dot display layer, a micro-LED display layer, or a nano-LED display layer. For example, the display layer 100 may be referred to as a "display panel".

[0061] The sensor layer 200 may be provided on the display layer 100. The sensor layer 200 may sense an external input 2000 applied from the outside. The external input 2000 may include any input method capable of providing a change in capacitance in the sensor layer 200. For example, the sensor layer 200 may sense not only a passive input method such as a user's body, but also an input by an active input method providing a transmission signal. For example, the sensor layer 200 may be referred to as a "sensor", "touch layer", "touch panel", "input sensing layer", or "input sensing panel".

[0062] The main driver 1000C may control the overall operation of the display device 1000. For example, the main driver 1000C may control the operation of the driving controller 100C and the touch integrated circuit 200C. The main driver 1000C may include at least one microprocessor, and the main driver 1000C may be referred to as a "host". The main driver 1000C may also include a graphics controller.

[0063] The driving controller 100C may drive the display layer 100. The driving controller 100C may receive the image data RGB and the control signal D-CS from the main driver 1000C. The control signal D-CS may include various signals. For example, the control signal D-CS may include an input vertical synchronization signal, an input horizontal synchronization signal, a main clock, and a data enable signal. The driving controller 100C may generate a scanning control signal and a data control signal for controlling the driving of the display layer 100 based on the control signal D-CS.

[0064] The touch integrated circuit 200C may drive the sensor layer 200. The touch integrated circuit 200C may receive a control signal I-CS from the main driver 1000C. The control signal I-CS may include a clock signal.

[0065] The touch integrated circuit 200C may calculate the input coordinate information based on the signal received from the sensor layer 200, and may provide the coordinate signal I-SS having the coordinate information to the main driver 1000C. The main driver 1000C performs an operation corresponding to the user input based on the coordinate signal I-SS. For example, the main driver 1000C may operate the driving controller 100C so that a new image is displayed on the display layer 100.

[0066] Figure 4A is a cross-sectional view of a display device according to an embodiment of the present invention.

[0067] Reference Figure 4A The display layer 100 may include a base layer 110 , a circuit layer 120 , a light emitting element layer 130 and an encapsulation layer 140 .

[0068] The base layer 110 may be a member that provides a base surface on which the circuit layer 120 is disposed. The base layer 110 may be, for example, a glass substrate, a metal substrate, a polymer substrate, etc. However, the embodiments of the present invention are not limited thereto, and the base layer 110 may be an inorganic layer, an organic layer, or a composite material layer.

[0069] The base layer 110 may have a multi-layer structure. For example, the base layer 110 may include a first synthetic resin layer, a silicon oxide (SiO x) layer, an amorphous silicon (a-Si) layer disposed on the silicon oxide layer, and a second synthetic resin layer disposed on the amorphous silicon layer. For example, the silicon oxide layer and the amorphous silicon layer may be referred to as a “matrix barrier layer”.

[0070] Each of the first synthetic resin layer and the second synthetic resin layer may include a polyimide resin. In addition, each of the first synthetic resin layer and the second synthetic resin layer may include at least one of an acrylate resin, a methacrylate resin, a polyisoprene resin, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyamide resin, and a perylene resin.

[0071] The circuit layer 120 may be disposed on the base layer 110. The circuit layer 120 may include, for example, an insulating layer, a semiconductor pattern, a conductive pattern, and a signal line. The insulating layer, the semiconductor layer, and the conductive layer may be formed on the base layer 110 by a method such as coating, evaporation, etc. Thereafter, the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned by performing a photolithography process multiple times. Thereafter, the semiconductor pattern, the conductive pattern, and the signal line included in the circuit layer 120 may be formed.

[0072] The light emitting element layer 130 may be disposed on the circuit layer 120. The light emitting element layer 130 may include a light emitting element. For example, the light emitting element layer 130 may include an organic light emitting material, quantum dots, quantum rods, micro LEDs, or nano LEDs.

[0073] The encapsulation layer 140 may be disposed on the light emitting element layer 130. The encapsulation layer 140 may protect the light emitting element layer 130 from foreign substances such as moisture, oxygen, and dust particles. For example, the encapsulation layer 140 may include an inorganic layer and an organic layer.

[0074] The sensor layer 200 may be disposed on the display layer 100. The sensor layer 200 may sense an external input applied from the outside. The external input may be a user input. The user input may include various types of external inputs such as a part of the user's body, light, heat, a pen, or pressure.

[0075] The sensor layer 200 may be formed on the display layer 100 through a continuous process. For example, the sensor layer 200 may be represented as being directly disposed on the display layer 100. "Directly disposed" may mean that a third component is not disposed between the sensor layer 200 and the display layer 100. For example, a separate bonding member may not be disposed between the sensor layer 200 and the display layer 100. In addition, the sensor layer 200 may be bonded to the display layer 100 through a bonding member. The bonding member may include a common adhesive or a common adhesive.

[0076] The display device 1000 may further include an anti-reflection layer and an optical layer disposed on the sensor layer 200. The anti-reflection layer may reduce reflectivity of external light incident from outside the display device 1000. The optical layer may increase front brightness of the display device 1000 by controlling the direction of light incident from the display layer 100.

[0077] Figure 4B is a cross-sectional view of a display device according to an embodiment of the present invention.

[0078] Reference Figure 4B , the display device 1000_1 may include a display layer 100_1 and a sensor layer 200_1. The display layer 100_1 may include a base substrate 110_1, a circuit layer 120_1, a light emitting element layer 130_1, a package substrate 140_1, and a bonding member 150_1.

[0079] Each of the base substrate 110_1 and the encapsulation substrate 140_1 may be, for example, a glass substrate, a metal substrate, or a polymer substrate, but the present invention is not particularly limited thereto.

[0080] The bonding member 150_1 may be disposed between the base substrate 110_1 and the encapsulation substrate 140_1. The bonding member 150_1 may bond the encapsulation substrate 140_1 to the base substrate 110_1 or the circuit layer 120_1. The bonding member 150_1 may include an inorganic material or an organic material. For example, the inorganic material may include a glass frit seal, and the organic material may include a photocurable resin or a photoplastic resin. However, the material constituting the bonding member 150_1 is not limited to the example.

[0081] The sensor layer 200_1 may be disposed on the encapsulation substrate 140_1. For example, the sensor layer 200_1 may be directly disposed on the encapsulation substrate 140_1. "Directly disposed" may mean that a third component is not disposed between the sensor layer 200_1 and the encapsulation substrate 140_1. For example, a separate adhesive member may not be disposed between the sensor layer 200_1 and the display layer 100_1. However, embodiments of the present invention are not limited thereto, and an adhesive layer may be disposed between the sensor layer 200_1 and the encapsulation substrate 140_1.

[0082] Figure 5 According to an embodiment of the present invention, Figure 1 A cross-sectional view of the display device taken along line II'.

[0083] Reference Figure 5 , the display device 1000 may include a display layer 100 and a sensor layer 200 disposed on the display layer 100 .

[0084] The display layer 100 may include a base layer 110 , a circuit layer 120 disposed on the base layer 110 , a light emitting element layer 130 , and an encapsulation layer 140 .

[0085] The base layer 110 may include, for example, a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. For example, the synthetic resin layer may be a polyimide resin layer, and its material is not specifically limited thereto. For example, the synthetic resin layer may include at least one of an acrylate resin, a methacrylate resin, polyisoprene, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyamide resin, and a perylene resin. In addition, the base layer may include a glass substrate, a metal substrate, an organic / inorganic composite substrate, and the like.

[0086] At least one inorganic layer may be formed on the upper surface of the base layer 110. For example, the inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed of multiple layers. The multiple inorganic layers may constitute a barrier layer BRL and / or a buffer layer BFL to be described later. The barrier layer BRL and the buffer layer BFL may be selectively provided.

[0087] The barrier layer BRL can prevent foreign matter from entering from the outside. The barrier layer BRL may include, for example, a silicon oxide layer and a silicon nitride layer. Each of the silicon oxide layer and the silicon nitride layer may include a plurality of layers, and the plurality of silicon oxide layers and silicon nitride layers may be alternately stacked with each other.

[0088] The buffer layer BFL may be disposed on the barrier layer BRL. The buffer layer BFL may increase the bonding force between the base layer 110 and the semiconductor pattern and / or the conductive pattern. The buffer layer BFL may include, for example, a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked with each other.

[0089] The semiconductor pattern may be disposed on the buffer layer BFL. For example, the semiconductor pattern may be directly disposed on the buffer layer BFL. Hereinafter, the semiconductor pattern disposed on the buffer layer BFL may be a first semiconductor pattern. The first semiconductor pattern may include, for example, a silicon semiconductor. The first semiconductor pattern may include, for example, polycrystalline silicon. However, embodiments of the present invention are not limited thereto. For example, the first semiconductor pattern may include amorphous silicon.

[0090] The first semiconductor pattern has different electrical characteristics from each other depending on whether the first semiconductor pattern is doped. The first semiconductor pattern may include a doped region and an undoped region. The doped region may be doped with an N-type dopant or a P-type dopant. The P-type transistor may include a doped region doped with a P-type dopant, and the N-type transistor may include a doped region doped with an N-type dopant.

[0091] The doped region has a higher conductivity than the undoped region and is basically operated as an electrode or a signal line. The undoped region basically corresponds to the active region (or channel) of the transistor. In other words, a portion of the first semiconductor pattern may be the active region of the transistor. Another portion of the first semiconductor pattern may be the source or drain of the transistor. Another portion of the first semiconductor pattern may be a connection signal line (or connection electrode). Figure 5 A first transistor T1 is shown as an example of a first semiconductor pattern.

[0092] The first semiconductor pattern of the first transistor T1 may include a first electrode S1 of the first transistor T1, a channel portion A1, and a second electrode D1. The first electrode S1 and the second electrode D1 of the first transistor T1 may extend from the channel portion A1 in opposite directions.

[0093] Figure 5 FIG. 4 shows a portion of a connection signal line CSL formed by a semiconductor pattern.

[0094] The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may be stacked with a plurality of pixels and may cover the first semiconductor pattern. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The first insulating layer 10 may include, for example, at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In an embodiment of the present invention, the first insulating layer 10 may be a silicon oxide layer having a single-layer structure. Not only the first insulating layer 10 but also other insulating layers of the circuit layer 120 to be described later may be inorganic layers and / or organic layers, and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the above materials.

[0095] The third electrode G1 of the first transistor T1 is disposed on the first insulating layer 10. The third electrode G1 may be a part of the metal pattern. The third electrode G1 of the first transistor T1 overlaps the channel portion A1 of the first transistor T1. The third electrode G1 of the first transistor T1 may be used as a mask in the process of doping the first semiconductor pattern.

[0096] The second insulating layer 20 covering the third electrode G1 is disposed on the first insulating layer 10. The second insulating layer 20 is stacked with a plurality of pixels. The second insulating layer 20 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. In an embodiment of the present invention, the second insulating layer 20 may be a silicon oxide layer having a single-layer structure.

[0097] The upper electrode UE may be disposed on the second insulating layer 20. The upper electrode UE may overlap the third electrode G1. The upper electrode UE may be a portion of a metal pattern or a portion of a doped semiconductor pattern. A portion of the third electrode G1 and the upper electrode UE overlapping the portion of the third electrode G1 may form a capacitor. In an embodiment of the present invention, the upper electrode UE may be omitted.

[0098] In an embodiment of the present invention, the second insulating layer 20 may be replaced by an insulating pattern. For example, the insulating pattern may be formed by the second insulating layer 20. The upper electrode UE may be arranged on the insulating pattern. The upper electrode UE may be used as a mask for forming the insulating pattern from the second insulating layer 20.

[0099] The third insulating layer 30 covers the upper electrode UE and is disposed on the second insulating layer 20. In an embodiment of the present invention, the third insulating layer 30 may be a silicon oxide layer having a single-layer structure. The semiconductor pattern may be disposed on the third insulating layer 30. For example, the semiconductor pattern may be directly disposed on the third insulating layer 30. Hereinafter, the semiconductor pattern directly disposed on the third insulating layer 30 may be referred to as a second semiconductor pattern. The second semiconductor pattern may include, for example, a metal oxide. The oxide semiconductor may include a crystalline oxide semiconductor or an amorphous oxide semiconductor. For example, the oxide semiconductor may include an oxide of a metal (e.g., zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti), etc.) or a mixture of these metals (e.g., zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti), etc.) and oxides of these metals. The oxide semiconductor may include, for example, indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZO), indium zinc oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium zinc tin oxide (IZTO), zinc tin oxide (ZTO), etc.

[0100] The second semiconductor pattern may include a plurality of regions identified according to whether the metal oxide is reduced. The region in which the metal oxide is reduced (hereinafter referred to as a "reduction region") has a higher conductivity than the region in which the metal oxide is not reduced (hereinafter referred to as a "non-reduction region"). The reduction region basically has the function of an electrode or a signal line. The non-reduction region basically corresponds to the channel portion of the transistor. In other words, a portion of the second semiconductor pattern may be the channel portion of the transistor, and another portion of the second semiconductor pattern may be the first electrode or the second electrode of the transistor. Figure 5 A third transistor T3 is shown as an example of a second semiconductor pattern.

[0101] The second semiconductor pattern of the third transistor T3 may include a first electrode S3, a channel portion A3, and a second electrode D3. The first electrode S3 and the second electrode D3 may include a metal reduced from a metal oxide semiconductor. The first electrode S3 and the second electrode D3 of the third transistor T3 may extend from the channel portion A3 in opposite directions. The first electrode S3 and the second electrode D3 may include a metal layer containing a reduced metal.

[0102] The fourth insulating layer 40 covering the second semiconductor pattern may be disposed on the third insulating layer 30. In an embodiment of the present invention, the fourth insulating layer 40 may be a silicon oxide layer having a single-layer structure. The third electrode G3 of the third transistor T3 is disposed on the fourth insulating layer 40. The third electrode G3 may be a part of the metal pattern. The third electrode G3 of the third transistor T3 overlaps the channel portion A3 of the third transistor T3.

[0103] In an embodiment of the present invention, the fourth insulating layer 40 may be replaced by an insulating pattern. For example, the insulating pattern may be formed by the fourth insulating layer 40. The third electrode G3 of the third transistor T3 may be disposed on the insulating pattern. In an embodiment of the present invention, the third electrode G3 may have the same shape as the insulating pattern in a plan view. In an embodiment of the present invention, for ease of description, one third electrode G3 is shown, but the third transistor T3 may include two third electrodes.

[0104] The fifth insulating layer 50 covering the third electrode G3 is disposed on the fourth insulating layer 40. In an embodiment of the present invention, the fifth insulating layer 50 may include a silicon oxide layer and a silicon nitride layer. The fifth insulating layer 50 may include a plurality of silicon oxide layers and a plurality of silicon nitride layers alternately stacked on each other.

[0105] At least one insulating layer is further disposed on the fifth insulating layer 50. In an embodiment of the present invention, a sixth insulating layer 60 and a seventh insulating layer 70 may be disposed on the fifth insulating layer 50. Each of the sixth insulating layer 60 and the seventh insulating layer 70 may be an organic layer, and may have a single-layer structure or a multi-layer structure. For example, each of the sixth insulating layer 60 and the seventh insulating layer 70 may be a polyimide resin layer having a single-layer structure. However, the present invention is not limited thereto. For example, the sixth insulating layer 60 and the seventh insulating layer 70 may include at least one of an acrylate resin, a methacrylate resin, polyisoprene, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyamide resin, and a perylene resin.

[0106] The first connection electrode CNE10 may be disposed on the fifth insulating layer 50. The first connection electrode CNE10 may be connected to the connection signal line CSL through a first contact hole CH1 penetrating the first insulating layer 10 to the fifth insulating layer 50. The second connection electrode CNE20 may be connected to the first connection electrode CNE10 through a contact hole CH-60 penetrating the sixth insulating layer 60. In an embodiment of the present invention, at least one of the fifth insulating layer 50 and the sixth insulating layer 60 may be omitted.

[0107] The light emitting element layer 130 may include a light emitting element ED and a pixel defining layer PDL. The anode AE ​​of the light emitting element ED may be disposed on the seventh insulating layer 70. The anode AE ​​of the light emitting element ED may be connected to the second connection electrode CNE20 through a contact hole CH-70 penetrating the seventh insulating layer 70. The light emitting element ED may include an organic light emitting diode.

[0108] The opening OP of the pixel defining layer PDL exposes at least a portion of the anode AE ​​of the light emitting element ED. The opening OP of the pixel defining layer PDL may define an emission region PXA. For example, a plurality of pixels may be arranged on a plane of the display layer 100 based on a specific rule. The region in which a plurality of pixels are arranged may be a pixel region. One pixel region may include an emission region PXA and a non-emission region NPXA adjacent to the emission region PXA. The non-emission region NPXA may surround the emission region PXA.

[0109] The hole control layer HCL may be provided in common in the emission region PXA and the non-emission region NPXA; however, the present invention is not limited thereto. A common layer such as the hole control layer HCL may be formed in common in a plurality of pixels. The hole control layer HCL may include a hole transport layer and a hole injection layer.

[0110] The light emitting layer EML may be disposed on the hole control layer HCL. The light emitting layer EML may be disposed in a region corresponding to the opening OP. The light emitting layer EML may be individually formed in each of the plurality of pixels.

[0111] In the embodiment of the present invention, a patterned light emitting layer EML is shown. However, the light emitting layer EML may be provided in a plurality of pixels together. In this case, the light emitting layer EML may generate white light or blue light. In addition, the light emitting layer EML may have a multi-layer structure.

[0112] The electron control layer ECL may be disposed on the light emitting layer EML. The electron control layer ECL may include an electron transport layer and an electron injection layer. The cathode CE of the light emitting element ED may be disposed on the electron control layer ECL. The electron control layer ECL and the cathode CE may be disposed together in a plurality of pixels.

[0113] The encapsulation layer 140 is disposed on the cathode CE. The encapsulation layer 140 may cover a plurality of pixels. In an embodiment of the present invention, the encapsulation layer 140 directly covers the cathode CE. In an embodiment of the present invention, the display layer 100 may further include a covering layer directly covering the cathode CE. In an embodiment of the present invention, the stacked structure of the light emitting element ED may have the same Figure 5 The structure shown in is the vertical opposite structure.

[0114] The encapsulation layer 140 may be disposed on the light emitting element layer 130. The encapsulation layer 140 may include an inorganic layer, an organic layer, and an inorganic layer sequentially stacked on each other, and the layers constituting the encapsulation layer 140 are not limited thereto.

[0115] The inorganic layer can protect the light emitting element layer 130 from moisture and oxygen, and the organic layer can protect the light emitting element layer 130 from foreign matter such as dust particles. The inorganic layer may include, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, etc. The organic layer may include, for example, an acrylic organic layer, but the present invention is not limited thereto.

[0116] The sensor layer 200 may include a base layer 201 , a first conductive layer 202 , a sensing insulating layer 203 , a second conductive layer 204 , and a cover insulating layer 205 .

[0117] For example, the base layer 201 may be an inorganic layer including at least one of silicon nitride, silicon oxynitride, and silicon oxide. In addition, the base layer 201 may be an organic layer including epoxy resin, acrylate resin, or imide resin. The base layer 201 may have a single-layer structure, or may have a multi-layer structure stacked in the third direction DR3.

[0118] Each of the first conductive layer 202 and the second conductive layer 204 may have a single-layer structure, or may have a multi-layer structure in which layers are stacked in the third direction DR3.

[0119] The conductive layer of the single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include, for example, molybdenum, silver, titanium, copper, aluminum, or an alloy thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium zinc tin oxide (IZTO), etc. In addition, the transparent conductive layer may include a conductive polymer such as PEDOT, a metal nanowire, graphene, etc.

[0120] The conductive layer of the multilayer structure may include a metal layer. For example, the metal layer may have a three-layer structure of titanium / aluminum / titanium. The conductive layer of the multilayer structure may include at least one metal layer and at least one transparent conductive layer.

[0121] At least one of the sensing insulating layer 203 and the capping insulating layer 205 may include an inorganic film. For example, the inorganic film may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0122] At least one of the sensing insulating layer 203 and the cover insulating layer 205 may include an organic film. The organic film may include, for example, at least one of acrylate resin, methacrylate resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and perylene resin.

[0123] Figure 6 is a block diagram showing a touch integrated circuit inspection apparatus according to an embodiment of the present invention.

[0124] Reference Figure 6 , the touch integrated circuit inspection apparatus TIA can inspect defects and performance degradation of the touch integrated circuit 200C.

[0125] The touch integrated circuit inspection apparatus TIA may include an inspection board IB and an inspection part (or inspection circuit) IP.

[0126] The inspection board IB may be electrically connected to the touch integrated circuit 200C. For example, the inspection board IB may be connected to the circuit board PB through a connector to be electrically connected to the touch integrated circuit 200C. The inspection board IB may be driven in response to a signal provided from the touch integrated circuit 200C.

[0127] The inspection board 1B may include a plurality of first electrodes TX and a plurality of second electrodes RX. This will be described later.

[0128] The inspection part IP may be electrically connected to the inspection board IB through the circuit board PB. For example, the inspection part IP may be connected to the circuit board PB through a connector or the like. For example, the inspection part IP may be an inspection circuit. For example, the inspection part IP may include a memory and a processor.

[0129] The inspection part IP may drive the inspection board IB by using the touch integrated circuit 200C. The inspection part IP may receive an inspection result obtained by driving the inspection board IB from the touch integrated circuit 200C. The inspection part IP may inspect a defect in the touch integrated circuit 200C based on the inspection result.

[0130] The touch integrated circuit 200C may be implemented as an integrated circuit (IC), and may be mounted on a separate circuit board PB in a chip on film (COF) method to be electrically connected to the sensor layer 200 .

[0131] According to an embodiment of the present invention, a plurality of circuit boards PB may be provided, each of which has a touch integrated circuit 200C mounted thereon. In other words, the touch integrated circuit inspection apparatus TIA may inspect each of the plurality of touch integrated circuits 200C.

[0132] According to an embodiment of the present invention, the touch integrated circuit inspection device TIA can inspect the performance of each of the plurality of touch integrated circuits 200C under the same conditions. By comparing the inspection results of the plurality of touch integrated circuits 200C, a touch integrated circuit 200C with a defect can be easily screened. Afterwards, the touch integrated circuit 200C with a defect can be controlled to operate normally through performance adjustment. Therefore, a touch integrated circuit inspection device TIA with improved inspection reliability can be provided.

[0133] Figure 7 is a conceptual diagram illustrating an inspection board according to an embodiment of the present invention.

[0134] Reference Figure 6 and Figure 7 , the inspection board IB may include a base layer BS, a plurality of first electrodes TX, a plurality of second electrodes RX, a first resistor R1, a first capacitor C1, a second resistor R2, and a second capacitor C2.

[0135] The base layer BS may have a plane defined by a first direction DR1 and a second direction DR2 intersecting the first direction DR1. The base layer BS may include a base layer 201 (see Figure 5 ) are made of substantially the same material. A plurality of first electrodes TX, a plurality of second electrodes RX, a first resistor R1, a first capacitor C1, a second resistor R2, and a second capacitor C2 may be disposed on the base layer BS.

[0136] Each of the plurality of first electrodes TX may extend in the second direction DR2. The plurality of first electrodes TX may be spaced apart from each other in the first direction DR1. The plurality of first electrodes TX may include a conductive material. For example, the plurality of first electrodes TX may include a conductive layer 202 (see Figure 5 ) and the second conductive layer 204 (see Figure 5 ) of the same material. The plurality of first electrodes TX may have a diamond pattern.

[0137] Each of the plurality of first electrodes TX may include a sensing pattern SE1 and a bridge pattern SP1. Two sensing patterns SE1 adjacent to each other in the second direction DR2 may be electrically connected to each other through two bridge patterns SP1, but are not particularly limited thereto. The sensing pattern SE1 and the bridge pattern SP1 may be disposed at different layers from each other.

[0138] Each of the plurality of second electrodes RX may extend in the first direction DR1. The plurality of second electrodes RX may be spaced apart from each other in the second direction DR2. The plurality of second electrodes RX may include a conductive material. For example, the plurality of second electrodes RX may include a conductive layer 202 (see Figure 5 ) and the second conductive layer 204 (see Figure 5 The plurality of second electrodes RX may have a diamond pattern.

[0139] Each of the plurality of second electrodes RX may include a first portion SE2 and a second portion SP2. The two bridge patterns SP1 may intersect the second portion SP2 in an insulating manner. The first portion SE2 and the second portion SP2 may be integrated with each other and may be disposed at the same layer as each other.

[0140] The number of the first electrodes TX may be the same as the number of the second electrodes RX. For example, the plurality of first electrodes TX may have 50 electrodes, and the plurality of second electrodes RX may have 50 electrodes. To this end, when viewed from above a plane, the plurality of first electrodes TX and the plurality of second electrodes RX may have a square shape.

[0141] According to an embodiment of the present invention, the inspection unit IP of the touch integrated circuit inspection apparatus TIA may drive the inspection board IB by electrically connecting at least a portion of the plurality of first electrodes TX and the plurality of second electrodes RX. The inspection board IB may be driven by the display layer 100 (see FIG. Figure 2 ) and sensor layer 200 (see Figure 2 ) is connected to an appropriate number of electrodes among a plurality of first electrodes TX and a plurality of second electrodes RX in the shape of a touch integrated circuit 200C to correspond to various models. For example, when the touch integrated circuit 200C is used for a watch, the circuit board PB can be electrically connected to "n" first electrodes TX ("n" is a positive integer) and "m" second electrodes RX ("m" is a positive integer) of the inspection board IB having a size corresponding to the watch. When the touch integrated circuit 200C is used for a mobile device, the circuit board PB can be electrically connected to "k" first electrodes TX ("k" is a positive integer) and "l" second electrodes RX ("l" is a positive integer) of the inspection board IB having a size corresponding to the mobile device. In this case, "n" can be less than "k" and "m" can be less than "l". The inspection board IB of the touch integrated circuit inspection device TIA can easily inspect the touch integrated circuit 200C by corresponding to various models. Therefore, a touch integrated circuit inspection device TIA with improved inspection reliability can be provided.

[0142] The first resistor R1 may be electrically connected to one end of each of the plurality of first electrodes TX. The first resistor R1 may include a variable resistor. One end of the first resistor R1 may be connected to one end of each of the plurality of first electrodes TX, and the other end of the first resistor R1 may be connected to the first capacitor C1 and the first terminal P1.

[0143] The first capacitor C1 may be connected between the first resistor R1 and the ground electrode GND. The first capacitor C1 may be a variable capacitor.

[0144] The second resistor R2 may be electrically connected to one end of each of the plurality of second electrodes RX. The second resistor R2 may include a variable resistor. One end of the second resistor R2 may be connected to one end of each of the plurality of second electrodes RX, and the other end of the second resistor R2 may be connected to the second capacitor C2 and the second terminal P2.

[0145] The second capacitor C2 may be connected between the second resistor R2 and the ground electrode GND. The second capacitor C2 may be a variable capacitor.

[0146] The inspection board IB may be electrically connected to the circuit board PB through the first terminal P1 and the second terminal P2. In this case, the inspection board IB may have substantially the same function as the sensor layer 200. The touch integrated circuit 200C may easily drive the inspection board IB, and the inspection part IP may receive the inspection result through the inspection board IB.

[0147] According to an embodiment of the present invention, the inspection board 1B may adjust the element value of each of the first resistor R1, the first capacitor C1, the second resistor R2, and the second capacitor C2 to match the sensor layer 200 included in various product groups (see Figure 2 ) corresponds. When inspecting the touch integrated circuit 200C, the manufacturing of the sensor layer 200 (see Figure 2 ). When inspecting the touch integrated circuit 200C in various product groups, the touch integrated circuit 200C can be inspected by using one inspection board IB. As a result, the inspection cost can be reduced and the inspection process can be shortened. Therefore, a touch integrated circuit inspection device TIA with improved inspection reliability can be provided.

[0148] Figure 8 According to an embodiment of the present invention, Figure 7 A cross-sectional view of the inspection plate taken along line II'.

[0149] Reference Figure 7 and Figure 8 , the bridge pattern SP1 may be disposed on the base layer BS.

[0150] The first insulating layer IN1 may cover the base layer BS and the bridge pattern SP1. The first insulating layer IN1 may include an insulating material. For example, the first insulating layer IN1 may include a layer that is substantially parallel to the sensing insulating layer 203 (see FIG. 2 ). Figure 5 ) of the same material.

[0151] The bridge pattern SP1 and the first insulating layer IN1 may form a first layer L1.

[0152] The sensing pattern SE1, the first portion SE2, and the second portion SP2 may be disposed on the first insulating layer IN1. The sensing pattern SE1, the first portion SE2, and the second portion SP2 may be disposed on the same layer as each other. For example, a portion of each of the plurality of first electrodes TX and the plurality of second electrodes RX may be disposed on the same layer as each other.

[0153] The second insulating layer IN2 may cover the first insulating layer IN1, the sensing pattern SE1, the first portion SE2, and the second portion SP2. The second insulating layer IN2 may include an insulating material. For example, the second insulating layer IN2 may include a conductive layer that is coplanar with the capping insulating layer 205 (see FIG. 2 ). Figure 5 ) of the same material.

[0154] The sensing pattern SE1 may be connected to the bridge pattern SP1 through a contact hole CNT-I penetrating the first insulating layer IN1.

[0155] The second insulating layer IN2 , the sensing pattern SE1 , the first portion SE2 , and the second portion SP2 may form a second layer L2 .

[0156] The inspection board 1B may have a bottom bridging structure. However, this is an example, and the stacking structure of the inspection board 1B according to the embodiment of the present invention is not limited thereto. For example, the inspection board 1B may have a top bridging structure in which the positions of the first layer L1 and the second layer L2 are exchanged with each other.

[0157] Fig. 9 According to an embodiment of the present invention, by cutting and Figure 7 A cross-sectional view of the inspection plate obtained from a portion corresponding to the area AA'. Fig. 9 In the description of Figure 8 The same components are described, and therefore, descriptions thereof are omitted or briefly discussed to avoid redundancy.

[0158] Reference Figure 7 and Fig. 9 , the ground electrode GND may be disposed on the base layer BS. The ground electrode GND may be disposed on the same layer as the bridge pattern SP1. For example, the ground electrode GND may be disposed on the same layer as at least some of the portions of each of the plurality of first electrodes TX.

[0159] The first insulating layer IN1 may cover the ground electrode GND. The ground electrode GND may be referred to as a 'first electrode of the first capacitor C1'.

[0160] The second electrode of the first capacitor C1 may be disposed on the first insulating layer IN1 .

[0161] The second insulating layer IN2 may cover the second electrode of the first capacitor C1 and may be disposed on the first insulating layer IN1 .

[0162] Fig.10 is a plan view showing an inspection plate according to an embodiment of the present invention.

[0163] Reference Fig.10 , the inspection board IB-1 may include a base layer BS, a plurality of first electrodes TX-1, and a plurality of second electrodes RX-1. However, this is an example, and the inspection board IB-1 according to an embodiment of the present invention may also include a plurality of resistors and a plurality of capacitors, or may include a plurality of ground layers.

[0164] Each of the plurality of first electrodes TX-1 may extend in the second direction DR2. The plurality of first electrodes TX-1 may be spaced apart from each other in the first direction DR1. The plurality of first electrodes TX-1 may have a stripe pattern. For example, each of the plurality of first electrodes TX-1 may have a rectangular shape.

[0165] Each of the plurality of second electrodes RX-1 may extend in the first direction DR1. The plurality of second electrodes RX-1 may be spaced apart from each other in the second direction DR2. The plurality of second electrodes RX-1 may have a stripe pattern. For example, each of the plurality of second electrodes RX-1 may have a rectangular shape.

[0166] Fig.11 is a plan view showing an inspection plate according to an embodiment of the present invention. Fig.12 is a cross-sectional view showing an inspection plate according to an embodiment of the present invention. Fig.11 and Fig.12 In the description of Figure 7 and Figure 8 The same components are described, and thus their descriptions are omitted or briefly discussed to avoid redundancy.

[0167] Reference Fig.11 and Fig.12 The inspection board IB-2 may include a first ground layer GNL1, a second layer L2 disposed below the first ground layer GNL1, a first layer L1 disposed below the second layer L2, a base layer BS disposed below the first layer L1, and a second ground layer GNL2 disposed below the base layer BS.

[0168] The first layer L1 and the second layer L2 may include a plurality of first electrodes TX and a plurality of second electrodes RX.

[0169] The first ground layer GNL1 may be disposed on the plurality of first electrodes TX and the plurality of second electrodes RX. A plurality of first slits SL1 may be defined in the first ground layer GNL1, each of the plurality of first slits SL1 extending in the second direction DR2 and the plurality of first slits SL1 being spaced apart from each other in the first direction DR1. For example, a plurality of first slits SL1 may be formed in the first ground layer GNL1. The first ground layer GNL1 may include a conductive material.

[0170] According to a plan view, the plurality of first slits SL1 may overlap the plurality of first electrodes TX and the plurality of second electrodes RX.

[0171] The second ground layer GNL2 may be disposed under the plurality of first electrodes TX and the plurality of second electrodes RX. The second ground layer GNL2 may include a conductive material. The second ground layer GNL2 according to an embodiment of the present invention may be omitted.

[0172] According to an embodiment of the present invention, the first resistor R1 (see Figure 7 ), the first capacitor C1 (see Figure 7 ), the second resistor R2 (see Figure 7 ) and the second capacitor C2 (see Figure 7 ).

[0173] Fig.13 is a plan view showing a first ground layer according to an embodiment of the present invention. Fig.14 is a plan view showing a second ground layer according to an embodiment of the present invention.

[0174] Reference Fig.13 and Fig.14 , a plurality of first slits SL1 may be formed in the first ground layer GNL1 , each of the plurality of first slits SL1 extending in the second direction DR2 and the plurality of first slits SL1 being spaced apart from each other in the first direction DR1 .

[0175] A plurality of first electrodes TX (see Fig.11 ) may be controlled by a width W1 of each of the plurality of first slits SL1 in the first direction DR1.

[0176] A plurality of second slits SL2 may be formed in the second ground layer GNL2 , each of the plurality of second slits SL2 extending in the first direction DR1 and the plurality of second slits SL2 being spaced apart from each other in the second direction DR2 .

[0177] According to the plan view, the plurality of second slits SL2 may be aligned with the plurality of first electrodes TX (see Fig.11 ) and a plurality of second electrodes RX (see Fig.11 ) overlap.

[0178] Fig.15 is a plan view showing an inspection plate according to an embodiment of the present invention. Fig.15 In the description of Figure 7 The same components are described herein, and thus their descriptions are omitted or briefly discussed to avoid redundancy.

[0179] Reference Fig.15 , the inspection board IB-3 may include a base layer BS (see Figure 7 ), multiple first electrodes TX, multiple second electrodes RX and a third ground layer GNL3.

[0180] The third ground layer GNL3 may be disposed on the plurality of first electrodes TX and the plurality of second electrodes RX.

[0181] A plurality of openings HA may be defined in the third ground layer GNL3, each of the plurality of openings HA having a polygonal shape and arranged in the first direction DR1 and the second direction DR2. For example, the plurality of openings HA may be formed in the third ground layer GNL3.

[0182] According to the plan view, the plurality of openings HA may overlap the plurality of first electrodes TX and the plurality of second electrodes RX. Fig.11 ) can be controlled by the area of ​​each of the multiple openings HA.

[0183] Fig.16 An inspection result of measuring the self-capacitance of each channel according to an embodiment of the present invention is shown.

[0184] exist Fig.16 , the horizontal axis indicates a plurality of first electrodes TX (see Figure 7 ) channels, the vertical axis indicates the IP address of the inspection unit (see Figure 6 ) measured in a plurality of first electrodes TX (see Figure 7 ) in each of the self-capacitances.

[0185] Reference Figure 6 , Figure 7 and Fig.16 , the touch integrated circuit inspection apparatus TIA may inspect the performance of each of the three touch integrated circuits 200C. The three touch integrated circuits 200C may include a first touch integrated circuit, a second touch integrated circuit, and a third touch integrated circuit.

[0186] The touch integrated circuit inspection device TIA may be electrically connected to the circuit board PB on which the first touch integrated circuit is mounted, and may inspect the performance of the first touch integrated circuit. In this case, the inspection unit IP may receive the first inspection result TIC1. The first inspection result TIC1 may be provided as a graph obtained by measuring the self-capacitance of a channel of each of the plurality of first electrodes TX.

[0187] The touch integrated circuit inspection device TIA may be electrically connected to the circuit board PB on which the second touch integrated circuit is mounted, and may inspect the performance of the second touch integrated circuit. In this case, the inspection unit IP may receive the second inspection result TIC2. The second inspection result TIC2 may be provided as a graph obtained by measuring the self-capacitance of a channel of each of the plurality of first electrodes TX.

[0188] The first inspection result TIC1 and the second inspection result TIC2 according to an embodiment of the present invention may have substantially similar values ​​to each other. In this way, the first touch integrated circuit and the second touch integrated circuit may be classified as quality products (eg, without defects and with normal functions).

[0189] The touch integrated circuit inspection device TIA may be electrically connected to the circuit board PB on which the third touch integrated circuit is mounted, and may inspect the performance of the third touch integrated circuit. In this case, the inspection unit IP may receive the third inspection result TIC3. ​​The third inspection result TIC3 may be provided as a graph obtained by measuring the self-capacitance of the channel of each of the plurality of first electrodes TX.

[0190] The third inspection result TIC3 according to an embodiment of the present invention may have a value different from the value corresponding to the first inspection result TIC1 and the second inspection result TIC2. In this way, the third touch integrated circuit may be classified as a defective product. Afterwards, the circuit board PB on which the third touch integrated circuit separated from the touch integrated circuit inspection device TIA is mounted can be corrected to have a value similar to the value corresponding to the first inspection result TIC1 and the second inspection result TIC2 through the step of adjusting the performance. In this way, the circuit board PB on which the third touch integrated circuit is mounted can be controlled to operate normally.

[0191] According to an embodiment of the present invention, the touch integrated circuit inspection device TIA can inspect the performance of each of the plurality of touch integrated circuits 200C under the same conditions. By comparing the inspection results of the plurality of touch integrated circuits 200C, a touch integrated circuit 200C with a defect can be easily screened. Afterwards, the touch integrated circuit 200C with a defect can be controlled to operate normally through performance adjustment. Therefore, a touch integrated circuit inspection device TIA with improved inspection reliability can be provided.

[0192] Although the embodiments of the present invention have been described for illustrative purposes, it will be appreciated by those skilled in the art that various modifications and substitutions are possible without departing from the scope and spirit of the present invention. Therefore, the technical scope of the present invention is not limited to the detailed description of this specification.

[0193] As described above, the touch integrated circuit inspection device is capable of inspecting the performance of each of a plurality of touch integrated circuits under the same conditions. By comparing the test results of a plurality of touch integrated circuits, a touch integrated circuit with a defect can be easily screened. Afterwards, the touch integrated circuit with a defect can be controlled to operate normally through performance adjustment. Therefore, a touch integrated circuit inspection device with improved inspection reliability can be provided.

[0194] While the present invention has been described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.

Claims

1. A touch integrated circuit inspection device, the touch integrated circuit inspection device comprising: an inspection board electrically connected to the touch integrated circuit; as well as An inspection circuit receives an inspection result from the touch integrated circuit, Wherein, the inspection board comprises: a plurality of first electrodes, each of the plurality of first electrodes extending in a first direction and the plurality of first electrodes being spaced apart from each other in a second direction intersecting the first direction; and a plurality of second electrodes, each of the plurality of second electrodes extending in the second direction and the plurality of second electrodes being spaced apart from each other in the first direction, and The number of the plurality of first electrodes is the same as the number of the plurality of second electrodes.

2. The touch integrated circuit inspection device according to claim 1, wherein: Each of the plurality of first electrodes and the plurality of second electrodes has a polygonal shape.

3. The touch integrated circuit inspection device according to claim 1, wherein: Each of the plurality of first electrodes and the plurality of second electrodes has a rectangular shape.

4. The touch integrated circuit inspection device according to claim 1, wherein: The first portion of each of the plurality of second electrodes and the plurality of first electrodes are disposed at the same layer.

5. The touch integrated circuit inspection device according to claim 4, wherein: The inspection panel also includes: a first resistor electrically connected to one end of each of the plurality of first electrodes; and The first capacitor is connected between the first resistor and the ground electrode.

6. The touch integrated circuit inspection device according to claim 5, wherein: The inspection panel also includes: a second resistor electrically connected to one end of each of the plurality of second electrodes; and A second capacitor is connected between the second resistor and the ground electrode.

7. The touch integrated circuit inspection device according to claim 5, wherein: The first resistor is a variable resistor, and Wherein, the first capacitor is a variable capacitor.

8. The touch integrated circuit inspection device according to claim 5, wherein: The ground electrode is disposed at the same layer as the second portion of each of the plurality of second electrodes.

9. The touch integrated circuit inspection device according to claim 1, wherein: The inspection panel also includes: A first ground layer, disposed on the plurality of first electrodes and the plurality of second electrodes; and The second ground layer is disposed below the plurality of first electrodes and the plurality of second electrodes.

10. The touch integrated circuit inspection device according to claim 9, wherein: a plurality of first slits are provided in the first ground layer, each of the plurality of first slits extends in the second direction and the plurality of first slits are spaced apart from each other in the first direction, and The plurality of first slits overlap with the plurality of first electrodes and the plurality of second electrodes.

11. The touch integrated circuit inspection device according to claim 10, wherein: The self-capacitance of each of the plurality of first electrodes is controlled by the width of each of the plurality of first slits in the first direction.

12. The touch integrated circuit inspection device according to claim 10, wherein: a plurality of second slits are provided in the second ground layer, each of the plurality of second slits extending in the first direction and the plurality of second slits being spaced apart from each other in the second direction, and The plurality of second slits overlap the plurality of first electrodes and the plurality of second electrodes.

13. The touch integrated circuit inspection device according to claim 9, wherein: A plurality of openings are provided in the first ground layer, each of the plurality of openings has a polygonal shape and the plurality of openings are arranged in the first direction and the second direction, and The plurality of openings overlap with the plurality of first electrodes and the plurality of second electrodes.

14. A touch integrated circuit inspection device, the touch integrated circuit inspection device comprising: Check the board, electrically connected to the touch IC, Wherein, the inspection board comprises: a plurality of first electrodes, each of the plurality of first electrodes extending in a first direction and the plurality of first electrodes being spaced apart from each other in a second direction intersecting the first direction; a plurality of second electrodes, each of the plurality of second electrodes extending in the second direction and the plurality of second electrodes being spaced apart from each other in the first direction; a first resistor electrically connected to one end of each of the plurality of first electrodes; and The first capacitor is connected between the first resistor and the ground electrode.

15. The touch integrated circuit inspection device according to claim 14, wherein: The first resistor is a variable resistor, and Wherein, the first capacitor is a variable capacitor.

16. The touch integrated circuit inspection device according to claim 14, wherein: The inspection panel also includes: a second resistor electrically connected to one end of each of the plurality of second electrodes; and A second capacitor is connected between the second resistor and the ground electrode.

17. The touch integrated circuit inspection device according to claim 14, wherein: The first portion of each of the plurality of second electrodes and the plurality of first electrodes are disposed at the same layer.

18. The touch integrated circuit inspection device according to claim 17, wherein: The ground electrode is disposed at the same layer as the second portion of each of the plurality of second electrodes.

19. The touch integrated circuit inspection device according to claim 14, wherein: At least one of the plurality of first electrodes and the plurality of second electrodes has a rhombus shape.

20. The touch integrated circuit inspection device according to claim 14, wherein: At least one of the plurality of first electrodes and the plurality of second electrodes has a rectangular shape.

Images