Modified semiconductor wafer and modification method and application thereof

Abstract

The invention provides a modified semiconductor wafer and a modification method and application thereof. The modification method comprises the following steps: mixing an alkaline substance, a fluxing agent and a metal oxide, and then carrying out heat treatment to obtain a molten etching agent; placing a semiconductor wafer above the molten-state etching agent for preheating, then dipping the semiconductor wafer in the molten-state etching agent for standing to obtain an etched semiconductor wafer, and then taking out the etched semiconductor wafer for post-processing to obtain the modified semiconductor wafer. Through the high-temperature etching method, the Warp value and the Bow value of the wafer are rapidly and efficiently reduced, the wafer flatness is remarkably improved, the geometric performance of the wafer can be effectively improved, the downstream use requirement is met, the manufacturing difficulty and the production cost of the wafer are reduced, the process can be simplified, and the production efficiency is improved. The problems of long time consumption, high cost and easy generation of internal material defects in the traditional process are solved.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors, and in particular relates to a modified semiconductor wafer and a modification method and application thereof. Background Art

[0002] As a wide bandgap semiconductor, single crystal silicon carbide has the characteristics of high thermal conductivity and high saturated electron drift rate. It can work at higher power levels, higher temperatures and more severe environments, and has many advantages that ordinary silicon-based semiconductors cannot meet. In recent years, wide bandgap semiconductors have attracted more and more attention, so it is more and more important to obtain high-quality silicon carbide substrate materials. The high quality mentioned here not only refers to the quality of the crystal itself, but also the high quality and excellent flatness parameters of the surface of the silicon carbide single crystal. Epitaxial growth is highly dependent on the substrate. When the wafer is bent or the surface is undulating, the quality of the film will be seriously affected. Even when used as a seed crystal, the grown bulk single crystal material will be seriously affected by the surface defects, stress and flatness of the substrate. All defects on the substrate will generally be copied to the new epitaxial material as is. Such defects will not only cause leakage, but also significantly reduce electron mobility.

[0003] Patent CN102569055A discloses a method for adjusting the surface and flatness of a silicon carbide single crystal wafer, which overcomes the defects of traditional wet etching by using a potassium hydroxide + sodium hydroxide molten salt oxygen blowing method, greatly improves the wafer quality, and greatly improves the wafer flatness, but the oxygen blowing amount needs to be continuously adjusted during the whole process, and the preparation method is relatively complicated; Patent CN109321980A discloses a high-flatness, low-damage large-diameter single crystal silicon carbide substrate, which is processed by a grinding wheel consolidated abrasive, and the obtained single crystal silicon carbide substrate has good surface data; Patent CN109545680A discloses a rapid preparation method for a high-flatness, low-damage single crystal silicon carbide substrate, which Single crystal silicon carbide is processed by fully consolidated abrasive and then chemically mechanically polished to obtain a single crystal silicon carbide substrate with high flatness and low damage; CN117174572A discloses a method for improving local anomalies in the flatness of a silicon carbide substrate, which first tests the thickness of the substrate with flatness anomalies and sorts it, then analyzes and locates the area according to the distribution of the flatness LTV and TTV, then determines the direction of the substrate on the ceramic disk according to the flatness anomaly position, and finally selects the rough polishing and fine polishing processes with matching removal amounts according to the test values ​​of LTV and TTV for polishing, and finally achieves uniform flatness of the entire wafer; CN113584596A discloses an annealing method for improving the flatness of a silicon carbide wafer.

[0004] In the above-mentioned prior art, a silicon carbide substrate with high flatness is obtained either by physical grinding and polishing, which inevitably produces other defects or cracks during the processing; or the flatness of the substrate is improved by annealing, but the annealing time is long and other defects may also occur.

[0005] Therefore, how to improve the flatness of the chip without damaging it, while solving the problems of being time-consuming, costly and causing internal material defects, is one of the important directions of current research. Summary of the invention

[0006] In view of the deficiencies of the prior art, the purpose of the present invention is to provide a modified semiconductor wafer and its modification method and application. The present invention uses a high-temperature etching method to achieve rapid and efficient reduction of the Warp value and Bow value of the wafer, significantly improves the wafer flatness, effectively improves the wafer geometric performance, meets downstream use requirements, reduces its manufacturing difficulty and production cost, and simplifies the process, solving the problems of traditional processes that are time-consuming, costly, and prone to internal material defects.

[0007] In order to achieve the purpose of the invention, the present invention adopts the following technical solutions:

[0008] In a first aspect, the present invention provides a method for modifying the surface shape of a semiconductor wafer, the modification method comprising the following steps:

[0009] The alkaline substance, flux and metal oxide are mixed and then heat treated to obtain a molten etchant.

[0010] The semiconductor wafer is placed above the molten etchant for preheating, then immersed in the molten etchant and allowed to stand to obtain an etched semiconductor wafer, and then the etched semiconductor wafer is taken out for post-processing to obtain a modified semiconductor wafer.

[0011] The present invention uses a high-temperature etching method to quickly and efficiently reduce the Warp value (Warp is a global characteristic of a silicon wafer, indicating the maximum deviation of the silicon wafer surface from the plane, and it measures the distance between the highest point and the lowest point of the silicon wafer) and the Bow value (Bow refers to the curvature of the silicon wafer, and the Bow value is defined by measuring the maximum deviation between the center and the edge of the silicon wafer) of the wafer, and significantly improves the flatness of the wafer. It can effectively improve the geometric performance of the wafer, meet the downstream use requirements, reduce its manufacturing difficulty and production cost, and simplify the process, and solve the problems of long time consumption, high cost and easy occurrence of internal material defects in traditional processes.

[0012] Among them, the present invention introduces a co-solvent into the etchant to accelerate the melting efficiency of the alkaline substance and improve the stability of the molten substance; the introduction of metal oxides can decompose to form oxygen during the etching process (i.e., the preheating and standing process), thereby improving the etching efficiency. At the same time, the presence of oxygen can alleviate the phenomenon of blackening of the carbon surface of the semiconductor wafer caused by the etching process.

[0013] The present invention places the semiconductor wafer on top of the molten etchant for preheating, which can prevent the semiconductor wafer from cracking due to excessive temperature.

[0014] Preferably, the alkaline substance includes any one of NaOH, KOH, Ca(OH)2 or NaHCO3, or a combination of at least two thereof.

[0015] Preferably, the flux includes any one of Na2B4O7, PbO or ZnO, or a combination of at least two of them.

[0016] Preferably, the metal oxide comprises Na2O2 and / or K2O2.

[0017] Preferably, the mass ratio of the alkaline substance, flux and metal oxide is (20-50):(1-5):(5-10), and the mass ratio of the three can be any ratio that satisfies this range. For example, relatively speaking, the mass of the alkaline substance can be any ratio within the range of 20-50, such as 20, 30, 40 or 50, etc., the mass of the flux can be any ratio within the range of 1-5, such as 1, 2, 3, 4 or 5, etc., and the mass of the metal oxide can be any ratio within the range of 5-10, such as 5, 6, 7, 8, 9 or 10, etc.

[0018] In the present invention, the combination of alkaline substances, flux and metal oxides in a suitable mass ratio helps the alkaline substances to fully melt without causing waste. At the same time, the metal oxide can provide an appropriate amount of oxygen within a suitable range, thereby improving etching efficiency and wafer quality. Excessive oxygen may cause oxidation of the wafer surface.

[0019] Preferably, the heat treatment temperature is 300-600°C, for example, 300°C, 350°C, 400°C, 450°C, 500°C, 550°C or 600°C.

[0020] In the present invention, a suitable heat treatment temperature is helpful to maintain the molten state of the etchant.

[0021] Preferably, the heat treatment holding time is 20-60 min, for example, 20 min, 30 min, 40 min, 50 min or 60 min.

[0022] Preferably, the semiconductor wafer comprises a silicon carbide wafer.

[0023] Preferably, the semiconductor wafer is placed above the molten etchant at a height of 5-15 cm, for example, 5 cm, 8 cm, 10 cm, 12 cm or 15 cm.

[0024] In the present invention, placing the semiconductor wafer at an appropriate height is more conducive to fully preheating the semiconductor wafer. If the position is too low, the preheating rate will be too fast and cracks will be easily generated. If the position is too high, the preheating efficiency will be affected.

[0025] Preferably, the preheating process of the semiconductor wafer is performed in an etchant vapor atmosphere.

[0026] In the present invention, the etchant steam preheats the wafer more gently and evenly, and the etchant can be further stabilized while the wafer is preheated, which is beneficial for subsequent etching of the wafer.

[0027] Preferably, the preheating time is 1-10 min, for example, it can be 1 min, 2 min, 3 min, 4 min, 5 min, 6 min, 7 min, 8 min, 9 min or 10 min.

[0028] In the present invention, the preheating process of appropriate time helps the semiconductor wafer to be fully preheated and heated, and avoids the semiconductor wafer being directly placed in the molten etchant, otherwise it is easy to cause uneven temperature on the wafer surface, resulting in inconsistent etching effect, and even cracking. If the preheating time is too long, it is easy to cause defects and reduce the flatness of the wafer.

[0029] It should be noted that the etchant is always in a molten state.

[0030] Preferably, the standing time is 5s-10min, for example, it can be 5s, 1min, 3min, 5min, 7min, 9min or 10min, etc., preferably 30s-5min.

[0031] In the present invention, the standing still process of appropriate time helps to etch the semiconductor wafer appropriately and fully. If the etching time is too short, the semiconductor wafer cannot be fully etched, and the purpose of improving the surface quality of the wafer cannot be achieved; if the etching time is too long, it is easy to cause unnecessary defects in the semiconductor wafer, affecting the final flatness of the wafer.

[0032] Preferably, the post-processing step includes a cooling process, and the operation method of the cooling process includes:

[0033] The taken-out etched semiconductor wafer is placed on top of the molten etchant.

[0034] In the present invention, placing the etched semiconductor wafer above the molten etchant to cool it down can buffer the cooling rate and prevent the semiconductor wafer from cracking during the cooling process, thereby preventing unnecessary losses.

[0035] Preferably, the modification method comprises the following steps:

[0036] The alkaline substance, flux and metal oxide are mixed in a mass ratio of (20-50):(1-5):(5-10), and then put into a crucible, heated to 300-600°C at a heating rate of 5-15°C / min (for example, 5°C / min, 6°C / min, 7°C / min, 8°C / min, 9°C / min, 10°C / min, 11°C / min, 12°C / min°C / min, 13°C / min°C / min or 14°C / min, etc.), and heat treated for 20-60 minutes to obtain a molten etchant.

[0037] The cleaned silicon carbide wafer is placed above the molten etchant and the placement height is controlled to be 5-15 cm for preheating for 1-10 minutes, and then immersed in the molten etchant and allowed to stand for 5 seconds to 10 minutes to obtain an etched silicon carbide wafer.

[0038] Then, the etched silicon carbide wafer is taken out and placed above the molten etchant for cooling, and the placement height is controlled to be 20-30 cm (for example, it can be 20 cm, 21 cm, 22 cm, 23 cm, 24 cm, 25 cm, 26 cm, 27 cm, 28 cm, 29 cm or 30 cm, etc.), and the temperature is reduced to 80-120°C (for example, it can be 80°C, 90°C, 100°C, 110°C or 120°C, etc.), and then the wafer is washed with water and alcohol (the alcohol solvent used for alcohol washing can be, for example, methanol, ethanol, isopropanol, n-butanol or isobutanol, etc.), and then dried to obtain a modified silicon carbide wafer.

[0039] It should be noted that the main function of alcohol washing is to improve the cleaning effect of silicon carbide wafers.

[0040] In a second aspect, the present invention provides a modified semiconductor wafer, wherein the modified semiconductor wafer is modified by the modification method described in the first aspect.

[0041] In a third aspect, the present invention provides a use of the modified semiconductor wafer as described in the second aspect in preparing a substrate or a seed crystal.

[0042] The numerical range described in the present invention not only includes the point values ​​listed above, but also includes any point values ​​between the above numerical ranges that are not listed. Due to space limitations and for the sake of simplicity, the present invention no longer exhaustively lists the specific point values ​​included in the range.

[0043] Compared with the prior art, the present invention has the following beneficial effects:

[0044] The present invention uses a high-temperature etching method to quickly and efficiently reduce the Warp value and Bow value of the chip, significantly improve the flatness of the chip, effectively improve the geometric performance of the chip, meet downstream usage requirements, reduce its manufacturing difficulty and production cost, and simplify the process to solve the problems of traditional processes that are time-consuming, costly, and prone to internal material defects. DETAILED DESCRIPTION

[0045] The technical solution of the present invention is further described below by specific implementation methods. It should be understood by those skilled in the art that the embodiments are only to help understand the present invention and should not be regarded as specific limitations of the present invention.

[0046] Example 1

[0047] This embodiment provides a method for modifying the surface shape of a semiconductor wafer, and the modification method comprises the following steps:

[0048] (1) 30 parts of alkaline substance, 2 parts of flux and 8 parts of metal oxide are mixed, then placed in a crucible that is resistant to temperature and strong alkali, heated to 500° C. at a heating rate of 5° C. / min and heat treated for 30 min to obtain a molten etchant.

[0049] Among them, the mass ratio of alkaline substance, flux and metal oxide is 30:2:8, the alkaline substance is KOH, the flux is Na2B4O7, and the metal oxide is Na2O2.

[0050] (2) The cleaned silicon carbide wafer is placed above the molten etchant and the placement height is controlled to be 5 cm for preheating for 5 minutes, and then immersed in the molten etchant and allowed to stand for 8 seconds to obtain an etched silicon carbide wafer.

[0051] (3) The etched silicon carbide wafer is taken out and placed 20 cm above the molten etchant to cool down. After cooling down to 100° C., the wafer is cleaned with hot water and ethanol at one time, and then dried to obtain a modified silicon carbide wafer.

[0052] Example 2

[0053] This embodiment provides a method for modifying the surface shape of a semiconductor wafer, and the modification method comprises the following steps:

[0054] (1) 20 parts of alkaline substance, 5 parts of flux and 10 parts of metal oxide are mixed, then placed in a crucible that is resistant to temperature and strong alkali, heated to 300° C. at a heating rate of 10° C. / min and heat treated for 60 min to obtain a molten etchant.

[0055] The mass ratio of the alkaline substance, flux and metal oxide is 20:5:10, the alkaline substance is NaOH, the flux is PbO, and the metal oxide is K2O2.

[0056] (2) The cleaned silicon carbide wafer is placed above the molten etchant and the placement height is controlled to be 10 cm for preheating for 7 minutes, and then immersed in the molten etchant and allowed to stand for 1 minute to obtain an etched silicon carbide wafer.

[0057] (3) The etched silicon carbide wafer is taken out and placed 20 cm above the molten etchant to cool down. After cooling down to 80° C., the wafer is cleaned with hot water and ethanol at one time, and then dried to obtain a modified silicon carbide wafer.

[0058] Example 3

[0059] This embodiment provides a method for modifying the surface shape of a semiconductor wafer, and the modification method comprises the following steps:

[0060] (1) 50 parts of alkaline substance, 1 part of flux and 5 parts of metal oxide are mixed, then placed in a crucible that is resistant to temperature and strong alkali, heated to 600° C. at a heating rate of 15° C. / min and heat treated for 20 minutes to obtain a molten etchant.

[0061] The mass ratio of the alkaline substance, flux and metal oxide is 50:1:5, the alkaline substance is Ca(OH)2, the flux is ZnO, and the metal oxide is Na2O2.

[0062] (2) The cleaned silicon carbide wafer is placed above the molten etchant and the placement height is controlled to be 15 cm for preheating for 10 minutes, and then immersed in the molten etchant and allowed to stand for 2 minutes to obtain an etched silicon carbide wafer.

[0063] (3) The etched silicon carbide wafer is taken out and placed 20 cm above the molten etchant to cool down. After cooling down to 120° C., the wafer is cleaned with hot water and ethanol at one time, and then dried to obtain a modified silicon carbide wafer.

[0064] Example 4

[0065] The difference between this embodiment and embodiment 1 is that the amount of the flux in step (1) is 0.1 parts, so that the mass ratio of the alkaline substance, the flux and the metal oxide is 30:0.1:8.

[0066] The remaining modification methods and parameters were the same as those in Example 1.

[0067] Example 5

[0068] The difference between this embodiment and embodiment 1 is that the number of parts of the flux in step (1) is 10 parts, so that the mass ratio of the alkaline substance, the flux and the metal oxide is 30:10:8.

[0069] The remaining modification methods and parameters were the same as those in Example 1.

[0070] Example 6

[0071] The difference between this embodiment and embodiment 1 is that the amount of the metal oxide in step (1) is 1 part, so that the mass ratio of the alkaline substance, the flux and the metal oxide is 30:2:1.

[0072] The remaining modification methods and parameters were the same as those in Example 1.

[0073] Example 7

[0074] The difference between this embodiment and embodiment 1 is that the amount of the metal oxide in step (1) is 20 parts, so that the mass ratio of the alkaline substance, the flux and the metal oxide is 30:2:20.

[0075] The remaining modification methods and parameters were the same as those in Example 1.

[0076] Example 8

[0077] The difference between this embodiment and embodiment 1 is that the placement height of the silicon carbide wafer in step (2) is 1 cm.

[0078] The remaining modification methods and parameters were the same as those in Example 1.

[0079] Example 9

[0080] The difference between this embodiment and embodiment 1 is that the placement height of the silicon carbide wafer in step (2) is 20 cm.

[0081] The remaining modification methods and parameters were the same as those in Example 1.

[0082] Example 10

[0083] The difference between this embodiment and embodiment 1 is that the preheating time in step (2) is 30 seconds.

[0084] The remaining modification methods and parameters were the same as those in Example 1.

[0085] Embodiment 11

[0086] The difference between this embodiment and embodiment 1 is that the standing time in step (2) is 12 minutes.

[0087] The remaining modification methods and parameters were the same as those in Example 1.

[0088] Example 12

[0089] The difference between this embodiment and embodiment 1 is that the standing time in step (2) is 3 seconds.

[0090] The remaining modification methods and parameters were the same as those in Example 1.

[0091] Comparative Example 1

[0092] The difference between this comparative example and Example 1 is that no flux is added.

[0093] The remaining modification methods and parameters were the same as those in Example 1.

[0094] Comparative Example 2

[0095] The difference between this comparative example and Example 1 is that no metal oxide is added.

[0096] The remaining modification methods and parameters were the same as those in Example 1.

[0097] Comparative Example 3

[0098] The difference between this comparative example and Example 1 is that step (2) does not involve a preheating process.

[0099] The remaining modification methods and parameters were the same as those in Example 1.

[0100] Performance Testing

[0101] The flatness of the modified silicon carbide wafers obtained in the above embodiments and comparative examples is measured, and the specific steps include:

[0102] The flatness of the modified silicon carbide wafer is tested using a semiconductor wafer geometric morphology automatic inspection machine to obtain the Warp value and Bow value. The smaller the absolute values ​​of the Warp value and Bow value, the better the flatness of the silicon carbide wafer.

[0103] The test results are shown in Table 1.

[0104] Table 1

[0105]

[0106]

[0107] analyze:

[0108] As can be seen from the above table, the present invention uses a high-temperature etching method to achieve a rapid and efficient reduction in the Warp value and Bow value of the wafer. The smaller the absolute values ​​of the Warp value and Bow value, the better the flatness of the silicon carbide wafer. After testing, the technical solution provided by this application can significantly reduce the absolute values ​​of the Warp value and Bow value, while the wafer is intact. It can be seen that the modification method provided by the present invention significantly improves the flatness of the wafer, which can effectively improve the geometric performance of the wafer, meet downstream use requirements, reduce its manufacturing difficulty and production cost, and simplify the process to solve the problems of long time consumption, high cost and easy occurrence of internal material defects in traditional processes.

[0109] It can be seen from Example 1 and Examples 4-5 that if the amount of flux used is too little, the etching effect will be slow, uneven etching will occur, and the final flatness of the chip will be affected; if the amount of flux used is too much, the etching effect will be too fast, and it will be difficult to accurately control the etching effect, thus affecting the flatness of the chip.

[0110] It can be seen from Examples 1 and 6-7 that if the amount of metal oxide used is too little, too little oxygen is decomposed and the etching efficiency is reduced; if the amount of metal oxide used is too much, too much oxygen is decomposed and the local etching effect of the semiconductor wafer is too fast, resulting in reduced wafer flatness.

[0111] It can be seen from Example 1 and Examples 8-9 that if the placement height of the silicon carbide wafer is too low, the wafer preheating is prone to unevenness, resulting in inconsistent etching effects; if the placement height of the silicon carbide wafer is too high, the wafer preheating is not sufficient, affecting the final etching effect.

[0112] It can be seen from Example 1 and Examples 10-12 that if the preheating time is too short, the chip is not fully preheated, affecting the final etching effect; if the standing time is too short, the etching effect cannot be fully achieved; if the standing time is too long, it is easy to cause unnecessary defects and affect the final chip flatness.

[0113] It can be seen from Example 1 and Comparative Example 1 that if no flux is added, the etching efficiency is reduced, affecting the final etching effect.

[0114] It can be seen from Example 1 and Comparative Example 2 that if metal oxide is not added, oxygen cannot be decomposed to improve the etching effect, resulting in reduced flatness.

[0115] It can be seen from Example 1 and Comparative Example 3 that if the preheating process is not performed, the temperature of the wafer is prone to be uneven during etching, resulting in uneven etching effect and affecting the overall flatness of the wafer.

[0116] The applicant declares that the present invention illustrates the process method of the present invention through the above-mentioned embodiments, but the present invention is not limited to the above-mentioned process steps, that is, it does not mean that the present invention must rely on the above-mentioned process steps to be implemented. Those skilled in the art should understand that any improvement of the present invention, equivalent replacement of the raw materials selected by the present invention, addition of auxiliary components, selection of specific methods, etc., all fall within the protection scope and disclosure scope of the present invention.

Claims

1. A method for modifying the surface shape of a semiconductor wafer, characterized in that: The modification method comprises the following steps: The alkaline substance, flux and metal oxide are mixed and then heat treated to obtain a molten etchant; The semiconductor wafer is placed above the molten etchant for preheating, then immersed in the molten etchant and allowed to stand to obtain an etched semiconductor wafer, and then the etched semiconductor wafer is taken out for post-processing to obtain a modified semiconductor wafer.

2. The modification method according to claim 1, characterized in that: The alkaline substance includes any one of NaOH, KOH, Ca(OH)2 or NaHCO3 or a combination of at least two thereof; Preferably, the flux comprises any one or a combination of at least two of Na2B4O7, PbO or ZnO; Preferably, the metal oxide comprises Na2O2 and / or K2O2.

3. The modification method according to claim 1 or 2, characterized in that: The mass ratio of the alkaline substance, flux and metal oxide is (20-50):(1-5):(5-10).

4. The modification method according to any one of claims 1 to 3, characterized in that: The temperature of the heat treatment is 300-600°C; Preferably, the heat treatment is carried out for 20-60 minutes.

5. The modification method according to any one of claims 1 to 4, characterized in that: The semiconductor wafer comprises a silicon carbide wafer; Preferably, the semiconductor wafer is placed above the molten etchant at a height of 5-15 cm.

6. The modification method according to any one of claims 1 to 5, characterized in that: The semiconductor wafer is preheated in an etchant vapor atmosphere; Preferably, the preheating time is 1-10 min.

7. The modification method according to any one of claims 1 to 6, characterized in that: The standing time is 5s-10min, preferably 30s-5min; Preferably, the post-processing step includes a cooling process, and the operation method of the cooling process includes: The taken-out etched semiconductor wafer is placed on top of the molten etchant.

8. The modification method according to any one of claims 1 to 7, characterized in that: The modification method comprises the following steps: The alkaline substance, flux and metal oxide are mixed in a mass ratio of (20-50):(1-5):(5-10), then put into a crucible, and heated to 300-600° C. at a heating rate of 5-15° C. / min for 20-60 min to obtain a molten etchant; Placing the cleaned silicon carbide wafer above the molten etchant and controlling the placement height to be 5-15 cm for preheating for 1-10 minutes, then dipping it into the molten etchant and standing for 5 seconds to 10 minutes to obtain an etched silicon carbide wafer; Then, the etched silicon carbide wafer is taken out and placed above the molten etchant for cooling, and the placement height is controlled to be 20-30 cm. After cooling to 80-120° C., the wafer is washed with water and alcohol, and dried to obtain a modified silicon carbide wafer.

9. A modified semiconductor wafer, characterized in that: The modified semiconductor wafer is obtained by modification using the modification method according to any one of claims 1 to 8.

10. Use of the modified semiconductor wafer according to claim 9 in preparing a substrate or a seed crystal.

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