Addition module, data processing method and related device

Abstract

The invention belongs to the technical field of data processing, and particularly relates to an addition module, a data processing method and a related device. The addition module is used for realizing data processing of the plurality of counters, the addition module is used for realizing a counting function in the plurality of counters, and each of the plurality of counters in the addition module is composed of a shared adder, a selector and a corresponding register. The registers update currently stored count values in a specified time period based on a loading signal, the selector transmits the count values stored in the plurality of registers to the shared adder in different specified time periods, and the shared adder calculates counting results corresponding to the plurality of registers based on the received count values; in this way, the count value stored in the corresponding register is updated. The addition module can gate the registers in a time-sharing manner through the adder, and the multiple registers share the hardware architecture of the counter, so that the chip area occupied by the multiple counters is greatly reduced, the chip power consumption is reduced, and the signal transmission path time delay of the counters is reduced.

Description

Technical Field

[0001] The present application belongs to the field of data processing technology, and in particular, relates to an addition module, a data processing method and related devices. Background Art

[0002] A counter is a common module in circuits that is used to record and accumulate input signal pulses or clock cycles. Counters can track the number of input pulses or cycles and are often used in applications such as counting, timing, and frequency measurement.

[0003] In the related art, a traditional counter includes a register and an adder. The register is used to store the current accumulated value, and the adder increments the value in the register (usually by one). However, this counter configuration occupies a large area on the chip. Especially when a large number of counters are required, more chip resources will be occupied, limiting the integration and design flexibility of other functional modules. In addition, each counter requires an independent register and adder, which will lead to increased power consumption, increased area, and increased path delay. In large-scale integrated systems, high power consumption will increase heat dissipation requirements, reduce the energy efficiency of the equipment, and increase the complexity and cost of system design.

[0004] Therefore, it is urgent to design a new technical solution to overcome at least one technical problem existing in the counter in the related art. Summary of the invention

[0005] The present application provides an addition module, a data processing method and related devices to solve at least one of the technical problems that traditional counters occupy more hardware resources, have a high chip area occupancy rate, consume a lot of power, and have a long path time.

[0006] In a first aspect, the present application provides an adding module for realizing data processing of multiple counters, wherein the adding module is used to realize counting functions in multiple counters, and the multiple counters in the adding module are respectively composed of a shared adder, a selector, and corresponding registers; wherein

[0007] Each register of the plurality of registers is configured to store a count value corresponding to a counter; receive a load signal through a load signal terminal; and update a currently stored count value within a specified time period based on the load signal;

[0008] A selector is configured to transmit count values ​​stored in a plurality of registers to the shared adder respectively within different specified time periods;

[0009] The shared adder is configured to sequentially receive count values ​​stored in a plurality of registers, and respectively calculate count results corresponding to the plurality of registers based on the received count values, so as to update the count values ​​stored in the corresponding registers.

[0010] In an optional embodiment, the register further includes an input terminal and an output terminal; the register updates the currently stored count value within a specified period based on the load signal, and is specifically configured as follows:

[0011] Determine whether the load signal is in a valid state in the current cycle; if the load signal is in a valid state in the current cycle, determine whether the register is in a valid state in the current cycle; send the currently stored count value to the adder through the output end; in the next cycle, receive the target count value to be updated through the input end, and update the currently stored count value to the target count value; the target count value is calculated by the shared adder.

[0012] In an optional embodiment, the selector at least includes input terminals respectively connected to the plurality of registers, a plurality of address selection signal terminals corresponding one-to-one to the plurality of registers, and an output terminal connected to the shared adder;

[0013] The selector transmits the count values ​​stored in multiple registers to the shared adder respectively in different specified time periods, and is specifically configured as follows: in each cycle, the address selection signal in the current cycle is received through the address selection signal terminal; based on the address selection signal in the current cycle, the register in the valid state in the current cycle is determined; the input terminal corresponding to the register in the valid state is selected, and the count value stored in the register in the valid state is received through the input terminal; the count value received in the current cycle is sent to the shared adder through the output terminal.

[0014] In an optional embodiment, the address selection signals received by the selector through the plurality of address selection signal terminals are consistent with the load signals received by the plurality of registers through the load signal terminals.

[0015] In an optional embodiment, the number of registers in a valid state in each specified time period is 1.

[0016] In an optional embodiment, the encoding form of the address selection signal is a one-hot code.

[0017] In an optional embodiment, the shared adder includes at least an output end respectively connected to a plurality of registers, and an input end connected to a selector; the shared adder receives count values ​​stored in the plurality of registers in sequence, and calculates count results corresponding to the plurality of registers based on the received count values, and is specifically configured as follows: in each cycle, the count value stored in the register in a valid state in the current cycle is received from the selector side; in each cycle, the sum of the received count value and the accumulated value is calculated to obtain a target count value to be updated; and the target count value is transmitted to the corresponding register through the output end so that the corresponding register updates the stored count value in the next cycle.

[0018] In an optional embodiment, the register, before receiving the target count value to be updated through the input terminal in the next cycle and updating the currently stored count value to the target count value, is also configured to: set the input terminal to be in an open state in the next cycle based on the load signal; wherein the input terminal in the open state is used to receive the target count value transmitted by the shared adder.

[0019] In an optional embodiment, the multiple counters are in a mutually exclusive state.

[0020] In an optional embodiment, the multiple counters are in a mutually exclusive state, which includes: the load signals corresponding to the multiple registers are in a mutually exclusive state, or the load signals corresponding to the multiple registers are 0.

[0021] In an optional embodiment, the load signal corresponding to the multiple registers is a single bit; the single bit signal of the load signal is used to indicate that the corresponding register is in a valid state, or the single bit signal of the load signal is used to indicate that the corresponding register is not in a valid state.

[0022] In a second aspect, an embodiment of the present application provides a data processing method based on an addition module, which is used to implement the addition module described in the first aspect. The method is used to implement data processing of multiple counters, and the addition module is used to implement the counting function in multiple counters, and the multiple counters in the addition module are respectively composed of a shared adder, a selector, and a corresponding register; the method includes:

[0023] Storing a count value corresponding to the counter through each register of the plurality of registers;

[0024] For each register of the plurality of registers, receiving a load signal through a load signal terminal, and updating a currently stored count value within a specified time period based on the load signal;

[0025] The count values ​​stored in the plurality of registers are transmitted to the shared adder respectively in different specified time periods through the selector;

[0026] The count values ​​stored in the multiple registers are received in sequence through the shared adder, and the count results corresponding to the multiple registers are calculated respectively based on the received count values, so as to update the count values ​​stored in the corresponding registers.

[0027] In a third aspect, an embodiment of the present application provides an electronic device, including a processor or a hardware circuit, wherein the processor or the hardware circuit is used to implement the addition module described in the first aspect.

[0028] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, on which computer program instructions are stored. When the computer program instructions are executed, the addition module described in the first aspect is implemented.

[0029] In a fifth aspect, an embodiment of the present application provides a chip, including a processor and / or a hardware circuit, wherein the processor and / or the hardware circuit is used to implement the addition module described in the first aspect.

[0030] In an embodiment of the present application, an addition module is used to implement data processing of multiple counters, and the addition module is used to implement the counting function in multiple counters. Multiple counters in the addition module are respectively composed of a shared adder, a selector, and corresponding registers. Each of the multiple registers is configured to store the count value corresponding to the counter; receive a load signal through a load signal terminal; and update the currently stored count value within a specified time period based on the load signal. The selector is configured to transmit the count values ​​stored in multiple registers to the shared adder respectively within different specified time periods. The shared adder is configured to receive the count values ​​stored in multiple registers in sequence, and calculate the count results corresponding to the multiple registers respectively based on the received count values, so as to update the count values ​​stored in the corresponding registers. In summary, the addition module can complete the data processing of multiple counters without deploying multiple counters separately through the hardware architecture of the adder time-sharing selection register and the multi-register shared counter, and realize the counting function of multiple counters, which greatly reduces the chip area occupied by multiple counters, reduces chip power consumption, and reduces the signal transmission path delay of the counter. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0032] Figure 1 is a structural block diagram of an addition module in an embodiment of the present application;

[0033] Figure 2 A circuit diagram of a register in an adding module according to an embodiment of the present application;

[0034] Figure 3 is a flow chart of a data processing method based on an addition module according to an embodiment of the present application;

[0035] Figure 4 It is a structural block diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0038] A counter is a common module in circuits that is used to record and accumulate input signal pulses or clock cycles. It usually consists of a register and an adder. In related technologies, each traditional counter contains a register and an adder, and this configuration occupies a large area on the chip. Especially when a large number of counters are required, more chip resources will be occupied, limiting the integration and design flexibility of other functional modules. Each counter requires a separate register and adder, which will lead to increased power consumption, increased area, and increased path delay. In large-scale integrated systems, high power consumption will increase heat dissipation requirements, reduce the energy efficiency of the device, and increase the complexity and cost of system design. In addition, each counter is an independent entity and is difficult to expand or modify. For applications that require frequent changes in the number or function of counters, this rigid structure may not be able to effectively cope with changes in demand.

[0039] In addition, in the related art, each counter operates independently and requires additional control logic to manage operations within the clock cycle. These logics include timing control, signal transmission, and state management, which increases the complexity of the design and the difficulty of verification. For example, when multiple counters operate in parallel, additional timing control circuits and synchronization logic are required to ensure that their timing is correct and avoid data corruption or counting errors, which increases design costs and development time.

[0040] Therefore, it is urgent to design a new technical solution to overcome at least one of the above technical problems.

[0041] In order to solve at least one of the above technical problems, an embodiment of the present application provides an addition module, a data processing method and related devices.

[0042] Specifically, in an embodiment of the present application, an addition module is used to implement data processing of multiple counters, and the addition module is used to implement the counting function in multiple counters. The multiple counters in the addition module are respectively composed of a shared adder, a selector, and corresponding registers. Each of the multiple registers is configured to store a count value corresponding to the counter; receive a load signal through a load signal terminal; and update the currently stored count value within a specified time period based on the load signal. The selector is configured to transmit the count values ​​stored in the multiple registers to the shared adder respectively within different specified time periods. The shared adder is configured to receive the count values ​​stored in the multiple registers in sequence, and calculate the count results corresponding to the multiple registers based on the received count values, so as to update the count values ​​stored in the corresponding registers.

[0043] From a technical perspective, the addition module can complete the data processing of multiple counters without deploying multiple counters separately through the adder time-sharing selection register and the hardware architecture of multiple registers sharing counters, thereby realizing the counting function of multiple counters, greatly reducing the chip area occupied by multiple counters, reducing chip power consumption, and reducing the signal transmission path delay of the counters.

[0044] The addition module, data processing method and related devices provided in the embodiments of the present application are described below in conjunction with the accompanying drawings.

[0045] Figure 1 An addition module is provided in the embodiment of the present application. Figure 1 As shown, in the embodiment of the present application, the addition module is used to implement data processing of multiple counters. It can be understood that the addition module is a hardware or software module that performs addition operations. In the counter design, the addition module is responsible for adding the current count value to the specified increment (usually 1) to generate a new count value.

[0046] The data processing of multiple counters refers to processing and updating the data of multiple counters. Each counter has its own storage unit (such as the register in the embodiment of the present application) to save the current count value. When a certain counter needs to be updated, the addition module is responsible for calculating the new count result. When multiple counters need to be updated, according to the input control signal, the counter to be processed is selected, its current value is input into the addition module, added with the increment (such as 1), and then the result is written back to the counter. This process is called data processing of counters.

[0047] In the embodiment of the present application, the adding module is used to implement the counting function in multiple counters. The basic function of a counter is to accumulate the number of some events or signals. For example, a counter can be used to record the number of times or accumulated time, etc.

[0048] In multiple counters, the counting function is realized by sharing the adder, which means that a single adding module can be used in turn among multiple counters through the sharing mechanism to realize the counting operation of each counter. This sharing design can reduce hardware resources, so that there is no need to equip each counter with a separate adder and related hardware circuits, such as connecting wires and other related circuit devices, which greatly reduces the chip area occupied by the adding module and simplifies the hardware structure of the adding module.

[0049] like Figure 1 As shown, multiple counters in the adding module are respectively composed of a shared adder, a selector, and a corresponding register. The adding module includes the following structure:

[0050] Each register of the plurality of registers is configured to store a count value corresponding to a counter; receive a load signal through a load signal terminal; and update a currently stored count value within a specified time period based on the load signal;

[0051] A selector is configured to transmit count values ​​stored in a plurality of registers to the shared adder respectively within different specified time periods;

[0052] The shared adder is configured to sequentially receive count values ​​stored in a plurality of registers, and respectively calculate count results corresponding to the plurality of registers based on the received count values, so as to update the count values ​​stored in the corresponding registers.

[0053] In the embodiment of the present application, multiple counters are in a mutually exclusive state. That is, in one clock cycle, only one counter can perform an accumulation operation. This mutual exclusion mechanism ensures that in any given clock cycle, at most only one counter in the addition module has a high load signal, thereby allowing the counter to operate. This mechanism is implemented by control logic, and an arbitration circuit, a state machine or a priority encoder is usually used to ensure signal mutual exclusion. This not only prevents race conditions and resource conflicts, ensures the correctness of data updates, but also improves resource efficiency by sharing the addition module through time division multiplexing. This design strategy ensures the consistency and correctness of data, simplifies the addition module and reduces the control complexity, so that shared resources can be used safely and effectively in a multi-counter environment.

[0054] It can be understood that the multiple counters are in a mutually exclusive state, which can be the case that the load signals corresponding to the multiple registers are in a mutually exclusive state. For example, assume that there are three counters (Counter A, Counter B, and Counter C), each of which has a corresponding load signal (Load_A, Load_B, Load_C). The control logic is designed so that in any given clock cycle, only one load signal is high, allowing the corresponding counter to perform an accumulation operation, while the load signals of the other counters remain low. For example, in the first clock cycle, Load_A is high, and the value of Counter A is updated; in the second clock cycle, Load_B is high, and the value of Counter B is updated; in the third clock cycle, Load_C is high, and the value of Counter C is updated. Such a design ensures that at most only one counter is selected for operation at the same time.

[0055] Alternatively, assuming that 0 is invalid and 1 is valid, then multiple counters are in a mutually exclusive state, or the load signals corresponding to multiple registers are 0, and at most only one register's load signal is 1. Exemplarily, the load signals of all counters may be zero, indicating that no counter needs to be updated in the current clock cycle. For example, still taking three counters (Counter A, Counter B, and Counter C) as an example, in a specific clock cycle, since no event or condition triggers the operation of any counter, all load signals (Load_A, Load_B, Load_C) remain zero, indicating that no counter value needs to be updated. In this case, the system will not perform any operation on the counter data in the current cycle, but wait for the condition change in the next cycle.

[0056] Through these two methods, resources can be managed effectively to avoid contention for shared resources at the same time. The design of the control load signal ensures the scheduling and coordination of operations, thereby maintaining the stability and efficiency of the addition module.

[0057] Further optionally, the load signals corresponding to the multiple registers are single-bit. Here, the single-bit signal of the load signal is used to indicate that the corresponding register is in a valid state, or the single-bit signal of the load signal is used to indicate that the corresponding register is not in a valid state.

[0058] For example, when the load signal is high, it indicates that the corresponding register is in a valid state and data can be written or operated. When the signal is low, the register is in an inactive state and no updates are performed. One of the main benefits of this design is that it greatly simplifies the control logic, because the selection and control of the register can be completed only through a single-bit signal, reducing hardware complexity and cost. In addition, by clarifying the operating state of the register, unnecessary energy consumption can also be reduced, because only the required registers will be effectively activated, while the non-working registers remain static. This not only improves the overall efficiency of the system, but also extends the service life of the device in some application scenarios. At the same time, this approach also has a positive impact on data consistency and reliability, avoiding data conflicts caused by register competition in the same clock cycle, making the system operation more robust. It is especially suitable for application scenarios in high-performance computing and resource-constrained environments. This approach can achieve complex multi-counter and multi-register management with minimal control overhead.

[0059] As an optional embodiment, the register further includes an input terminal and an output terminal. Here, the input terminals of the plurality of registers are connected to the shared adder, and the output terminals of the plurality of registers are connected to the selector. Based on the above structure, the register updates the currently stored count value within a specified period based on the load signal, and is specifically configured as follows:

[0060] Determine whether the load signal is in a valid state in the current cycle; if the load signal is in a valid state in the current cycle, determine whether the register is in a valid state in the current cycle; send the currently stored count value to the adder through the output end; in the next cycle, receive the target count value to be updated through the input end, and update the currently stored count value to the target count value. Wherein, the target count value is calculated by the shared adder.

[0061] A register is a basic digital circuit element used to store data or status information. For example, it consists of a group of flip-flops that can store and maintain binary bit data under the control of a clock signal. Registers are widely used in computers and digital systems to store operands, intermediate results, counter status, etc. Their input and output terminals are used to receive and output data, respectively.

[0062] In the embodiment of the present application, the combination of registers, shared adders and selectors forms an efficient data processing architecture. Each register has an input and an output: the input is connected to the shared adder and receives the output of the adder to update its data; the output is connected to the selector and outputs the currently stored count value for use by other circuit modules. This design allows multiple registers to be calculated through a shared adder, which not only saves hardware resources but also simplifies the design of the system.

[0063] Specifically, when the register's load signal is in a valid state in the current clock cycle, the register is activated. It sends the currently stored count value to the shared adder through the output terminal to perform the necessary calculation operations. Then, in the next cycle, the register receives the target count value calculated by the adder through its input terminal and stores it. This design allows register data to be updated efficiently in each clock cycle while using shared resources for centralized calculations.

[0064] From the technical effect point of view, by sharing the adder to process the data of multiple registers, the hardware resource investment can be significantly reduced, and the cost and power consumption can be reduced. Secondly, this effective state judgment mechanism based on the load signal ensures the orderly processing of data and prevents data conflicts or errors. Finally, it can optimize the system performance of the system where multiple counters are located, improve the operation speed, and effectively utilize the parallel computing potential between registers and adders. This is especially useful in scenarios that require fast and efficient data processing, such as real-time data analysis, digital signal processing and other fields.

[0065] As an optional embodiment, the selector includes at least input terminals connected to multiple registers, multiple address signal terminals corresponding to the multiple registers, and an output terminal connected to the shared adder. Exemplarily, the selector can be a multiplexer, that is, a digital circuit device, which functions to select an output from multiple input signals. The selector determines which input is connected to the output based on a control signal (or address signal). It is particularly suitable for scenarios where multiple data sources need to be routed to a single processing path.

[0066] In an optional embodiment, the selector includes at least an input terminal connected to a plurality of registers, a plurality of address selection signal terminals corresponding to each register, and an output terminal connected to a shared adder. The input terminal of the selector is connected to the output terminals of the plurality of registers, and each register can be regarded as a data source. Each register has a corresponding address selection signal terminal. The address selection signal is used to control the selector, instructing it to select the output data of which register among the numerous inputs. The output terminal of the selector is connected to the shared adder. Through the control of the address selection signal, the selector sends the output value of the specified register to the adder for further calculation processing.

[0067] The role of the selector in the system structure of this application is mainly reflected in the following aspects: First, data routing management. The selector effectively manages the data flow of multiple registers through the address selection signal, so that the system can process the data of a specific register at the same time without sending all the data to the adder for calculation at the same time. This can reduce computational complexity and resource occupancy. Second, improve resource utilization. By centrally selecting and managing data flows, the selector can help the shared adder process the required data more effectively, thereby improving the operational efficiency of the entire system. Third, flexibility and controllability. The selector provides great flexibility for the system. The system can dynamically select the data output by different registers for operation as needed without changing the hardware connection. This helps the system flexibly switch between different operating modes to meet various application requirements. In general, the selector is a key component in complex digital systems. Through intelligent data selection and routing, it not only simplifies circuit design, but also improves system efficiency and performance.

[0068] Based on the above structure, the selector transmits the count values ​​stored in the multiple registers to the shared adder in different specified time periods, and is specifically configured as follows:

[0069] In each cycle, the address selection signal of the current cycle is received through the address selection signal terminal; based on the address selection signal of the current cycle, the register in the valid state in the current cycle is determined; the input terminal corresponding to the register in the valid state is selected, and the count value stored in the register in the valid state is received through the input terminal; the count value received in the current cycle is sent to the shared adder through the output terminal.

[0070] Based on the above structure, the selector effectively manages the data transmission between multiple registers and the shared adder in different specified time periods, achieving efficient calculation and data processing. By receiving the address selection signal in each cycle, the selector can accurately control which register's data is selected and transmitted. This ensures that only the currently required register is activated and its count value is sent to the adder for processing, avoiding unnecessary data flow and bandwidth consumption. Since the selector can centrally select specific register data and route it to the shared adder, this configuration optimizes the use of hardware resources. The adder does not need to face the data provided by each register at the same time, thereby reducing complexity and improving overall computing power. Through precise address selection and data transmission, the selector improves the processing efficiency of the system. It only needs to operate when valid data arrives, reducing the time and computing resources wasted on processing invalid or redundant data. In this way, the computing unit can be fully utilized in each cycle to improve the system throughput. This mechanism enables the system to dynamically process different register data according to demand. When the application scenario changes, the selector can adjust the data flow through simple signal switching, which is faster and more flexible. The selector ensures that data can be managed in an orderly manner during transmission, avoiding data conflicts and consistency issues that may be caused by accessing multiple registers at the same time. This supports the reliability and accuracy of the system. In summary, these functions help the system to be more functional through complex but efficient data transmission mechanisms, suitable for a variety of application scenarios, especially in environments that require efficient data management and calculations.

[0071] Optionally, the addressing signal received by the selector through the multiple addressing signal terminals is consistent with the loading signal received by the multiple registers through the loading signal terminals. This consistency ensures that when the data of a certain register needs to be updated or calculated, the selector simultaneously selects the data of the register to be sent to the shared adder, and functionally achieves consistent behavior, that is, the register data that needs to be updated automatically participates in the calculation.

[0072] For example, Figure 1 In the circuit structure shown, the selector can access n+1 addressing signals, and each addressing signal is received by a corresponding addressing signal port. Correspondingly, the register can access n+1 loading signals, and each loading signal is received by the loading signal terminal set in the corresponding register. Here, n is a positive integer. For example, it can be 3, or other values.

[0073] Further optionally, the encoding form of the address selection signal is a one-hot code. One-hot code is a form of encoding in which each state is represented by a series of bits, and at any time, only one bit is high (1), and the other bits are low (0). For example, for four registers, four-bit one-hot codes 0001, 0010, 0100, and 1000 can be used to represent the activated registers respectively. In this way, each state has a unique position representation, the decoding logic is simple, and no complex judgment logic is required to determine which register is in the activated state. One-hot encoding naturally prevents multiple registers from being selected at the same time, because at any time, there will only be one high-level bit. One-hot code can be quickly implemented in hardware, showing great advantages in speed, and is suitable for scenarios that require fast selection and switching.

[0074] In general, by making the address selection signal consistent with the loading signal and using one-hot encoding, the control logic of the system is simplified and the reliability and speed are improved, so that it can run more smoothly in an environment that requires efficient and accurate data processing.

[0075] As an optional embodiment, the shared adder includes at least output terminals connected to a plurality of registers respectively, and an input terminal connected to the selector. The shared adder is a hardware module for performing addition operations, which is shared among a plurality of data sources, thereby optimizing resource usage and improving computing efficiency. This is especially true in scenarios where centralized computing of a large amount of data is required.

[0076] The input of the shared adder is directly connected to the output of multiple registers. This means that the adder can directly obtain data from multiple registers for calculation. This design allows multiple registers to output data to the adder at different time periods, realizing centralized data processing. The selector can select the data of a specific register to be input to the adder. The selector determines which register's output data is to be transmitted to the adder for calculation based on the control signal (such as the address selection signal). This coordination makes data path management more efficient.

[0077] Usually in a digital system, hardware adders are limited. In the present application, by designing a shared adder, the needs of multiple data sources for addition operations can be met without increasing too much hardware complexity. This resource sharing reduces hardware occupancy and power consumption. The shared adder can centrally process the outputs of multiple registers, especially under the precise control of the selector, and can effectively transmit and process the required data in each cycle, thereby improving the overall operation efficiency. There is no need to configure a separate adder for each register, thereby reducing the hardware complexity and cost of the system, making the overall system easier to manage and maintain.

[0078] When data from different sources need to be aggregated, shared adders can perform addition and subtraction operations very effectively, and are used in signal processing, numerical calculation and other fields. In the loop structure, selectors and registers can be used for polling, and the data in each cycle can be accumulated one by one. This is especially useful for systems that need to dynamically adjust operations (such as real-time systems). In short, shared adders play an important role in digital system optimization. By properly configuring selectors and registers, it effectively coordinates data flow and operations, improving the performance and resource utilization of the overall system.

[0079] Based on the above structure, the shared adder sequentially receives the count values ​​stored in the multiple registers, and respectively calculates the count results corresponding to the multiple registers based on the received count values, and is specifically configured as follows:

[0080] In each cycle, the count value stored in the register in the valid state in the current cycle is received from the selector side; in each cycle, the sum of the received count value and the accumulated value is calculated to obtain the target count value to be updated; through the output end, the target count value is transmitted to the corresponding register so that the corresponding register updates the stored count value in the next cycle. Exemplarily, the accumulated value can be set to 1. In actual applications, it can also be set to other values.

[0081] In the above structure, the shared adder processes the count values ​​from multiple registers in turn and calculates the update results to form a dynamic cyclic update system. In each cycle, the adder receives the count value of the current valid register and calculates the sum of the count value and the accumulated value. This means that as the calculation proceeds, the data is constantly updated in real time. This dynamic accumulation process enables the system to continuously track and update the value, which is suitable for applications that require continuous data processing. By transmitting the target count value back to the corresponding register, the system implements a real-time feedback loop so that the register stores the latest calculation result in the next cycle. This real-time feedback mechanism enables the system to respond quickly to input changes and achieve rapid adjustment and adaptation. The shared adder avoids the need to configure a separate adder for each register, effectively reducing the occupation of hardware resources, while ensuring that multiple registers can successfully complete the calculation task. This saves resources and maintains the efficiency of the system. This structure ensures that the calculation result of each cycle can be seamlessly passed to the next cycle, forming a chained, cycle-by-cycle precise calculation process. This is very beneficial for tasks that rely on continuous precision calculations. Since the adder performs targeted calculations based on the selection results of the selector, it can easily adapt to different input conditions and operation requirements. This flexibility enables the system to cope with a variety of complex data processing requirements. This year-on-year on-site update and direct transmission mode reduces the delay in data processing, making the system more agile, especially showing obvious advantages in real-time computing processes.

[0082] Overall, these steps ensure that the addition module can perform data processing operations efficiently and coherently through step-by-step accumulation and real-time updating, ensuring data consistency and reliability of results, which is particularly important in high-performance computing environments.

[0083] As an optional embodiment, the register, before receiving the target count value to be updated through the input terminal in the next cycle and updating the currently stored count value to the target count value, is further configured to: set the input terminal to be in an open state in the next cycle based on the load signal.

[0084] The input terminal in the open state is used to receive the target count value transmitted by the shared adder.

[0085] In this optional embodiment, the input of the register is set to an open state by a load signal in the next cycle to receive the target count value transmitted from the shared adder. The input of the register is controlled by the load signal to ensure that data is received and updated only in a specific cycle. This precise control can ensure the synchronization of data updates and avoid errors or inconsistencies caused by unnecessary data input. Since the input is only turned on in the required cycle, the risk of accidental writing or erroneous data transmission is reduced, and the reliability and stability of the system are improved. The input is only turned on during the necessary time period, thereby reducing unnecessary circuit activities and optimizing the power consumption of the register. This is particularly important for large integrated circuits and helps the overall energy saving of the system. Each register is updated only when needed, ensuring a clear and orderly data flow, helping to optimize the performance of the system, so that the entire module can operate efficiently in a high-load or high-frequency environment. The ability to quickly receive and update data makes the system more responsive and suitable for real-time calculations and rapidly changing data environments. By only receiving the count value of the shared adder, the update process will not be affected by other potential interferences, ensuring that the register obtains the latest data that is accurately calculated. Each update is a planned result, reducing the risk of inconsistency in data transmission and storage. There is no need for complex logic to determine when to update the register, relying only on the single control of the load signal, which greatly simplifies the circuit design and implementation complexity. As a result, the addition module can adapt to different application requirements, and the frequency and timing of data updates can be changed by adjusting the control signal.

[0086] In general, by controlling the open state of the input terminal at a specific moment, precise control of the register update process is achieved, which improves the efficiency, accuracy and reliability of data processing without increasing system complexity and energy consumption.

[0087] As an optional example, the circuit structure of the register of the D flip-flop (D Flip-Flop, DFF) loading the signal terminal is shown in FIG. Figure 2As shown. The D flip-flop is a commonly used storage unit in digital circuits to store one bit of information. Unlike general latches, the D flip-flop samples and outputs the input signal under the control of the clock signal, so it plays a key role in digital circuit design. The D input represents the data input terminal, and the D flip-flop only samples the signal at the D input terminal at the rising edge (or falling edge, depending on the design) of the clock signal. The Q output represents the output terminal, which stores and outputs the value of the sampled D input signal until the next clock edge triggers an input update. At the valid edge of the clock signal, the D flip-flop updates its output state. The input signal is usually sampled at the rising edge (positive edge) or the falling edge (negative edge).

[0088] Thus, the D flip-flop is an edge-triggered device that operates only on the valid edge of the clock signal. The D flip-flop is used to store state information in logic circuits to form registers, shift registers, counters, etc. This can effectively avoid the uncertainty caused by level triggering compared to static or level-triggered latches. Under the triggering action of the clock, the D flip-flop latches the signal at the input to the output. As long as the clock signal is not triggered, the output value remains unchanged. Through the synchronous control of the clock signal, the D flip-flop can ensure that the data exchange and operation between different modules can be coordinated.

[0089] In an embodiment of the present application, an addition module is used to implement data processing of multiple counters, and the addition module is used to implement the counting function in multiple counters. Multiple counters in the addition module are respectively composed of a shared adder, a selector, and corresponding registers. Each of the multiple registers is configured to store the count value corresponding to the counter; receive a load signal through a load signal terminal; and update the currently stored count value within a specified time period based on the load signal. The selector is configured to transmit the count values ​​stored in multiple registers to the shared adder respectively within different specified time periods. The shared adder is configured to receive the count values ​​stored in multiple registers in sequence, and calculate the count results corresponding to the multiple registers respectively based on the received count values, so as to update the count values ​​stored in the corresponding registers. In summary, the addition module can complete the data processing of multiple counters without deploying multiple counters separately through the hardware architecture of the adder time-sharing selection register and the multi-register shared counter, and realize the counting function of multiple counters, which greatly reduces the chip area occupied by multiple counters, reduces chip power consumption, and reduces the signal transmission path delay of the counter.

[0090] Figure 3 A data processing method based on an addition module is provided in an embodiment of the present application, and the method is used to implement data processing of multiple counters. The addition module in the embodiment of the present application is used to implement the counting function in multiple counters. Furthermore, the multiple counters in the addition module are respectively composed of a shared adder, a selector, and a corresponding register. Figure 3 As shown, the method includes:

[0091] 301. Storing a count value corresponding to a counter through each register of a plurality of registers;

[0092] 302. For each register of the plurality of registers, receive a load signal through a load signal terminal, and update a currently stored count value within a specified period of time based on the load signal;

[0093] 303. Transmitting the count values ​​stored in the plurality of registers to the shared adder respectively in different designated time periods through the selector;

[0094] 304. Receive count values ​​stored in a plurality of registers in sequence through a shared adder, and calculate count results corresponding to the plurality of registers based on the received count values, so as to update the count values ​​stored in the corresponding registers.

[0095] In an optional embodiment, the register further includes an input terminal and an output terminal; for each of the plurality of registers, receiving a load signal through the load signal terminal, and updating a currently stored count value within a specified period of time based on the load signal, including:

[0096] Determining whether the loading signal is in a valid state in the current cycle;

[0097] If the load signal is in a valid state in the current cycle, determining that the register is in a valid state in the current cycle;

[0098] Send the currently stored count value to the adder through the output terminal;

[0099] In the next cycle, the target count value to be updated is received through the input terminal, and the currently stored count value is updated to the target count value; the target count value is calculated by the shared adder.

[0100] In an optional embodiment, the selector at least includes input terminals connected to the plurality of registers, a plurality of address signal terminals corresponding to the plurality of registers, and an output terminal connected to the shared adder. The count values ​​stored in the plurality of registers are transmitted to the shared adder in different specified time periods through the selector, including:

[0101] In each cycle, the location selection signal in the current cycle is received through the location selection signal terminal;

[0102] Based on the address selection signal in the current cycle, determine the register in the valid state in the current cycle;

[0103] Selecting the input terminal corresponding to the register in the valid state, and receiving the count value stored in the register in the valid state through the input terminal;

[0104] The count value received in the current cycle is sent to the shared adder through the output terminal.

[0105] In an optional embodiment, the address selection signals received by the selector through the plurality of address selection signal terminals are consistent with the load signals received by the plurality of registers through the load signal terminals.

[0106] In an optional embodiment, the number of registers in a valid state in each specified time period is 1.

[0107] In an optional embodiment, the encoding form of the address selection signal is a one-hot code.

[0108] In an optional embodiment, the shared adder includes at least output terminals connected to the plurality of registers, and an input terminal connected to the selector. The count values ​​stored in the plurality of registers are sequentially received, and the count results corresponding to the plurality of registers are calculated based on the received count values, including:

[0109] In each cycle, the count value stored in the register in the valid state in the current cycle is received from the selector side;

[0110] In each cycle, the sum of the received count value and the accumulated value is calculated to obtain the target count value to be updated;

[0111] The target count value is transmitted to the corresponding register through the output terminal, so that the corresponding register updates the stored count value in the next cycle.

[0112] In an optional embodiment, before receiving the target count value to be updated through the input terminal in the next cycle and updating the currently stored count value to the target count value, the method further includes:

[0113] Based on the loading signal, setting the input terminal to be in an open state in the next cycle;

[0114] The input terminal in the open state is used to receive the target count value transmitted by the shared adder.

[0115] In an optional embodiment, the multiple counters are in a mutually exclusive state.

[0116] In an optional embodiment, the multiple counters are in a mutually exclusive state, which includes: the load signals corresponding to the multiple registers are in a mutually exclusive state, or the load signals corresponding to the multiple registers are 0.

[0117] In an optional embodiment, the load signal corresponding to the multiple registers is a single bit; the single bit signal of the load signal is used to indicate that the corresponding register is in a valid state, or the single bit signal of the load signal is used to indicate that the corresponding register is not in a valid state.

[0118] It should be noted that regarding the data processing method based on the addition module provided by the implementation of this application, the implementation details of each step are the same as the implementation process of the corresponding function in the aforementioned method embodiment. For details, please refer to the description of the corresponding part of the aforementioned method embodiment, which will not be repeated here.

[0119] Based on the same implementation principle, the embodiment of the present application also provides an electronic device, Figure 4 is a structural block diagram of the electronic device 400, such as Figure 4 As shown, the electronic device 400 includes: a processor 401, a memory 402, a communication interface 403, a communication bus 404 and a controller 405; wherein the processor 401, the memory 402, and the communication interface 403 communicate with each other via the communication bus 404; the memory 402 is used to store computer programs; the processor 401 is used to execute the programs stored in the memory 402 to implement corresponding processing functions; the communication interface 404 is used for communication between the electronic device 400 and other devices; and the controller 405 is used to implement the data transmission method described in the above method embodiment.

[0120] In the embodiment of the present application, the communication bus 404 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus 404 may be divided into an address bus, a data bus, a control bus, etc., and the specific form is not limited. For ease of representation, Figure 4 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0121] The memory 402 may include a random access memory (RAM) or a non-volatile memory (non-volatile memory), such as at least one disk memory. Optionally, the memory may also be at least one storage device located away from the processor 401 .

[0122] Processor 401 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other editable logic devices, discrete gate or transistor logic devices, discrete hardware components, and the specific form can be determined according to actual needs.

[0123] Accordingly, an embodiment of the present application further provides a computer-readable storage medium storing a computer program, which, when executed, can implement each step that can be executed by an electronic device in the above method embodiment.

[0124] It should be noted that although one or more embodiments of the present application provide method operation steps as described in the embodiments or flowcharts, more or fewer operation steps may be included based on conventional or non-creative labor. The order of steps listed in the embodiments is only one way of executing the order of many steps and does not represent the only execution order. When the actual device or client product is executed, it can be executed in sequence or in parallel according to the method shown in the embodiments or the drawings (for example, in a parallel processor or multi-threaded processing environment).

[0125] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, devices (systems) or computer program products. Therefore, the embodiments of the present application may take the form of complete hardware embodiments, complete software embodiments or embodiments combining software and hardware. Moreover, one or more embodiments of the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0126] One or more embodiments of the present application are described with reference to flowcharts and / or block diagrams of methods, apparatus (systems) and computer program products according to one or more embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0127] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0128] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0129] Each embodiment in this application is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device and system embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0130] In this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. For those of ordinary skill in the art, the specific meaning of the above terms in one or more embodiments of the present application can be understood according to the specific circumstances.

[0131] It should be noted that, in the absence of conflict, the features in one or more embodiments of the present application and the embodiments may be combined with each other. The one or more embodiments of the present application are not limited to any single aspect, nor to any single embodiment, nor to any combination and / or replacement of these aspects and / or embodiments. Moreover, each aspect and / or embodiment of one or more embodiments of the present application may be used alone or in combination with one or more other aspects and / or embodiments thereof.

[0132] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of one or more embodiments of the present application, rather than to limit them. Although one or more embodiments of the present application have been described in detail with reference to the aforementioned embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the aforementioned embodiments can still be modified, or some or all of the technical features therein can be replaced by equivalents. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of one or more embodiments of the present application, and they should all be included in the scope of the claims and specifications of one or more embodiments of the present application.

[0133] One or more embodiments of the present application are described above in conjunction with optional implementation methods, but these implementation methods are only exemplary and serve only as an illustration. On this basis, multiple replacements and improvements can be made to one or more embodiments of the present application, all of which fall within the scope of protection of one or more embodiments of the present application.

Claims

1. An addition module, characterized in that: It is used to realize data processing of multiple counters, and the adding module is used to realize the counting function of multiple counters. The multiple counters in the adding module are respectively composed of a shared adder, a selector, and corresponding registers; wherein Each register of the plurality of registers is configured to store a count value corresponding to the counter; and receive a load signal through a load signal terminal; updating a currently stored count value within a specified period of time based on the load signal; A selector is configured to transmit count values ​​stored in a plurality of registers to the shared adder respectively within different specified time periods; The shared adder is configured to sequentially receive count values ​​stored in a plurality of registers, and respectively calculate count results corresponding to the plurality of registers based on the received count values, so as to update the count values ​​stored in the corresponding registers.

2. The addition module according to claim 1, characterized in that: The register also includes input and output terminals; The register updates the currently stored count value within a specified period based on the load signal, and is specifically configured as follows: Determining whether the loading signal is in a valid state in the current cycle; If the load signal is in a valid state in the current cycle, determining that the register is in a valid state in the current cycle; Send the currently stored count value to the adder through the output terminal; In the next cycle, the target count value to be updated is received through the input terminal, and the currently stored count value is updated to the target count value; the target count value is calculated by the shared adder.

3. The addition module according to claim 2, characterized in that: The selector at least comprises input terminals respectively connected to the plurality of registers, a plurality of address selection signal terminals corresponding one-to-one to the plurality of registers, and an output terminal connected to the shared adder; The selector transmits the count values ​​stored in multiple registers to the shared adder in different specified time periods, and is specifically configured as follows: In each cycle, the location selection signal of the current cycle is received through the location selection signal terminal; Based on the address selection signal in the current cycle, determine the register in the valid state in the current cycle; Selecting the input terminal corresponding to the register in the valid state, and receiving the count value stored in the register in the valid state through the input terminal; The count value received in the current cycle is sent to the shared adder through the output terminal.

4. The addition module according to claim 3, characterized in that: The address selection signals received by the selector through the plurality of address selection signal terminals are consistent with the load signals received by the plurality of registers through the load signal terminals.

5. The addition module according to claim 3, characterized in that: The number of registers in the valid state during each specified period is 1.

6. The addition module according to claim 3, characterized in that: The encoding form of the location selection signal is one-hot code.

7. The adding module according to claim 2, characterized in that: The shared adder at least includes output terminals respectively connected to a plurality of registers, and an input terminal connected to the selector; The shared adder sequentially receives count values ​​stored in the multiple registers, and respectively calculates count results corresponding to the multiple registers based on the received count values, and is specifically configured as follows: In each cycle, the count value stored in the register in the valid state in the current cycle is received from the selector side; In each cycle, the sum of the received count value and the accumulated value is calculated to obtain the target count value to be updated; The target count value is transmitted to the corresponding register through the output terminal, so that the corresponding register updates the stored count value in the next cycle.

8. The adding module according to claim 7, characterized in that: The register receives the target count value to be updated through the input terminal in the next cycle and updates the currently stored count value to the target count value, and is further configured as follows: Based on the loading signal, setting the input terminal to be in an open state in the next cycle; The input terminal in the open state is used to receive the target count value transmitted by the shared adder.

9. A data processing method based on an addition module, characterized in that: The method is used to realize data processing of multiple counters, wherein the adding module is used to realize the counting function of multiple counters, and the multiple counters in the adding module are respectively composed of a shared adder, a selector, and corresponding registers; the method comprises: Storing a count value corresponding to the counter through each register of the plurality of registers; For each register of the plurality of registers, receiving a load signal through a load signal terminal, and updating a currently stored count value within a specified time period based on the load signal; The count values ​​stored in the plurality of registers are transmitted to the shared adder respectively in different specified time periods through the selector; The count values ​​stored in the multiple registers are received in sequence through the shared adder, and the count results corresponding to the multiple registers are calculated respectively based on the received count values, so as to update the count values ​​stored in the corresponding registers.

10. An electronic device, characterized in that: It comprises a processor or a hardware circuit, wherein the processor or the hardware circuit is used to implement the addition module described in any one of claims 1 to 8.

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