Display device

Abstract

Provided is a novel display device capable of suppressing a decrease in display quality caused by an increase in resistance of a wiring for supplying an input signal to a scanning signal line drive circuit. A GOA-type liquid crystal display device (100) according to one embodiment of the present invention has a plurality of pixels arranged in a matrix, a plurality of gate bus lines, a plurality of source bus lines, a gate drive circuit (120), a source drive circuit (140), and an input signal line (150) for supplying an input signal to the gate drive circuit (120). The gate drive circuit (120) has a shift register circuit (SR), each stage of the shift register circuit (SR) has an input terminal connected to an input signal line (150) via a branch line (152) and an output terminal connected to a gate bus line, and the gate drive circuit (SR) is configured such that the gate drive circuit (SR) is configured such that the gate drive circuit (SR) is configured such that the gate drive circuit (SR) is configured such that the gate drive circuit (SR) is switched between the adjacent branch lines. The input signal line has at least one first unit portion (UR1) having a smaller resistance value than a unit portion adjacent to the first unit portion on the downstream side in the input direction.

Description

Technical Field

[0001] The present invention relates to an active matrix display device, and more particularly to a display device in which a scanning signal line drive circuit for providing a scanning signal for selecting a pixel row is integrally provided with an active matrix substrate of a display panel. The present invention relates to, for example, a liquid crystal display device in which a gate drive circuit is integrally provided with an active matrix substrate of a liquid crystal display panel (so-called gate on array (GOA) type). Background Art

[0002] As liquid crystal display devices become larger and / or more precise, the degradation of display quality caused by the increase in wiring resistance in the gate drive circuit of a GOA type liquid crystal display device has become a problem. For example, the voltage level of the gate signal and / or the waveform of the gate on pulse varies according to the wiring resistance, and as a result, it is visually recognized as uneven brightness of the display.

[0003] Therefore, for example, the liquid crystal display device described in Patent Document 1 has a driving circuit capable of making the waveform of a driving signal uniform. The driving circuit has a plurality of shift registers, each of which has an input terminal, an output terminal, and a switching element connected between the input terminal and the output terminal, wherein the input terminal of each shift register is connected to a plurality of branch points on an input signal line disposed on a display panel, and the output terminal of each shift register is connected to a plurality of output signal lines disposed on the display panel, and a prescribed driving signal is output from the output terminal based on a prescribed signal input through the input terminal of each shift register, and the resistance value between the input terminal and the output terminal of the switching element when the switching element is in the on state is different for all or part of the plurality of shift registers depending on the position of the branch point to which the input terminal is connected. Prior art literature Patent Literature

[0004] Patent Document 1: International Publication No. 2018 / 055769 Summary of the invention Technical Problems to be Solved by the Invention

[0005] An object of the present invention is to provide a novel display device capable of suppressing a decrease in display quality due to an increase in resistance of wiring for supplying input signals to a scanning signal line driving circuit. Technical solutions for solving technical problems

[0006] According to an embodiment of the present invention, solutions described in the following items are provided.

[0007] [Project 1] A display device includes: a plurality of pixels arranged in a matrix having a plurality of pixel rows and a plurality of pixel columns; a plurality of scanning signal lines respectively associated with any of the plurality of pixel rows; a plurality of display signal lines respectively associated with any of the plurality of pixel columns; a scanning signal line driving circuit for supplying scanning signals to the plurality of scanning signal lines, the scanning signals including a selection pulse for selecting any of the plurality of pixel rows; a display signal line driving circuit for supplying display signals to the plurality of display signal lines; and a plurality of input signal lines for providing input signals to the scanning signal line driving circuit, wherein the scanning signal line driving circuit has a shift register circuit, the shift register circuit has a plurality of stages, and the plurality of stages respectively have: an input terminal, a plurality of input terminals connected via branch lines; ... connected to any one of the multiple input signal lines; and an output terminal connected to any one of the multiple scanning signal lines, the scanning signal line driving circuit is configured to apply the selection pulse to the multiple scanning signal lines in sequence along the scanning direction according to the input signal, the scanning signal line driving circuit and the multiple input signal lines are formed on the same substrate as the multiple scanning signal lines, and when the adjacent branches of the input signal lines are taken as unit parts, at least one of the multiple input signal lines has a plurality of unit parts, and the plurality of unit parts have at least one first unit part, and the resistance value of the first unit part is smaller than the resistance value of the unit part adjacent to the first unit part on the downstream side of the input direction of the input signal.

[0008] [Project 2] In the display device described in item 1, the at least one first unit portion includes a plurality of first unit portions, and the first unit portion with a smaller resistance value is located more upstream in the input direction. [Item 3] In the display device described in item 1 or 2, the at least one first unit portion has a portion having a line width wider than a unit portion adjacent to the first unit portion on the downstream side of the input direction.

[0009] [Item 4] The display device described in any one of items 1 to 3, wherein the plurality of unit portions include at least one second unit portion, and the resistance value of the at least one second unit portion is equal to the resistance value of the unit portion adjacent to the second unit portion on the downstream side of the input direction.

[0010] [Item 5] In the display device described in any one of items 1 to 4, each of the plurality of unit portions has a predetermined line width.

[0011] [Item 6] In the display device described in any one of items 1 to 5, the at least one input signal line has more of the first unit parts in the upstream part from the middle of the upstream end and the downstream end of the input direction to the upstream end than in the downstream part from the middle of the upstream end and the downstream end of the input direction to the downstream end.

[0012] [Item 7] In the display device described in any one of items 1 to 4 and 6, the at least one first unit portion has a portion whose line width becomes narrower toward the downstream in the input direction.

[0013] [Item 8] The display device described in any one of items 1 to 7, wherein the multiple pixels respectively have: a display medium layer; a pair of electrodes arranged in an opposing manner with the display medium layer interposed therebetween; and a TFT whose drain electrode is connected to one of the pair of electrodes, the multiple scanning signal lines are multiple gate bus lines, the multiple display signal lines are multiple source bus lines, the gate electrode of the TFT is connected to the gate bus line associated with a pixel row, the pixel row includes pixels including the TFT, the source electrode of the TFT is connected to the source bus line associated with a pixel column, the pixel column includes pixels including the TFT, the scanning signal line driving circuit is a gate driving circuit, the scanning signal is a gate scanning signal that includes a gate on pulse that turns the TFT into an on state as the selection pulse, the display signal line driving circuit is a source driving circuit, and the display signal is a source signal.

[0014] [Item 9] In the display device described in Item 8, the display medium layer is a liquid crystal layer. Beneficial Effects

[0015] According to an embodiment of the present invention, for example, a new display device is provided that can suppress the degradation of display quality caused by the increase of resistance of wiring for supplying input signals to a scanning signal line driving circuit. According to an embodiment of the present invention, for example, a structure simpler than the liquid crystal display device of Patent Document 1 can suppress the degradation of display quality caused by the increase of resistance of wiring for supplying input signals to a gate driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 1 is a schematic plan view of a liquid crystal display device 100 according to an embodiment of the present invention. Figure 2 It is a schematic diagram showing the circuit structure for outputting the gate scanning signal GS. Figure 3 1 is a schematic diagram showing the connection relationship between one input signal line 150 and each stage of the shift register circuit SR. Figure 4A 1 is a schematic diagram showing a connection relationship between one input signal line 150 and each stage of the shift register circuit SR in the liquid crystal display device 100 . Figure 4B 1 is a schematic diagram showing the connection relationship between three input signal lines 150 and each stage of the shift register circuit SR. Figure 4C 1 is a schematic diagram showing the connection relationship between three input signal lines 150 and each stage of the shift register circuit SR. Figure 5A 1 is a schematic diagram showing a pulse waveform of a gate-on pulse GOP in a conventional liquid crystal display device. Figure 5B 2 is a schematic diagram showing a pulse waveform of a gate-on pulse GOP in the liquid crystal display device 100 . DETAILED DESCRIPTION

[0017] The display device of the embodiment of the present invention comprises: a plurality of pixels arranged in a matrix, with a plurality of pixel rows and a plurality of pixel columns; a plurality of scanning signal lines respectively associated with any of the plurality of pixel rows; a plurality of display signal lines respectively associated with any of the plurality of pixel columns; a scanning signal line driving circuit for supplying scanning signals to the plurality of scanning signal lines, the scanning signals comprising a selection pulse for selecting any of the plurality of pixel rows; a display signal line driving circuit for supplying display signals to the plurality of display signal lines; and a plurality of input signal lines for supplying input signals to the scanning signal line driving circuit, the scanning signal line driving circuit comprising a shift register circuit for shifting The bit register circuit has a plurality of stages, each of which has an input terminal connected to any one of a plurality of input signal lines via a branch line and an output terminal connected to any one of a plurality of scanning signal lines, the scanning signal line driving circuit is configured to sequentially apply a selection pulse to the plurality of scanning signal lines along a scanning direction according to an input signal, the scanning signal line driving circuit and the plurality of input signal lines are formed on the same substrate as the plurality of scanning signal lines, at least one unit branch line portion of the plurality of input signal lines has a unit portion between an adjacent unit branch line, and the unit input signal line portion has a portion with a smaller resistance value than a downstream portion in an input direction of the plurality of unit input signals. Typically, at least one first unit portion includes a plurality of first unit portions, and is arranged in such a manner that a first unit portion with a smaller resistance value is located upstream in the input direction.

[0018] An active matrix display device in which each pixel has a TFT is exemplified below. The active matrix display device of the embodiment is characterized in that the plurality of pixels respectively have: a display medium layer; a pair of electrodes arranged in an opposing manner across the display medium layer; and a TFT whose drain electrode is connected to one of the pair of electrodes, the plurality of scanning signal lines are a plurality of gate bus lines, the plurality of display signal lines are a plurality of source bus lines, the gate electrode of the TFT is connected to the gate bus line associated with a pixel row, the pixel row includes pixels having the TFT, the source electrode of the TFT is connected to the source bus line associated with a pixel column, the pixel column includes pixels having the TFT, the scanning signal line driving circuit is a gate driving circuit, the scanning signal is a gate scanning signal including a gate conduction pulse for turning on the TFT as the selection pulse, the display signal line driving circuit is a source driving circuit, and the display signal is a source signal.

[0019] Hereinafter, an active matrix liquid crystal display device in which the display medium layer is a liquid crystal layer will be described with reference to the drawings. Note that the liquid crystal display device according to the embodiment of the present invention is not limited to the device exemplified below.

[0020] Figure 1 is a schematic plan view of a liquid crystal display device 100 according to an embodiment of the present invention.

[0021] The liquid crystal display device 100 has a plurality of pixels P arranged in a matrix, and the plurality of pixels P have a plurality of pixel rows (m rows) and a plurality of pixel columns (n ​​columns). The liquid crystal display device 100 is an active matrix liquid crystal display device, and has a thin film transistor (TFT) and a liquid crystal capacitor Clc for each pixel P. The pixel P may also have an auxiliary capacitor Cs (not shown) electrically connected in parallel with the liquid crystal capacitor Clc. Here, for simplicity, the description related to the auxiliary capacitor Cs is omitted. The liquid crystal capacitor Clc is, for example, also referred to as a pixel electrode (not shown) formed on the active matrix substrate 110 and a common electrode (also referred to as an opposing electrode, not shown) arranged in a manner opposite to the pixel electrode via a liquid crystal layer (not shown). The common electrode is, for example, formed on an opposing substrate 112 arranged opposite to the active matrix substrate 110.

[0022] The area where multiple pixels P are formed is called an active area AA or a display area. Sometimes, pixels in k rows and 1 columns within pixels arranged in m rows and n columns are represented as P(k, l). k, l, m, and n are positive integers that satisfy the relationship of 1≤k≤m, 1≤l≤n. For example, in a so-called full HD liquid crystal display device, m=1080, n=1920×3 (when a color display pixel is composed of R pixels, G pixels, and B pixels, the "pixel" mentioned here is sometimes referred to as a "dot", and a "color display pixel" composed of 3 "dots" is referred to as a "pixel"). Multiple pixels respectively have: a liquid crystal capacitor, including a pixel electrode; and a TFT, whose drain electrode is connected to the pixel electrode.

[0023] The liquid crystal display device 100 further comprises: a plurality of gate bus lines GB (m lines), each associated with any one of the plurality of pixel rows; and a plurality of source bus lines SB (n lines), each associated with any one of the plurality of pixel columns. The gate electrode of the TFT of each pixel is connected to the gate bus line GB associated with the pixel row including the pixel, and the source electrode of the TFT is connected to the source bus line SB associated with the pixel column including the pixel.

[0024] The liquid crystal display device 100 further includes: a gate drive circuit 120 that provides a gate scanning signal including a gate on pulse GOP for turning on the TFT to the plurality of gate bus lines GB; a source drive circuit 140 that provides a source signal to the plurality of source bus lines SB; and a plurality of input signal lines 150 (see Figure 2 ), which provides an input signal to the gate driving circuit 120. The input signal line for supplying an input signal to the source driving circuit 140 is omitted here.

[0025] The liquid crystal display device 100 is a GOA type, and the gate drive circuit 120 is formed on the active matrix substrate 110 in the same manner as the pixel electrodes, TFTs, multiple source bus lines SB, and multiple gate bus lines GB. As is well known, the active matrix substrate 110 is formed by, for example, forming a conductive layer (metal layer), a semiconductor layer, and an insulating layer on a glass substrate by a known method. The source drive circuit 140 can be mounted on the active matrix substrate 110 as a source drive IC, or a flexible substrate carrying a source drive IC can be connected to the active matrix substrate 110.

[0026] The gate drive circuit 120 and the source drive circuit 140 are controlled by a control circuit (not shown). The control circuit has a display control circuit and a power supply circuit composed of a timing controller. The display control circuit provides the required control signals to the gate drive circuit 120 and the source drive circuit 140, respectively, and the power supply circuit provides the required power supply voltage to the gate drive circuit 120 and the source drive circuit 140, respectively. The gate drive circuit 120 provides a gate scanning signal so that a gate conduction pulse GOP that turns the TFT into a conductive state is applied to a plurality of gate buses GB in sequence along the scanning direction, and the source drive circuit 140 provides a source signal to a plurality of source buses SB so that a grayscale voltage that should be displayed by the pixel is applied to the pixel electrode connected to the TFT that turns into a conductive state by the gate conduction pulse. The structure and operation of the control circuit are well known, so a detailed description is omitted. The embodiment of the present invention has a feature on a plurality of input signal lines 150 that provide input signals from the control circuit to the gate drive circuit 120, and other structures can appropriately apply known structures.

[0027] Next, refer to Figure 2 . Figure 2 It is a schematic diagram showing the circuit configuration for outputting the gate scanning signal GS.

[0028] The G0A type gate driving circuit 120 is composed of a shift register circuit SR, and the shift register circuit SR has a plurality of stages (sometimes referred to as unit circuits or shift circuits).

[0029] A plurality of input signals are supplied to the gate drive circuit 120 from a control circuit (not shown) via a plurality of input signal lines 150. Here, the input signals are clock signals CLK1, 2, 3, 4 and a reference voltage Vss, and each input signal line is sometimes referred to as a clock signal line CLK1, 2, 3, 4 and a reference voltage signal line Vss. The clock signal CLK, the reference voltage signal Vss, the Set signal and the Reset signal are input to each stage of the shift register circuit SR. The Set signal and the Reset signal use signals generated at other stages. A gate scan signal GS is output from each stage of the shift register circuit SR to a gate bus GB corresponding to each pixel row. Figure 2 In FIG. 1 , the gate signal corresponding to the k-th pixel row is represented as GS(k), and the k-th stage of the shift register circuit SR is represented as SR(k).

[0030] The gate driving circuit 120 is configured to apply gate-on pulses GOP to a plurality of gate buses GB in sequence along a scanning direction according to an input signal. Figure 2As shown, it is the direction from the first pixel row located at the top of the active area AA toward the pixel row located at the bottom. The side of the input signal line 150 close to the control circuit (for example, a timing controller, not shown) is expressed as upstream, and the side away from it is expressed as downstream. The input signal flows from upstream to downstream in the input signal line 150. The direction in which the input signal flows in the input signal line 150 is called the input direction of the input signal. Here, the case where the input direction of the input signal is consistent with the scanning direction is illustrated, but the embodiments of the present invention are not limited to this, and also include the case where the input direction of the input signal is inconsistent with the scanning direction. For example, when the input signal is input from the upper and lower ends of the active area AA toward the center, the upper end and the lower end of the active area AA become the upstream (the most upstream, the upstream end), and the center of the active area AA becomes the downstream (the most downstream, the downstream end).

[0031] Next, refer to Figure 3 . Figure 3 1 is a schematic diagram showing the connection relationship between an input signal line 150 and each stage of the shift register circuit SR. Figure 2 The connection relationship between the clock signal line CLK1 and each stage of the shift register circuit SR is shown.

[0032] Each of the multiple stages of the shift register circuit SR includes an input terminal (IN) connected to any one of the multiple input signal lines 150 via a branch line 152, and an output terminal (Gout) connected to any one of the multiple gate bus lines GB. If the space between adjacent branch lines 152 of the input signal line 150 is defined as a unit portion UR, the input signal line 150 includes multiple unit portions UR.

[0033] The multiple input signal lines in the existing GOA type liquid crystal display device are formed by a conductive layer with a certain line width from upstream to downstream, and the resistance value per unit length is constant, and each unit part UR has a certain resistance value. Therefore, before the input signal reaches the downstream of the input signal line, it is attenuated and / or delayed by the influence of the resistance corresponding to the length of the input signal line. The upstream of the input signal line becomes the path of the multi-stage input signal to the shift register. Therefore, the upstream of the input signal line, the larger the current value. The larger the current value, the greater the voltage drop and the Joule heat. Therefore, the more upstream of the input signal line, the greater the attenuation and / or delay of the input signal. In addition, since the heat generated by Joule heat is greater upstream, the degree of non-uniformity of the temperature distribution of the liquid crystal display device is greater upstream of the input signal line. For example, Figure 5AAs shown, the pulse waveform of the gate-on pulse output from the gate drive circuit is significantly different on the upstream side and the downstream side. The difference in the pulse waveform of the gate-on pulse affects the display. For example, when the entire display area displays a certain intermediate grayscale, the upper side is brighter and the lower side is darker, resulting in uneven brightness. In addition, since the degree of change in the pulse waveform is greater on the upstream side than on the downstream side, the degree of uneven brightness is greater (steeper) on the upper side and less noticeable (smooth) on the lower side. In addition, since the characteristics of TFT are affected by temperature, the reduction in display quality caused by the uneven temperature distribution is also easily apparent on the upper side of the display area.

[0034] In the liquid crystal display device 100 of the embodiment of the present invention, by reducing the resistance of the input wiring on the upstream side, changes in the pulse waveform of the gate conduction pulse and / or the uneven temperature distribution of the liquid crystal display device are suppressed, thereby suppressing the reduction in display quality caused by increased wiring resistance.

[0035] Next, refer to Figure 4A . Figure 4A 1 is a schematic diagram showing a connection relationship between an input signal line 150 and each stage of the shift register circuit SR in the liquid crystal display device 100 according to the embodiment of the present invention, and Figure 3 Similarly, indicating Figure 2 The connection relationship between the clock signal line CLK1 and each stage of the shift register circuit SR is shown in FIG. The input signal line 150 has a plurality of unit parts UR having a plurality of first unit parts UR1 with a resistance value smaller than that of the unit parts UR adjacent to the downstream in the input direction, and the first unit parts UR1 with a smaller resistance value are located more upstream in the input direction. Figure 4A As shown, the first unit section UR1 may be provided on the upstream side, and at least one (usually multiple) second unit section UR2 having the same resistance value as the unit section adjacent to the downstream may be provided on the downstream side. In addition, the input signal line 150 has more first unit sections UR1 in the upstream section from the middle of the upstream end and the downstream end in the input direction to the upstream end than in the downstream section from the middle of the upstream end and the downstream end in the input direction to the downstream end.

[0036] The unit part UR located upstream in the input direction among the plurality of unit parts UR is a first unit part UR1 whose resistance value decreases as it is located upstream. That is, the resistance value of the first unit part UR1(1) located most upstream is smaller than the resistance value of the first unit part UR1(2) located downstream thereof, and the resistance value of the first unit part UR1(2) is smaller than the resistance value of the first unit part UR1(3) located downstream thereof. This relationship may also be maintained until the unit part UR located most downstream. In this case, it is preferred that the difference in resistance value between the unit parts UR1 adjacent to the downstream increases as it is located upstream. Figure 4AThe second unit portion UR2 (268) and the second unit portion UR2 (269) have the same resistance value.

[0037] The difference in resistance value is, for example, Figure 4B As shown, the line width of the conductive layer forming the input signal line 150 can be adjusted. The plurality of first unit portions UR1 may each have a portion whose line width is wider than the unit portion UR adjacent to the first unit portion UR1 on the downstream side. For example, the first unit portion UR1 has a portion whose line width is wider than the maximum line width of the unit portion adjacent to the downstream, and does not have a portion whose line width is narrower than the maximum line width of the unit portion adjacent to the downstream. The first unit portion UR1 may have a portion whose line width is narrower as it approaches the downstream. In addition, the line width of the input signal line 150 may be continuously and gradually narrowed from the most upstream side to the most downstream side. Alternatively, the resistance value may be adjusted by changing the length of the unit portion UR. Of course, both the line width and the length may be adjusted.

[0038] In addition, if Figure 4C As shown, the line width of each unit portion UR can be made constant or gradually narrowed. If the line width of each unit portion UR is set to be constant, the accuracy of patterning of the conductive layer can be improved compared to a continuous and gradual narrowing of the line width. In addition, it is easy to inspect the patterning of the conductive layer.

[0039] By changing the resistance value of the input signal line 150 in this way, for example, Figure 5B As shown in FIG. 1 , the gate-on pulse output from the gate drive circuit suppresses the difference in pulse waveform between the upstream side and the downstream side. Figure 5A By comparison, it is found that the change of the waveform on the upstream side can be suppressed, and the change of the pulse waveform between adjacent pixel rows (for example, Figure 5B That is, in the liquid crystal display device 100 according to the embodiment of the present invention, the reduction in display quality caused by the increase in the resistance value of the input signal line 150 is suppressed.

[0040] In the above description, the clock signal line CLK1 is exemplified as the input signal line 150, but it is preferable that the same is applied to all the clock signal lines CLK1 to CLK4. It is applicable to the reference voltage signal line Vss and can also be applied to the clock signal line And the reference voltage signal line Vss. In addition, the configuration of the input signal line 150 is not limited to Figure 2 Example shown.

[0041] In an active matrix liquid crystal display device, the timing of applying a gate-on pulse GOP and the timing of supplying a source signal need to be consistent. If the gate-on pulse GOP is delayed, a deviation occurs between the timing of supplying the source signal. If the deviation in timing differs between pixel rows, it is visually recognized as a reduction in display quality. As a method for preventing the above-mentioned problem, there is a known method of intentionally slightly shifting the timing of the gate-on pulse GOP and the timing of supplying the source signal. However, as described above, if the delay difference between adjacent pixel rows of the gate-on pulse GOP is larger on the upstream side than on the downstream side in the input direction, and differs greatly depending on the pixel row, then making the shift between the timing of the gate-on pulse GOP and the timing of supplying the source signal constant and not depending on the pixel row requires complex timing adjustment, which cannot effectively suppress the reduction in display quality. In the liquid crystal display device 100 of the embodiment of the present invention, since the deviation of the delay of the gate conduction pulse GOP can be suppressed and the delay difference between adjacent pixel rows can be made uniform in the entire panel, no complicated timing adjustment is required, thereby effectively suppressing the misalignment between the timing of the gate conduction pulse GOP and the supply source signal from becoming excessive.

[0042] In the above, a GOA type liquid crystal display device is exemplified, but it is not limited thereto. The active matrix display device of the embodiment of the present invention may also be other display devices such as an electrophoretic display device having an electrophoretic display layer as a display medium layer. In addition, the method of selecting a pixel row is not limited to TFT, and other switching elements may be used. Industrial Applicability

[0043] The display device according to the embodiment of the present invention can improve the display quality of a large-scale or high-definition display device. Description of Reference Numerals

[0044] 100: Active matrix liquid crystal display device 110: Active matrix substrate 112: Opposing substrate 120: Gate drive circuit 140: Source drive circuit 150: Input signal line 152: Branch AA: Active Area Clc: Liquid crystal capacitor Cs: auxiliary capacitor GB: Gate bus GS: Gate scan signal P: Pixel SB: Source Bus SR: Shift Register Circuit UR: Unit Part UR1: First unit part UR2: Second unit section

Claims

1. A display device, characterized in that: include: A plurality of pixels are arranged in a matrix having a plurality of pixel rows and a plurality of pixel columns; A plurality of scanning signal lines, respectively associated with any one of the plurality of pixel rows; A plurality of display signal lines, respectively associated with any one of the plurality of pixel columns; A scanning signal line driving circuit supplies scanning signals to the plurality of scanning signal lines, wherein the scanning signals include a selection pulse for selecting any one of the plurality of pixel rows; a display signal line driving circuit for supplying display signals to the plurality of display signal lines; as well as A plurality of input signal lines provide input signals to the scanning signal line driving circuit, Wherein, the scanning signal line driving circuit has a shift register circuit, The shift register circuit has a plurality of stages, The plurality of stages respectively include: an input terminal connected to any one of the plurality of input signal lines via a branch line; and an output terminal connected to any one of the plurality of scanning signal lines. The scanning signal line driving circuit is configured to apply the selection pulse to the plurality of scanning signal lines in sequence along the scanning direction according to the input signal. The scanning signal line driving circuit and the plurality of input signal lines are formed on the same substrate as the plurality of scanning signal lines. When adjacent branches in the input signal line are regarded as unit parts, at least one input signal line among the multiple input signal lines has multiple unit parts, and the multiple unit parts have at least one first unit part, and the resistance value of the first unit part is smaller than the resistance value of the unit part adjacent to the first unit part on the downstream side of the input direction of the input signal.

2. The display device according to claim 1, characterized in that The at least one first unit portion includes a plurality of first unit portions, and a first unit portion having a smaller resistance value is located upstream in the input direction.

3. The display device according to claim 1, characterized in that The at least one first unit portion has a portion having a line width wider than a unit portion adjacent to the first unit portion on the downstream side in the input direction.

4. The display device according to claim 1, characterized in that The plurality of unit sections have at least one second unit section having a resistance value equal to a resistance value of a unit section adjacent to the second unit section on a downstream side in the input direction.

5. The display device according to claim 1, characterized in that The plurality of unit portions each have a prescribed line width.

6. The display device according to claim 1, characterized in that: The at least one input signal line has more first unit portions in an upstream portion from a middle between the upstream end and the downstream end in the input direction to the upstream end than in a downstream portion from a middle between the upstream end and the downstream end in the input direction to the downstream end.

7. The display device according to claim 1, characterized in that: The at least one first unit portion has a portion whose line width becomes narrower as it moves downstream in the input direction.

8. The display device according to any one of claims 1 to 7, characterized in that: The plurality of pixels each include: a display medium layer; a pair of electrodes arranged in an opposing manner across the display medium layer; and a TFT having a drain electrode connected to one of the pair of electrodes. The plurality of scanning signal lines are a plurality of gate bus lines, and the plurality of display signal lines are a plurality of source bus lines. The gate electrode of the TFT is connected to a gate bus associated with a pixel row, the pixel row includes pixels including the TFT, the source electrode of the TFT is connected to a source bus associated with a pixel column, the pixel column includes pixels including the TFT, The scanning signal line driving circuit is a gate driving circuit, and the scanning signal is a gate scanning signal including a gate-on pulse for turning on the TFT as the selection pulse. The display signal line driving circuit is a source driving circuit, and the display signal is a source signal.

9. The display device according to claim 8, characterized in that: The display medium layer is a liquid crystal layer.

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