Array signal digital generation method

Abstract

The invention discloses an array signal digital generation method. The method comprises the following steps: generating control words according to array signal generation parameters; each processing unit for generating the array signal enables each control word to take effect according to the enable pulse; generating a signal effective identifier according to the pulse control word; according to the frequency control word, the phase control word and the signal effective identifier, generating a decimal sampling point delay signal of each channel of the array; performing integer sampling point delay on the decimal sampling point delay signal of each channel of the array according to the delay control word; according to the amplitude control word, amplitude adjustment is carried out on the signal after the integer sampling point of each channel of the array is delayed, and an expected array signal is obtained; and performing signal synchronization of each channel of the array at an array signal receiving end. According to the method, digital generation of array signals is realized in a mode of combining integer sampling point delay and decimal sampling point delay, relatively few resources are consumed, and engineering realization is simpler and more convenient; a synchronization method among a plurality of processing units is provided, generation of array signals of different scales can be met, and expandability of engineering implementation is achieved.

Description

Technical Field

[0001] The invention relates to array signal processing technology, in particular to a signal digital generation method. Background Art

[0002] Arrays are widely used in radar, electronic countermeasures, sonar, communications and other fields. Array signal processing systems usually require near-field testing, far-field testing, and field testing. The test conditions are relatively complex and have strict phase requirements on the analog front end and the external environment. Based on the spatial delay characteristics of the array signal, the array signal is directly generated in a digital way. When the front-end conditions are not available or the performance indicators are not met in the early stages of development, preliminary testing and verification of the array signal processing system can be carried out to accelerate the system development and debugging cycle.

[0003] At present, the digital signal generation mainly adopts direct digital frequency synthesizer. Under the action of system clock, the frequency control word is accumulated by phase accumulator, the accumulated result is truncated and then converted into analog signal through D / A. If each channel of array generates signal separately and then delays the signal (usually filtering), more resources are required, which is not conducive to the generation of multi-channel array signal. If the array is large and multiple processing units are required to generate array signals at the same time, then there will be synchronization problems between multiple processing units, that is, the delay relationship between the signals of each channel of the array caused by the difference in control effective time and data transmission time is destroyed. Summary of the invention

[0004] The purpose of the present invention is to provide a method for digitally generating array signals.

[0005] The technical solution to achieve the purpose of the present invention is: a method for digitally generating array signals, comprising the following steps:

[0006] Step 1: Generate a control word according to array signal generation parameters, wherein the control word includes a pulse control word, a frequency control word, a phase control word, a delay control word and an amplitude control word;

[0007] Step 2: Make each control word effective according to the enable pulse;

[0008] Step 3: Pulse modulation is performed according to the pulse control word to generate a signal valid flag. If it is a continuous wave, the signal valid flag is always high; if it is a pulse, the signal valid flag is high only within the pulse width. When the signal valid flag is low, no signal occurs;

[0009] Step 4: According to the frequency control word p inc , phase control word p off The sum signal is effectively identified, and a fractional sampling point delay signal of each channel of the array is generated;

[0010] Step 5: Delay the fractional sampling point delay signal of each channel of the array by an integer sampling point according to the delay control word;

[0011] Step 6: According to the amplitude control word, the amplitude of the signal after the integer sampling point delay of each channel of the array is adjusted to obtain the desired array signal;

[0012] Step 7: Synchronize the signals of each channel of the array at the array signal receiving end.

[0013] Preferably, the specific steps of generating each control word according to the array signal generation parameter in step 1 are:

[0014] Step 1.1: Generate a pulse control word according to continuous wave or pulse parameters, wherein the pulse control word includes a pulse width and a pulse period;

[0015] Step 1.2: Calculate the integer sampling point delay and the fractional sampling point delay according to the delay of each channel of the array;

[0016] Step 1.3: Calculate the phase increment p between sampling points of each channel of the array according to the signal characteristics inc , i.e., the frequency control word;

[0017] Step 1.4: Calculate the phase offset p of each channel of the array based on the signal characteristics off , i.e., the phase control word;

[0018] Step 1.5: Generate an amplitude control word according to the amplitude parameters of each channel of the array to adjust the signal amplitude of each channel of the array.

[0019] Preferably, the integer sampling point delay I n That is, the delay control word, τ n =I n T s +F n T s , f s is the sampling rate, T s =1 / f s is the sampling period, is the integer sampling point delay, is the fractional sampling point delay, Indicates rounding down.

[0020] Preferably, the phase increment p between sampling points is inc The specific calculation method is:

[0021] For a frequency of f o For a sinusoidal signal, the phase increment between sampling points is:

[0022]

[0023] Among them, K is the frequency control word width, f s is the sampling rate, f0 is the frequency;

[0024] For linear frequency modulation signals The phase increment between sampling points is:

[0025]

[0026] Where k = B / T is the frequency modulation slope, T is the signal time width, B is the signal bandwidth, rect(·) is the rectangular function, f tg =kt g Each step time t g Increased frequency, t g It is usually an integer number of sampling point time intervals, and t is the cumulative time for the signal to occur.

[0027] Preferably, the specific steps of making each control word effective according to the enable pulse are:

[0028] Step 2.1: Determine the number of processing units required for array signal generation, use one of the processing units as a source, generate an enable pulse, and transmit it to the remaining processing units;

[0029] Step 2.2: Each processing unit makes each control word effective according to the enable pulse.

[0030] Preferably, step 4 is based on the frequency control word p inc , phase control word p off The specific steps of summing up the signal valid identification and generating the fractional sampling point delay signal of each channel of the array are as follows:

[0031] Step 4.1: When the signal is valid and marked as high, according to the frequency control word p inc and phase control word p off Generate real-time phase word p rt ;

[0032] Step 4.2: Get the real-time phase word p rt The high K′ bits of , K′≤K, are added with a pseudo-random number using jitter injection technology to obtain a phase word after jitter injection;

[0033] Step 4.3: Obtain the cosine value of the phase word after jitter injection, wherein the cosine value is the fractional sampling point delay signal.

[0034] Preferably, the real-time phase word is specifically:

[0035] Preferably, the specific steps of synchronizing the signals of each channel of the array at the array signal receiving end in step 7 are:

[0036] Step 7.1: In each processing unit, each channel signal and enable pulse of the array are bound and output to the array signal receiving end;

[0037] Step 7.2: At the array signal receiving end, according to the time difference of the enable pulse of each channel signal, the delay correction of each channel signal is performed to synchronize the array channel signals.

[0038] Compared with the prior art, the present invention has the following significant advantages: the present invention realizes digital generation of array signals by combining integer sampling point delay with decimal sampling point delay, consumes relatively few resources, and is simpler to implement in engineering; a synchronization method between multiple processing units is provided, which can meet the generation of array signals of different scales and has the scalability of engineering implementation. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 It is a schematic diagram of the digital generation of array signals of the present invention.

[0040] Figure 2 It is a schematic diagram of synchronization among multiple processing units of the present invention.

[0041] Figure 3 The figure is a phase difference effect diagram between signals of a 4-channel array realized by the present invention. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0043] like Figures 1 to 3 As shown, a signal digital generation method, the specific steps are:

[0044] Step 1: Generate various control words according to the array signal generation parameters, including pulse control word, frequency control word, phase control word, delay control word and amplitude control word;

[0045] Step 1.1: Generate a pulse control word according to continuous wave or pulse parameters, wherein the pulse control word includes a pulse width and a pulse period;

[0046] The unit of pulse control word is sampling period T s , and take an integer, which is convenient for generating effective signal identification.

[0047] Step 1.2: Delay τ of each channel of the array n Calculate integer sampling point delay I n and fractional sampling point delay F n , where the integer sampling point delay In That is, the delay control word;

[0048] Here is τ n =I n T s +F n T s , where f s is the sampling rate, T s =1 / f s is the sampling period, is the integer sampling point delay, is the fractional sampling point delay, Indicates rounding down.

[0049] For array signals, assume that the array consists of a set of omnidirectional array elements, and the positions of N array elements are p n ,n=0,1,…N-1. The plane wave is incident in direction a, then the theoretical delay of each channel of the array is τ n =a T p n / c, where c is the propagation speed of electromagnetic waves in the medium. If the transmission delay difference of the signal of each channel of the array before processing is considered in the application, then the delay of each channel of the array will be added with a delay. For digital generation, these delays should be determined.

[0050] In practical applications, the n The specific value of is not important, but F n T s In this embodiment, a 4-channel array signal is generated with a sampling rate of f s =10.24Gsps, the delay of each channel is τ0=0ps, τ1=3155ps, τ2=3375ps, τ3=3435ps, then I0=0, I1=32, I2=34, I3=35, F0T s =0,F1T s =30ps,F2T s =54.6875ps,F3T s =17.03125ps.

[0051] Step 1.3: Calculate the phase increment p between sampling points of each channel of the array according to the signal characteristics inc , i.e., the frequency control word;

[0052] For a frequency of f o The sinusoidal signal, Wherein, K is the frequency control word width.

[0053] For linear frequency modulation signals Where k = B / T is the frequency modulation slope, T is the signal time width, B is the signal bandwidth, and rect(·) is the rectangular function. Its frequency control word is Among them, f tg =kt g Each step time t g Increased frequency, t g It is usually an integer number of sampling point time intervals, and t is the cumulative time for the signal to occur.

[0054] In practical applications, each channel of the array usually shares a frequency control word.

[0055] In this embodiment, taking a linear frequency modulation signal as an example, f o =8GHz, k=5×10 12 Hz / s, T=10us, step time is t g =T s Here, K=32.

[0056] Step 1.4: Calculate the phase offset p of each channel of the array based on the signal characteristics off , i.e., the phase control word;

[0057] For a frequency of f o The sinusoidal signal, Among them, θ n is the initial phase difference of each channel of the array.

[0058] For linear frequency modulation signals

[0059] In practical applications, the bit width of the phase control word may be inconsistent with the bit width of the frequency control word, so that the phase control word can obtain better phase accuracy. In the embodiment, the bit width of the phase control word is still 32, and the initial phase difference of each channel of the array is set to 0, that is, θ n =0.

[0060] Step 1.5: Generate an amplitude control word according to the amplitude parameters of each channel of the array to adjust the signal amplitude of each channel of the array.

[0061] Since the amplitude adjustment is performed in the digital signal, the amplitude control word here is actually a relative value, and its maximum value is the maximum amplitude value of the signal that can be generated. This control word is not required to be a constant value. In this embodiment, the amplitude control word takes a constant value.

[0062] Step 2: Each processing unit generating array signals makes each control word effective according to the enable pulse;

[0063] Step 2.1: Determine the number of processing units required for array signal generation, use one of the processing units as a source, generate an enable pulse, and transmit it to the remaining processing units;

[0064] The so-called processing unit is usually an FPGA. The transmission of the enable pulse between the processing units can use a transmission form such as LVDS.

[0065] The form of transmitting the enable pulse between the processing units is not limited, and can be cascade transmission of each unit, or transmission from the source to the remaining units, or a mixture of these two forms. It should be noted that attention should be paid to the maximum transmission delay to avoid consuming too many resources for subsequent delay correction. In this embodiment, two processing units are taken as an example.

[0066] Step 2.2: Each processing unit makes each control word effective according to the enable pulse;

[0067] In practical applications, the enable pulse is usually periodic so that when the array signal undergoes parameter changes, the updated control words are made effective, thereby changing the generated signal.

[0068] Step 3: Perform pulse modulation according to the pulse control word to generate a signal valid flag. When the signal valid flag is low, no signal is generated. If it is a continuous wave, the signal valid flag is always high; if it is a pulse, the signal valid flag is high only within the pulse width.

[0069] In practical applications, it is better to accurately identify the effective signal to the sampling point, or it can be accurate to the system clock period T clk , where T clk =1 / f clk , f clk is the system clock frequency, usually the sampling rate f s is the system clock f clk Each channel of the array usually shares a signal valid identifier.

[0070] Step 4: According to the frequency control word p inc , phase control word p off The sum signal is effectively identified, and a fractional sampling point delay signal of each channel of the array is generated;

[0071] Step 4.1: When the signal is valid and marked as high, according to the frequency control word p inc and phase control word p off Generate real-time phase word p rt ,

[0072] In practical applications, in the system clock f clk Under this condition, it can be realized in the form of accumulation If the sampling rate f sis the system clock f clk L times, then L points need to be generated in parallel; if the sampling rate f s is the system clock f clk 1 / L, then every L / f clk Generate 1 point. In this embodiment, take f clk =320MHz, generating 32 points in parallel.

[0073] Step 4.2: Get the real-time phase word p rt The high K′ bits of , K′≤K, are added with a pseudo-random number using jitter injection technology to obtain a phase word after jitter injection;

[0074] Here we take the real-time phase word p rt The high K′ bits of the digits are used to reduce the pressure of subsequent operations; the jitter injection is used to improve the spectrum quality. If this is not a concern, this step can be omitted. In this embodiment, K′=24.

[0075] Step 4.3: The phase word after jitter injection is used as the CORDIC input to obtain the cosine value, which is the fractional sampling point delay signal;

[0076] Using CORDIC to obtain the cosine value uses relatively few resources, especially at high phase accuracy. If this is not a concern, you can also use a table lookup method to obtain the cosine value. It should be noted that the amplitude bit width of the signal needs to be determined at this step based on the actual application requirements.

[0077] Step 5: Delay the fractional sampling point delay signal of each channel of the array by an integer sampling point according to the delay control word;

[0078] Step 6: According to the amplitude control word, the amplitude of the signal after the integer sampling point delay of each channel of the array is adjusted to obtain the desired array signal;

[0079] If there is no need to adjust the signal amplitude, this step can be omitted.

[0080] Step 7: Synchronize the signals of each channel of the array at the array signal receiving end;

[0081] Step 7.1: In each processing unit, each channel signal and enable pulse of the array are bound and output to the array signal receiving end;

[0082] Step 7.2: At the array signal receiving end, according to the time difference of the enable pulse of each channel signal, the delay correction of each channel signal is performed to synchronize the array channel signals.

[0083] Combining the embodiments, it can be seen that the implementation of the delay of each channel of the array is mainly divided into decimal sampling point delay and integer sampling point delay. The decimal sampling point delay is implemented by the frequency control word and phase control word of each channel, which is a resource that must be consumed for the digital generation of the signal; the integer sampling point delay only consumes a small amount of additional logic resources. In comparison, if a filter is used to implement the delay of the signals of each channel of the array, the multiplication and accumulation operations in the filter will consume a lot of resources.

[0084] It can be seen from the embodiments that by transmitting enable pulses between multiple processing units and making the control word effective according to the enable pulses, the delay relationship of the signals of each channel of the array can be effectively tracked, the synchronization problem between multiple processing units is solved, the signal generation of arrays of different scales can be met, and the scalability of engineering implementation is possessed.

Claims

1. A method for digitally generating an array signal, characterized in that: The steps include: Step 1: Generate a control word according to array signal generation parameters, wherein the control word includes a pulse control word, a frequency control word, a phase control word, a delay control word and an amplitude control word; Step 2: Make each control word effective according to the enable pulse; Step 3: Pulse modulation is performed according to the pulse control word to generate a signal valid flag. If it is a continuous wave, the signal valid flag is always high; If it is a pulse, the signal valid flag is high only within the pulse width. When the signal valid flag is low, no signal occurs. Step 4: According to the frequency control word p inc , phase control word p off The sum signal is effectively identified, and a fractional sampling point delay signal of each channel of the array is generated; Step 5: Delay the fractional sampling point delay signal of each channel of the array by an integer sampling point according to the delay control word; Step 6: According to the amplitude control word, the amplitude of the signal after the integer sampling point delay of each channel of the array is adjusted to obtain the desired array signal; Step 7: Synchronize the signals of each channel of the array at the array signal receiving end.

2. The array signal digital generation method according to claim 1, characterized in that: The specific steps of generating each control word according to the array signal generation parameters in step 1 are: Step 1.1: Generate a pulse control word according to continuous wave or pulse parameters, wherein the pulse control word includes a pulse width and a pulse period; Step 1.2: Calculate the integer sampling point delay and the fractional sampling point delay according to the delay of each channel of the array; Step 1.3: Calculate the phase increment p between sampling points of each channel of the array according to the signal characteristics inc , i.e., the frequency control word; Step 1.4: Calculate the phase offset p of each channel of the array based on the signal characteristics off , i.e., the phase control word; Step 1.5: Generate an amplitude control word according to the amplitude parameters of each channel of the array to adjust the signal amplitude of each channel of the array.

3. The array signal digital generation method according to claim 2, characterized in that: Integer sampling point delay I n That is, the delay control word, τ n =I n T s +F n T s , f s is the sampling rate, T s =1 / f s is the sampling period, is the integer sampling point delay, is the fractional sampling point delay, Indicates rounding down.

4. The array signal digital generation method according to claim 2, characterized in that: The phase increment p between sampling points inc The specific calculation method is: For a frequency of f o For a sinusoidal signal, the phase increment between sampling points is: Among them, K is the frequency control word width, f s is the sampling rate, f0 is the frequency; For linear frequency modulation signals The phase increment between sampling points is: Where k = B / T is the frequency modulation slope, T is the signal time width, B is the signal bandwidth, rect(·) is the rectangular function, f tg =kt g Each step time t g Increased frequency, t g It is usually an integer number of sampling point time intervals, and t is the cumulative time for the signal to occur.

5. The array signal digital generation method according to claim 1, characterized in that: The specific steps to make each control word effective according to the enable pulse are: Step 2.1: Determine the number of processing units required for array signal generation, use one of the processing units as a source, generate an enable pulse, and transmit it to the remaining processing units; Step 2.2: Each processing unit makes each control word effective according to the enable pulse.

6. The array signal digital generation method according to claim 1, characterized in that: Step 4: According to the frequency control word p inc , phase control word p off The specific steps of summing up the signal valid identification and generating the fractional sampling point delay signal of each channel of the array are as follows: Step 4.1: When the signal is valid and marked as high, according to the frequency control word p inc and phase control word p off Generate real-time phase word p rt ; Step 4.2: Get the real-time phase word p rt The high K' bit, K'≤K, uses the jitter injection technology, and adds a pseudo-random number to it to obtain the phase word after jitter injection; Step 4.3: Obtain the cosine value of the phase word after jitter injection, wherein the cosine value is the fractional sampling point delay signal.

7. The array signal digital generation method according to claim 6, characterized in that: The real-time phase word is specifically:

8. The array signal digital generation method according to claim 1, characterized in that: The specific steps of synchronizing the signals of each channel of the array at the array signal receiving end in step 7 are: Step 7.1: In each processing unit, each channel signal and enable pulse of the array are bound and output to the array signal receiving end; Step 7.2: At the array signal receiving end, according to the time difference of the enable pulse of each channel signal, the delay correction of each channel signal is performed to synchronize the array channel signals.

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