Multi-network-port POE design method based on 5G intelligent gateway

Abstract

The invention discloses a multi-network-port POE design method based on a 5G intelligent gateway, and relates to the field of gateway design. The mainboard module of the improved 5G intelligent gateway comprises a CPU processor, a DDR, an EMMC, a PMU power management unit, an HDMI screen, a Switch chip, an Ethernet PHY chip, a 5G module and a wifi module, the CPU processor is directly or indirectly connected with each module, the CPU processor is connected with the Ethernet PHY chip through one path of RGMII interface for optical port communication, the CPU processor is connected with the Ethernet PHY chip through the other path of RGMII interface, and the 5G module is connected with the wifi module through the other path of RGMII interface. The method comprises the following steps of: providing a PSE (Power Source Element) chip with an NMOS (N-channel Metal Oxide Semiconductor) tube, converting the NMOS tube into a plurality of network ports through a Switch chip, supplying power to the PSE chip after isolating a magnetic bead at a DC3.3 V input end of the Switch chip, supplying power to the PSE chip after isolating a magnetic bead through another DC48V input end, controlling the on-off of the NMOS tube through the PSE chip when the plurality of network ports are connected to PD equipment, automatically detecting and classifying the PD equipment, and providing 48V direct current for the PD equipment through the PSE chip after the voltage reaches 48V.

Description

Technical Field

[0001] The present invention discloses a multi-network port POE design method based on a 5G intelligent gateway, and relates to the field of gateway design. Background Art

[0002] POE is sometimes referred to as Power over Ethernet. It is the latest standard specification for transmitting data and electrical power simultaneously using existing standard Ethernet transmission cables, while maintaining compatibility with existing Ethernet systems and users.

[0003] Currently, there is no relevant multi-port POE design based on 5G smart gateways, which is not conducive to the development and efficiency improvement of IoT technology. Summary of the invention

[0004] In view of the problems of the prior art, the present invention provides a multi-port POE design method based on a 5G smart gateway, which not only meets the demand for POE multi-port in the project, but also has the advantages of easy use and debugging, and has wide application value.

[0005] The specific scheme proposed by the present invention is:

[0006] The present invention provides a multi-network port POE design method based on a 5G intelligent gateway, and improves the mainboard module of the 5G intelligent gateway, wherein the mainboard module includes a CPU processor, DDR, EMMC, PMU power management, HDMI screen, Switch chip, Ethernet PHY chip, 5G module, and wifi module.

[0007] The CPU processor is directly or indirectly connected to each module. The CPU processor is connected to the Ethernet PHY chip through one RGMII interface for optical port communication, and is connected to the Ethernet PHY chip through another RGMII interface, and then converted to multiple network ports through the Switch chip.

[0008] The PSE chip is powered by isolating the magnetic beads at the DC3.3V input end of the Switch chip. At the same time, the PSE chip is powered by isolating the magnetic beads at another DC48V input end. When multiple network ports are connected to PD devices, the NMOS tube is controlled by the PSE chip to automatically detect and classify the PD devices. After the voltage reaches 48V, the PSE chip provides 48V DC power to the PD devices.

[0009] Furthermore, in the multi-port POE design method based on 5G smart gateway, the CPU processor is directly connected to DDR, EMMC, and PMU power management respectively, the CPU processor is connected to the HDMI screen through the HDMI interface, connected to the wifi module through the PCIE interface, and connected to the 5G module through the USB interface.

[0010] Furthermore, in the multi-port POE design method based on 5G smart gateway, the CPU processor is connected to the Ethernet PHY chip through an RGMII interface for optical port communication, including: selecting the RTL8211FS-CG chip as the Ethernet PHY chip, providing a 25M external crystal oscillator, a reset signal and an interrupt through the RTL8211FS-CG chip, and the CPU processor is connected to the RTL8211FS-CG chip to the optical port through the RGMII interface.

[0011] Furthermore, in the multi-network port POE design method based on 5G smart gateway, another RGMII interface is connected to the Ethernet PHY chip, and then converted to multiple network ports through the Switch chip, including: selecting the RTL8211FS-CG chip as the Ethernet PHY chip, selecting the RTL8370MB-CG chip as the Switch chip,

[0012] The CPU processor is connected to the RTL8211FS-CG chip through the RGMII interface to convert to an optical port, and is connected to the RTL8370MB-CG chip through the optical port to convert to a multi-network port. The RTL8370MB-CG chip provides a 25M external crystal oscillator and reset signal, and obtains external 3.3V and 1.1V power supply.

[0013] The present invention also provides a multi-network port POE motherboard based on a 5G intelligent gateway. The motherboard module of the 5G intelligent gateway includes a CPU processor, DDR, EMMC, PMU power management, HDMI screen, Switch chip, Ethernet PHY chip, 5G module, and wifi module.

[0014] The CPU processor is directly or indirectly connected to each module. The CPU processor is connected to the Ethernet PHY chip through one RGMII interface for optical port communication, and is connected to the Ethernet PHY chip through another RGMII interface, and then converted to multiple network ports through the Switch chip.

[0015] The PSE chip is powered by isolating the magnetic beads at the DC3.3V input end of the Switch chip. At the same time, the PSE chip is powered by isolating the magnetic beads at another DC48V input end. When multiple network ports are connected to PD devices, the NMOS tube is controlled by the PSE chip to automatically detect and classify the PD devices. After the voltage reaches 48V, the PSE chip provides 48V DC power to the PD devices.

[0016] Furthermore, the CPU processor of the multi-port POE motherboard based on the 5G smart gateway is directly connected to the DDR, EMMC, and PMU power management respectively. The CPU processor is connected to the HDMI screen through the HDMI interface, to the wifi module through the PCIE interface, and to the 5G module through the USB interface.

[0017] Furthermore, the CPU processor of the multi-port POE motherboard based on the 5G smart gateway is connected to the Ethernet PHY chip through an RGMII interface for optical port communication, wherein the RTL8211FS-CG chip is selected as the Ethernet PHY chip, and the RTL8211FS-CG chip provides a 25M external crystal oscillator, a reset signal and an interrupt, and the CPU processor is connected to the RTL8211FS-CG chip to the optical port through the RGMII interface.

[0018] Furthermore, another RGMII interface of the multi-network-port POE motherboard based on the 5G smart gateway is connected to the Ethernet PHY chip, and then converted to a multi-network port through the Switch chip, wherein the RTL8211FS-CG chip is selected as the Ethernet PHY chip, and the RTL8370MB-CG chip is selected as the Switch chip.

[0019] The CPU processor is connected to the RTL8211FS-CG chip through the RGMII interface to convert to an optical port, and is connected to the RTL8370MB-CG chip through the optical port to convert to a multi-network port. The RTL8370MB-CG chip provides a 25M external crystal oscillator and reset signal, and obtains external 3.3V and 1.1V power supply.

[0020] The benefits of the present invention are:

[0021] Compared with the existing 5G gateway, the present invention implements a multi-port POE design based on the RGMII interface protocol of the 5G smart gateway. Multiple gateways can be connected in parallel for large-scale networking. Each gateway can be connected to multiple POE cameras, HDMI screens, etc., and so on, which can meet various complex application scenarios in the industry. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a schematic diagram of the overall framework of the 5G smart gateway involved in the present invention.

[0023] Figure 2 This is a schematic diagram of the RGMII optical port framework.

[0024] Figure 3 This is a schematic diagram of the optical port to network port framework.

[0025] Figure 4 This is a schematic diagram of the network port POE function framework. DETAILED DESCRIPTION

[0026] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention.

[0027] Example 1

[0028] The present invention provides a multi-network port POE design method based on a 5G intelligent gateway, and improves the mainboard module of the 5G intelligent gateway, wherein the mainboard module includes a CPU processor, DDR, EMMC, PMU power management, HDMI screen, Switch chip, Ethernet PHY chip, 5G module, and wifi module.

[0029] The CPU processor is directly or indirectly connected to each module. The CPU processor is directly connected to DDR, EMMC, and PMU power management. The CPU processor is connected to the HDMI screen through the HDMI interface, to the wifi module through the PCIE interface, and to the 5G module through the USB interface.

[0030] The CPU processor is connected to the Ethernet PHY chip through an RGMII interface for optical communication. Figure 2 , which may include: selecting the RTL8211FS-CG chip as the Ethernet PHY chip, providing a 25M external crystal oscillator, a reset signal and an interrupt through the RTL8211FS-CG chip, and connecting the CPU processor to the RTL8211FS-CG chip optical port through the RGMII interface.

[0031] Connect to the Ethernet PHY chip through another RGMII interface, and then convert it to multiple network ports through the Switch chip. Figure 3 , which can include: selecting the RTL8211FS-CG chip as the Ethernet PHY chip, selecting the RTL8370MB-CG chip as the Switch chip,

[0032] The CPU processor is connected to the RTL8211FS-CG chip through the RGMII interface to convert to an optical port, and is connected to the RTL8370MB-CG chip through the optical port to convert to a multi-network port. The RTL8370MB-CG chip provides a 25M external crystal oscillator and reset signal, and obtains external 3.3V and 1.1V power supply.

[0033] refer to Figure 4 , after isolating the magnetic beads at the DC3.3V input end of the Switch chip, the PSE chip is powered. The PSE chip selects the PSE TPS23861PWER chip, and at the same time uses another DC48V input end to isolate the magnetic beads and power the PSE chip. When multiple network ports are connected to the PD device, the NMOS tube is controlled by the PSE chip to automatically detect and classify the PD device, and after the voltage reaches 48V, the PSE chip provides 48V DC power to the PD device.

[0034] In the present invention, the CPU can realize multi-network port design through the RGMII interface plus the Ethernet PHY chip and the Switch. The network port POE function needs to add a POE chip output to the network port transformer to provide 48V to achieve, which not only meets the demand for multiple network ports but also increases the network port POE function. In addition to meeting the demand for multiple network ports with POE in actual projects, it also has the advantages of easy use, easy debugging, and easy procurement.

[0035] Example 2

[0036] The present invention also provides a multi-network port POE motherboard based on a 5G intelligent gateway. The motherboard module of the 5G intelligent gateway includes a CPU processor, DDR, EMMC, PMU power management, HDMI screen, Switch chip, Ethernet PHY chip, 5G module, and wifi module.

[0037] The CPU processor is directly or indirectly connected to each module. The CPU processor is connected to the Ethernet PHY chip through one RGMII interface for optical port communication, and is connected to the Ethernet PHY chip through another RGMII interface, and then converted to multiple network ports through the Switch chip.

[0038] The PSE chip is powered by isolating the magnetic beads at the DC3.3V input end of the Switch chip. At the same time, the PSE chip is powered by isolating the magnetic beads at another DC48V input end. When multiple network ports are connected to PD devices, the NMOS tube is controlled by the PSE chip to automatically detect and classify the PD devices. After the voltage reaches 48V, the PSE chip provides 48V DC power to the PD devices.

[0039] As the information interaction and execution process between the modules in the above-mentioned mainboard are based on the same concept as the embodiment of the method of the present invention, the specific contents can be found in the description of the embodiment of the method of the present invention and will not be repeated here.

[0040] Similarly, the motherboard of the present invention implements a multi-port POE design based on the RGMII interface protocol of the 5G smart gateway, and can connect multiple gateways in parallel for large-scale networking. Each gateway can connect multiple POE cameras, HDMI screens, etc., and so on, which can meet various complex application scenarios in the industry.

[0041] It should be noted that not all steps and modules in the above-mentioned processes and mainboard structures are necessary, and some steps or modules can be ignored according to actual needs. The execution order of each step is not fixed and can be adjusted as needed. The system structure described in the above-mentioned embodiments can be a physical structure or a logical structure, that is, some modules may be implemented by the same physical entity, or some modules may be implemented by multiple physical entities, or some components in multiple independent devices may be implemented together.

[0042] The above-described embodiments are only preferred embodiments for fully illustrating the present invention, and the protection scope of the present invention is not limited thereto. Equivalent substitutions or changes made by those skilled in the art based on the present invention are within the protection scope of the present invention. The protection scope of the present invention shall be subject to the claims.

Claims

1. A multi-port POE design method based on 5G intelligent gateway, characterized by Improve the mainboard module of the 5G smart gateway, where the mainboard module includes CPU processor, DDR, EMMC, PMU power management, HDMI screen, Switch chip, Ethernet PHY chip, 5G module, and wifi module. The CPU processor is directly or indirectly connected to each module. The CPU processor is connected to the Ethernet PHY chip through one RGMII interface for optical port communication, and is connected to the Ethernet PHY chip through another RGMII interface, and then converted to multiple network ports through the Switch chip. The PSE chip is powered by isolating the magnetic beads at the DC3.3V input end of the Switch chip. At the same time, the PSE chip is powered by isolating the magnetic beads at another DC48V input end. When multiple network ports are connected to PD devices, the NMOS tube is controlled by the PSE chip to automatically detect and classify the PD devices. After the voltage reaches 48V, the PSE chip provides 48V DC power to the PD devices.

2. According to a multi-port POE design method based on 5G intelligent gateway according to claim 1, it is characterized in that The CPU processor is directly connected to DDR, EMMC, and PMU power management respectively. The CPU processor is connected to the HDMI screen through the HDMI interface, to the wifi module through the PCIE interface, and to the 5G module through the USB interface.

3. According to a multi-port POE design method based on 5G intelligent gateway according to claim 1, it is characterized in that The CPU processor is connected to the Ethernet PHY chip through an RGMII interface for optical port communication, including: selecting the RTL8211FS-CG chip as the Ethernet PHY chip, providing a 25M external crystal oscillator, a reset signal and an interrupt through the RTL8211FS-CG chip, and the CPU processor is connected to the RTL8211FS-CG chip through the RGMII interface to the optical port.

4. According to a multi-port POE design method based on 5G intelligent gateway according to claim 1, it is characterized in that One RGMII interface is connected to the Ethernet PHY chip, and then converted to multiple network ports through the Switch chip, including: selecting the RTL8211FS-CG chip as the Ethernet PHY chip, selecting the RTL8370MB-CG chip as the Switch chip, The CPU processor is connected to the RTL8211FS-CG chip through the RGMII interface to convert to an optical port, and is connected to the RTL8370MB-CG chip through the optical port to convert to a multi-network port. The RTL8370MB-CG chip provides a 25M external crystal oscillator and reset signal, and obtains external 3.3V and 1.1V power supply.

5. A multi-port POE motherboard based on 5G smart gateway, characterized by 5G The mainboard module of the intelligent gateway includes CPU processor, DDR, EMMC, PMU power management, HDMI screen, Switch chip, Ethernet PHY chip, 5G module, and wifi module. The CPU processor is directly or indirectly connected to each module. The CPU processor is connected to the Ethernet PHY chip through one RGMII interface for optical port communication, and is connected to the Ethernet PHY chip through another RGMII interface, and then converted to multiple network ports through the Switch chip. The PSE chip is powered by isolating the magnetic beads at the DC3.3V input end of the Switch chip. At the same time, the PSE chip is powered by isolating the magnetic beads at another DC48V input end. When multiple network ports are connected to PD devices, the NMOS tube is controlled by the PSE chip to automatically detect and classify the PD devices. After the voltage reaches 48V, the PSE chip provides 48V DC power to the PD devices.

6. A multi-network port POE motherboard based on a 5G smart gateway according to claim 5, characterized in that The CPU processor is directly connected to DDR, EMMC, and PMU power management respectively. The CPU processor is connected to the HDMI screen through the HDMI interface, to the wifi module through the PCIE interface, and to the 5G module through the USB interface.

7. According to claim 5, a multi-network port POE motherboard based on a 5G smart gateway is characterized in that The CPU processor is connected to the Ethernet PHY chip through an RGMII interface for optical communication. The RTL8211FS-CG chip is selected as the Ethernet PHY chip. The RTL8211FS-CG chip provides a 25M external crystal oscillator, reset signal and interrupt. The CPU processor is connected to the RTL8211FS-CG chip through the RGMII interface to the optical port.

8. According to claim 5, a multi-network port POE motherboard based on a 5G smart gateway is characterized in that One RGMII interface is connected to the Ethernet PHY chip, and then converted to multiple network ports through the Switch chip. The RTL8211FS-CG chip is selected as the Ethernet PHY chip, and the RTL8370MB-CG chip is selected as the Switch chip. The CPU processor is connected to the RTL8211FS-CG chip through the RGMII interface to convert to an optical port, and is connected to the RTL8370MB-CG chip through the optical port to convert to a multi-network port. The RTL8370MB-CG chip provides a 25M external crystal oscillator and reset signal, and obtains external 3.3V and 1.1V power supply.

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