Chip insulation defect detection device and method during chip aging test

Abstract

The present invention discloses a chip insulation defect detection device and method in a chip aging test process, which includes: a detection power supply; a conductive unit; a head end wire, a tail end wire, and a plurality of intermediate wires; a voltage sampling unit, which is respectively connected to the conductive unit, and is used to obtain the corresponding current voltage analog signal generated by the current flowing through each wire to the conductive unit, and convert the current voltage analog signal into a current voltage digital signal; and a host computer, which is used to determine whether a chip and the conductive unit are short-circuited according to the mapping relationship between all current voltage digital signals and the number of sampled voltage chips, and determine the number of the chip that is short-circuited. The present invention is based on a pre-constructed mapping relationship between sampled voltage and the number of chips. By comparing the current voltage digital signal obtained by automatic detection with the mapping relationship, it is possible to quickly determine whether a chip has an insulation defect and the position of the chip that is short-circuited.

Description

Technical Field

[0001] The present invention relates to the technical field of chip quality detection, and in particular to a device and method for detecting chip insulation defects in a chip aging test process. Background Art

[0002] In the aging process of chips (such as high-power infrared laser chips), power needs to be supplied to the positive and negative electrodes of the chip. Before power supply, it is necessary to determine whether the positive and negative electrodes of each chip are short-circuited to the aging test platform, and record information such as the chip number, detection time, and insulation resistance data. Based on the insulation resistance information, it is determined whether the chip is short-circuited to the aging test platform. This process is currently completed manually.

[0003] However, based on different chip quality requirements, the aging time of different chips (ranging from 8 hours to several months) is different. If the aging time is long (for example, 1 month or several months), it is necessary to frequently and regularly check the insulation resistance of the chip to determine whether there is a short circuit and repeat the measurement and recording of the insulation resistance. If this work is entirely done manually, there are the following defects: The above-mentioned insulation resistance detection and recording have a long time period and high repeatability, which leads to the chip number, insulation resistance detection time, insulation resistance and other information being easily misplaced when personnel perform detection and data recording in different time periods. If some of the information is found to be missed after the detection is completed, the detection time window has been missed and cannot be re-measured. Summary of the invention

[0004] In view of the shortcomings of the prior art, the present invention provides a chip insulation defect detection device and method during the chip aging test process. The device and method are based on a pre-constructed mapping relationship between the sampling voltage and the number of chips. By comparing the current voltage digital signal obtained by automatic detection with the mapping relationship, it can quickly determine whether there is an insulation defect in the chip and the location of the chip where a short circuit occurs.

[0005] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0006] On the one hand, a chip insulation defect detection device in a chip aging test process is provided, which includes:

[0007] The detection power supply has a positive power supply V+ and a negative power supply V-, and the positive power supply V+ is connected to n chips D connected in series in sequence. 1 , D 2 ,...,D n In the first chip D 1 Each chip has a unique number corresponding to it;

[0008] Conductive unit;

[0009] The first end of the wire has one end connected to n chips D connected in series. 1 , D 2 ,...,D n In the embodiment, the positive electrode of the first chip D1 has its other end connected to the conductive unit;

[0010] The tail wire has one end connected to n chips D connected in series. 1 , D 2 ,...,D n In the nth chip D n The negative electrode of the conductive unit is connected to the other end;

[0011] Several intermediate wires, and one end of each intermediate wire is connected to chip D at the same time n-1 The negative electrode and chip D n The positive electrode of the conductive unit is connected to the other end;

[0012] A voltage sampling unit, which is respectively connected to the conductive unit and the negative electrode V- of the power supply, and is used to obtain a corresponding current voltage analog signal generated by the current flowing through each wire to the conductive unit, and convert each current voltage analog signal into a corresponding current voltage digital signal;

[0013] and a host computer connected to the voltage sampling unit, for determining whether a chip is short-circuited with the conductive unit and determining the chip number of the short-circuited chip according to all current voltage digital signals and the mapping relationship between the sampled voltage and the number of chips.

[0014] Preferably, the conductive unit is made of a conductive metal material, and has a contact resistance less than 1Ω.

[0015] Preferably, the voltage sampling unit includes: a sampling resistor, which is simultaneously connected to the conductive unit and the negative electrode V- of the power supply, and is used to obtain a current voltage analog signal generated by the current flowing to the conductive unit through different wires; and a signal conversion unit, which is used to convert each current voltage analog signal into a corresponding current voltage digital signal.

[0016] Preferably, each current voltage analog signal is subjected to signal amplification and filtering before being converted by the signal conversion unit.

[0017] Preferably, the mapping relationship between the sampled voltage and the number of chips includes a first mapping relationship when all chips are not short-circuited with the conductive unit and a second mapping relationship when at least one chip is short-circuited with the conductive unit.

[0018] Preferably, the first mapping relationship and / or the second mapping relationship is constructed in advance, which includes the following steps:

[0019] According to formula (1), the corresponding voltage value Vdsp generated by the current output by the detection power supply after flowing through different numbers of chips connected in series is obtained:

[0020] (1);

[0021] Wherein, V1 is the supply voltage of the detection power supply; n x is the number of chips through which the current output by the power supply flows; VD is the voltage drop generated when the current flows through each chip; R s is the resistance value of the sampling resistor; R a K is the chip insulation resistance; a is the signal amplification factor;

[0022] All the voltage values ​​Vdsp obtained and the number of chips n through which the current output by the detection power supply flows x Fitting is performed to obtain a linear function curve.

[0023] Preferably, when only one chip has an insulation performance defect, the insulation resistance value of the chip with the insulation performance defect is used as the chip insulation resistance; when multiple chips have insulation performance defects, the insulation resistance values ​​of all chips with insulation performance defects are calculated in parallel, and the result of the parallel calculation is used as the chip insulation resistance.

[0024] Preferably, determining whether a chip is short-circuited with a conductive unit and determining the chip number of the short-circuited chip according to all current voltage digital signals and the mapping relationship between the sampled voltage and the number of chips includes the following:

[0025] If all current voltage digital signals are within the voltage value range corresponding to the first mapping relationship, it is considered that the insulation performance of all chips meets the requirements and no short circuit occurs.

[0026] Preferably, determining whether a chip is short-circuited with a conductive unit and determining the chip number of the short-circuited chip according to all current voltage digital signals and the mapping relationship between the sampled voltage and the number of chips includes the following:

[0027] If at least one current voltage digital signal is not within the voltage value range corresponding to the first mapping relationship, the current voltage digital signal is compared with the voltage value corresponding to the second mapping relationship, and n is determined according to the comparison result. x The value of x The value of determines the chip number where the short circuit occurs.

[0028] On the other hand, a chip insulation defect detection method implemented by the above insulation defect detection device is also provided, which comprises the following steps:

[0029] Set the insulation detection time through the host computer;

[0030] When the insulation monitoring time is reached, the host computer automatically controls the switch to close, so as to supply power to the n chips D connected in series in sequence through the detection power supply. 1 , D 2 ,...,D n powered by;

[0031] Automatically acquire each current voltage analog signal generated by the current flowing through different wires to the conductive unit through the voltage sampling unit, and automatically convert each current voltage analog signal into a corresponding current voltage digital signal;

[0032] The host computer receives all current voltage digital signals, and automatically outputs the detection results according to the mapping relationship between all current voltage digital signals and the sampling voltage-chip quantity, and saves the detection results, which include: whether there is a short circuit between a chip and a conductive unit, and the chip number that determines the short circuit.

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] The present invention can be based on a pre-constructed mapping relationship between sampling voltage and chip quantity. By comparing the current voltage digital signal obtained by automatic detection with the mapping relationship, it can quickly determine whether there is an insulation defect in the chip and the location of the chip where a short circuit occurs. At the same time, the detection results can be automatically output to facilitate automated management, while saving a lot of time costs for manual sorting of tables, and greatly reducing the occurrence of data omissions and errors caused by manual data recording, thereby improving the efficiency of chip aging detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is the overall structure diagram of the chip insulation defect detection device in the present invention;

[0036] Figure 2 The linear function curve obtained by fitting when the insulation performance of all chips in series is good;

[0037] Figure 3 Among all the chips in series, only one chip has insulation performance defects (take R a =1000Ω), the linear function curve obtained by fitting;

[0038] Figure 4 Among all the chips in series, only one chip has insulation performance defects (take R a =50Ω), the linear function curve obtained by fitting;

[0039] Figure 5Among all the chips in series, multiple chips have insulation defects (take R a =500Ω), the linear function curve obtained by fitting. DETAILED DESCRIPTION

[0040] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] Embodiment 1:

[0042] like Figure 1 As shown, this embodiment provides a chip insulation defect detection device in a chip aging test process, which includes:

[0043] The detection power supply 1 has a positive power supply V+ and a negative power supply V-, and the positive power supply V+ is connected to n chips D1, D2, ..., D n , the positive electrode of the first chip D1, the chip may be a laser chip, and each chip has a unique number corresponding to it, and has a PN junction, so each chip can be equivalent to a diode, and when current flows through each chip, a voltage drop will be generated, and n is a positive integer greater than or equal to 2;

[0044] Conductive unit 2, in this embodiment, the conductive unit 2 is made of conductive metal materials such as iron, and the contact resistance is less than 1Ω;

[0045] The first end wire 3 has one end connected to n chips D connected in series. 1 , D 2 ,...,D n In the first chip D 1 The positive electrode of the conductive unit 2 is connected to the other end;

[0046] The tail wire 4 has one end connected to n chips D connected in series. 1 , D 2 ,...,D n In the nth chip D n The negative electrode of the conductive unit 2 is connected to the other end;

[0047] A plurality of intermediate wires 5, and one end of each intermediate wire 5 is simultaneously connected to the chip D n-1 The negative electrode and chip D n The positive electrode of the chip D n-1 、Chip Dn are two adjacent chips among the n chips connected in series;

[0048] The voltage sampling unit 6 is connected to the conductive unit 2 and the negative electrode V- of the power supply, and is used to obtain the current voltage analog signal corresponding to the current flowing through each wire to the conductive unit 2 (that is, after the current flows through a certain wire to the conductive unit 2, a current voltage analog signal corresponding to the wire will be generated. For example, after the current flows directly to the conductive unit 2 through the head end wire 3, a current voltage analog signal will be generated. The current passes through the chip D 1 Afterwards, through chip D 1 , D 2 After the intermediate wire 5 between the conductive units 2 flows to the conductive unit 2, a current voltage analog signal will also be generated, and so on), and each current voltage analog signal is converted into a corresponding current voltage digital signal; specifically, the voltage sampling unit 6 includes: a sampling resistor 61, which is simultaneously connected to the conductive unit 2 and the negative electrode V- of the power supply, and is used to obtain the current voltage analog signal generated by the current flowing to the conductive unit 2 through different wires; and a signal conversion unit 62, which is used to convert each current voltage analog signal into a corresponding current voltage digital signal; preferably, each current voltage analog signal is subjected to signal amplification and filtering before being converted by the signal conversion unit 62;

[0049] And a host computer 7, which is connected to the signal conversion unit 62 of the voltage sampling unit 6, is used to determine whether there is a short circuit between the chip and the conductive unit 2 (that is, whether the chip has an insulation performance defect) according to all current voltage digital signals and the mapping relationship between the sampled voltage and the number of chips, and determine the chip number that has a short circuit.

[0050] Furthermore, the mapping relationship between the sampled voltage and the number of chips includes a first mapping relationship when all chips are not short-circuited with the conductive unit 2 and a second mapping relationship when at least one chip is short-circuited with the conductive unit 2 .

[0051] Specifically, the first mapping relationship and / or the second mapping relationship may be constructed in advance (in this embodiment, the construction steps of the first mapping relationship and the second mapping relationship are the same), which includes the following steps:

[0052] Building the above insulation defect detection device;

[0053] According to formula (1), the corresponding voltage value Vdsp generated by the current output by the detection power supply 1 flowing through different numbers of chips connected in series is obtained:

[0054] (1);

[0055] Wherein, V1 is the supply voltage of detection power supply 1; n x To detect the number of chips through which the current output by power supply 1 flows, n x is a positive integer greater than or equal to 0 and less than or equal to n; VD is the voltage drop generated when current flows through each chip; R s is the resistance value of the sampling resistor 61; R a K is the chip insulation resistance obtained in real time; a is the signal amplification factor, and its value range is (0, 0.5];

[0056] Based on the number of chips n through which the current output by the detection power supply 1 flows x And the voltage value Vdsp is fitted to obtain a mapping relationship between the sampling voltage and the number of chips, and the mapping relationship can be a linear function; specifically, when the chips of different numbers connected in series are not short-circuited with the conductive unit 2, the obtained mapping relationship is the first mapping relationship, and when at least one chip among the chips of different numbers connected in series is short-circuited with the conductive unit 2, the obtained mapping relationship is the second mapping relationship.

[0057] like Figure 1 As shown, the current output by the detection power supply 1 starts from the positive electrode V+ of the power supply, flows through each chip in series in sequence, and flows to the conductive unit 2 through each wire (including the head wire 3, the tail wire 4 and each intermediate wire 5). The sampling module 61 thus collects the corresponding voltage analog signals generated when the current passes through different numbers of chips and the corresponding wires to flow to the conductive unit 2, and further converts all voltage analog signals into corresponding voltage digital signals through the signal conversion unit 62, which is the voltage value Vdsp.

[0058] like Figure 2 As shown, when the insulation performance of all the chips connected in series is good, they will not leak electricity to the conductive unit 2 obviously. When the current output by the detection power supply 1 flows through each chip in turn, each voltage drop VD generated is basically the same, and the insulation resistance corresponding to each chip meets the requirements, such as being greater than or equal to 10MΩ;

[0059] For example, when n=24, the supply voltage V1=30V, the voltage drop VD generated when the current flows through each chip is the same, and the insulation resistance corresponding to each chip is the same (in this case, the chip insulation resistance R a =10MΩ), and VD=1.2V, K a =0.1 and the resistance value of the sampling resistor 61 is R s =100kΩ, according to formula (1), the current flowing through the different numbers (i.e., n x After the chip is connected to the chip with different values, the corresponding voltage Vdsp generated is, specifically, when nx =0, the current has not flowed through any chip, and no voltage drop VD is generated. At the same time, part of the current flows through the head-end wire 3 to the conductive unit 2. The voltage value Vdsp calculated according to formula (1) is 0.03V. When n x =1, the current only flows through chip D1, which generates a voltage drop VD. At the same time, part of the current flows to the conductive unit 2 through the intermediate wire 5 between chip D1 and chip D2. The calculated voltage value Vdsp=0.029V. Similarly, when n x =24, the current flows through chip D1 to chip D24, and 24 voltage drops VD are generated. At the same time, part of the current flows to the conductive unit 2 through the tail wire 4, and the calculated voltage value Vdsp=0.001V;

[0060] Furthermore, all the voltage values ​​Vdsp and the number of chips n are obtained. x Fitting is performed to obtain Figure 2 The linear function curve (i.e. the first mapping relationship) shown.

[0061] When only one chip (for example, the first chip D1) has insulation defects, it will obviously leak electricity to the conductive unit 2, and the corresponding insulation resistance will be greatly reduced, such as the insulation resistance is reduced to 0-1000Ω, and the insulation performance of other chips is normal, and the insulation resistance is maintained at or greater than 10MΩ;

[0062] At this time, the insulation resistance value of the chip with insulation performance defects can be used as the chip insulation resistance. Assuming R a =1000Ω, other calculated parameters, including n, n x 、V1、VD、R s , K a The above contents are the same, and the corresponding voltage value Vdsp is calculated according to formula (1) and fitted to obtain Figure 3 The linear function curve (i.e., the second mapping relationship) shown.

[0063] Similarly, when only one chip (for example, the first chip D1) has insulation defects, if R a =50Ω, other calculation parameters are the same, and the corresponding voltage value Vdsp is calculated according to formula (1), and the corresponding fitting is obtained Figure 4 The linear function curve (i.e., the second mapping relationship) shown.

[0064] When multiple chips have insulation defects, the corresponding insulation resistance will be greatly reduced. For example, the insulation resistance of a single chip will be reduced to 0-1000Ω, while the insulation performance of other chips is normal, and the insulation resistance remains greater than or equal to 10MΩ;

[0065] At this time, the insulation resistance values ​​of all chips with insulation performance defects can be calculated in parallel, and the result of the parallel calculation (the parallel calculation result is also within 1000Ω) is used as the chip insulation resistance. Assuming that the resistance value obtained by parallel calculation is 500Ω, then R a =500Ω, other calculated parameters, including n, n x 、V1、VD、R s , K a The above contents are the same, and the corresponding voltage value Vdsp is calculated according to formula (1) and fitted to obtain Figure 5 The linear function curve (i.e., the second mapping relationship) shown.

[0066] from Figure 3-5 It can be seen that when the chip insulation resistance R a When the value range of is 0~1000Ω, the mapping relationship between the sampling voltage and the number of chips obtained by fitting has basically the same change trend. When the current flows through two adjacent chips, the difference in the voltage value Vdsp generated is stable at 0.118V-0.120V. This shows that in this embodiment, after the chip is connected to the conductive unit 2 through different wires, the voltage sampling unit 6 can accurately detect the corresponding voltage value with high detection accuracy, so that the constructed mapping relationship is more accurate.

[0067] Further, determining whether a chip is short-circuited with the conductive unit 2 and the chip number that is short-circuited according to all current voltage digital signals and the mapping relationship between the sampled voltage and the number of chips includes the following:

[0068] If all current voltage digital signals are within the voltage value range corresponding to the first mapping relationship, such as within the above R a =10MΩ, when the voltage value of the linear function obtained is within the range of Vdsp (i.e., within 0-30mV), it is considered that the insulation performance of all chips meets the requirements and no short circuit occurs;

[0069] If at least one current voltage digital signal is not within the voltage value range corresponding to the first mapping relationship, the current voltage digital signal is compared with the voltage value corresponding to the second mapping relationship, and n is determined according to the comparison result. x The value of n x The value of determines the chip number where the short circuit occurs. For example, if the two current voltage digital signals are 2.4V and 0.5V respectively, Figure 5 It can be seen that the corresponding n x The values ​​are 5 and 20, which means that the chips numbered 5 and 20 are short-circuited.

[0070] Therefore, the insulation defect detection device in this embodiment has a simple structure and is easy to operate. It can be based on the pre-constructed mapping relationship between the sampling voltage and the number of chips. By comparing the current voltage digital signal obtained by automatic detection with the mapping relationship, it can quickly determine whether there is an insulation defect in the chip and the location of the chip where the short circuit occurs, so as to facilitate automated management. At the same time, it saves a lot of time cost for manual sorting of tables, and greatly reduces the occurrence of data omissions and errors caused by manual data recording, thereby improving the efficiency of chip aging detection.

[0071] Embodiment 2:

[0072] This embodiment provides a chip insulation defect detection method implemented by the chip insulation defect detection device described in Embodiment 1, which includes the following steps:

[0073] S1. Setting the insulation detection time through the host computer 7, such as 8:00, 12:00, 16:00, and 20:00 every Monday are all insulation detection times;

[0074] S2. When the insulation monitoring time is reached, the host computer 7 automatically controls the switch K1 to close, so as to detect the power supply 1 to the n chips D connected in series in sequence. 1 , D 2 ,...,D n powered by;

[0075] S3, automatically acquiring each current voltage analog signal generated by the current flowing through different wires to the conductive unit 2 through the voltage sampling unit 6, and automatically converting each current voltage analog signal into a corresponding current voltage digital signal;

[0076] S4, the host computer 7 receives all current voltage digital signals, and automatically outputs the detection result according to the mapping relationship between all current voltage digital signals and the sampling voltage-chip number, and saves the detection result, the detection result includes: whether there is a short circuit between the chip and the conductive unit 2, and the chip number of the short circuit; wherein the mapping relationship can be pre-stored in the host computer 7, and the process of obtaining the detection result is the same as the content of "determining whether there is a short circuit between the chip and the conductive unit 2, and determining the chip number of the short circuit according to the mapping relationship between all current voltage digital signals and the sampling voltage-chip number" in Example 1, and at the same time, the judgment result can be output in the form of text documents such as txt, word, and excel;

[0077] S5, the upper computer 7 automatically controls the switch K1 to be disconnected, and the detection power supply 1 stops supplying power.

[0078] In summary, it can be seen that the insulation defect detection device in the present invention has a simple structure, is easy to operate, and can record data reliably. After the detection time is set by the host computer, detection can be performed at any time within 24 hours a day. It can be based on the pre-constructed mapping relationship between the sampling voltage and the number of chips. By comparing the current voltage digital signal obtained by automatic detection with the mapping relationship, it can quickly determine whether there is an insulation defect in any chip and the location of the chip where a short circuit occurs. At the same time, the detection results can be automatically output to facilitate automated management, while saving a lot of time costs for manual sorting of tables, and greatly reducing the occurrence of data omissions and incorrect filling due to manual data recording, thereby improving the efficiency of chip aging detection.

[0079] It should be noted that the technical features in the above-mentioned embodiments 1 to 3 can be combined arbitrarily, and the combined technical solutions all belong to the protection scope of the present application. And in this article, terms such as "including", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of further restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.

[0080] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A chip insulation defect detection device in a chip aging test process, characterized in that: include: The detection power supply has a positive power supply V+ and a negative power supply V-, and the positive power supply V+ is connected to n chips D1, D2, ..., D n In the figure, the positive terminal of the first chip D1, each chip has a unique corresponding number; Conductive unit; The first end of the wire has one end connected to n chips D1, D2, ..., D n In the embodiment, the positive electrode of the first chip D1 has its other end connected to the conductive unit; The tail wire has one end connected to n chips D1, D2, ..., D in series. n In the nth chip D n The negative electrode of the conductive unit is connected to the other end; A plurality of intermediate wires, wherein between each two adjacent chips, one end of an intermediate wire is connected to the negative electrode of the previous chip and the positive electrode of the next chip at the same time, and the other end is connected to the conductive unit; A voltage sampling unit, which is respectively connected to the conductive unit and the negative electrode V- of the power supply, and is used to obtain a corresponding current voltage analog signal generated by the current flowing through each wire to the conductive unit, and convert each current voltage analog signal into a corresponding current voltage digital signal; and a host computer connected to the voltage sampling unit, for determining whether a chip is short-circuited with the conductive unit and determining the chip number of the short-circuited chip according to all current voltage digital signals and the mapping relationship between the sampled voltage and the number of chips.

2. The chip insulation defect detection device according to claim 1, characterized in that: The conductive unit is made of a conductive metal material, and has a contact resistance less than 1Ω.

3. The chip insulation defect detection device according to claim 1, characterized in that: The voltage sampling unit includes: a sampling resistor, which is simultaneously connected to the conductive unit and the negative electrode V- of the power supply, and is used to obtain a current voltage analog signal generated by the current flowing to the conductive unit through different wires; and a signal conversion unit, which is used to convert each current voltage analog signal into a corresponding current voltage digital signal.

4. The chip insulation defect detection device according to claim 3, characterized in that: Each current voltage analog signal undergoes signal amplification and filtering before being converted by the signal conversion unit.

5. The chip insulation defect detection device according to claim 3, characterized in that: The mapping relationship between the sampling voltage and the number of chips includes a first mapping relationship when all chips are not short-circuited with the conductive unit and a second mapping relationship when at least one chip is short-circuited with the conductive unit.

6. The chip insulation defect detection device according to claim 5, characterized in that: The first mapping relationship and / or the second mapping relationship is constructed in advance, which includes the following steps: According to formula (1), the corresponding voltage value Vdsp generated by the current output by the detection power supply after flowing through different numbers of chips connected in series is obtained: （1）； Wherein, V1 is the supply voltage of the detection power supply; n x is the number of chips through which the current output by the power supply flows; VD is the voltage drop generated when the current flows through each chip; R s is the resistance value of the sampling resistor; R a K is the chip insulation resistance; a is the signal amplification factor; All the voltage values ​​Vdsp obtained and the number of chips n through which the current output by the detection power supply flows x Fitting is performed to obtain a linear function curve.

7. The chip insulation defect detection device according to claim 6, characterized in that: When only one chip has an insulation performance defect, the insulation resistance value of the chip with the insulation performance defect is used as the chip insulation resistance; when multiple chips have insulation performance defects, the insulation resistance values ​​of all chips with insulation performance defects are calculated in parallel, and the result of the parallel calculation is used as the chip insulation resistance.

8. The chip insulation defect detection device according to claim 5, characterized in that: According to all current voltage digital signals and the mapping relationship between the sampled voltage and the number of chips, it is determined whether a chip is short-circuited with the conductive unit, and the chip number of the short-circuited chip is determined, including the following contents: If all current voltage digital signals are within the voltage value range corresponding to the first mapping relationship, it is considered that the insulation performance of all chips meets the requirements and no short circuit occurs.

9. The chip insulation defect detection device according to claim 5, characterized in that: According to all current voltage digital signals and the mapping relationship between the sampled voltage and the number of chips, it is determined whether a chip is short-circuited with the conductive unit, and the chip number of the short-circuited chip is determined, including the following contents: If at least one current voltage digital signal is not within the voltage value range corresponding to the first mapping relationship, the current voltage digital signal is compared with the voltage value corresponding to the second mapping relationship, and n is determined according to the comparison result. x The value of x The value of determines the chip number where the short circuit occurs.

10. A chip insulation defect detection method implemented by the insulation defect detection device according to any one of claims 1 to 9, characterized in that: The steps include: Set the insulation detection time through the host computer; When the insulation monitoring time is reached, the host computer automatically controls the switch to close, so as to supply the n chips D1, D2, ..., D1 connected in series in sequence through the detection power supply. n powered by; Automatically acquire each current voltage analog signal generated by the current flowing through different wires to the conductive unit through the voltage sampling unit, and automatically convert each current voltage analog signal into a corresponding current voltage digital signal; The host computer receives all current voltage digital signals, and automatically outputs the detection results according to the mapping relationship between all current voltage digital signals and the sampling voltage-chip quantity, and saves the detection results, which include: whether there is a short circuit between a chip and a conductive unit, and the chip number that determines the short circuit.

Images