Device failure test method and test device, electronic equipment and storage medium
By performing failure tests on standard devices and the device under test in multiple states, comparing the standard curve group and the test curve group, the problem of inability to accurately locate the device failure point in the prior art is solved, and an accurate analysis of the failure position and mode of the device is achieved.
Patent Information
- Application Number
- CN202411610482.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-12
- Publication Date
- 2025-03-07
AI Technical Summary
In the prior art, plate electrode failure analysis cannot accurately determine the location of the failure point, and the dewelding test may damage the welding joints, resulting in the inability to distinguish between the original welding problem and the failure during the test.
By determining the various states of the standard device and the device under test, failure test is performed, the standard curve group and the test curve group are obtained, and the two are compared to determine the failure position and mode of the device.
The device failure position and mode are accurately positioned, avoiding the problem of damage to solder joints due to de-welding tests, and can more accurately analyze the device failure state.
Smart Images
Figure CN119575125A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of device testing technology, and in particular to a device failure testing method, a testing device, an electronic device and a storage medium. Background Art
[0002] In the prior art, there are multiple board tests. Due to the development of high-density packaged devices such as BGA (Ball Grid Array), the density of device solder joints is high and invisible from the outside. Testers locate the approximate location of the failure based on the on-board test results and directly desolder the device, which will damage the solder joints and the original failure state. They can only infer that the failure may be caused by the solder joints based on the qualified functional test of the desoldered device, and cannot further locate whether it is the original welding problem or the failure caused during the test process; or remelting is performed to eliminate the problem of cold soldering, which not only cannot detect solder joint defects, but also has a high density of solder joints. After remelting, it may cause failure again such as overlapping short circuits, and also destroys the original failure state. Summary of the invention
[0003] In view of this, the purpose of the present application is to propose a device failure test method, a test apparatus, an electronic device and a storage medium to solve the problem that the existing plate failure analysis cannot accurately determine the failure point location.
[0004] Based on the above purpose, the present application provides a device failure testing method, comprising:
[0005] Determine various states of standard devices;
[0006] According to preset test points, failure tests are performed on various states of the standard device to obtain a standard curve group;
[0007] Determine various states of the device under test;
[0008] According to the preset test points, failure tests are performed on various states of the device under test to obtain a test curve group;
[0009] The curves in the standard curve group and the test curve group are compared to determine the failure position and failure mode of the device under test.
[0010] Optionally, multiple states of standard devices are determined, including:
[0011] In response to the standard device retaining the substrate and being connected to the IC, determining that the standard device is in a complete standard device state;
[0012] In response to the standard device not retaining the substrate and not being connected to the IC, determining that the standard device is in a disassembled standard device state;
[0013] In response to the standard device having the substrate left and not connected to the IC, it is determined that the standard device is in the on-board standard device state.
[0014] Optionally, the standard curve group includes a standard curve of a complete standard device state, a standard curve of a disassembled standard device state, and a standard curve of an on-board standard device state;
[0015] The method of performing failure tests on various states of the standard device according to preset test points to obtain a standard curve includes:
[0016] According to the preset test points, a failure test is performed on the standard device in the complete standard device state to obtain a standard curve of the complete standard device state;
[0017] According to the preset test points, a failure test is performed on the standard device in the disassembled device state to obtain a standard curve of the disassembled standard device state;
[0018] According to the preset test points, a failure test is performed on the standard device in the on-board standard device state to obtain a standard curve of the on-board standard device state.
[0019] Optionally, determine multiple states of the device under test, including:
[0020] In response to the device under test retaining the substrate and being connected to the IC, determining that the device under test is in a complete device under test state;
[0021] In response to the device under test not retaining the substrate and not being connected to the IC, determining that the device under test is in a disassembled device under test state;
[0022] In response to the device under test having the substrate left and not connected to the IC, it is determined that the device under test is in the on-board device under test state.
[0023] Optionally, the test curve group includes a test curve of a complete device under test state, a test curve of a disassembled device under test state, and a test curve of an on-board device under test state;
[0024] The method of performing failure tests on various states of the device under test according to the preset test points to obtain a test curve group includes:
[0025] According to the preset test points, a failure test is performed on the device under test in the complete device under test state to obtain a test curve of the complete device under test state;
[0026] According to the preset test points, a failure test is performed on the device under test in the disassembled device state to obtain a test curve of the disassembled standard component state;
[0027] According to the preset test points, a failure test is performed on the device under test in the on-board device under test state to obtain a test curve of the on-board device under test state.
[0028] Optionally, the failure location includes the device itself, the substrate or the solder joint;
[0029] The step of comparing the standard curve group with the curves in the test curve group to determine the failure position of the device under test includes:
[0030] In response to the waveform amplitudes of the standard curve of the disassembled standard device state and the test curve of the disassembled device under test state being greater than a preset threshold, determining that the failure position of the device under test is the device itself;
[0031] In response to the waveform amplitudes of the standard curve of the on-board standard device state and the test curve of the on-board tested device state being greater than a preset threshold, determining that the failure position during the tested period is the substrate;
[0032] In response to the waveform amplitudes of the standard curve of the complete standard test device state and the test curve of the complete device under test state being greater than a preset threshold, it is determined that the failure position of the device under test is a solder joint.
[0033] Optionally, the failure mode includes: an open circuit failure mode and a short circuit failure mode;
[0034] Comparing the standard curve group with the curves in the test curve group to determine the failure mode of the device under test, including:
[0035] In response to the waveform amplitudes of the standard curve of the complete standard test device state and the test curve of the complete device under test state being greater than a preset threshold, the waveform amplitudes of the standard curve of the disassembled standard device state and the test curve of the disassembled device under test state being greater than a preset threshold, and the waveform amplitudes of the standard curve of the on-board standard device state and the test curve of the on-board device under test state being greater than a preset threshold, determining that the failure mode of the device under test is a short-circuit failure mode;
[0036] In response to the fact that the waveform amplitudes of the standard curve of the complete standard test device state and the test curve of the complete device under test state are greater than a preset threshold, the waveform amplitudes of the standard curve of the disassembled standard device state and the test curve of the disassembled device under test state are greater than a preset threshold, or the waveform amplitudes of the standard curve of the on-board standard device state and the test curve of the on-board device under test state are greater than a preset threshold, it is determined that the failure mode during the test is an open circuit failure mode.
[0037] Based on the same inventive concept, the present application also provides a device failure test device, comprising:
[0038] A first determination module is configured to determine multiple states of a standard device;
[0039] A first test module is configured to perform failure tests on multiple states of the standard device according to preset test points to obtain a standard curve group;
[0040] A second determination module is configured to determine multiple states of the device under test;
[0041] A second test module is configured to perform failure tests on multiple states of the device under test according to the preset test points to obtain a test curve group;
[0042] The third determination module is configured to compare the curves in the standard curve group and the test curve group to determine the failure position and failure mode of the device under test.
[0043] Based on the same inventive concept, the present application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements any of the above-described methods when executing the program.
[0044] Based on the same inventive concept, the present application also provides a non-transitory computer-readable storage medium, which stores computer instructions, and the computer instructions are used to enable a computer to execute any of the methods described above.
[0045] As can be seen from the above, the present application provides a device failure test method, test device, electronic device and storage medium, the test method includes: determining multiple states of a standard device; performing failure tests on multiple states of the standard device according to preset test points to obtain a standard curve group; determining multiple states of the device under test; performing failure tests on multiple states of the device under test according to the preset test points to obtain a test curve group; comparing the standard curve group with the curves in the test curve group to determine the failure position and failure mode of the device under test. By first determining multiple states of the standard device, performing failure tests on multiple states of the standard device according to preset test points to obtain a standard curve group, that is, obtaining the TDR curves of the non-failed device under multiple states. After determining multiple states of the device under test, performing failure tests on multiple states of the device under test according to preset test points to obtain a test curve group, that is, obtaining the TDR curves of the failed device under multiple states. By comparing the TDR curves of the non-failed device in various states with the TDR curves of the failed device in various states, the waveform change of the TDR curve can be determined, and then it can be determined in which state the tested device is abnormal, and the failure point location and failure mode can be accurately determined. The problem of desoldering the device, damaging the solder joints, and destroying the original failure state is avoided. BRIEF DESCRIPTION OF THE DRAWINGS
[0046] In order to more clearly illustrate the technical solutions in the present application or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0047] Figure 1 A schematic diagram of a device failure testing method flow chart of an embodiment of the present application;
[0048] Figure 2 A schematic diagram of a cross-sectional structure of a device according to an embodiment of the present application;
[0049] Figure 3 A schematic diagram of the framework structure of a device failure testing device according to an embodiment of the present application;
[0050] Figure 4 A schematic diagram of the hardware structure of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION
[0051] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.
[0052] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be the usual meanings understood by people with ordinary skills in the field to which the present application belongs. The "first", "second" and similar words used in the embodiments of the present application do not represent any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0053] With the widespread application of large-scale integrated circuits, various chip packaging forms have emerged to meet different needs, and typical packages include DIP, SOP, QFP, etc. As the scale of integrated circuits continues to expand, the package size is required to be smaller and thinner, and high-density packages such as BGA and flip-chip soldering have emerged. Its high-density I / O pin distribution and complex internal structure and manufacturing process make it easy to cause chip failure during the production and manufacturing of integrated circuits, and also bring great difficulties to IC testing and failure analysis.
[0054] High-density packaging is a requirement for high-performance integrated circuits and systems. As the integration of devices becomes higher and higher, the number of package pins required is increasing, and the spacing between pins is getting smaller and smaller, which makes packaging more difficult and reliability issues more prominent. High-density ceramic flip-chip packaging is a development direction. In the flip-chip structure, the electrical connection path between the chip and the substrate is realized by the metal bumps on the chip. The chip working surface faces down, the bump size is about 100μm, and it is assembled on the substrate by reflow soldering and other methods. At the same time, there is a protective filler (usually epoxy resin) in the gap between the chip surface and the substrate. Due to the special structure of the flip-chip package, the failure analysis and positioning of the flip-chip package is more difficult than the traditional packaging form.
[0055] In electronic packaging, solder joints provide electrical connections between chips and packages, between different packages, between devices and printed circuit boards, etc., and provide mechanical support for various connected devices. Solder joints in electronic packaging play multiple roles such as mechanical connection, electrical connection and thermal connection. As electronic products and devices are increasingly miniaturized, lightweight and high-performance, the size of solder joints is getting smaller and smaller, and the number is increasing. The realization of electronic product functions depends on these tiny and huge number of solder joints to provide reliable connections. It can be said that solder joints run through the entire life cycle of electronic products and experience many different application environments. The reliability of solder joints directly affects the stability and reliability of the entire electronic product.
[0056] From the perspective of the board level, the device is soldered to the PCB board through solder joints, and the metal layers of the PCB board are connected to the vias through holes. The intermittent on and off phenomenon at the board level is mostly caused by connection problems. External connection problems mainly include PCB via problems, PCB printed line problems, and solder joint damage and failure. In most cases, board testing can only narrow the failure location to a certain range based on test data, and locate certain devices that may have failure phenomena. Since the board level is intermittent, it means that the chip itself has no abnormal function, but it cannot be ruled out whether there is an abnormality in the connection between the chip and the shell, such as the bonding point or the bump of the flip-chip soldering; or under environmental testing, the solder joints may be damaged and failed due to the mismatch of the thermal expansion coefficients of the solder joints, shells, and PCB boards; there may also be problems with the vias or printed lines of the PCB board.
[0057] For board-level failure analysis, it currently mainly relies on the test results of testers. First, preliminary device positioning is carried out to check whether it is a device problem, a solder joint problem or a PCB board problem, and then non-destructive testing is carried out. Since the solder joints are invisible from the outside, the internal solder joints can only be observed with the help of X-ray detectors to perform internal device inspections. However, due to the limited accuracy of the equipment, micro cracks at the μm level cannot be detected, and board-level X-ray inspections will also be blocked by other devices, affecting the judgment of the failure point.
[0058] In order to solve the above technical problems, refer to Figure 1 , the present application provides a device failure testing method, comprising the following steps:
[0059] Step 102: Determine multiple states of the standard device.
[0060] In this step, the test personnel disassemble the standard device to determine the various states of the standard device, and then the various states of the standard device can be tested for failure, which is more helpful to accurately determine the location of the failure point of the device. Exemplarily, the chip welded on the substrate is disassembled into multiple states. For example, the chip is welded on the substrate, but the chip is disconnected from the IC (Integrated Circuit), which is regarded as the on-board standard device state. The chip is disassembled on the substrate, which is regarded as the disassembled standard device state. The standard device is regarded as a complete standard device if it has not been disassembled.
[0061] Step 104: Perform failure tests on various states of the standard device according to preset test points to obtain a standard curve group.
[0062] In this step, the preset test points are test points determined by the tester according to the test requirements, for example, the first pin and the fifth pin of a chip are tested. The first pin and the fifth pin of the standard device are tested for failure under different states of the standard device to obtain a standard curve group under different states of the standard device.
[0063] Step 106: Determine multiple states of the device under test.
[0064] In this step, the tester disassembles the device under test, and exemplarily disassembles the chip soldered on the substrate into various states: for example, the chip is soldered on the substrate, but the chip is disconnected from the IC, which is considered as the state of the device under test on the board. The chip is disassembled on the substrate, which is considered as the state of the device under test disassembled. The device under test is considered as a complete device under test when it is not disassembled. The substrate can be a circuit board or a PCB board.
[0065] Step 108: Perform failure tests on various states of the device under test according to the preset test points to obtain a test curve group.
[0066] In this step, the preset test points are test points determined by the tester according to the test requirements, for example, testing the first pin and the fifth pin of a chip. Failure tests are performed on the first pin and the fifth pin of the device under test in different states of the device under test to obtain a test curve group of different states of the device under test.
[0067] Step 110: Compare the curves in the standard curve group and the test curve group to determine the failure position and failure mode of the device under test.
[0068] In this step, the standard curve group includes standard curves under three states of the standard device, and the test curve group includes test curves under three states of the device under test. The standard curve and the test curve under the same state are compared. Based on the comparison results, the failure position and failure mode of the device under test can be determined. In this way, the failure position of the device under test can be determined more accurately, avoiding the problem of desoldering the device, damaging the solder joints, and destroying the original failure state.
[0069] Specifically, through steps 102-110, multiple states of the standard device are first determined, and failure tests are performed on multiple states of the standard device according to preset test points to obtain a standard curve group, that is, the TDR curves of the non-failed device under multiple states are obtained. After determining multiple states of the device under test, failure tests are performed on multiple states of the device under test according to preset test points to obtain a test curve group, that is, the TDR curves of the failed device under multiple states are obtained. The TDR curves of the non-failed device under multiple states are compared with the TDR curves of the failed device under multiple states to determine the waveform changes of the TDR curve, and then it can be determined in which state the device under test is abnormal, and the failure point position and failure mode can be accurately determined. The problem of desoldering the device, destroying the solder joint, and destroying the original failure state is avoided. The exemplary TDR (time domain reflectometer) input pulse signal reflects the signal when the circuit inside the device fails. The user can judge the time domain waveform between the failed device and the non-failed device by comparing the reflected signal, and then the failure position and failure mode of the failed device can be accurately determined.
[0070] In some embodiments, multiple states of a standard device are determined, including:
[0071] In response to the standard device retaining the substrate and being connected to the IC, determining that the standard device is in a complete standard device state;
[0072] In response to the standard device not retaining the substrate and not being connected to the IC, determining that the standard device is in a disassembled standard device state;
[0073] In response to the standard device having the substrate left and not connected to the IC, it is determined that the standard device is in the on-board standard device state.
[0074] Specifically, the standard device is a non-failed device. When testing, the device under test needs to be tested with the same model and the same batch of chips as the standard device, so that accurate test results can be guaranteed. The standard device retains the substrate and is connected to the IC, that is, the standard device has not been disassembled, and is determined to be a complete standard device state of the standard device state. When the standard device is disassembled on the substrate and is not connected to the IC, that is, the standard device (which can be a chip) is completely disassembled, the state of the standard device is determined to be a disassembled standard device state. When the standard device remains on the substrate but the connection with the IC is cut off, the state of the standard device is determined to be an on-board standard device state. In this way, by performing failure tests on the three states, the failure position and failure mode of the device under test can be accurately determined.
[0075] In some embodiments, the standard curve group includes a standard curve for a complete standard device state, a standard curve for a disassembled standard device state, and a standard curve for an on-board standard device state;
[0076] The method of performing failure tests on various states of the standard device according to preset test points to obtain a standard curve includes:
[0077] According to the preset test points, a failure test is performed on the standard device in the complete standard device state to obtain a standard curve of the complete standard device state;
[0078] According to the preset test points, a failure test is performed on the standard device in the disassembled device state to obtain a standard curve of the disassembled standard device state;
[0079] According to the preset test points, a failure test is performed on the standard device in the on-board standard device state to obtain a standard curve of the on-board standard device state.
[0080] Specifically, the exemplary preset test points are the first pin and the fifth pin of the chip. When performing failure tests on various states of the standard device state, the first pin and the fifth pin of the standard device in the complete standard device state, the standard device in the disassembled standard device state, and the standard device in the on-board standard device state are connected to the TDR tester respectively, and the standard curve of the complete standard device state, the standard curve of the disassembled standard device state, and the standard curve of the on-board standard device state are obtained respectively through the TDR tester. That is, the standard curves of the three states of the non-failed device are obtained, which is convenient for comparison with the test curves of the corresponding states of the failed device, and the failure position and failure mode of the failed device are accurately determined according to the waveform changes of the curves.
[0081] In some embodiments, multiple states of the device under test are determined, including:
[0082] In response to the device under test retaining the substrate and being connected to the IC, determining that the device under test is in a complete device under test state;
[0083] In response to the device under test not retaining the substrate and not being connected to the IC, determining that the device under test is in a disassembled device under test state;
[0084] In response to the device under test having the substrate left and not connected to the IC, it is determined that the device under test is in the on-board device under test state.
[0085] Specifically, the device under test retains the substrate and is connected to the IC, that is, the device under test has not been disassembled, and the state of the device under test is determined to be the complete device under test state. When the device under test is disassembled on the substrate and is not connected to the IC, that is, the device under test (which can be a chip) is completely disassembled, the state of the device under test is determined to be the disassembled device under test state. When the device under test remains on the substrate but the connection with the IC is cut off, the state of the device under test is determined to be the device under test state. In this way, by performing failure tests on the three states, the test curve obtained by the failure test of the device under test is compared with the standard curve obtained by the aging test of the standard device, and the failure position and failure mode of the device under test can be accurately determined.
[0086] In some embodiments, the test curve group includes a test curve of a complete device under test state, a test curve of a disassembled device under test state, and a test curve of an on-board device under test state;
[0087] The method of performing failure tests on various states of the device under test according to the preset test points to obtain a test curve group includes:
[0088] According to the preset test points, a failure test is performed on the device under test in the complete device under test state to obtain a test curve of the complete device under test state;
[0089] According to the preset test points, a failure test is performed on the device under test in the disassembled device state to obtain a test curve of the disassembled standard component state;
[0090] According to the preset test points, a failure test is performed on the device under test in the on-board device under test state to obtain a test curve of the on-board device under test state.
[0091] Specifically, the exemplary preset test points are the first pin and the fifth pin of the chip. When failure tests are performed on various states of the device under test, the first pin and the fifth pin of the device under test in the complete device under test state, the device under test in the disassembled device under test state, and the device under test in the board state are respectively connected through the TDR tester, and the test curves of the complete device under test state, the test curves of the disassembled device under test state, and the test curves of the board state are respectively obtained through the TDR tester. That is, the test curves of the three states of the failed device are obtained, which is convenient for comparison with the standard curves of the corresponding states of the non-failed device, and the failure position and failure mode of the failed device can be accurately determined according to the waveform changes of the curves.
[0092] In some embodiments, Figure 2 As shown in the structure, the failure location includes the device itself, the substrate or the solder joint;
[0093] The step of comparing the standard curve group with the curves in the test curve group to determine the failure position of the device under test includes:
[0094] In response to the waveform amplitudes of the standard curve of the disassembled standard device state and the test curve of the disassembled device under test state being greater than a preset threshold, determining that the failure position of the device under test is the device itself;
[0095] In response to the waveform amplitudes of the standard curve of the on-board standard device state and the test curve of the on-board tested device state being greater than a preset threshold, determining that the failure position during the tested period is the substrate;
[0096] In response to the waveform amplitudes of the standard curve of the complete standard test device state and the test curve of the complete device under test state being greater than a preset threshold, it is determined that the failure position of the device under test is a solder joint.
[0097] Specifically, the standard curve of the disassembled standard test device state is compared with the test curve of the disassembled device state, and the curve waveform is observed. If the waveform amplitude of the test curve of the disassembled device state is greater than a preset threshold (exemplarily greater than 0.1V), the failure point position of the device under test is determined to be the device itself. Since only the chip itself is left after the device under test is disassembled, the failure point position of the device under test is determined to be the device itself. The standard curve of the board standard test device state is compared with the test curve of the board device state, and the curve waveform is observed. If the waveform amplitude of the test curve of the board device state is greater than a preset threshold (exemplarily greater than 0.1V), the failure point position of the device under test is determined to be the substrate. Due to the test of the board device state, the device under test retains the substrate. If there is no problem with the device under test itself, there must be a problem with the substrate. Compare the standard curve of the complete standard test device state with the test curve of the complete device under test state, observe the curve waveform, if the waveform amplitude of the test curve of the complete device under test state is greater than the preset threshold (exemplarily greater than 0.1V), then determine that the failure point of the device under test is the solder joint. Since the device under test is a complete device and has not been disassembled, if both of the above two conditions are not met, it means that there is no problem with the substrate and the device itself, and it is determined that there is a problem at the welding point between the two. Therefore, determine that the failure point of the device under test is the solder joint. When testing, it is necessary to follow the steps to ensure the accuracy of the test and locate the failure position more accurately.
[0098] In some embodiments, the failure modes include: an open circuit failure mode and a short circuit failure mode;
[0099] Comparing the standard curve group with the curves in the test curve group to determine the failure mode of the device under test, including:
[0100] In response to the waveform amplitudes of the standard curve of the complete standard test device state and the test curve of the complete device under test state being greater than a preset threshold, the waveform amplitudes of the standard curve of the disassembled standard device state and the test curve of the disassembled device under test state being greater than a preset threshold, and the waveform amplitudes of the standard curve of the on-board standard device state and the test curve of the on-board device under test state being greater than a preset threshold, determining that the failure mode of the device under test is a short-circuit failure mode;
[0101] In response to the fact that the waveform amplitudes of the standard curve of the complete standard test device state and the test curve of the complete device under test state are greater than a preset threshold, the waveform amplitudes of the standard curve of the disassembled standard device state and the test curve of the disassembled device under test state are greater than a preset threshold, or the waveform amplitudes of the standard curve of the on-board standard device state and the test curve of the on-board device under test state are greater than a preset threshold, it is determined that the failure mode during the test is an open circuit failure mode.
[0102] Specifically, the standard curve of the disassembled standard test device state is compared with the test curve of the disassembled device under test state, and the waveform of the curve is observed. If the waveform amplitude of the test curve of the disassembled device under test state is greater than a preset threshold value (exemplarily greater than 0.1V), since only the chip itself is left after the device under test is disassembled, the failure point of the device under test is determined to be the device itself. The standard curve of the board standard test device state is compared with the test curve of the board device under test state, and the waveform of the curve is observed. If the waveform amplitude of the test curve of the board device under test state is greater than a preset threshold value (exemplarily greater than 0.1V), since the board device under test state test retains the substrate, if there is no problem with the device under test itself, there must be a problem with the substrate, therefore, the failure point of the device under test is determined to be the substrate. Compare the standard curve of the complete standard test device state with the test curve of the complete device under test state, and observe the curve waveform. If the waveform amplitude of the test curve of the complete device under test state is greater than the preset threshold (exemplarily greater than 0.1V), since the device under test is a complete device and has not been disassembled, if both of the above two conditions are not met, it means that there is no problem with the substrate and the device itself, and it is determined that there is a problem at the welding point between the two. Therefore, the failure point position of the device under test is determined to be the solder joint. When there are problems with the above curves, the device under test will short-circuit, so the failure mode is a short-circuit failure mode.
[0103] Compare the standard curve of the device state under the disassembled standard test with the test curve of the device under test under the disassembled machine, and observe the waveform of the curve. If the waveform amplitude of the test curve of the device under test under the disassembled machine is greater than the preset threshold value (exemplarily greater than 0.1V), since only the chip itself is left after the device under test is disassembled, the failure point of the device under test is determined to be the device itself. Compare the standard curve of the device state under the board standard test with the test curve of the device under test under the board, and observe the waveform of the curve. If the waveform amplitude of the test curve of the device under test under the board is greater than the preset threshold value (exemplarily greater than 0.1V), since the device under test retains the substrate in the test of the device under test under the board, if there is no problem with the device under test itself, there must be a problem with the substrate. Therefore, the failure point of the device under test is determined to be the substrate. Compare the standard curve of the complete standard test device state with the test curve of the complete device under test state, and observe the curve waveform. If the waveform amplitude of the test curve of the complete device under test state is greater than the preset threshold (exemplarily greater than 0.1V), since the device under test is a complete device and has not been disassembled, if both of the above two conditions are not met, it means that there is no problem with the substrate and the device itself, and it is determined that there is a problem at the welding point between the two. Therefore, the failure point position of the device under test is determined to be the solder joint. When there is a problem with one of the above curves, the device under test will be open circuit, so the failure mode is the open circuit failure mode.
[0104] This application uses TDR testing, uses the minimum sample size, compares time domain waveforms, and performs preliminary positioning of the failure site. There are differences in the waveform peak time lines of different sample state tests. The time line is divided into three areas by the waveform peak time of normal devices (on the board) and normal devices (disassembled parts). By comparing the waveform peak time obtained from the failed device (on the board) test, the failure location and mode of the failed device (on the board) are determined from the pre-divided areas, thereby formulating a failure analysis plan, which greatly shortens the failure analysis time.
[0105] It should be noted that the method of the embodiment of the present application can be performed by a single device, such as a computer or server. The method of this embodiment can also be applied to a distributed scenario and completed by multiple devices cooperating with each other. In the case of such a distributed scenario, one of the multiple devices can only perform one or more steps in the method of the embodiment of the present application, and the multiple devices will interact with each other to complete the described method.
[0106] It should be noted that the above describes some embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
[0107] Based on the same inventive concept, corresponding to any of the above-mentioned embodiment methods, the present application also provides a device failure testing apparatus.
[0108] refer to Figure 3 , the device failure testing device comprises:
[0109] A first determination module is configured to determine multiple states of a standard device;
[0110] A first test module is configured to perform failure tests on multiple states of the standard device according to preset test points to obtain a standard curve group;
[0111] A second determination module is configured to determine multiple states of the device under test;
[0112] A second test module is configured to perform failure tests on multiple states of the device under test according to the preset test points to obtain a test curve group;
[0113] The third determination module is configured to compare the curves in the standard curve group and the test curve group to determine the failure position and failure mode of the device under test.
[0114] Specifically, by first determining the various states of the standard device, and performing failure tests on the various states of the standard device according to preset test points, a standard curve group is obtained, that is, the TDR curves of the non-failed device under various states are obtained. After determining the various states of the device under test, and performing failure tests on the various states of the device under test according to preset test points, a test curve group is obtained, that is, the TDR curves of the failed device under various states are obtained. The TDR curves of the non-failed device under various states are compared with the TDR curves of the failed device under various states to determine the waveform changes of the TDR curve, and then it can be determined in which state the device under test is abnormal, and the failure point position and failure mode can be accurately determined. The problem of desoldering the device, damaging the solder joints, and destroying the original failure state is avoided.
[0115] For the convenience of description, the above device is described in terms of functions divided into various modules. Of course, when implementing the present application, the functions of each module can be implemented in the same or multiple software and / or hardware.
[0116] The apparatus of the above embodiment is used to implement a corresponding device failure test method in any of the above embodiments, and has the beneficial effects of the corresponding method embodiment, which will not be described in detail here.
[0117] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments, the present application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, a device failure testing method described in any of the above embodiments is implemented.
[0118] Figure 4 A more specific schematic diagram of the hardware structure of an electronic device provided in this embodiment is shown, and the device may include: a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050. The processor 1010, the memory 1020, the input / output interface 1030, and the communication interface 1040 are connected to each other through the bus 1050 in the device.
[0119] The processor 1010 can be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this specification.
[0120] The memory 1020 may be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 1020 may store an operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program codes are stored in the memory 1020 and are called and executed by the processor 1010.
[0121] The input / output interface 1030 is used to connect the input / output module to realize information input and output. The input / output module can be configured in the device as a component (not shown in the figure), or it can be externally connected to the device to provide corresponding functions. The input device may include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output device may include a display, a speaker, a vibrator, an indicator light, etc.
[0122] The communication interface 1040 is used to connect a communication module (not shown) to realize communication interaction between the device and other devices. The communication module can realize communication through a wired mode (such as USB, network cable, etc.) or a wireless mode (such as mobile network, WIFI, Bluetooth, etc.).
[0123] The bus 1050 includes a path that transmits information between the various components of the device (eg, the processor 1010, the memory 1020, the input / output interface 1030, and the communication interface 1040).
[0124] It should be noted that, although the above device only shows the processor 1010, the memory 1020, the input / output interface 1030, the communication interface 1040 and the bus 1050, in the specific implementation process, the device may also include other components necessary for normal operation. In addition, it can be understood by those skilled in the art that the above device may also only include the components necessary for implementing the embodiments of the present specification, and does not necessarily include all the components shown in the figure.
[0125] The electronic device of the above embodiment is used to implement a corresponding device failure test method in any of the above embodiments, and has the beneficial effects of the corresponding method embodiment, which will not be described in detail here.
[0126] Based on the same inventive concept, corresponding to any of the above-mentioned embodiment methods, the present application also provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer instructions, and the computer instructions are used to enable the computer to execute a device failure testing method as described in any of the above embodiments.
[0127] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device.
[0128] The computer instructions stored in the storage medium of the above embodiment are used to enable the computer to execute a device failure testing method as described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.
[0129] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application (including the claims) is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.
[0130] In addition, to simplify the description and discussion, and in order not to make the embodiments of the present application difficult to understand, the known power supply / ground connection with the integrated circuit (IC) chip and other components may or may not be shown in the provided drawings. In addition, the device can be shown in the form of a block diagram to avoid making the embodiments of the present application difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform to be implemented in the embodiments of the present application (that is, these details should be fully within the scope of understanding of those skilled in the art). In the case of elaborating specific details (e.g., circuits) to describe exemplary embodiments of the present application, it is obvious to those skilled in the art that the embodiments of the present application can be implemented without these specific details or when these specific details are changed. Therefore, these descriptions should be considered to be illustrative rather than restrictive.
[0131] Although the present application has been described in conjunction with specific embodiments of the present application, many replacements, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.
[0132] The embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of the present application.
Claims
1. A device failure testing method, characterized in that: include: Determine various states of standard devices; According to preset test points, failure tests are performed on various states of the standard device to obtain a standard curve group; Determine various states of the device under test; According to the preset test points, failure tests are performed on various states of the device under test to obtain a test curve group; The curves in the standard curve group and the test curve group are compared to determine the failure position and failure mode of the device under test.
2. The method according to claim 1, characterized in that Determines multiple states of standard devices, including: In response to the standard device retaining the substrate and being connected to the IC, determining that the standard device is in a complete standard device state; In response to the standard device not retaining the substrate and not being connected to the IC, determining that the standard device is in a disassembled standard device state; In response to the standard device having the substrate left and not connected to the IC, it is determined that the standard device is in the on-board standard device state.
3. The method according to claim 2, characterized in that The standard curve group includes a standard curve of a complete standard device state, a standard curve of a disassembled standard device state, and a standard curve of an on-board standard device state; The method of performing failure tests on various states of the standard device according to preset test points to obtain a standard curve includes: According to the preset test points, a failure test is performed on the standard device in the complete standard device state to obtain a standard curve of the complete standard device state; According to the preset test points, a failure test is performed on the standard device in the disassembled device state to obtain a standard curve of the disassembled standard device state; According to the preset test points, a failure test is performed on the standard device in the on-board standard device state to obtain a standard curve of the on-board standard device state.
4. The method according to claim 3, characterized in that Determine various states of the device under test, including: In response to the device under test retaining the substrate and being connected to the IC, determining that the device under test is in a complete device under test state; In response to the device under test not retaining the substrate and not being connected to the IC, determining that the device under test is in a disassembled device under test state; In response to the device under test having the substrate left and not connected to the IC, it is determined that the device under test is in the on-board device under test state.
5. The method according to claim 4, characterized in that The test curve group includes a test curve of a complete device under test state, a test curve of a disassembled device under test state, and a test curve of an on-board device under test state; The method of performing failure tests on various states of the device under test according to the preset test points to obtain a test curve group includes: According to the preset test points, a failure test is performed on the device under test in the complete device under test state to obtain a test curve of the complete device under test state; According to the preset test points, a failure test is performed on the device under test in the disassembled device state to obtain a test curve of the disassembled standard component state; According to the preset test points, a failure test is performed on the device under test in the on-board device under test state to obtain a test curve of the on-board device under test state.
6. The method according to claim 5, characterized in that The failure location includes the device itself, the substrate or the solder joint; The step of comparing the standard curve group with the curves in the test curve group to determine the failure position of the device under test includes: In response to the waveform amplitudes of the standard curve of the disassembled standard device state and the test curve of the disassembled device under test state being greater than a preset threshold, determining that the failure position of the device under test is the device itself; In response to the waveform amplitudes of the standard curve of the on-board standard device state and the test curve of the on-board tested device state being greater than a preset threshold, determining that the failure position during the tested period is the substrate; In response to the waveform amplitudes of the standard curve of the complete standard test device state and the test curve of the complete device under test state being greater than a preset threshold, it is determined that the failure position of the device under test is a solder joint.
7. The method according to claim 5, characterized in that The failure modes include: open circuit failure mode and short circuit failure mode; Comparing the standard curve group with the curves in the test curve group to determine the failure mode of the device under test, including: In response to the waveform amplitudes of the standard curve of the complete standard test device state and the test curve of the complete device under test state being greater than a preset threshold, the waveform amplitudes of the standard curve of the disassembled standard device state and the test curve of the disassembled device under test state being greater than a preset threshold, and the waveform amplitudes of the standard curve of the on-board standard device state and the test curve of the on-board device under test state being greater than a preset threshold, determining that the failure mode of the device under test is a short-circuit failure mode; In response to the fact that the waveform amplitudes of the standard curve of the complete standard test device state and the test curve of the complete device under test state are greater than a preset threshold, the waveform amplitudes of the standard curve of the disassembled standard device state and the test curve of the disassembled device under test state are greater than a preset threshold, or the waveform amplitudes of the standard curve of the on-board standard device state and the test curve of the on-board device under test state are greater than a preset threshold, it is determined that the failure mode during the test is an open circuit failure mode.
8. A device failure test apparatus, characterized in that: include: A first determination module is configured to determine multiple states of a standard device; A first test module is configured to perform failure tests on multiple states of the standard device according to preset test points to obtain a standard curve group; A second determination module is configured to determine multiple states of the device under test; A second test module is configured to perform failure tests on multiple states of the device under test according to the preset test points to obtain a test curve group; The third determination module is configured to compare the curves in the standard curve group and the test curve group to determine the failure position and failure mode of the device under test.
9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the method according to any one of claims 1 to 7 is implemented.
10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to enable a computer to execute the method according to any one of claims 1 to 7.