Non-stable state switch type anti-surge protection device

Abstract

The invention provides an unstable-state switching type anti-surge protection device, and belongs to the technical field of semiconductor protection. The punch-through isolation region divides the substrate into a first region and a second region which are independent from each other; a first TSS device region formed in the first region; a first resistance region formed in the second region; the dielectric layers are respectively formed on the surfaces of the first surface and the second surface which are opposite to each other; and the metal layer is formed on the surface of the dielectric layer, and the first resistance region is connected in parallel between the first electrode and the second electrode of the first TSS device region through the metal layer. The TSS device has the beneficial effects that the body resistor is connected in parallel between the two electrodes of the TSS device, so that when small current passes through, the voltage at the two ends of the device can be effectively reduced by the parallel body resistor; when a large current passes through, local temperature rise caused by heating of the body resistor affects an IBO parameter of the TSS device, so that the device enters a conducting state in advance, and the TSS device in the conducting state can lower a resistor end voltage, thereby reducing the level of the current flowing through the resistor.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor protection, and in particular to a non-stable switching type surge protection device. Background Art

[0002] With the rapid development of modern science and technology, electronic products are moving towards a more sophisticated and complex direction. This trend has made the surge resistance and anti-static ability of electronic equipment and devices a difficult problem that needs to be solved urgently. In practical applications, there are often huge surge voltages in the power grid, such as lightning overvoltage, operating overvoltage, transient overvoltage, etc. If these surge voltages cannot be released or absorbed in time, they may damage the precision components in the electronic equipment and hinder their normal operation. They may also directly damage the circuit, causing abnormal circuit operation and downtime, and even cause a series of safety problems, posing a potential threat to personnel and equipment. In order to cope with this problem, the application of surge protection devices has become particularly important.

[0003] At present, the common surge protection devices on the market are mainly divided into two categories: clamp-type surge protection devices and switch-type surge protection devices. Clamp-type surge protection devices, such as transient voltage suppressors (TVS) and metal oxide varistors (MOV), protect the circuit by limiting the peak voltage; while switch-type surge protection devices, such as semiconductor discharge tubes (TSS) and gas discharge tubes (GDT), can quickly turn on when the surge voltage is detected, and introduce the surge current into the ground wire, thereby protecting the circuit from damage. In practical applications, in order to further optimize the protection effect, switch-type surge protection devices and clamp-type surge protection devices are often used in series or parallel according to specific needs to achieve special purposes such as reducing device leakage, reducing capacitance, reducing peak residual voltage, and shutting off continuous current.

[0004] TSS devices are one of the representatives of semiconductor switch devices. Figure 1 As shown in the figure, as a bidirectional switch semiconductor device, TSS device has key electrical parameters such as breakdown voltage (VDRM), turn-on voltage (VBO) and minimum holding current (IH). Among them, VDRM represents the voltage value of TSS device during actual avalanche breakdown, while VBO is the starting voltage of device flyback, and IH is the minimum current required to ensure that the device can maintain the on state.

[0005] In general application scenarios, the performance of TSS devices mainly focuses on parameters such as residual voltage, capacitance, and surge capability. However, in some special cases, due to the interaction of inductance, capacitance, and resistance in the circuit, an input waveform with small current and large voltage may appear. For this waveform, under the sub-waveform, the traditional TSS device will have a voltage greater than VDRM but less than VBO. At this time, the device will undergo avalanche breakdown, but because the turning voltage VBO is not reached, it cannot enter the on state. Since the device cannot fully exert its surge protection capability without entering the on state, it may be damaged prematurely due to the inability to withstand high surge voltages. This problem is particularly prominent in the presence of high surge voltages. Summary of the invention

[0006] In order to solve the above technical problems, the present invention provides a non-steady-state switch type surge protection device.

[0007] The technical problem solved by the present invention can be achieved by adopting the following technical solutions:

[0008] An unstable switching type surge protection device, comprising:

[0009] a substrate comprising a first side and a second side opposite to each other;

[0010] A through isolation region is formed through the substrate to separate the substrate into a first region and a second region that are independent of each other;

[0011] a first TSS device region formed in the first region;

[0012] a first resistance region formed in the second region;

[0013] A dielectric layer is formed on surfaces of a first surface and a second surface of the substrate respectively, and windows corresponding to the first area and the second area are formed in the dielectric layers on the first surface and the second surface of the substrate respectively;

[0014] A metal layer is formed on the surface of the dielectric layer and fills the window. The first resistor region is connected in parallel between the first electrode and the second electrode of the first TSS device region through the metal layer.

[0015] Preferably, the first TSS device region comprises:

[0016] a first triode, wherein an emitter of the first triode forms a first electrode of the first TSS device region;

[0017] A second transistor, wherein the base of the second transistor is connected to the collector of the first transistor, the collector of the second transistor is connected to the base of the first transistor, and the emitter of the second transistor forms the second electrode of the first TSS device region.

[0018] Preferably, the substrate has a first conductivity type;

[0019] The first area includes:

[0020] A first doped region of a second conductivity type is formed in the substrate by doping from a first surface of the substrate;

[0021] A second doping region of a second conductivity type is formed in the substrate by doping from a second surface of the substrate;

[0022] A third doping region of the first conductivity type, formed in the first doping region;

[0023] The third doping region, the first doping region, the substrate, and the second doping region form the first TSS device region.

[0024] Preferably, the first area also includes:

[0025] A first trench is formed in the substrate from the first surface of the substrate and is located at both sides of the first doping region, wherein the depth of the first trench is greater than the depth of the first doping region;

[0026] A glass passivation layer is filled in the first groove, and the upper surface of the glass passivation layer is flush with the first surface of the substrate.

[0027] Preferably, the first resistance area includes one; or

[0028] The first resistance areas include two or more, and the two or more first resistance areas are connected in series.

[0029] Preferably, the first resistance region is a substrate of a region where the second region separated by two adjacent through isolation regions is located.

[0030] Preferably, the width of the first resistance region is 1 μm to 200 μm.

[0031] Preferably, the resistance of the first resistance zone is 500KΩ-100MΩ.

[0032] Preferably, it also includes:

[0033] A second TSS device region is formed in the first region, wherein the second TSS device region is formed in the substrate symmetrically with the first TSS device region to share the same substrate;

[0034] The first electrode of the second TSS device region is connected to the second electrode of the first TSS device region, and the second electrode of the second TSS device region is connected to the first electrode of the first TSS device region.

[0035] Preferably, the second TSS device region comprises:

[0036] a third triode, wherein an emitter of the third triode forms a first electrode of the second TSS device region;

[0037] A fourth triode, the base of the fourth triode is connected to the collector of the third triode, the collector of the fourth triode is connected to the base of the third triode, and the emitter of the fourth triode forms the second electrode of the second TSS device region.

[0038] Preferably, the substrate has a first conductivity type;

[0039] The first area includes:

[0040] A first doped region of a second conductivity type is formed in the substrate by doping from a first surface of the substrate;

[0041] A fourth doped region of the second conductivity type is formed in the substrate by doping from the second surface of the substrate;

[0042] A third doping region of the first conductivity type, formed in the first doping region;

[0043] A fifth doping region of the first conductivity type is formed in the fourth doping region, and the fifth doping region is staggered with the third doping region;

[0044] A sixth heavily doped region of the second conductivity type is formed by doping in the first doped region from the first surface of the substrate and penetrates the first doped region into the substrate;

[0045] A seventh heavily doped region of the second conductivity type is doped from the second surface of the substrate into the fourth doped region and penetrates the fourth doped region into the substrate, and the seventh heavily doped region is staggered with the sixth heavily doped region;

[0046] The third doping region, the first doping region, the substrate, and the seventh heavily doped region form the first TSS device region, and the fifth doping region, the fourth doping region, the substrate, and the sixth heavily doped region form the second TSS device region.

[0047] Preferably, the third doping region is a continuous doping region; or

[0048] The third doping region is a plurality of sub-doping regions arranged at intervals.

[0049] Preferably, a distance between an edge of the third doping region and an edge of the first resistance region is 30 μm to 360 μm.

[0050] Preferably, the first area also includes:

[0051] At least one first voltage divider ring region of a second conductivity type is formed in the substrate by doping from the first surface of the substrate.

[0052] Preferably, the fifth doping region is a continuous doping region; or

[0053] The fifth doping region is a plurality of sub-doping regions arranged at intervals.

[0054] Preferably, the first area also includes:

[0055] At least one second voltage divider ring region of a second conductivity type is formed in the substrate by doping from the second surface of the substrate.

[0056] Preferably, the through isolation region is also used to separate the substrate into a third region that is independent of the first region and the second region;

[0057] Also includes:

[0058] A second resistance region is formed in the third area, and the second resistance region is connected in parallel between the first electrode and the second electrode of the second TSS device region.

[0059] Preferably, a distance between an edge of the fifth doping region and an edge of the second resistance region is 30 μm to 360 μm.

[0060] Preferably, the second resistance area includes one; or

[0061] The second resistance areas include two or more, and the two or more second resistance areas are connected in series.

[0062] Preferably, the second resistance region is a substrate of a region where a third region separated by two adjacent through isolation regions is located.

[0063] Preferably, the width of the second resistance region is 1 μm to 200 μm.

[0064] Preferably, the resistance of the second resistance zone is 500KΩ-100MΩ.

[0065] The advantages or beneficial effects of the technical solution of the present invention are:

[0066] The present invention connects a parallel body resistor between two electrodes of the TSS device. When a small current passes through, the parallel body resistor can effectively reduce the voltage across the device. When a large current passes through, the local temperature rise caused by the heat generated by the body resistor is used to affect the IBO parameters of the TSS device, so that the device enters the on state in advance. The TSS device in the on state can lower the voltage at the resistor end, thereby reducing the current level flowing through the resistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] Figure 1 A schematic diagram of the forward and reverse overvoltage current discharge IV curve of a TSS device in the prior art;

[0068] Figure 2 A schematic diagram of a voltage-current-time curve of a TSS device connected in series with a high-power MOV or TVS in the prior art;

[0069] Figure 3 A schematic diagram of a voltage-current-time curve of a TSS device reducing a reverse breakdown current (IBO) in the prior art;

[0070] Figure 4 It is a schematic cross-sectional structure diagram of a non-stable switch type surge protection device in a preferred embodiment 1 of the present invention;

[0071] Figure 5 The equivalent circuit diagram of the non-stable switching type surge protection device in the preferred embodiment 1 of the present invention;

[0072] Figure 6 Schematic diagram of voltage-current-time curve of parallel body resistance of TSS device in preferred embodiment 1 of the present invention;

[0073] Figure 7a-7c It is a schematic cross-sectional structure diagram of each step of the method for preparing a non-stable switching type surge protection device in the preferred embodiment 1 of the present invention;

[0074] Figure 8 This is a schematic diagram of a voltage-current-time curve of a non-steady-state switch type surge protection device at a voltage of 3KV and a current of 50μA in a preferred embodiment 1 of the present invention;

[0075] Fig. 9 This is a schematic diagram of a voltage-current-time curve of a non-steady-state switch type surge protection device at a voltage of 160V and a current of 50μA in a preferred embodiment 1 of the present invention;

[0076] Fig.10 It is a schematic cross-sectional structure diagram of a non-stable switch type surge protection device in a preferred embodiment 2 of the present invention;

[0077] Fig.11It is a schematic cross-sectional structure diagram of a non-stable switch type surge protection device in a preferred embodiment 3 of the present invention;

[0078] Fig.12 The equivalent circuit diagram of the non-stable switch type surge protection device in the preferred embodiment 3 of the present invention;

[0079] Fig.13 It is a schematic cross-sectional structure diagram of a non-stable switch type surge protection device in a preferred embodiment 4 of the present invention;

[0080] Fig.14 The equivalent circuit diagram of the non-stable switch type surge protection device in the preferred embodiment 4 of the present invention;

[0081] Fig.15 It is a schematic cross-sectional structure diagram of a non-stable switch type surge protection device in a preferred embodiment 5 of the present invention;

[0082] Fig.16 This is an equivalent circuit diagram of a non-stable switching type surge protection device in a preferred embodiment 6 of the present invention.

[0083] Description of reference numerals:

[0084] 1. Substrate; 2. Through isolation region; 201. First region; 202. Second region; 3. First doped region; 4. Second doped region; 5. Third doped region; 6. First voltage divider ring region; 7. Dielectric layer; 8. Metal layer; 9. First resistance region; 10. Fourth doped region; 11. Fifth doped region; 12. Sixth heavily doped region; 13. Seventh heavily doped region; 14. Second voltage divider ring region; 15. Second resistance region; 16. First groove; 17. Glass passivation layer. DETAILED DESCRIPTION

[0085] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0086] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0087] The corresponding doping concentration is indicated in the drawings by indicating "+" or "++" after the doping type "N" or "P". For example, "N-" indicates a doping concentration that is lower than the doping concentration of the N-doping region, while the "N+ / N++" doping region has a doping concentration that is higher than the doping concentration of the N-doping region, and the "N++" doping region has a doping concentration that is higher than the doping concentration of the N+ doping region. Doping regions with the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different N-doping regions can have the same or different absolute doping concentrations.

[0088] TSS devices are often used in series with high-power MOV or TVS. When a surge current passes through, the TSS device turns on to protect the back-end circuit. In actual applications, due to the presence of inductors, capacitors, resistors and other components in the circuit, the surge waveform loaded on both ends of the TSS device will produce a phase difference between the voltage and current. Moreover, when the current flowing through the TSS device is in a low current state, the device will enter an avalanche breakdown state (at this time the voltage exceeds VDRM), but it has not fully entered the on state. In this state, since the device has not completely reversed its population, the present invention calls it a "stable state." In the stable state, if Figure 2 As shown, the voltage across the device is very high, and the open circuit voltage may be as high as thousands of volts.

[0089] After the TSS device is clamped, the current is approximately greater than the breakdown voltage VDRM of the TSS device. The current is usually only a few mA. However, due to the presence of the large voltage, the power loaded on both ends of the device is large, causing the device to be damaged prematurely. The embodiment of the present invention is intended to prevent the device from operating in the stable working area and prevent the device from premature surge failure.

[0090] like Figure 3 As shown in the figure, the traditional method attempts to alleviate the steady state phenomenon to a certain extent by reducing the reverse breakdown current (IBO), but IBO cannot be infinitely reduced. According to the stability of the existing process, in order to ensure the breakdown voltage VDRM parameter, IBO is generally at the lowest level of tens of milliamperes. It cannot be eliminated for currents of the microampere (μA) level.

[0091] In a preferred embodiment of the present invention, based on the above problems existing in the prior art, a non-stable switching type surge protection device is provided, by connecting a body resistor in parallel between two electrodes of a TSS device.

[0092] The working principle of this device is that when a small current passes through it, the body resistance can effectively reduce the voltage across the TSS device.

[0093] When a large current passes through, the temperature of the area near the resistor of the TSS device rises due to the heating effect of the body resistor. By taking advantage of the fact that the IBO of the TSS device increases with the temperature, the IBO parameters of the TSS device can be directly affected, so that the device enters the on state in advance. The TSS device in the on state can pull down the voltage at the resistor end, so that the current passing through the resistor will be reduced to a very low level.

[0094] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0095] Example 1

[0096] like Figure 4 As shown, embodiment 1 provides a non-steady-state switch type surge protection device, the device comprising:

[0097] A substrate 1, the substrate 1 comprising a first surface and a second surface opposite to each other;

[0098] A through isolation region 2 is formed through the substrate 1 to separate the substrate 1 into a first region 201 and a second region 202 that are independent of each other;

[0099] A first TSS device region TSS1 is formed in the first region 201;

[0100] A first resistance region 9 is formed in the second region 202;

[0101] The dielectric layer 7 is formed on the surfaces of the first and second surfaces of the substrate 1 respectively, and windows corresponding to the first region 201 and the second region 202 are formed in the dielectric layer 7 on the first and second surfaces of the substrate 1 respectively;

[0102] The metal layer 8 is formed on the surface of the dielectric layer 7 and fills the window. The first resistor region 9 is connected in parallel between the first electrode and the second electrode of the first TSS device region TSS1 through the metal layer 8 .

[0103] Specifically, in this embodiment, by connecting the first resistor region 9 in parallel between the first electrode and the second electrode of the first TSS device region TSS1, an unstable state can be introduced into the TSS device, thereby effectively reducing the failure rate of the TSS device and improving its surge capability under low current conditions.

[0104] As a preferred embodiment, wherein Figure 5 As shown, the first TSS device region TSS1 includes:

[0105] A first transistor Q1, wherein the emitter of the first transistor Q1 forms a first electrode of the first TSS device region TSS1;

[0106] The second transistor Q2 has a base connected to the collector of the first transistor Q1 , a collector connected to the base of the first transistor Q1 , and an emitter of the second transistor Q2 forming a second electrode of the first TSS device region TSS1 .

[0107] In this embodiment, the first transistor Q1 is an NPN transistor, and the second transistor Q2 is a PNP transistor.

[0108] Specifically, the first TSS device region TSS1 is composed of a first NPN transistor Q1 and a second PNP transistor Q2, and the bases and collectors of the two transistors are cross-connected.

[0109] As a preferred embodiment, the substrate 1 has a first conductivity type;

[0110] In this embodiment, the first conductivity type is N-type and the second conductivity type is P-type as an example, that is, the N-type doped substrate 1 process is adopted, and the resistivity of the substrate 1 is greater than 1Ωcm.

[0111] The first area 201 includes:

[0112] A first doping region 3 of a second conductivity type is formed in the substrate 1 by doping from the first surface of the substrate 1, and an upper surface of the first doping region 3 is flush with the first surface of the substrate 1;

[0113] A second doping region 4 of a second conductivity type is formed in the substrate 1 by doping from the second surface of the substrate 1, and a lower surface of the second doping region 4 is flush with the second surface of the substrate 1;

[0114] A third doping region 5 of the first conductivity type, formed in the first doping region 3;

[0115] The third doping region 5 , the first doping region 3 , the substrate 1 , and the second doping region 4 form a first TSS device region TSS1 .

[0116] Specifically, in this embodiment, the N-type third doping region 5 , the P-type first doping region 3 , the N-type doped substrate 1 , and the P-type second doping region 4 form a first TSS device region TSS1 of an NPNP structure.

[0117] The N-type third doping region 5, the P-type first doping region 3 and the N-type doped substrate 1 constitute an NPN-type first transistor Q1, and the P-type first doping region 3, the N-type doped substrate 1 and the P-type second doping region 4 constitute a PNP-type second transistor Q2.

[0118] In this embodiment, the third doped region 5 serves as the emission region of the device.

[0119] As a preferred embodiment, the first resistance area 9 includes one.

[0120] As a preferred embodiment, the first resistance region 9 is the substrate 1 in the region where the second region 202 separated by two adjacent through isolation regions 2 is located.

[0121] As a preferred embodiment, the width of the first resistance region 9 is 1 μm to 200 μm.

[0122] As a preferred embodiment, the resistance of the first resistor region 9 is 500KΩ to 100MΩ.

[0123] Specifically, in this embodiment, only one first resistor region 9 may be provided, and the resistance value of the first resistor R1 can be adjusted by adjusting the width of the first resistor region 9 .

[0124] As a preferred embodiment, the third doping region 5 is a continuous doping region.

[0125] In this embodiment, the depth of the third doping region 5 in the longitudinal direction of the device is smaller than that of the first doping region 3 .

[0126] In this embodiment, the width of the third doping region 5 is smaller than the width of the first doping region 3 .

[0127] As a preferred embodiment, the distance between the edge of the third doping region 5 and the edge of the first resistance region 9 is 30 μm to 360 μm.

[0128] As a preferred embodiment, the first area 201 further includes:

[0129] At least one first voltage divider ring region 6 of the second conductivity type is formed in the substrate 1 by doping from the first surface of the substrate 1 .

[0130] In this embodiment, a gap exists between the first voltage dividing ring region 6 and the edge of the first doping region 3 .

[0131] In this embodiment, the doping concentration of the first voltage divider ring area 6 is greater than the doping concentration of the first doping area 3. Preferably, the first voltage divider ring area 6 is a P++ type voltage divider ring. The first voltage divider ring area 6 can improve the reverse biased electric field morphology of the PN junction formed by the P-type first doping area 3 and the N-type doped substrate 1, effectively improving the product withstand voltage.

[0132] An embodiment of the present invention provides a planar non-stable switching type surge protection device. The device functional area adopts a structure in which an NPNP-doped unidirectional TSS device and a body resistor are connected in parallel. By introducing a non-stable state into the TSS device, the failure rate of the TSS device is effectively reduced and its surge capability under low current conditions is improved.

[0133] The device preparation method is as follows:

[0134] First, a 600 μm thick, 10 ΩCM resistivity, N-type arsenic-doped substrate 1 is used; the selected substrate 1 may also be cleaned and pre-treated to remove surface impurities and oxide layers.

[0135] Then, if Figure 7a As shown, the substrate 1 is through-diffused by aluminum (AL) diffusion method to form a through isolation region 2. The through isolation region 2 separates the substrate 1 into two independent regions: a first region 201 and a second region 202. The substrate of the second region 202 is the first resistor region 9.

[0136] In this embodiment, the width of the first resistance region 9 is preferably 2 μm.

[0137] Then, if Figure 7b As shown, P-type regions, namely, a P-type first doping region 3 and a P-type second doping region 4 are prepared on the first and second surfaces of the substrate respectively by B ion implantation. At this time, the main structure is a PNP structure.

[0138] Next, the emitter region is prepared by using a phosphorus diffusion method, that is, the third doping region 5 is formed in the P-type first doping region 3 of the PNP structure.

[0139] In this embodiment, Figure 7c As shown, the first distance between the edge of the third doping region 5 and the edge of the first resistance region 9 is L1, and L1 is preferably 120 μm.

[0140] Finally, the dielectric layer 7 and the metal layer 8 are prepared. The dielectric layer 7 plays an insulating role and can be made of SiO2 or SiN and other insulating materials. The metal layer 8 can be made of commonly used metals such as AG or AL to achieve electrical connection.

[0141] The final device structure is as follows Figure 7c As shown, the finished device thickness is greater than 200 μm.

[0142] The finished device structure is a unidirectional TSS structure connected in parallel with a bulk resistor. This structure not only has the surge suppression capability of the TSS device, but also further improves the device's withstand voltage performance and stability through the parallel resistor.

[0143] In this embodiment, the breakdown voltage (VDRM) of the device finally prepared reaches 150V, indicating that the device has good voltage resistance performance.

[0144] At the same time, the voltage-current-time curve of the device under the surge condition of 3KV voltage and 50μA current is as follows: Figure 8 As shown. Among them, the horizontal axis is time T (unit: milliseconds\ms), the left vertical axis is voltage U (unit: volts\V), and the right vertical axis is current I (unit: amperes\A).

[0145] like Fig. 9 As shown, compared with the prior art, the device of the present invention has a smaller residual voltage due to the existence of the parallel resistor, thereby being able to better protect the device from damage.

[0146] When a small current passes through, the parallel first resistance area 9 can effectively reduce the voltage across the device; when a large current passes through, due to the heating effect of the first resistance area 9, the local temperature of the area of ​​the first TSS device area TSS1 close to the first resistance area 9 increases. By utilizing the characteristic that the device IBO parameter increases with the increase in temperature, the IBO parameter of the first TSS device area TSS1 can be directly affected, so that the device enters the on state in advance. The first TSS device area TSS1 in the on state can lower the voltage across the first resistance area 9, so that the current passing through the first resistance area 9 will be reduced to a very low level.

[0147] Example 2

[0148] Embodiment 2 provides a high IH planar non-steady-state switch type surge protection device, which differs from Embodiment 1 in that the emission region adopts a short-circuit structure. Other structures and preparation methods are similar to those of Embodiment 1 and will not be described in detail here.

[0149] As a preferred embodiment, wherein Fig.10 As shown, the third doping region 5 is a plurality of sub-doping regions arranged at intervals.

[0150] Specifically, compared with the continuous third doping region 5 in embodiment 1, the third doping region 5 in embodiment 2 is replaced by a plurality of sub-doping regions arranged in an interval manner to increase the device holding current IH, thereby optimizing the overall performance of the device.

[0151] Further, in this embodiment, if Fig.10 As shown, the second distance between the edge of the third doping region 5 and the edge of the first resistance region 9 is L2, and L2 is preferably 30 μm.

[0152] Furthermore, the finished device prepared in this embodiment has a thickness of 1000 μm and a breakdown voltage (VDRM) of 200V.

[0153] Example 3

[0154] Embodiment 3 provides a bidirectional non-steady-state switch type surge protection device, which is different from Embodiment 1 in that the main structure adopts a bidirectional TSS device to achieve a bidirectional protection function. Other structures and preparation methods are similar to those of Embodiment 1 and will not be described in detail here.

[0155] As a preferred embodiment, wherein Fig.11 and Fig.12 As shown, it also includes:

[0156] A second TSS device region TSS2 is formed in the first region 201 . The second TSS device region TSS2 is formed in the substrate 1 symmetrically with the first TSS device region TSS1 to share the same substrate 1 .

[0157] The first electrode of the second TSS device region TSS2 is connected to the second electrode of the first TSS device region TSS1 , and the second electrode of the second TSS device region TSS2 is connected to the first electrode of the first TSS device region TSS1 .

[0158] Specifically, in this embodiment, a bidirectional TSS device is formed by two unidirectional TSS devices with opposite structures to form a bidirectional conduction path. The formation principle and working principle of the bidirectional TSS device are similar to those of the unidirectional TSS device in the above technical solution.

[0159] The first TSS device region TSS1 and the second TSS device region TSS2 can share the same first resistance region 9, introducing an unstable state to the first TSS device region TSS1 and the second TSS device region TSS2, thereby effectively reducing the failure rate of the TSS device and improving its surge capability under low current conditions.

[0160] Furthermore, the second TSS device region TSS2 is centrally symmetric to the first TSS device region TSS1 , that is, in the second region, the first TSS device region TSS1 rotates 180 degrees around a certain point and can completely overlap with the second TSS device region TSS2 after the rotation.

[0161] As a preferred embodiment, the second TSS device region TSS2 includes:

[0162] a third transistor Q3, wherein the emitter of the third transistor Q3 forms a first electrode of the second TSS device region TSS2;

[0163] The fourth transistor Q4, the base of the fourth transistor Q4 is connected to the collector of the third transistor Q3, the collector of the fourth transistor Q4 is connected to the base of the third transistor Q3, and the emitter of the fourth transistor Q4 forms the second electrode of the second TSS device region TSS2.

[0164] Specifically, in this embodiment, the third transistor Q3 is an NPN transistor, and the fourth transistor Q4 is a PNP transistor.

[0165] Specifically, the first TSS device region TSS1 is composed of an NPN-type third transistor Q3 and a PNP-type PNP-type transistor, and the bases and collectors of the two transistors are cross-connected.

[0166] Further, the collector of the first triode Q1, the base of the second triode Q2, the collector of the third triode Q3 and the base of the fourth triode Q4 are connected together.

[0167] As a preferred embodiment, the substrate 1 has a first conductivity type;

[0168] In this embodiment, the first conductivity type is N-type and the second conductivity type is P-type as an example, that is, the N-type doped substrate 1 process is adopted, and the resistivity of the substrate 1 is greater than 1Ωcm.

[0169] like Fig.11 As shown, the first area 201 includes:

[0170] A first doping region 3 of a second conductivity type is formed in the substrate 1 by doping from the first surface of the substrate 1;

[0171] A fourth doping region 10 of the second conductivity type is formed in the substrate 1 by doping from the second surface of the substrate 1;

[0172] A third doping region 5 of the first conductivity type, formed in the first doping region 3;

[0173] A fifth doping region 11 of the first conductivity type is formed in the fourth doping region 10, and the fifth doping region 11 is staggered with the third doping region 5;

[0174] A sixth heavily doped region 12 of the second conductivity type is formed by doping in the first doped region 3 from the first surface of the substrate 1 and penetrates the first doped region 3 to the substrate 1;

[0175] A seventh heavily doped region 13 of the second conductivity type is doped and formed in the fourth doped region 10 from the second surface of the substrate 1 and penetrates the fourth doped region 10 to the substrate 1, and the seventh heavily doped region 13 is staggered with the sixth heavily doped region 12;

[0176] The third doping region 5, the first doping region 3, the substrate 1, and the seventh heavily doped region 13 form a first TSS device region TSS1, and the fifth doping region 11, the fourth doping region 10, the substrate 1, and the sixth heavily doped region 12 form a second TSS device region TSS2.

[0177] Specifically, in this embodiment, the N-type third doping region 5 , the P-type first doping region 3 , the N-type doped substrate 1 , and the P+ type seventh heavily doped region 13 form a first TSS device region TSS1 of an NPNP structure.

[0178] Among them, the N-type third doping region 5, the P-type first doping region 3 and the N-type doped substrate 1 constitute the NPN-type first transistor Q1, and the P-type first doping region 3, the N-type doped substrate 1 and the P+ type seventh heavily doped region 13 constitute the PNP-type second transistor Q2.

[0179] Specifically, the N-type fifth doping region 11 , the P-type fourth doping region 10 , the N-type doped substrate 1 , and the P+ type sixth heavily doped region 12 form a second TSS device region TSS2 of an NPNP structure.

[0180] Among them, the N-type fifth doping region 11, the P-type fourth doping region 10 and the N-type doped substrate 1 constitute the NPN-type third transistor Q3, and the P-type fourth doping region 10, the N-type doped substrate 1 and the P+ type sixth heavily doped region 12 constitute the PNP-type fourth transistor Q4.

[0181] Specifically, in this embodiment, the doping concentration of the sixth heavily doped region 12 is greater than the doping concentration of the first doped region 3 , and the doping concentration of the seventh heavily doped region 13 is greater than the doping concentration of the fourth doped region 10 .

[0182] The sixth heavily doped region 12 and the seventh heavily doped region 13 can shorten the longitudinal length of the substrate 1. At the same time, the doping concentrations of the first doped region 3 and the fourth doped region 10 are increased to form a better ohmic contact.

[0183] As a preferred embodiment, the through isolation region 2 is also used to separate the substrate 1 into a third region that is independent of the first region 201 and the second region 202;

[0184] Also includes:

[0185] The second resistance region 15 is formed in the third region, and the second resistance region 15 is connected in parallel between the first electrode and the second electrode of the second TSS device region TSS2.

[0186] Specifically, in this embodiment, the second resistance area 15 is connected in parallel with the first resistance area 9 .

[0187] In this embodiment, the third region and the first region 201 are respectively located on two sides of the second region 202 , that is, the second resistance region 15 and the first resistance region 9 are respectively located on two sides of the first region.

[0188] In this embodiment, the second resistor region 15 is also connected in parallel between the first electrode and the second electrode of the second TSS device region TSS2 through the metal layer 8 .

[0189] As a preferred embodiment, the distance between the edge of the fifth doping region 11 and the edge of the second resistance region 15 is 30 μm to 360 μm.

[0190] Furthermore, the distance between the edge of the third doping region 5 and the edge of the first resistance region 9 is the same as the distance between the edge of the fifth doping region 11 and the edge of the second resistance region 15 .

[0191] Further, in this embodiment, if Fig.11 As shown, the third distance between the edge of the third doping region 5 and the edge of the first resistance region 9 is L3, and L3 is preferably 60 μm.

[0192] As a preferred embodiment, the second resistance area 15 includes one.

[0193] As a preferred embodiment, the second resistance region 15 is the substrate 1 in a region where the third region separated by two adjacent through isolation regions 2 is located.

[0194] As a preferred embodiment, the width of the second resistance region 15 is 1 μm to 200 μm.

[0195] As a preferred embodiment, the resistance of the second resistance area 15 is 500KΩ-100MΩ.

[0196] Specifically, in this embodiment, only one second resistor region 15 may be provided, and the resistance value of the second resistor R2 can be adjusted by adjusting the width of the second resistor region 15 .

[0197] As a preferred embodiment, the fifth doping region 11 is a continuous doping region.

[0198] In this embodiment, the fifth doping region 11 is less deep than the fourth doping region 10 in the longitudinal direction of the device.

[0199] In this embodiment, the third doping region 5 and the fifth doping region 11 serve as the emission region of the device.

[0200] As a preferred embodiment, the fifth doping region 11 is a plurality of sub-doping regions arranged at intervals.

[0201] Specifically, the emitter region adopts a short-circuit structure, and a plurality of sub-doped regions are arranged in an interval manner to increase the device holding current IH, thereby optimizing the overall performance of the device.

[0202] As a preferred embodiment, the first area 201 further includes:

[0203] At least one second voltage divider ring region 14 of a second conductivity type is formed in the substrate 1 by doping from the second surface of the substrate 1 .

[0204] In this embodiment, a gap exists between the second voltage dividing ring region 14 and the edge of the fourth doping region 10 .

[0205] In this embodiment, the doping concentration of the second voltage divider ring area 14 is greater than the doping concentration of the fourth doping area 10. Preferably, the second voltage divider ring area 14 is a P++ type voltage divider ring. The second voltage divider ring area 14 can improve the reverse biased electric field morphology of the PN junction formed by the P-type fourth doping area 10 and the N-type doped substrate 1, thereby effectively improving the product withstand voltage.

[0206] Furthermore, the thickness of the finished device prepared in this embodiment is 250 μm.

[0207] Example 4

[0208] This embodiment 4 provides a bidirectional non-stable switch type surge protection device, the device body also adopts a bidirectional TSS structure to achieve a bidirectional protection function. The difference between it and embodiment 3 is that the body resistor adopts a series structure.

[0209] The other structures and preparation methods are similar to those in Example 3 and will not be described in detail here.

[0210] As a preferred embodiment, wherein Fig.13 and Fig.14 As shown, the first resistance area 9 includes two or more first resistance areas 9, and the two or more first resistance areas 9 are connected in series; and / or

[0211] The second resistance areas 15 include two or more, and the two or more second resistance areas 15 are connected in series.

[0212] In this embodiment, two or more first resistance regions 9 are connected in series via the metal layer 8 .

[0213] In this embodiment, two or more second resistance regions 15 are connected in series through the metal layer 8 .

[0214] Specifically, in this embodiment, the embodiment of the present invention can remove the resistance area on one side, and the remaining resistance area on one side is set to multiple to form a structure in which multiple resistors are connected in series.

[0215] like Fig.13 and Fig.14 As shown, it is taken as an example that the second resistance area 15 is removed, the first resistance area 9 is retained, and the first resistance area 9 is set to three, namely, the first sub-resistor R11, the second sub-resistor R12 and the third sub-resistor R13.

[0216] Among them, the first end of the first sub-resistor R11 is electrically connected to the first electrode of the first TSS device (or the second electrode of the second TSS device) through the metal layer 8, the second end of the first sub-resistor R11 is electrically connected to the first end of the second sub-resistor R12 through the metal layer 8, the second end of the second sub-resistor R12 is electrically connected to the first end of the third sub-resistor R13 through the metal layer 8, and the second end of the third sub-resistor R13 is electrically connected to the second electrode of the first TSS device (or the first electrode of the second TSS device) through the metal layer 8.

[0217] Specifically, the first dielectric layer 71 covers the edge of the seventh heavily doped region 13 and the edge of the first sub-resistor R11 , and the second dielectric layer 72 covers the through isolation region 2 between the first sub-resistor R11 and the second sub-resistor R12 .

[0218] The third dielectric layer 73 is connected across the first dielectric layer 71 and the second dielectric layer 72 so that the metal layer used for electrical connection at the second end of the first sub-resistor R11 and the first end of the second sub-resistor R12 is isolated by the dielectric layer 7, so that the first sub-resistor R11, the second sub-resistor R12 and the third sub-resistor R13 are connected in series to increase the resistance value of the parallel resistor of the TSS device.

[0219] Furthermore, the resistance areas on both sides may be retained at the same time, and the specific number of resistance areas on both sides may be selected as needed.

[0220] Example 5

[0221] Embodiment 5 provides a unidirectional non-stable switch type surge protection device, which is different from Embodiment 1 in that the device adopts a table passivation process. Specifically, the first voltage divider ring area 66 in Embodiment 1 is replaced by a groove structure, and the cutoff function is achieved by using glass passivation technology.

[0222] As a preferred embodiment, wherein Fig.15 As shown, the first area 201 also includes:

[0223] A first trench 16 is formed in the substrate 1 from the first surface of the substrate 1 and is located at both sides of the first doping region 3, and the depth of the first trench 16 is greater than the depth of the first doping region 3;

[0224] The glass passivation layer 17 fills the first groove 16 , and the upper surface of the glass passivation layer 17 is flush with the first surface of the substrate 1 .

[0225] Specifically, in this embodiment, the terminal structure is formed by using the trench technology and the glass passivation technology to replace the first voltage divider ring area of ​​the embodiment 1, which can improve the withstand voltage of the device, improve the reliability of the device, and reduce leakage.

[0226] Furthermore, after forming the third doping region 5 and before preparing the dielectric layer, the first trench 16 and the glass passivation layer 17 are prepared, and the preparation process is as follows:

[0227] First, a wet etching process is used to form first trenches 16 on both sides of the first doping region 3 in the substrate 1;

[0228] Then, the photoresist method is used to fill the grooves with photoresist material containing glass powder, and then sintering is performed. Under high temperature environment, the photoresist containing glass powder undergoes pyrolysis and melting, and the glass component gradually fills and solidifies inside the grooves to form a dense glass passivation layer.

[0229] Through the insulating properties of the trench structure and the glass passivation structure, the adverse effects that may be caused by the external environment on the inside of the device are effectively isolated, thereby improving the overall reliability and voltage resistance of the device.

[0230] Example 6

[0231] The device structure and preparation method formed in Example 6 are similar to those in Example 1, except that the N-type in Example 1 is changed to P-type and the P-type is changed to N-type, that is, the first conductivity type is P-type and the second conductivity type is N-type.

[0232] The equivalent circuit is Fig.16 As shown, in this embodiment, the first transistor Q1 is a PNP transistor, and the second transistor Q2 is an NPN transistor. Therefore, they will not be described in detail here.

[0233] The advantages or beneficial effects of adopting the above technical solution are: the present invention connects a parallel body resistor between the two electrodes of the TSS device. When a small current passes through, the parallel body resistor can effectively reduce the voltage across the device; when a large current passes through, the local temperature increase caused by the heat generated by the body resistor is utilized to affect the IBO parameters of the TSS device, so that the device enters the on state in advance. The TSS device in the on state can lower the voltage at the resistor end, thereby reducing the current level flowing through the resistor.

[0234] The above are only preferred embodiments of the present invention, and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the contents of this specification and illustrations should be included in the protection scope of the present invention.

Claims

1. An unstable switching type surge protection device, characterized in that: include: a substrate comprising a first side and a second side opposite to each other; A through isolation region is formed through the substrate to separate the substrate into a first region and a second region that are independent of each other; a first TSS device region formed in the first region; a first resistance region formed in the second region; A dielectric layer is formed on surfaces of a first surface and a second surface of the substrate respectively, and windows corresponding to the first area and the second area are formed in the dielectric layers on the first surface and the second surface of the substrate respectively; A metal layer is formed on the surface of the dielectric layer and fills the window. The first resistor region is connected in parallel between the first electrode and the second electrode of the first TSS device region through the metal layer.

2. The non-steady-state switch type surge protection device according to claim 1, characterized in that: The first TSS device region comprises: a first triode, wherein an emitter of the first triode forms a first electrode of the first TSS device region; A second transistor, wherein the base of the second transistor is connected to the collector of the first transistor, the collector of the second transistor is connected to the base of the first transistor, and the emitter of the second transistor forms the second electrode of the first TSS device region.

3. The non-steady-state switch type surge protection device according to claim 1, characterized in that: The substrate has a first conductivity type; The first area includes: A first doped region of a second conductivity type is formed in the substrate by doping from a first surface of the substrate; A second doping region of a second conductivity type is formed in the substrate by doping from a second surface of the substrate; A third doping region of the first conductivity type, formed in the first doping region; The third doping region, the first doping region, the substrate, and the second doping region form the first TSS device region.

4. The non-steady-state switch type surge protection device according to claim 3, characterized in that: The first area also includes: A first trench is formed in the substrate from the first surface of the substrate and is located at both sides of the first doping region, wherein the depth of the first trench is greater than the depth of the first doping region; A glass passivation layer is filled in the first groove, and the upper surface of the glass passivation layer is flush with the first surface of the substrate.

5. The non-steady-state switch type surge protection device according to claim 1, characterized in that: The first resistance region comprises one; or The first resistance areas include two or more, and the two or more first resistance areas are connected in series.

6. The non-steady-state switch type surge protection device according to claim 1, characterized in that: The first resistance region is a substrate of a region where the second region separated by two adjacent through isolation regions is located.

7. The non-steady-state switch type surge protection device according to claim 1, characterized in that: The width of the first resistance region is 1 μm to 200 μm.

8. The non-steady-state switch type surge protection device according to claim 1, characterized in that: The resistance of the first resistance zone is 500KΩ to 100MΩ.

9. The non-steady-state switch type surge protection device according to claim 1, characterized in that: Also includes: A second TSS device region is formed in the first region, wherein the second TSS device region is formed in the substrate symmetrically with the first TSS device region to share the same substrate; The first electrode of the second TSS device region is connected to the second electrode of the first TSS device region, and the second electrode of the second TSS device region is connected to the first electrode of the first TSS device region.

10. The non-steady-state switch type surge protection device according to claim 9, characterized in that: The second TSS device region comprises: a third triode, wherein an emitter of the third triode forms a first electrode of the second TSS device region; A fourth triode, the base of the fourth triode is connected to the collector of the third triode, the collector of the fourth triode is connected to the base of the third triode, and the emitter of the fourth triode forms the second electrode of the second TSS device region.

11. The non-steady-state switch type surge protection device according to claim 10, characterized in that: The substrate has a first conductivity type; The first area includes: A first doped region of a second conductivity type is formed in the substrate by doping from a first surface of the substrate; A fourth doped region of the second conductivity type is formed in the substrate by doping from the second surface of the substrate; A third doping region of the first conductivity type, formed in the first doping region; A fifth doping region of the first conductivity type is formed in the fourth doping region, and the fifth doping region is staggered with the third doping region; A sixth heavily doped region of the second conductivity type is formed by doping in the first doped region from the first surface of the substrate and penetrates the first doped region into the substrate; A seventh heavily doped region of the second conductivity type is doped from the second surface of the substrate into the fourth doped region and penetrates the fourth doped region into the substrate, and the seventh heavily doped region is staggered with the sixth heavily doped region; The third doping region, the first doping region, the substrate, and the seventh heavily doped region form the first TSS device region, and the fifth doping region, the fourth doping region, the substrate, and the sixth heavily doped region form the second TSS device region.

12. The non-steady-state switch type surge protection device according to claim 3 or 11, characterized in that: The third doping region is a continuous doping region; or The third doping region is a plurality of sub-doping regions arranged at intervals.

13. The non-steady-state switch type surge protection device according to claim 3 or 11, characterized in that: The distance between the edge of the third doping region and the edge of the first resistance region is 30 μm to 360 μm.

14. The non-stable switching type surge protection device according to claim 3 or 11, characterized in that: The first area also includes: At least one first voltage divider ring region of a second conductivity type is formed in the substrate by doping from the first surface of the substrate.

15. The non-steady-state switch type surge protection device according to claim 11, characterized in that: The fifth doping region is a continuous doping region; or The fifth doping region is a plurality of sub-doping regions arranged at intervals.

16. The non-steady-state switch type surge protection device according to claim 11, characterized in that: The first area also includes: At least one second voltage divider ring region of a second conductivity type is formed in the substrate by doping from the second surface of the substrate.

17. The non-steady-state switch type surge protection device according to claim 11, characterized in that: The through isolation region is also used to separate the substrate into a third region that is independent of the first region and the second region; Also includes: A second resistance region is formed in the third area, and the second resistance region is connected in parallel between the first electrode and the second electrode of the second TSS device region.

18. The non-steady-state switch type surge protection device according to claim 17, characterized in that: The distance between the edge of the fifth doping region and the edge of the second resistance region is 30 μm to 360 μm.

19. The non-steady-state switch type surge protection device according to claim 17, characterized in that: The second resistance region comprises one; or The second resistance areas include two or more, and the two or more second resistance areas are connected in series.

20. The non-steady-state switch type surge protection device according to claim 17, characterized in that: The second resistance region is a substrate of a region where the third region separated by two adjacent through isolation regions is located.

21. The non-steady-state switch type surge protection device according to claim 17, characterized in that: The width of the second resistance region is 1 μm to 200 μm.

22. The non-steady-state switch type surge protection device according to claim 17, characterized in that: The resistance of the second resistance zone is 500KΩ to 100MΩ.

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