Method and equipment for L5 direct acquisition and NH bit synchronization

Abstract

A method and apparatus are provided in which data is loaded from memory to an input sample memory (ISM) of a user equipment (UE). The data corresponds to an input from an L5 antenna of the UE. A first high resolution correlation (HRC) engine of the UE performs coherent correlation and accumulation on the data for at least one code-frequency offset combination to generate coherent correlation results. A second HRC engine of the UE processes the coherent correlation results by performing at least frequency widening and non-coherent accumulation to generate non-coherent correlation results indicating at least peak accumulation of correlation.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Application No. 63 / 581,854, filed in the U.S. Patent and Trademark Office on September 11, 2023, the disclosure of which is incorporated herein by reference in its entirety as if fully set forth herein. Technical Field

[0003] The present disclosure generally relates to the acquisition of Global Navigation Satellite System (GNSS) signals. More specifically, the subject matter disclosed herein relates to the direct acquisition of GNSS L5 signals. Background Art

[0004] The Global Positioning System (GPS) is available for civilian use, utilizing the L1 (1575.42 megahertz (MHz)) signal, followed by the L2 (1227.60 MHz) signal. The chip rate of the pseudo-noise (PN) code modulated onto these signals and used to acquire and track signals from satellites is within 1 MHz for both the L1 and L2 signals. The PN chip rate and PN code length of the GPS L5 (1176.45 MHz) "modernized" signal are ten times that of the L1 signal. Because the PN code is faster and longer, acquisition of the L5 signal is more difficult than acquisition of the L1 and L2 signals.

[0005] To solve this problem, the L1 or L2 signal is acquired and tracked first. Information from the tracked channel is used to narrow the time / frequency search for acquiring the L5 signal.

[0006] One problem with the above approach is that a requirement arises to directly acquire the L5 signal without first acquiring the L1 or L2 signal. Summary of the invention

[0007] To overcome these problems, systems and methods for L5 direct acquisition and L5 Neumann Hoffman (NH) synchronization functions are described herein.

[0008] The above methods improve upon previous methods because they do not require acquisition and tracking of L1 or L2 signals to narrow the time / frequency search. Thus, the GNSS system can operate in L1-only mode, L5-only mode, or L1 and L5 modes, allowing the flexibility to operate in the most efficient configuration for power and performance.

[0009] In an embodiment, a method is provided in which data is loaded from a memory to an input sample memory (ISM) of a user equipment (UE). The data corresponds to an input from an L5 antenna of the UE. A first high resolution correlation (HRC) engine of the UE performs coherent correlation and accumulation on the data for at least one code-frequency offset combination to generate a coherent correlation result. A second HRC engine of the UE processes the coherent correlation result by performing at least frequency widening and non-coherent accumulation to generate a non-coherent correlation result indicating at least a peak accumulation of correlation.

[0010] In an embodiment, a UE is provided, comprising an ISM configured to store data from a memory. The data corresponds to an input from an L5 antenna of the UE. The UE further comprises a first HRC engine configured to perform coherent correlation and accumulation on the data for at least one code-frequency offset combination to generate a coherent correlation result. The UE further comprises a second HRC engine configured to process the coherent correlation result by performing at least frequency broadening and non-coherent accumulation to generate a non-coherent correlation result indicating at least a peak accumulation of correlation.

[0011] In an embodiment, a UE is provided, comprising a processor and a non-transitory computer-readable storage medium storing instructions. When executed, the instructions cause the processor to load data from a memory to an ISM of the UE. The data corresponds to an input from an L5 antenna of the UE. The instructions also cause the processor to perform coherent correlation and accumulation on the data for at least one code-frequency offset combination by a first HRC engine of the UE to generate a coherent correlation result. The instructions also cause the processor to: process the coherent correlation result by a second HRC engine of the UE by performing at least frequency broadening and non-coherent accumulation to generate a non-coherent correlation result indicating at least a peak accumulation of correlation. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In the following sections, various aspects of the subject matter disclosed herein will be described with reference to exemplary embodiments shown in the accompanying drawings, in which:

[0013] Figure 1 is a diagram showing a communication system according to an embodiment;

[0014] Figure 2 is a diagram showing a GNSS signal processing system according to an embodiment;

[0015] Figure 3 is a diagram showing a system for L5 signal direct acquisition processing according to an embodiment;

[0016] Figure 4 is a diagram showing a system for L5 signal direct acquisition processing in NH synchronization mode according to an embodiment;

[0017] Figure 5 is a diagram showing a data flow and a processing order for L5 signal direct acquisition processing according to an embodiment;

[0018] Figure 6 is a diagram showing a data flow and a processing order for L5 signal direct acquisition processing in NH synchronization mode according to an embodiment;

[0019] Figure 7 is a flow chart illustrating a method for L5 signal direct acquisition processing at a unified configurable HRC (ucHRC) SS2 according to an embodiment;

[0020] Figure 8 is a flow chart illustrating a method for L5 signal direct acquisition processing at ucHRC SS3 according to an embodiment;

[0021] Fig. 9 is a flowchart showing a method for L5 signal direct acquisition processing in NH synchronization mode according to an embodiment;

[0022] Fig.10 is a diagram showing a code and frequency execution order for L5 signal direct acquisition according to an embodiment;

[0023] Fig.11 is a diagram showing a form of storage for correlation processing at an ISM according to an embodiment

[0024] Fig.12 is a diagram showing a code step example for L5 signal direct acquisition according to an embodiment;

[0025] Fig.13 is a diagram showing a processing order of NH alignment for each pre-detection integration interval (PDI) according to an embodiment;

[0026] Fig.14 is a diagram showing an ISM for L5 signal direct acquisition according to an embodiment;

[0027] Fig.15 is a diagram showing an ISM for L5 signal direct acquisition in NH synchronization mode according to an embodiment;

[0028] Fig.16 is a diagram illustrating ucHRC RAM coherent buffer storage according to an embodiment;

[0029] Fig.17 is a diagram showing an NCS structure for L5 signal direct acquisition according to an embodiment;

[0030] Fig.18is a diagram showing an NCS structure for L5 signal direct acquisition in NH synchronization mode according to an embodiment;

[0031] Fig.19 is a diagram showing a peak area buffer for L5 signal direct acquisition according to an embodiment;

[0032] Fig. 20 is a diagram showing a sequence for updating peak values ​​and peak regions according to an embodiment;

[0033] Fig.21 is a diagram showing a ucHRC SS2 data flow in L5 signal direct acquisition according to an embodiment;

[0034] Fig. 22 is a diagram showing a ucHRC SS3 data flow in L5 signal direct acquisition according to an embodiment;

[0035] Fig.23 is a diagram showing a ucHRC SS3 data flow in L5 signal direct acquisition in NH synchronization mode according to an embodiment;

[0036] Fig.24 is a flowchart illustrating a method for L5 signal direct acquisition processing according to an embodiment; and

[0037] Fig.25 is a block diagram of an electronic device in a network environment according to an embodiment. DETAILED DESCRIPTION

[0038] In the following detailed description, many specific details are set forth in order to provide a thorough understanding of the present disclosure. However, those skilled in the art will appreciate that the disclosed aspects may be practiced without these specific details. In other instances, well-known methods, processes, components, and circuits are not described in detail to avoid obscuring the subject matter disclosed herein.

[0039] References to "one embodiment" or "an embodiment" throughout the specification mean that the specific features, structures, or characteristics described in conjunction with the embodiment may be included in at least one embodiment disclosed herein. Therefore, the phrases "in one embodiment" or "in an embodiment" or "according to an embodiment" (or other phrases with similar meanings) that appear throughout this specification may not necessarily all refer to the same embodiment. In addition, the specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In this regard, as used herein, the word "exemplary" means "used as an example, instance, or illustration". Any embodiment described herein as "exemplary" should not be interpreted as necessarily being preferred or advantageous over other embodiments. In addition, the specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In addition, depending on the context discussed herein, a singular term may include a corresponding plural form, and a plural term may include a corresponding singular form. Similarly, hyphenated terms (e.g., "two-dimensional," "predetermined," "pixel-specific," etc.) may occasionally be used interchangeably with corresponding non-hyphenated versions (e.g., "two-dimensional," "predetermined," "pixel-specific," etc.), and capitalized terms (e.g., "Counter Clock," "Row Select," "PIXOUT," etc.) may be used interchangeably with corresponding non-capitalized versions (e.g., "counter clock," "row select," "pixout," etc.). Such occasional interchangeable usage should not be considered inconsistent with each other.

[0040] In addition, depending on the context of the discussion herein, singular terms may include corresponding plural forms, and plural terms may include corresponding singular forms. It should also be noted that the various drawings (including component drawings) shown and discussed herein are for illustrative purposes only and are not drawn to scale. For example, for clarity, the size of some elements may be enlarged relative to other elements. In addition, if deemed appropriate, reference numerals are repeated in the drawings to indicate corresponding and / or similar elements.

[0041] The terms used herein are only used for the purpose of describing some example embodiments and are not intended to limit the claimed subject matter. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "include" and / or "comprise" specify the presence of the features, integers, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups thereof.

[0042] It should be understood that when an element or layer is referred to as being on, "connected to" or "coupled to" another element or layer, it can be directly on, directly connected to or coupled to another element or layer, or there can be intermediate elements or layers. In contrast, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element or layer, there are no intermediate elements or layers. The same reference numerals always refer to the same elements. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items.

[0043] As used herein, the terms "first", "second", etc. are used as labels for the nouns that precede them and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) unless explicitly defined as such. In addition, the same figure mark may be used across two or more figures to refer to parts, components, blocks, circuits, units, or modules with the same or similar functions. However, such use is only for simplicity of illustration and ease of discussion; it does not mean that the construction or architectural details of such components or units are the same in all embodiments, or that such commonly referenced parts / modules are the only way to implement some example embodiments disclosed herein.

[0044] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the subject matter belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly so defined herein.

[0045] As used herein, the term "module" refers to any combination of software, firmware, and / or hardware configured to provide the functionality described herein in conjunction with the module. For example, software may be embodied as a software package, code, and / or instruction set or instructions, and the term "hardware" as used in any embodiment described herein may include, for example, components, hardwired circuits, programmable circuits, state machine circuits, and / or firmware storing instructions executed by programmable circuits, either alone or in any combination. Modules may be collectively or individually embodied as circuits forming part of a larger system, such as, but not limited to, an integrated circuit (IC), a system on a chip (SoC), a component, and the like.

[0046] Figure 1 is a diagram showing a communication system according to an embodiment. Figure 1In the illustrated architecture, a control path 102 may enable the transmission of control information through a network established between a base station, access point (AP) or gNode B (gNB) 104, a first user equipment (UE) 106, and a second UE 108. A data path 110 may enable the transmission of data (and some control information) between the first UE 106 and the second UE 108. The control path 102 and the data path 110 may be on the same frequency or may be on different frequencies. A satellite 112 may provide GNSS signals to the first UE 106 and the second UE 108.

[0047] Figure 2 2 is a diagram showing a GNSS signal processing system according to an embodiment. The system includes a front end processor (FEP) 202, which can receive radio frequency (RF) inputs from two antennas after the RF inputs have been converted into digital data streams. The FEP 202 can perform digital mixing, filtering, noise removal, and quantization. The resulting data streams can be output from the FEP 202 and can be stored in a set of circular buffers or input sample memories 204 with various data widths and various sampling frequencies. The ISM 204 can have regions of different global network satellite systems (GNSS) (e.g., Galileo, Beidou, Glonass, and GPS L1) for normal resolution correlator engines 208 to process, and regions of different GNSS (e.g., Beidou L5, GPS L5, and GPS L1) for ucHRC 210 to process. The ISM 204 can also store playback data from a double data rate (DDR) memory 206, which can be an external random access memory (RAM).

[0048] The data from the ISM 204 can be processed in a time-division multiplexed manner by two correlator engines 208 and 210. Specifically, the data from the ISM 204 can be replayed into the correlator engines 208 and 210 at a very high rate so that various satellite constellations (e.g., GPS, Galileo, BeiDou, and Glonass) can be simultaneously acquired and tracked by the correlator engines 208 and 210. The normal resolution correlator engine (e.g., waverider) 208 can be used to acquire and track normal resolution ISM data. Specifically, the normal resolution correlator engine 208 can process live data for acquisition, reacquisition, or tracking, and can process playback data for acquisition, test reacquisition, or test tracking.

[0049] The ucHRC 210 can track L5 signals. Specifically, the ucHRC 210 can process ISM data of higher frequency and larger data width (number of bits) than the normal resolution correlator engine 208, but therefore, it can only search a smaller time / frequency window to find new signals. Specifically, the ucHRC 210 can process live data for reacquisition or tracking, can process playback data for test reacquisition or test tracking, and can process on-demand playback data for L5 direct acquisition.

[0050] Data from the correlator engines 208 and 210 can be provided to highly configurable memory. Digital signal processing (DSP) RAM 212 can be accessed for normal resolution correlator engine processing and report dumps from ucHRC processing. RAM 214 can be accessed for ucHRC processing.

[0051] Figure 3 is a diagram showing a system for L5 signal direct acquisition processing according to an embodiment. L5 ISM data has high resolution and high PN code chip rate, and may need to search 20460 PN code chips per millisecond (ms). The frequency range searched may require six frequency steps.

[0052] Figure 3 The system can adapt the basic structure of ucHRC processing with added functionality that allows the L5 signal to be acquired directly with a sufficiently wide search window for the required L5 time / frequency uncertainty, without using information obtained from L1 or L2 signal tracking. This can be done by processing the live data from the L5 antenna through the FEP and saving the resulting data in the large external DDR memory 302 instead of Figure 2 The ucHRC may be used to capture a large buffer of data in the normal cycle ISM 204. The ISM 204 may contain a continuous data stream with a moving window of about a few ms long, while the external DDR memory 302 may hold a single snapshot that may be hundreds of ms long. The DDR memory 302 may capture data from the real-time data processing. Once the DDR memory 302 captures the data from the real-time data processing, the data may be repeatedly played back into the ucHRC, once for each L5 satellite being captured. This playback of data may be under the control of the ISM direct memory access (DMA) controller 304 and may be pulled in by the correlation engine processing as needed.

[0053] Thus, data can be pulled from the DDR memory 302 into the cyclic 3ms ISM 306 1 ms at a time. Although described with respect to specific data intervals and ISM sizes, Figure 3, but the embodiments are not limited thereto. For example, if the NH alignment is known, weak signal acquisition can be performed with a longer PDI. The ISM 306 can be in the ucHRC memory or the DSP RAM. The first coherent correlator engine (e.g., ucHRC subsystem 2 (SS2)) 308 can process 1ms of data for an array of time and frequency offsets, and can accumulate and store the results of each time / frequency offset in a ping-pong manner in a coherent integration time (CIT) memory 310. Each ping area and each pong area can have four CIT areas, and each CIT area can include 320 correlator taps. When the ucHRC SS2 308 processes the time / frequency offset and stores it in the CIT memory 310 (e.g., ping), the second coherent correlator engine (e.g., ucHRC subsystem 3 (SS3)) 312 can read and process the previous coherent data stored in the CIT memory 310 (e.g., from the pong area). Therefore, ucHRC SS2 308 and ucHRC SS3 312 can slide within the time and frequency range required for L5 acquisition.

[0054] ucHRC SS2 308 may perform coherent correlation and accumulation, which compares the ISM data to a unique reference code (e.g., a PN code) modulated onto the signal from each satellite. The proper time / frequency alignment may be found by correlating the input signal with various time alignments and frequency offsets, accumulating the correlations over time, and looking for the peak accumulation. All other time / frequency alignments may look like noise and may have low accumulation values.

[0055] ucHRC SS3 312 can retrieve coherent data (e.g., data in complex I / Q form) from CIT memory 310 and perform additional processing at fast Fourier transform (FFT) module 314, frequency selection module 316, and non-coherent summation (NCS) module 318. FFT module 314 can allow the generation of additional frequency bins, which can be used to widen the frequency range covered by each time / frequency offset. Specifically, FFT module 314 can perform a four-input eight-point FFT, which outputs eight frequency values ​​for each of 320 correlator taps. Frequency selection module 316 can discard the outer frequency bins and select the center 5 frequency bins. NCS module 318 can allow non-coherent (amplitude instead of I / Q) accumulation of signals over a longer period of time than coherent summation can cover. Without this additional processing, the L5 signal structure can limit the coherent accumulation to 1ms. By taking the complex data output of the FFT and converting them to amplitude (incoherent data), the signal can accumulate NCS over a long period of time (such as hundreds of ms). This can allow the correct time / frequency offset to become larger than other offsets, which can be interpreted as noise.

[0056] The processing results at ucHRC SS3 312 may be stored in DSP RAM 320. NCS accumulation may be used as a scratch region and may be discarded after peaks and reports are generated. The report may include peaks, peak regions, and associated parameters, as described in more detail below.

[0057] Figure 4 1 is a diagram showing a system for L5 signal direct acquisition processing in NH synchronization mode according to an embodiment. Specifically, the L5 signal may include an NH code modulated on top of the original signal and a PN code. Each NH code bit is 1 ms long, and the NH code bit is repeated every 100 ms. Although the specific code bit length and repetition are described Figure 4 , but the embodiments are not limited thereto and may be different for different signals. The L5 signal direct acquisition process may find the correct time / frequency of the signal within 1 ms by limiting the coherent integration to 1 ms, but this does not inform which of the 100 possible repeated NH code alignments is correct. This determination may be performed by the L5 signal NH synchronization mode. Only one code step and one frequency step are required because the NH bit synchronization is performed after the L5 signal direct acquisition has found the correct tap and frequency position.

[0058] As controlled by the ISM DMA controller 404, data may be pulled from the DDR memory 402 10 ms at initialization and then 4 ms at a time into the cyclic 10 ms ISM 406. Although described with respect to specific data intervals and ISM sizes, Figure 4 , but the embodiment is not limited thereto. The ISM 406 may be in the ucHRC memory or the DSP RAM. The ucHRC SS2 408 may process the 4ms data of the time and frequency offset array and may accumulate and store the results of each time / frequency offset into the CIT memory 410.

[0059] ucHRC SS2 408 may perform coherent correlation and accumulation, which compares the ISM data to a unique reference code (e.g., a PN code) modulated onto the signal from each satellite, as described above with respect to Figure 3 as described.

[0060] ucHRC SS3 412 may retrieve coherent data (e.g., data in complex I / Q form) from CIT memory 410. ucHRC SS3 412 repeatedly processes the CIT data, but for each pass, it uses a different NH code alignment at NH erasure module 422. Only a correct alignment will produce a large NCS signal. ucHRC SS3 412 may perform additional processing at FFT module 414, frequency selection module 416, and NCS module 418, as described above with respect to Figure 3 as described.

[0061] The results of processing at the ucHRC SS3 412 may be stored in the DSP RAM 420. The NCS accumulation may be used as a scratch region and may be discarded after peak generation and reporting.

[0062] Regarding handshake control, ucHRC SS2 can set (and ucHRC SS3 can reset) the "pdiAReady" parameter and the "pdiBReady" parameter, which informs ucHRC SS3 when it is ready to process ping or pong data. ucHRC SS3 can also set (and ucHRC SS2 can reset) the "termination" parameter to inform ucHRC SS2 that it has completed the processing (ncsCountMod) of all codes and frequency steps for all non-coherent residences (for example, processing 150ms of data in 150 PDIs), and ucHRC SS2 can move to the next channel. ucHRC SS2 can control the scaling value associated with the four CIT coherent accumulations of the PDI, information about the current channel being processed, and the location where the data is stored and used. ucHRC SS2 can also control information about the current count of the data being processed, such as, for example, code step, frequency step, NCS count, and NH step. The NCS count can be the current PDI number being processed, and the NH step can be the NH alignment offset number (for NH bit synchronization).

[0063] Figure 5 is a diagram showing the data flow and processing order for L5 signal direct acquisition processing according to an embodiment. New 1 ms data may be loaded from the DDR memory into the 3 ms cyclic ISM 502. The ucHRC SS2 504 may process the data once for each code step and each frequency step (e.g., (c0, f0), (c1, f0), ... (c63, f0), (c0, f1), ... (c63, f5)). After each step is processed by the ucHRC SS2 504, it stores the coherent correlation results at the CIT memory 506 in a ping-pong manner for processing by the ucHRC SS3 508, which is performed after the processing of the ucHRC SS2 504, as described above with respect to Figure 3 After all code steps and frequency steps are processed, the data for the next 1ms can be loaded into the ISM 502 from the DDR memory, or the data for the next 1ms can be preloaded into the ISM 502 while the current 1ms is in use. This process can be repeated until all data from the DDR memory is processed (e.g., 150 PDIs for each 1ms).

[0064] Figure 66 is a diagram showing the data flow and processing order for L5 signal direct acquisition processing in NH synchronization mode according to an embodiment. A new set of 4ms data can be loaded from the DDR memory into the 10ms cyclic ISM 602. The ucHRC SS2604 can process the data once and write the coherent correlation results directly and unmodulated into the CIT memory 606 once. Modulation of four 1ms CIT data with different NH alignments can be performed in the ucHRC SS3 608. For each NH alignment, the ucHRC SS3 608 can modulate each of the four 1ms CIT data with an NH bit (e.g., [NH(0), NH(1), NH(2), NH(3)], [NH(4), NH(5), NH(6), NH(7)], ...). After processing all NH alignments, the next 4ms of data can be loaded from the DDR memory into the ISM 602, or the next 4ms of data can be preloaded into the ISM 602 while the current 4ms is in use. This process may be repeated until all data from the DDR memory has been processed (eg, 150 / 4=37 PDIs each 4 ms).

[0065] Figure 7 704 is a flow chart showing a method for performing L5 signal direct acquisition processing at ucHRC SS2 according to an embodiment. The method starts at 702, and at 704, 3ms of data can be loaded from the DDR memory into the ISM, as described above with respect to Figure 3 and Figure 5 At 706, the ucHRC SS2 may reset the code step count, frequency step count, and NCS count. At 708, the ucHRC SS2 may process 1 ms of ISM data in a series of code and frequency steps, as described above with respect to Figure 5 At 710, ucHRC SS2 may determine whether the processed code / frequency step of the ISM data is at the final code step based on the code step count. If ucHRC SS2 determines that the processed code / frequency step of the ISM data is not at the final code step, ucHRC SS2 may increase the code step count at 712 and may return to 708 to process the next code / frequency step of the ISM data.

[0066] If the ucHRC SS2 determines that the processed code / frequency step of the ISM data is at the final code step, then at 714, the ucHRC SS2 may determine whether the processed code / frequency step of the ISM data is at the final frequency step. If the ucHRC SS2 determines that the processed code / frequency step of the ISM data is not at the final frequency step, then at 716, the ucHRC SS2 may increase the frequency step count and at 718, may reset the code step count before returning to 708 to process the next code / frequency step of the ISM data.

[0067] If ucHRC SS2 determines that the processed code / frequency step of the ISM data is at the final frequency step, then at 720, ucHRC SS2 may determine whether the processed 1ms of data is the final 1ms of data from the DDR memory. If ucHRC SS2 determines that the processed 1ms of data is not the last 1ms of data from the DDR memory, then ucHRC SS2 may request the next 1ms of data from the DDR memory at 722, increase the NCS count at 724, and reset the code step count and frequency step count at 726, and then return to 708 to process the code / frequency step of the next 1ms of data from the ISM. If the processed 1ms of data is the final 1ms of data from the DDR memory, then ucHRC SS3 may retain the NCS peak at 728 before processing the next channel.

[0068] Figure 8 806 and 808. FIG. 807 is a flowchart showing a method for performing L5 signal direct acquisition processing at ucHRC SS3 according to an embodiment. The method starts at 802 and ucHRC SS3 may be initialized at 804. ucHRC SS3 may wait for a PDI ready notification at 806 and may process a ready PDI at 808.

[0069] At 810, the ucHRC SS3 may determine whether the processed PDI is at the final code step. If the ucHRC SS3 determines that the PDI is not at the final code step, the ucHRC SS3 may update magSum at 812 and may wait for the next ready PDI at 814 before returning to 808 to process the next PDI. If the ucHRC SS3 determines that the PDI is at the final code step, the ucHRC SS3 may update magSum at 816 and may update bias, biasSum, and noiseSum at 818. At 820, the ucHRC SS3 may save the peak report.

[0070] At 822, ucHRC SS3 may determine whether the processed PDI is at the final frequency step. If ucHRC SS3 determines that the PDI is not at the final frequency step, ucHRC SS3 may reset magSum at 824 and may wait for the next ready PDI at 826 before returning to 808 to process the next PDI. If ucHRC SS3 determines that the PDI is at the final frequency step, ucHRC SS3 may determine whether the processed PDI is at the final PDI step at 828. If ucHRC SS3 determines that the processed PDI is not at the final PDI step, ucHRC SS3 may reset magSum at 830 and may wait for the next ready PDI at 832 before returning to 808 to process the next PDI.

[0071] If ucHRC SS3 determines that the processed PDI is the final PDI, ucHRC SS3 may save the area around the top peak at 834 and may advance to the next channel at 836 before returning to 804 to initialize ucHRC SS3.

[0072] Fig. 9 is a flow chart showing a method for performing L5 signal direct acquisition processing in NH synchronization mode according to an embodiment. The method starts at 902, and at 904, 10ms of data can be loaded from the DDR memory into the ISM. At 906, ucHRC SS2 can reset the NH alignment and NCS count. At 908, ucHRC SS2 can process 4ms of data from the ISM. At 910, ucHRC SS3 can be correlated with NH code modulation, and at 912, ucHRC SS3 can process four CITs. At 914, ucHRC SS3 can determine whether the processed CIT is in the final NH alignment. If ucHRC SS3 determines that the processed CIT is not at the final NH alignment, ucHRC SS3 can advance to the next NH alignment at 916 and then return to the correlation with NH code modulation at 910. If ucHRC SS3 determines that the processed CIT is in the final NH alignment, ucHRC SS3 can determine whether the PDI is in the final PDI step. If ucHRC SS3 determines that the PDI is not at the final PDI step, ucHRC SS2 may request the next 4 ms of data from the DDR memory at 920, advance the NCS count by 4 ms at 922, and reset the NH alignment at 924, and then return to 908 to allow ucHRC SS2 to process the next 4 ms of data from the ISM at 908. If ucHRC SS3 determines that the PDI is at the final PDI step, the NCS peak may be retained at 926 before processing the next channel.

[0073] Fig.10 1004。It is a diagram showing the code and frequency execution order for direct acquisition of L5 signals according to an embodiment. In the first PDI 1002 (ncsCount 0), processing can start at the first code step and the first frequency step (c0, f0). Before moving to the first code step at the subsequent frequency step (c0, f1), processing can be performed by each of the 64 code steps while maintaining the first frequency step (c63, f0). Processing can be performed in a similar manner through all six frequency steps until the final code step of the final frequency step (c63, f5) is reached. After processing all code steps and frequency steps for the first PDI 1002, the second PDI (ncsCount 1) 1004 can be retrieved. After processing all code steps and frequency steps for the second PDI 1004, the third PDI (ncsCount 3) 1006 can be retrieved.

[0074] For each frequency step, after processing all code steps, the eight largest peak correlations for the code step can be saved in a peak buffer 1008. The peak buffer can contain additional information, including the position (code step / frequency step), offset, and scale associated with each peak. A separate peak buffer can be generated for each frequency step.

[0075] The NCS region includes 320 tap locations for 64 code steps and 6 frequency steps. All tap / code / frequency incoherent correlations can be accumulated on top of each other at each PDI. These correlations are in incoherent form (i.e., amplitude, not I / Q) and are represented as mantissa and exponent (e.g., 8-bit amplitude, 3-bit scale). After all PDIs have been processed (e.g., 150 PDIs of 1 ms each) and all correlation amplitudes have been accumulated on top of each other, a final set of peak buffers can be generated for each frequency step, as described with respect to Fig.10 As shown and described. After all PDIs have been processed, a set of peak region buffers can be generated. Each peak region buffer is associated with a peak buffer and contains the correlation of code / frequency steps around each peak in the peak buffer. This allows interpolation of peaks with surrounding values.

[0076] Fig.111 is a diagram showing a storage format for correlation processing at an ISM according to an embodiment. As shown in (a), the first form of storage is a one-time storage, in which the entire range of data (e.g., 150ms) is captured and immediately available for correlation engine processing at ISM 1102. Multiple channels can process the common ISM 1102 continuously. As shown in (b), the second form of storage is a real-time or real-time running playback, in which the ISM 1104 can be a moving window (e.g., 100 microseconds (μs)) that is advanced or accelerated in real time. Multiple channels (running at a high clock speed) can access the moving window continuously. This allows ISM data to be used to capture and / or track multiple satellites simultaneously. As shown in (c), the third form of storage is on-demand storage, in which the ISM 1106 is preloaded with start data stored in DDR memory. Thereafter, all code / frequency steps or NH alignments are processed for the PDI contained in ISM1106. When this is completed, the next PDI can be loaded into the ISM in a circular buffer manner and the process is repeated. In this way, the ISM moving window slides down all available data. Specifically, for L5 direct acquisition, the ISM 1106 receives 1ms of data for 3ms at a time. All twenty thousand code taps and six frequency steps are processed before moving to the next ms. For NH bit synchronization, the ISM 1106 receives 4ms of data for 10ms at a time. All 100 NH code alignments are processed before moving to the next PDI.

[0077] Fig.12 is a diagram showing the implementation of code step size for L5 signal direct acquisition according to an embodiment. Specifically, Fig.12 The code step size is shown to be generated by offsetting the 1 ms data range 1202 processed by the correlation engine. Each code step size produces 320 correlator taps that are offset from each other by 1 / 20 μs, covering a time range of 16 μs. Each code step size (e.g., code step size -1 1206) is offset by 16 μs from the previous code step size (e.g., code step size -0 1204). The final code step size -63 1208 can reach the subsequent 1 ms.

[0078] Fig.13is a diagram showing the processing order of NH alignment for each PDI according to an embodiment. The first 4ms PDI may be processed starting from the first NH alignment (PDI_0, NH_align 0 130 2) until the last NH alignment (PDI_0, NH_align N 1304). Subsequently, the second 4ms PDI may be processed starting from the first NH alignment (PDI 1, NH align 0 1306) until the last NH alignment (PDI 1, NH align N 1308). This process continues through all 4ms PDIs.

[0079] Fig.14 1404. FIG. 1405 is a diagram showing an ISM for L5 signal direct acquisition according to an embodiment. Based on a request from the ucHRC SS2, data may be pulled from the DDR memory 1402 into the cyclic 3ms ISM 1404. The first 1ms of data 1408 may be stored starting at the ISM base address 1406, followed by the second 1ms of data 1410 and the third 1ms of data 1412. The fourth 1ms of data may then be stored starting again at the ISM base address 1406. The ucHRC SS2 may process 1ms of data at a time.

[0080] Fig.15 1 is a diagram showing an ISM for direct acquisition of L5 signals in NH sync mode according to an embodiment. Based on a request from the ucHRC SS2, data may be pulled from the DDR memory 1502 into the cyclic ISM 1404. The first 4 ms of data 1508 is stored starting at the ISM base address 1506, followed by the second and third 4 ms of data 1510 and 1512. The fourth 4 ms of data will then be stored starting again from the ISM base address 1506. The ucHRC SS2 may process 4 ms of data at a time.

[0081] Fig.16 1604, and then vice versa. Each of the ping storage area 1602 and the pong storage area 1604 may contain four CITs 1606. For example, the ping storage area 1602 may include CIT 0A, CIT 1A, CIT 2A, and CIT 3A, and the pong storage area may include CIT 0B, CIT 1B, CIT 2B, and CIT 3B. For L5 direct fetch, each CIT is 1 / 4ms; for L5 direct acquisition in NH synchronous mode, each CIT is 1ms. Although specific CITs are described Fig.16 , but the embodiments are not limited thereto. For example, for weak signal acquisition, when the NH alignment is known, each CIT can be 1 ms and the PDI can be 4 ms. Four CITs constitute a single PDI. For L5 direct acquisition, the PDI is 1 ms, and for L5 direct acquisition in NH synchronization mode, the PDI is 4 ms. Each CIT contains 320 correlator taps (e.g., corr 0 to corr 319) spaced 1 / 20 sμ apart. Each CIT can have its own scaling parameters (e.g., AS0, AS1, AS2, and AS3).

[0082] Fig.17 is a diagram showing an NCS structure for L5 signal direct acquisition according to an embodiment. The NCS structure contains the correlation sum of each code step and frequency step, starting from NCS base address 1702, with code step 0, frequency step 0 1704, and continuing to code step 63, frequency step 5 1706. Each code / frequency step may contain 320 8-bit amplitude correlator taps 1708, spaced 1 / 20 μs apart, each correlator tap having five FFT frequency bins.

[0083] Fig.18 is a diagram showing an NCS structure for L5 signal direct acquisition in NH synchronization mode according to an embodiment. The NCS structure contains the relevant sum of each NH code alignment, each NH code alignment starting at the NCS base address 1802, with code step 0, frequency step 0 and NH step 0 1804, and continuing through NH step 99 1806. Only code step 0 and frequency step 0 are required because NH bit synchronization is performed only after the L5 signal direct acquisition has found the correct tap and frequency position. Each NH code alignment step contains 320 correlator taps 1808 of 8-bit amplitude spaced 1 / 20 μs apart. NH step 0 is [NH(0), NH(1), NH(2), NH(3)]. NH step 1 is [NH(1), NH(2), NH(3), NH(4)]. NH step 2 is [NH(2), NH(3), NH(4), NH(5)].

[0084] Fig.19is a diagram showing a peak region buffer for direct acquisition of an L5 signal according to an embodiment. Each peak has an associated peak region buffer that contains all code / frequency steps around the peak. This allows for interpolation of correlations around the peak. For example, a peak 1902, f(m) at step size c(n) is surrounded by peak regions at step sizes c(n+1), f(m-1)1904, c(n+1), f(m)1906, c(n+1), f(m+1)1908, c(n), f(m-1)1910, c(n), f(m+1)1912, c(n-1), f(m-1)1914, c(n-1), f(m)1916, and c(n-1), f(m+1)1918.

[0085] The NCS memory can be used as a scratch area, meaning that after all codes / frequency steps have been executed, after all PDIs have been processed, and after all peaks and peak regions have been generated, the sequencer can proceed with the L5 signal direct acquisition of the next satellite or channel. While the NCS area can be cleared for reuse for the next satellite or channel, the ping-pong memory area for peaks and peak regions can be utilized to allow the data for the last satellite to be available to the software when the next satellite is processed. The peak memory can contain six peak buffers (one peak buffer per frequency step), each peak buffer can contain eight peaks, and each peak can have an associated peak region buffer as described above.

[0086] Fig. 20 2006 . Each peak buffer 2006 may contain eight peaks, but the embodiment is not limited thereto. For each peak, a peak buffer 2006 having a peak value is generated. Fig.19 A peak region 2008 is generated starting at a peak region base address 2010 after all PDIs have been processed (e.g., 150 PDIs for 150 ms of data). A peak region buffer 2012 is generated for each frequency step. The NCS region can be used as a scratch region, meaning that the peaks and peak region buffers are saved for software, but the NCS region can be used to process the next satellite.

[0087] Fig.212104 (e.g., 10 samples). The NCO 2102 may also provide a carrier phase (e.g., x10) for use at a sample rotator 2106 (e.g., x10) to rotate the captured samples 2104. The rotated samples may be formed into a delay chain 2108 (e.g., 20 samples) and may be summed up to 1 / 10 μs samples. The summed samples 2110 (e.g., 10 groups of 5 sums) may be correlated at a correlator 2114 with various offsets of the PN code from the code generator 2112. Each offset of the code to the sample represents another correlator tap. The correlations of all correlator taps (eg, 320) may be accumulated at accumulator 2116, auto-scaled to CIT (1 / 4 ms) at auto-scaling module 2118, and then dumped into coherent RAM 2120. Four CITs may be saved to form the PDI for ucHRC SS3 processing.

[0088] Fig. 22 2204. It is a diagram showing the ucHRC SS3 data flow in the L5 signal direct acquisition according to an embodiment. Four rows of data (e.g., ucRAMdata0, ucRAMdata1, ucRAMdata2, and ucRAMdata3) can be read from the ucHRC RAM 2202 to the four-row depth register 2204. The sampling selection module 2206 can select four CIT samples (e.g., dataIQCIT0, dataIQCIT1, dataIQCIT2, and dataIQCIT3) for a single correlator tap, which cancels the "twiddling" to allow effective FFT butterfly sampling input requirements. The four CIT samples can be scaled separately at the scaling module 2208 before being input to the four-input eight-point FFT module 2210 for FFT processing. The aggregation module (or frequency selection module) 2212 can only allow the center five frequency bins to pass to the NCS scaling module 2214 because the outer bins have signal strength drops. The NCS scaling module can scale the input before the NCS module 2216 performs the non-coherent (amplitude) accumulation. Various offset and scaling parameters are generated to allow efficient use of the data range. The DSP RAM 2218 can store the results of the correlation.

[0089] Fig.23 is a diagram illustrating ucHRC SS3 data flow in L5 signal direct acquisition in NH synchronization mode according to an embodiment. Fig.23 The data flow is similar to the above Fig. 22The described process functions similarly and includes similar modules, except that separate NH removal modules 2302 are added (e.g., NH(0), NH(1), NH(2), and NH(3)) which receive input from separate scaling modules 2208 and provide output to the FFT module 2210.

[0090] Although it is described that PDI=1 ms is obtained for L5 signals and PDI=4 ms is obtained for L5 signals with NH synchronization, embodiments are not limited thereto and various PDI settings may be used to help optimize system performance.

[0091] Fig.24 is a flow chart illustrating a method for L5 signal direct acquisition processing according to an embodiment.

[0092] At 2402, the UE's FEP may process the input from the L5 antenna after conversion into a digital data stream. At 2404, the processed data may be stored at the DDR memory. At 2406, the data may be loaded from the DDR memory to the UE's ISM.

[0093] At 2408, the first HRC engine of the UE may perform coherent correlation and accumulation on the data for at least one code-frequency offset combination to generate a coherent correlation result. The data may include 1 ms of data or 4 ms of data. The at least one code-frequency offset combination may include multiple offset combinations, and coherent correlation and accumulation may be performed sequentially on the data of each offset combination to generate a coherent correlation result for each offset combination. The coherent correlation result may include a peak accumulation of the code-frequency offset with correlation over time.

[0094] At 2410, each coherent correlation result may be stored at a CIT memory of the UE. Each region of the CIT may include four CIT regions, and each CIT region may include 320 correlator taps.

[0095] At 2412, the second HRC engine of the UE may process the coherent correlation result by performing at least frequency widening and non-coherent accumulation to generate a non-coherent correlation result indicating at least a correlated peak accumulation. One of the first area and the second area of ​​the CIT memory is used by the first HRC engine for data storage, while the other of the first area and the second area is accessed by the second HRC engine in a ping-pong manner for data retrieval. The processing of the coherent correlation result may include performing an FFT on the coherent correlation result to widen the frequency range covered by the corresponding code-frequency offset, selecting a plurality of center frequencies from the widened frequency range of the corresponding code-frequency offset, and performing non-coherent accumulation on the FFT coherent correlation result relative to the plurality of center frequencies to increase the accumulation time and generate a non-coherent correlation result. The coherent correlation result may be processed for each of a plurality of NH code alignments. The non-coherent correlation result may include a code-frequency offset with a correlated peak accumulation, and a code-frequency offset region for the peak accumulation.

[0096] At 2414, the non-coherent correlation results may be stored in a DSP RAM of the UE. At 2416, an input code offset and frequency offset may be determined based on the non-coherent correlation results.

[0097] Fig.25 is a block diagram of electronic devices in a network environment 2300 according to an embodiment.

[0098] refer to Fig.25 , the electronic device 2501 in the network environment 2500 can communicate with the electronic device 2502 via the first network 2598 (e.g., a short-range wireless communication network), or communicate with the electronic device 2504 or the server 2508 via the second network 2599 (e.g., a long-range wireless communication network). The electronic device 2501 can communicate with the electronic device 2504 via the server 2508. The electronic device can be embodied as described above with respect to Figure 1-3UE described. The electronic device 2501 may include a processor 2520, a memory 2530, an input device 2550, a sound output device 2555, a display device 2560, an audio module 2570, a sensor module 2576, an interface 2577, a tactile module 2579, a camera module 2580, a power management module 2588, a battery 2589, a communication module 2590, a user identification module (SIM) card 2596, or an antenna module 2597. In one embodiment, at least one of the components (e.g., the display device 2560 or the camera module 2580) may be omitted from the electronic device 2501, or one or more other components may be added to the electronic device 2501. Some components may be implemented as a single integrated circuit (IC). For example, a sensor module 2576 (e.g., a fingerprint sensor, an iris sensor, or an illumination sensor) may be embedded in a display device 2560 (e.g., a display).

[0099] The processor 2520 may execute software (eg, program 2540 ) to control at least one other component (eg, hardware or software component) of the electronic device 2501 coupled to the processor 2520 , and may perform various data processing or calculations, including GNSS processing.

[0100] As at least part of data processing or calculation, the processor 2520 may load commands or data received from another component (e.g., the sensor module 2576 or the communication module 2590) into the volatile memory 2532, process the commands or data stored in the volatile memory 2532, and store the resulting data in the non-volatile memory 2534. The processor 2520 may include a main processor 2521 (e.g., a central processing unit (CPU) or an application processor (AP)) and an auxiliary processor 2523 (e.g., a graphics processing unit (GPU), an image signal processor (ISP), a sensor hub processor, or a communication processor (CP)) that may operate independently of the main processor 2521 or in conjunction with the main processor 2521. Additionally or alternatively, the auxiliary processor 2523 may be adapted to consume less power than the main processor 2521, or to perform a specific function. The auxiliary processor 2523 may be implemented to be separate from the main processor 2521 or to be a part of the main processor 2521.

[0101] The auxiliary processor 2523 may replace the main processor 2521 when the main processor 2521 is in an inactive (e.g., sleeping) state, or control at least some of the functions or states related to at least one of the components of the electronic device 2501 (e.g., the display device 2560, the sensor module 2576, or the communication module 2590) together with the main processor 2521 when the main processor 2521 is in an active state (e.g., executing an application). The auxiliary processor 2523 (e.g., an image signal processor or a communication processor) may be implemented as a part of another component (e.g., a camera module 2580 or a communication module 2590) that is functionally related to the auxiliary processor 2523.

[0102] The memory 2530 may store various data used by at least one component of the electronic device 2501 (e.g., the processor 2520 or the sensor module 2576). The various data may include, for example, software (e.g., program 2540) and input data or output data for commands related thereto. The memory 2530 may include a volatile memory 2532 or a non-volatile memory 2534. The non-volatile memory 2534 may include an internal memory 2536 and / or an external memory 2538.

[0103] The program 2540 may be stored as software in the memory 2530 , and may include, for example, an operating system (OS) 2542 , middleware 2544 , or an application 2546 .

[0104] The input device 2550 may receive a command or data to be used by another component (eg, the processor 2520) of the electronic device 2501 from outside (eg, a user) of the electronic device 2501. The input device 2550 may include, for example, a microphone, a mouse, or a keyboard.

[0105] The sound output device 2555 can output sound signals to the outside of the electronic device 2501. The sound output device 2555 may include, for example, a speaker or a receiver. The speaker may be used for general purposes, such as playing multimedia or recording, and the receiver may be used to receive incoming calls. The receiver may be implemented as being separate from the speaker or as part of the speaker.

[0106] The display device 2560 can visually provide information to the outside (e.g., user) of the electronic device 2501. The display device 2560 may include, for example, a display, a hologram device, or a projector, and a control circuit for controlling a corresponding one of the display, the hologram device, and the projector. The display device 2560 may include a touch circuit suitable for detecting a touch or a sensor circuit (e.g., a pressure sensor) suitable for measuring the strength of the force caused by the touch.

[0107] The audio module 2570 can convert sound into an electrical signal, and vice versa. The audio module 2570 can obtain sound via the input device 2550, or output sound via the sound output device 2555 or the earphone of the external electronic device 2502 directly (eg, wired) or wirelessly coupled to the electronic device 2501.

[0108] The sensor module 2576 can detect the operating state (e.g., power or temperature) of the electronic device 2501 or the environmental state (e.g., the state of the user) outside the electronic device 2501, and then generate an electrical signal or data value corresponding to the detected state. The sensor module 2576 may include, for example, a gesture sensor, a gyroscope sensor, an atmospheric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an infrared (IR) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illumination sensor.

[0109] The interface 2577 may support one or more designated protocols for the electronic device 2501 to be directly (e.g., wired) or wirelessly coupled to the external electronic device 2502. The interface 2577 may include, for example, a high-definition multimedia interface (HDMI), a universal serial bus (USB) interface, a secure digital (SD) card interface, or an audio interface.

[0110] The connection terminal 2578 may include a connector via which the electronic device 2501 may be physically connected to the external electronic device 2502. The connection terminal 2578 may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (eg, a headphone connector).

[0111] The haptic module 2579 may convert the electrical signal into mechanical stimulation (eg, vibration or movement) or electrical stimulation that can be recognized by the user via tactile or kinesthetic sense. The haptic module 2579 may include, for example, a motor, a piezoelectric element, or an electrical stimulator.

[0112] The camera module 2580 may capture still images or moving images. The camera module 2580 may include one or more lenses, an image sensor, an image signal processor, or a flash. The power management module 2588 may manage the power supplied to the electronic device 2501. The power management module 2588 may be implemented as at least a portion of a power management integrated circuit (PMIC), for example.

[0113] The battery 2589 may supply power to at least one component of the electronic device 2501. The battery 2589 may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0114] The communication module 2590 may support establishing a direct (e.g., wired) communication channel or a wireless communication channel between the electronic device 2501 and an external electronic device (e.g., electronic device 2502, electronic device 2504, or server 2508), and perform communication via the established communication channel. The communication module 2590 may include one or more communication processors that may operate independently of the processor 2520 (e.g., AP) and support direct (e.g., wired) communication or wireless communication. The communication module 2590 may include a wireless communication module 2592 (e.g., a cellular communication module, a short-range wireless communication module, and / or a satellite or GNSS communication module) or a wired communication module 2594 (e.g., a local area network (LAN) communication module or a power line communication (PLC) module). A corresponding one of these communication modules can communicate with an external electronic device via a first network 2598 (e.g., a short-range communication network such as Bluetooth™, Wireless Fidelity (Wi-Fi) Direct, or Infrared Data Association (IrDA) standards) or a second network 2599 (e.g., a long-range communication network such as a cellular network, the Internet, or a computer network (e.g., a LAN or a wide area network (WAN)). These various types of communication modules can be implemented as a single component (e.g., a single IC), or can be implemented as multiple components separated from each other (e.g., multiple ICs). The wireless communication module 2592 can use user information (e.g., an International Mobile Subscriber Identity (IMSI)) stored in the user identification module 2596 to identify and authenticate the electronic device 2501 in the communication network (e.g., the first network 2598 or the second network 2599).

[0115] The antenna module 2597 may transmit or receive signals or power to or from the outside of the electronic device 2501 (e.g., an external electronic device). The antenna module 2597 may include one or more antennas, and from these, at least one antenna suitable for a communication scheme used in a communication network (such as the first network 2598 or the second network 2599) may be selected, for example, by the communication module 2590 (e.g., the wireless communication module 2592). Then, signals or power may be transmitted or received between the communication module 2590 and the external electronic device via the selected at least one antenna.

[0116] Commands or data may be sent or received between the electronic device 2501 and the external electronic device 2504 via a server 2508 coupled to the second network 2599. Each of the electronic devices 2502 and 2504 may be a device of the same type or a different type as the electronic device 2501. All or some operations to be performed at the electronic device 2501 may be performed at one or more of the external electronic devices 2502, 2504, or 2508. For example, if the electronic device 2501 should automatically or in response to a request from a user or another device to perform a function or service, the electronic device 2501 may request one or more external electronic devices to perform at least a part of the function or service, instead of performing the function or service, or in addition to performing the function or service, the electronic device 2501 may also request one or more external electronic devices to perform at least a part of the function or service. The one or more external electronic devices receiving the request may perform at least a part of the requested function or service, or an additional function or additional service related to the request, and transmit the result of the execution to the electronic device 2501. The electronic device 2501 may provide the result as at least part of the reply to the request with or without further processing the result. To this end, for example, cloud computing, distributed computing or client-server computing techniques may be used.

[0117] The embodiments of the subject matter and operations described in this specification may be implemented in digital electronic circuits, or in computer software, firmware or hardware, including the structures disclosed in this specification and their structural equivalents, or a combination of one or more of them. The embodiments of the subject matter described in this specification may be implemented as one or more computer programs, that is, one or more modules of computer program instructions, which are encoded on a computer storage medium for execution by a data processing device or for controlling the operation of a data processing device. Alternatively or additionally, program instructions may be encoded on an artificially generated propagation signal, such as a machine-generated electrical, optical or electromagnetic signal, which is generated to encode information for transmission to a suitable receiver device for execution by a data processing device. The computer storage medium may be a computer-readable storage device, a computer-readable storage substrate, a random or serial access memory array or device, or a combination thereof, or be included therein. In addition, although a computer storage medium is not a propagation signal, a computer storage medium may be a source or destination of computer program instructions encoded in an artificially generated propagation signal. The computer storage medium may also be one or more separate physical components or media (e.g., multiple CDs, disks or other storage devices), or be included in one or more separate physical components or media (e.g., multiple CDs, disks or other storage devices). Additionally, the operations described in this specification may be implemented as operations performed by a data processing apparatus on data stored on one or more computer-readable storage devices or received from other sources.

[0118] Although this specification may contain many specific implementation details, the implementation details should not be interpreted as a limitation on the scope of any claimed subject matter, but rather as a description of features specific to a particular embodiment. Certain features described in the context of separate embodiments in this specification may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations and even initially claimed, one or more features from the claimed combination may be deleted from the combination in some cases, and the claimed combination may be directed to a sub-combination or a variation of the sub-combination.

[0119] Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring that the operations be performed in the particular order shown or in sequence, or that all of the operations shown be performed, to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous. In addition, the separation of various system components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0120] Thus, specific embodiments of the subject matter have been described herein. Other embodiments are within the scope of the appended claims. In some cases, the actions set forth in the claims can be performed in a different order and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing may be advantageous.

[0121] As those skilled in the art will recognize, the innovative concepts described herein can be modified and varied over a wide range of applications. Therefore, the scope of the claimed subject matter should not be limited to any specific exemplary teachings discussed above, but rather is defined by the appended claims.

Claims

1. A method performed by a user equipment UE, comprising: Loading data from a memory to an input sample memory (ISM) of the UE, wherein the data corresponds to an input from an L5 antenna of the UE; performing, by a first high resolution correlation (HRC) engine of the UE, coherently correlating and accumulating the data for at least one code-frequency offset combination to generate a coherent correlation result; and The coherent correlation result is processed by a second HRC engine of the UE by performing at least frequency widening and non-coherent accumulation to generate a non-coherent correlation result indicating at least a peak accumulation of correlation.

2. The method according to claim 1, further comprising: processing, by a front end processor (FEP) of the UE, the input from the L5 antenna after conversion into a digital data stream; as well as Processed data is saved at the memory, wherein the memory comprises external double data rate (DDR) memory.

3. The method according to claim 1, wherein: The at least one code-frequency offset combination comprises a plurality of offset combinations; sequentially performing coherent correlation and accumulation on the data for each offset combination to generate a coherent correlation result for each offset combination; as well as The coherent correlation results are processed sequentially for each offset combination.

4. The method according to claim 3, further comprising: Each of the coherent correlation results is stored at a coherent integration time (CIT) memory of the UE, wherein one of a first area and a second area of ​​the CIT memory is used for data storage by a first HRC engine, and the other of the first area and the second area is accessed by the second HRC engine in a ping-pong manner for data retrieval.

5. The method according to claim 4, wherein: Each of the first region and the second region includes four CIT regions, and each CIT region includes 320 correlator taps.

6. The method according to claim 4, wherein: Processing the coherent correlation results includes, for each offset combination: performing a fast Fourier transform (FFT) on the coherent correlation results to widen the frequency range covered by the corresponding code-frequency offset; selecting a plurality of center frequencies from the widened frequency range for the corresponding code-frequency offsets; as well as Incoherent accumulation is performed on the FFT coherent correlation results relative to the plurality of center frequencies to increase an accumulation time and generate the incoherent correlation results.

7. The method according to claim 4, wherein: The data includes 1 millisecond (ms) of data and the ISM includes a 3ms cycle ISM, or the data includes 4ms of data and the ISM includes a 10ms cycle ISM.

8. The method according to claim 7, wherein: The data includes 1 ms of data for strong signal acquisition, followed by 4 ms of data for Neumann Hoffman (NH) synchronization and 4 ms of data for weak signal acquisition; or The data includes 1 ms of data for strong signal acquisition or 4 ms of data for weak signal acquisition with known NH code alignment.

9. The method according to claim 1, wherein: The at least one code-frequency offset combination comprises a single offset combination, and the method further comprises: The coherent correlation results are stored across four CIT regions of a CIT memory of the UE, wherein each CIT region includes 320 correlator taps.

10. The method according to claim 9, wherein: Processing the coherent correlation results comprises: for each of a plurality of NH code alignments: performing a fast Fourier transform (FFT) on the coherent correlation results to widen the frequency range covered by the corresponding code-frequency offset; selecting a plurality of center frequencies from the widened frequency range for the corresponding code-frequency offsets; and Incoherent accumulation is performed on the FFT coherent correlation results relative to the plurality of center frequencies to increase an accumulation time and generate the incoherent correlation results.

11. The method according to claim 9, wherein: The data includes 4 ms of data, and the ISM includes a 10 ms cyclic ISM.

12. The method of claim 1, wherein: The coherent correlation results include code-frequency offsets with peak accumulation of correlation over time; as well as The incoherent correlation results include a code-frequency offset having a correlated peak accumulation, and a code-frequency offset region having a peak accumulation.

13. The method according to claim 1, further comprising: storing the incoherent correlation results in a digital signal processing (DSP) random access memory (RAM) of the UE; as well as A code offset and a frequency offset of the input are determined based on the incoherent correlation results.

14. A user equipment UE, comprising: an input sample memory (ISM) configured to store data from a memory, wherein the data corresponds to an input from an L5 antenna of the UE; a first high resolution correlation (HRC) engine configured to perform coherent correlation and accumulation on the data for at least one code-frequency offset combination to generate a coherent correlation result; and A second HRC engine is configured to process the coherent correlation results by performing at least frequency widening and non-coherent accumulation to generate non-coherent correlation results indicating at least a peak accumulation of correlations.

15. The UE according to claim 14, further comprising: a front end processor (FEP) configured to process input from said L5 antenna after conversion into a digital data stream, Wherein, the processed data is stored at the memory, and the memory comprises an external double data rate (DDR) memory.

16. The UE according to claim 14, wherein: The at least one code-frequency offset combination comprises a plurality of offset combinations; sequentially performing the coherent correlation and accumulation on the data for each offset combination to generate a coherent correlation result for each offset combination; as well as The coherent correlation results are processed sequentially for each offset combination.

17. The UE according to claim 16, further comprising: a coherent integration time (CIT) memory configured to store each of the coherent correlation results, wherein one of a first area and a second area of ​​the CIT memory is used by the first HRC engine for data storage, while the other of the first area and the second area is accessed by the second HRC engine in a ping-pong manner for data retrieval, Wherein, processing the coherent correlation result includes, for each offset combination: performing a fast Fourier transform (FFT) on the coherent correlation results to widen the frequency range covered by the corresponding code-frequency offset; selecting a plurality of center frequencies from the widened frequency range for the corresponding code-frequency offsets; and Incoherent accumulation is performed on the FFT coherent correlation results relative to the plurality of center frequencies to increase an accumulation time and generate the incoherent correlation results.

18. The UE according to claim 14, wherein: The at least one code-frequency offset combination comprises a single offset combination, and further comprises: storing the coherent correlation results across four CIT regions of a CIT memory of the UE, wherein each CIT region includes 320 correlator taps, Wherein, processing the coherent correlation result comprises: for each of a plurality of Neumann Hoffman (NH) code alignments: performing a fast Fourier transform (FFT) on the coherent correlation results to widen the frequency range covered by the corresponding code-frequency offset; selecting a plurality of center frequencies from the widened frequency range for the corresponding code-frequency offsets; and Incoherent accumulation is performed on the FFT coherent correlation results relative to the plurality of center frequencies to increase an accumulation time and generate the incoherent correlation results.

19. The UE according to claim 14, wherein: The coherent correlation result includes a code-frequency offset having a peak accumulation of correlation over time, and the incoherent correlation result includes a code-frequency offset having a peak accumulation of correlation and a code-frequency offset region of the peak accumulation.

20. A user equipment UE, comprising: processor; as well as a non-transitory computer-readable storage medium storing instructions that, when executed, cause the processor to: Loading data from a memory into an input sample memory (ISM) of the UE, wherein the data corresponds to an input from an L5 antenna of the UE; performing, by a first high resolution correlation (HRC) engine of the UE, coherently correlating and accumulating the data for at least one code-frequency offset combination to generate a coherent correlation result; and The coherent correlation result is processed by a second HRC engine of the UE by performing at least frequency widening and non-coherent accumulation to generate a non-coherent correlation result indicating at least a peak accumulation of correlation.

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