Semiconductor device

Abstract

The semiconductor device includes: a substrate; a plurality of first FETs each provided with a plurality of first gate electrodes, the plurality of first FETs being arranged in the first direction on the substrate; a plurality of second FETs each provided with a plurality of second gate electrodes, the plurality of second FETs being arranged in the first direction; and a plurality of third FETs each provided with a plurality of third gate electrodes, the plurality of third FETs being arranged in the first direction, the plurality of second FETs being disposed between the plurality of third FETs and the plurality of first FETs in a second direction intersecting the first direction, and the plurality of second FETs being disposed between the plurality of third FETs and the plurality of first FETs in the second direction intersecting the first direction. A first distance at a central portion in the first direction of the plurality of first FETs, the plurality of second FETs, and the plurality of third FETs is greater than a second distance at a first end portion close to the first end in the first direction of the plurality of first FETs, the plurality of second FETs, and the plurality of third FETs, the second distance being less than a third distance at the first end portion.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] It is known that in a field effect transistor (FET) having a finger-shaped source electrode, a gate electrode, and a drain electrode, a plurality of unit FETs having a source electrode, a gate electrode, and a drain electrode are arranged in the extending direction of the electrode (for example, Patent Documents 1 to 3).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2002-299351

[0006] Patent Document 2: U.S. Patent Application Publication No. 2017 / 0271329

[0007] Patent Document 3: Japanese Patent Application Publication No. 2022-135899

[0008] In a semiconductor device in which a plurality of unit FETs are arranged, the heat dissipation of the unit FETs located in the center is worse than that of the unit FETs located at the ends. Therefore, the temperature difference between the unit FETs in the center and at the ends becomes large, so the characteristics of the unit FETs are not uniform. As a result, the characteristics of the semiconductor device are degraded. Summary of the invention

[0009] The present disclosure has been made in view of the above-mentioned problems, and an object of the present disclosure is to suppress degradation of characteristics.

[0010] One embodiment of the present disclosure is a semiconductor device, comprising: a substrate; a plurality of first FETs, each comprising a plurality of first gate electrodes, the plurality of first FETs being arranged in a first direction on the substrate; a plurality of second FETs, each comprising a plurality of second gate electrodes, the plurality of second FETs being arranged in the first direction; and a plurality of third FETs, each comprising a plurality of third gate electrodes, the plurality of third FETs being arranged in the first direction, the plurality of second FETs being arranged between the plurality of third FETs and the plurality of first FETs in a second direction intersecting the first direction, wherein a first distance is greater than a second distance, wherein the first distance is a distance between two second gate electrodes separated by one second gate electrode among the plurality of second gate electrodes at a center portion of the plurality of first FETs, the plurality of second FETs, and the plurality of third FETs in the first direction, and the second distance is a distance between two second gate electrodes separated by one second gate electrode among the plurality of second gate electrodes at a first end portion of the plurality of first FETs, the plurality of second FETs, and the plurality of third FETs in the first direction near a first end, and the second distance is less than a third distance, wherein the third distance is a distance between two first gate electrodes separated by one first gate electrode among the plurality of first gate electrodes at the first end portion.

[0011] Effects of the Invention

[0012] According to the present disclosure, degradation of characteristics can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a top view of the semiconductor device in Example 1.

[0014] Figure 2 yes Figure 1 A-A section view.

[0015] Figure 3 yes Figure 1 B-B section view.

[0016] Figure 4 It is a diagram showing the arrangement of gate electrodes in the semiconductor device of Comparative Example 1.

[0017] Figure 5 It is a diagram showing the arrangement of gate electrodes in a semiconductor device of Comparative Example 2.

[0018] Figure 6 It is a diagram showing the arrangement of gate electrodes in the semiconductor device of Example 1.

[0019] Figure 7 This is a diagram showing the arrangement of gate electrodes in the semiconductor device of Example 2.

[0020] Figure 8 It is a diagram showing the arrangement of gate electrodes in a semiconductor device of Comparative Example 3.

[0021] Fig. 9 It is a top view of the semiconductor device of Example 3.

[0022] Fig.10 It is a top view of a semiconductor device according to a first variation of the third embodiment.

[0023] Fig.11 1 is a diagram showing a distance D relative to a position X in the semiconductor device of the fourth embodiment.

[0024] Fig.12 1 is a diagram showing a distance D relative to a position X in a semiconductor device according to a first variation of the fourth embodiment.

[0025] Fig.13 1 is a diagram showing a distance D relative to a position X in a semiconductor device according to a second variation of the fourth embodiment.

[0026] Fig.14 1 is a diagram showing a distance D relative to a position X in a semiconductor device according to a third variation of the fourth embodiment.

[0027] Fig.15 This is a diagram showing the configuration of gate electrodes in a semiconductor device according to a fourth variation of the fourth embodiment.

[0028] Fig.16 This is a diagram showing the arrangement of gate electrodes in a semiconductor device according to a fifth variation of the fourth embodiment.

[0029] Description of Reference Numerals

[0030] 10, 10a: substrate;

[0031] 10b: semiconductor layer;

[0032] 11a, 11b, 11c: active area;

[0033] 12a, 12b, 12c: source electrodes;

[0034] 13, 13a, 13b: passive area;

[0035] 14a, 14b, 14c, 14ba, 14bb: gate electrodes;

[0036] 16a, 16b, 16c: drain electrodes;

[0037] 20: vias;

[0038] 22a, 22b: source wiring;

[0039] 24, 24a, 24b, 25a, 25b: gate wiring;

[0040] 27: drain bus;

[0041] 28: Gate busbar;

[0042] 30: insulation layer;

[0043] 50: Central;

[0044] 51, 52: end;

[0045] 51a, 52a: middle part;

[0046] 55, 56, 57: area;

[0047] 58: Arrow;

[0048] 100, 101, 104, 105, 106, 107, 108, 109, 110, 112, 114: semiconductor devices. DETAILED DESCRIPTION

[0049] [Description of Embodiments of the Present Disclosure]

[0050] First, the contents of the embodiments of the present disclosure will be listed and described.

[0051] (1) One embodiment of the present disclosure is a semiconductor device comprising: a substrate; a plurality of first FETs each having a plurality of first gate electrodes, the plurality of first FETs being arranged in a first direction on the substrate; a plurality of second FETs each having a plurality of second gate electrodes, the plurality of second FETs being arranged in the first direction; and a plurality of third FETs each having a plurality of third gate electrodes, the plurality of third FETs being arranged in the first direction, the plurality of second FETs being arranged between the plurality of third FETs and the plurality of first FETs in a second direction intersecting the first direction, wherein a first distance is greater than a second distance, wherein the first distance is a distance between two second gate electrodes separated by one second gate electrode among the plurality of second gate electrodes at a center portion of the plurality of first FETs, the plurality of second FETs, and the plurality of third FETs in the first direction, and the second distance is a distance between two second gate electrodes separated by one second gate electrode among the plurality of second gate electrodes at a first end portion of the plurality of first FETs, the plurality of second FETs, and the plurality of third FETs in the first direction near a first end, and the second distance is less than a third distance, wherein the third distance is a distance between two first gate electrodes separated by one first gate electrode among the plurality of first gate electrodes at the first end portion. Thus, heat can be dissipated from the second FET at the first end. Thus, the temperature distribution of the semiconductor device can be made uniform, so the characteristics of the FET can be made uniform. Thus, degradation of the characteristics of the semiconductor device can be suppressed.

[0052] (2) In the above (1), the first distance may be greater than a fourth distance, wherein the fourth distance is a distance between two first gate electrodes separated by one first gate electrode among the plurality of first gate electrodes at the central portion. Thus, the temperature distribution of the FET can be further uniformized. Thus, the degradation of the characteristics of the semiconductor device can be further suppressed.

[0053] (3) In the above (1), the second distance may be smaller than a fifth distance, wherein the fifth distance is a distance between two third gate electrodes separated by one third gate electrode among the plurality of third gate electrodes at the first end. Thus, the temperature distribution of the FET can be further uniformized. Thus, the degradation of the characteristics of the semiconductor device can be further suppressed.

[0054] (4) In the above (3), the first distance may be greater than a fourth distance, wherein the fourth distance is the distance between two first gate electrodes separated by one first gate electrode among the plurality of first gate electrodes at the central portion, and the first distance may be greater than a sixth distance, wherein the sixth distance is the distance between two third gate electrodes separated by one third gate electrode among the plurality of third gate electrodes at the central portion. Thus, the temperature distribution of the FET can be further uniformized. Thus, the degradation of the characteristics of the semiconductor device can be further suppressed.

[0055] (5) In any of the above (1) to (4), the seventh distance may be greater than the second distance and less than the first distance, wherein the seventh distance is the distance between two second gate electrodes separated by one second gate electrode among the plurality of second gate electrodes at the middle portion between the central portion and the first end portion in the first direction. Thus, the temperature distribution of the FET can be further uniformized. Thus, the degradation of the characteristics of the semiconductor device can be further suppressed.

[0056] (6) In the above (1), the first distance may be greater than an eighth distance, wherein the eighth distance is a distance between two second gate electrodes separated by one second gate electrode among the plurality of second gate electrodes at a second end portion of the plurality of first FETs, the plurality of second FETs, and the plurality of third FETs that is closer to the second end opposite to the first end than the central portion. Thus, the temperature distribution of the FETs can be further uniformized. Thus, the degradation of the characteristics of the semiconductor device can be further suppressed.

[0057] (7) In the above (4), the first distance may be greater than an eighth distance, wherein the eighth distance is the distance between two second gate electrodes separated by one second gate electrode among the plurality of second gate electrodes at the second end portion that is closer to the plurality of first FETs, the plurality of second FETs, and the plurality of third FETs than the central portion and is located at the second end opposite to the first end, and the eighth distance is less than a ninth distance, wherein the ninth distance is the distance between two first gate electrodes separated by one first gate electrode among the plurality of first gate electrodes at the second end portion, and the eighth distance is less than a tenth distance, wherein the tenth distance is the distance between two third gate electrodes separated by one third gate electrode among the plurality of third gate electrodes at the second end portion. Thus, the temperature distribution of the FETs can be further uniformized. Thus, the degradation of the characteristics of the semiconductor device can be further suppressed.

[0058] (8) In any one of the above (1) to (7), the third distance and the fourth distance may be equal to each other. This facilitates the design of the FET.

[0059] (9) In any of the above (1) to (8), the number of the plurality of first FETs, the number of the plurality of second FETs, and the number of the plurality of third FETs may be the same, thereby enabling the first source electrode to the third source electrode to be electrically connected to each other, and the first drain electrode to the third drain electrode to be electrically connected to each other.

[0060] (10) In any one of the above (1) to (9), the plurality of first FETs may include a plurality of first source electrodes and a plurality of first drain electrodes, the plurality of first gate electrodes may be respectively arranged between one of the plurality of first source electrodes and one of the first drain electrodes in the first direction, the plurality of second FETs may include a plurality of second source electrodes and a plurality of second drain electrodes, the plurality of second gate electrodes may be respectively arranged between one of the plurality of second source electrodes and one of the plurality of second drain electrodes in the first direction, and the plurality of third FETs may include a plurality of third source electrodes and a plurality of third drain electrodes, the plurality of third gate electrodes may be respectively arranged between one of the plurality of third source electrodes and one of the plurality of third drain electrodes in the first direction. Thus, a plurality of FETs may be configured.

[0061] (11) In the above (10), the substrate may include: a first active region, a second active region, and a third active region; a first inactive region disposed between the first active region and the second active region; and a second inactive region disposed between the second active region and the third active region, the plurality of first FETs disposed in the first active region, the plurality of second FETs disposed in the second active region, the plurality of third FETs disposed in the third active region, the plurality of first source electrodes connected to corresponding second source electrodes in the first inactive region, the plurality of first drain electrodes connected to corresponding second drain electrodes in the first inactive region, the plurality of second source electrodes connected to corresponding third source electrodes in the second inactive region, and the plurality of second drain electrodes connected to corresponding third drain electrodes in the second inactive region. Thus, the first source electrode to the third source electrode can be electrically connected to each other, and the first drain electrode to the third drain electrode can be electrically connected to each other.

[0062] [Details of the embodiments of the present disclosure]

[0063] Hereinafter, specific examples of semiconductor devices according to embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be noted that the present disclosure is not limited to these examples, but is indicated by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0064] [Example 1]

[0065] The following description will be given by taking as an example a semiconductor device used in an amplifier for amplifying a high-frequency signal of, for example, 0.5 GHz to 10 GHz in a mobile communication base station. Figure 1 This is a top view of the semiconductor device in Example 1. Figure 2 and Figure 3 They are Figure 1 A-A cross-sectional view and BB cross-sectional view. The thickness direction of the substrate 10 is set to the Z direction, the extension direction of the finger-shaped source electrodes 12a to the source electrodes 12c, the gate electrodes 14a to the gate electrodes 14c, and the drain electrodes 16a to the drain electrodes 16c is set to the Y direction (the second direction intersecting the first direction), and the arrangement direction of the source electrodes 12a to the source electrodes 12c, the gate electrodes 14a to the gate electrodes 14c, and the drain electrodes 16a to the drain electrodes 16c is set to the X direction (the first direction).

[0066] like Figures 1 to 3 As shown, in the semiconductor device 100 of the first embodiment, the substrate 10 includes a substrate 10a and a semiconductor layer 10b provided on the substrate 10a. In the XY plane parallel to the X direction and the Y direction, the region where the semiconductor layer 10b is inactivated by ion implantation or the like is the inactive region 13, the inactive region 13a and the inactive region 13b, and the region that is not inactivated (i.e., the region where a part of the substrate 10 is activated) is the active region 11a to the active region 11c. The active region 11a to the active region 11c extend in the X direction. The active region 11a to the active region 11c are arranged in the Y direction. Between the active region 11a and the active region 11b in the Y direction is the inactive region 13a (first inactive region). Between the active region 11b and the active region 11c in the Y direction is the inactive region 13b (second inactive region).

[0067] On the active region 11a (first active region) of the substrate 10, a plurality of unit FETs 35a (first FETs) are arranged in the X direction. On the active region 11b (second active region) of the substrate 10, a plurality of unit FETs 35b (second FETs) are arranged in the X direction. On the active region 11c (third active region) of the substrate 10, a plurality of unit FETs 35c (third FETs) are arranged in the X direction.

[0068] The unit FET 35a includes a source electrode 12a (first source electrode), a gate electrode 14a (first gate electrode), and a drain electrode 16a (first drain electrode). The source electrodes 12a and the drain electrodes 16a are alternately arranged in the X direction. One gate electrode 14a is provided between one source electrode 12a and one drain electrode 16a.

[0069] The unit FET 35b includes a source electrode 12b (second source electrode), a gate electrode 14b (second gate electrode), and a drain electrode 16b (second drain electrode). The source electrodes 12b and the drain electrodes 16b are alternately arranged in the X direction. One gate electrode 14b is provided between one source electrode 12b and one drain electrode 16b.

[0070] The unit FET 35c includes a source electrode 12c (third source electrode), a gate electrode 14c (third gate electrode), and a drain electrode 16c (third drain electrode). The source electrodes 12c and the drain electrodes 16c are alternately arranged in the X direction. One gate electrode 14c is provided between one source electrode 12c and one drain electrode 16c.

[0071] On the substrate 10, an insulating layer 30 is provided so as to cover the unit FETs 35a to 35c. Figures 1 to 3 In the figure, illustration of a source wiring connecting the source electrode 12a to the source electrode 12c, a gate wiring connecting the gate electrode 14a to the gate electrode 14c, and a drain wiring electrically connecting the drain electrode 16a to the drain electrode 16c is omitted.

[0072] When viewed from the Y direction, the plurality of unit FETs 35a, 35b, and 35c overlap each other. The unit FETs 35a to 35c have a central portion 50 in the X direction, an end portion 51 closer to the end E1 than the central portion 50, and an end portion 52 closer to the end E2 opposite to the end E1 than the central portion 50.

[0073] The gate electrodes 14a to 14c are each in a straight line extending in the Y direction. The distances between the source electrodes 12a to 12c and the gate electrodes 14a to 14c are substantially equal to each other, and the distances between the gate electrodes 14a to 14c and the drain electrodes 16a to 16c are substantially equal to each other. The widths (gate lengths) of the gate electrodes 14a and 14c in the X direction are substantially equal to each other.

[0074] The distance between the gate electrode 14a across the drain electrode 16a and the distance between the gate electrode 14a across the source electrode 12a may be different. Therefore, the distance D between the gate electrodes 14a is set to the distance between two gate electrodes 14a separated by one gate electrode 14a. The distance D between the gate electrodes 14b is set to the distance between two gate electrodes 14b separated by one gate electrode 14b, and the distance D between the gate electrodes 14c is set to the distance between two gate electrodes 14c separated by one gate electrode 14c.

[0075] In the plurality of unit FETs 35a, the plurality of distances D in the X direction between two gate electrodes 14a separated by one gate electrode 14a are substantially equal in the X direction. In the plurality of unit FETs 35c, the plurality of distances D in the X direction between two gate electrodes 14c separated by one gate electrode 14c are substantially equal in the X direction. That is, in the plurality of gate electrodes 14a, the distances DC1, DE1, and DE4 at the center 50, the end 51, and the end 52 are equal to each other. In the plurality of gate electrodes 14c, the distances DC3, DE3, and DE6 at the center 50, the end 51, and the end 52 are equal to each other.

[0076] In the plurality of unit FETs 35b, the interval between two gate electrodes 14b separated by one gate electrode 14b at the center portion 50 is larger than the interval between two gate electrodes 14b separated by one gate electrode 14b at the end portions 51 and 52. That is, in the plurality of gate electrodes 14b, the distance DC2 at the center portion 50 is larger than the distance DE2 and the distance DE5 at the end portions 51 and 52.

[0077] The position of the end E1 is roughly consistent among the plurality of unit FETs 35a, the plurality of unit FETs 35b, and the plurality of unit FETs 35c. The position of the end E2 is roughly consistent among the plurality of unit FETs 35a, the plurality of unit FETs 35b, and the plurality of unit FETs 35c. That is, when viewed from the Y direction, the unit FET 35a closest to the end E1, the unit FET 35b closest to the end E1, and the unit FET 35c closest to the end E1 overlap. When viewed from the Y direction, the unit FET 35a closest to the end E2, the unit FET 35b closest to the end E2, and the unit FET 35c closest to the end E2 overlap. The number of the plurality of unit FETs 35a, the plurality of unit FETs 35b, and the plurality of unit FETs 35c is the same as each other.

[0078] Under such a configuration, when distance DC2 is made larger than distance DE2 and distance DE5, distance DC2 becomes larger than distance DC1 and distance DC3, distance DE2 becomes smaller than distance DE1 and distance DE3, and distance DE5 becomes smaller than distance DE4 and distance DE6.

[0079] When the semiconductor device 100 is, for example, a nitride semiconductor device, the substrate 10a is, for example, a silicon carbide (SiC) substrate, a silicon (Si) substrate, a gallium nitride (GaN) substrate, or a sapphire (Al2O3) substrate. The semiconductor layer 10b includes, for example, a nitride semiconductor layer such as a gallium nitride layer, an aluminum gallium nitride (AlGaN) layer, and / or an indium gallium nitride (InGaN) layer. When the unit FETs 35a to 35c are GaN HEMTs (Gallium Nitride High Electron Mobility Transistors), the semiconductor layer 10b includes a gallium nitride channel layer provided on the substrate 10a and an aluminum gallium nitride barrier layer provided on the channel layer. When the semiconductor device 100 is, for example, a gallium arsenide (GaAs) semiconductor device, the substrate 10a is, for example, a gallium arsenide substrate. The semiconductor layer 10b includes, for example, an arsenide semiconductor layer such as a gallium arsenide layer, an aluminum gallium arsenide (AlGaAs) layer, and / or an indium gallium arsenide (InGaAs) layer. The semiconductor device 100 may be a silicon semiconductor device such as a LDMOS (Laterally Diffused Metal Oxide Semiconductor).

[0080] The source electrodes 12a to 12c and the drain electrodes 16a to 16c are metal films, for example, titanium films and aluminum films from the substrate 10 side. The gate electrodes 14a to 14c are metal films, for example, nickel films and gold films from the substrate 10 side. A low-resistance metal layer may also be provided on the source electrodes 12a to 12c and the drain electrodes 16a to 16c. The metal layer is, for example, a gold layer, and its resistivity is lower than the resistivity of the source electrodes 12a to 12c and the drain electrodes 16a to 16c. The insulating layer 30 is, for example, an inorganic insulating layer such as a silicon nitride layer or a silicon oxide layer, an organic insulating layer such as a polyimide layer or a BCB (Benzocyclobutene) layer, or a laminated film of an inorganic insulating layer and an organic insulating layer.

[0081] The width of the source electrodes 12a to 12c in the X direction is, for example, 5 μm to 150 μm. The gate length of the gate electrodes 14a to 14c in the X direction is, for example, 0.25 μm to 2 μm. The width of the drain electrodes 16a to 16c in the X direction is, for example, 5 μm to 150 μm. The gate width of the unit FETs 35a to 35c in the Y direction is, for example, 100 μm to 400 μm.

[0082] [Comparative Example 1]

[0083] Figure 41 is a diagram showing the configuration of the gate electrodes in the semiconductor device of Comparative Example 1. The upper diagram is a top view showing the configuration of the gate electrodes 14a to 14c in the semiconductor device 110 of Comparative Example 1. The middle diagram is a diagram showing the distance D in the X direction between two gate electrodes 14a to 14c separated by one gate electrode 14a to 14c relative to the position in the X direction of the semiconductor device 110. The lower diagram is a schematic diagram showing the temperature at the center line 54 in the Y direction of the semiconductor device 110 relative to the position in the X direction.

[0084] like Figure 4 As shown in the upper and middle figures of FIG. 1 , the distance D is equal to each other in the gate electrodes 14a to 14c, which is the distance D0. The heat generated in the plurality of unit FETs 35a and 35c and the unit FETs 35b located at the end portions 51 and 52 is easily diffused to the surroundings. On the other hand, the heat generated in the unit FETs 35b at the central portion 50 is difficult to diffuse to the surroundings. Therefore, as Figure 4 As shown in the figure below, the temperature of the unit FET 35b in the region 55 near the center in the X direction becomes high. Therefore, the temperature difference between the unit FET 35b in the region 55 and the unit FETs 35a to 35c at the end 51 and the end 52 becomes large. Therefore, the high-frequency characteristics and other characteristics of the unit FETs 35a to 35c become uneven. Therefore, the characteristics of the semiconductor device 110 deteriorate.

[0085] [Comparative Example 2]

[0086] Figure 5 1 and 12 are diagrams showing the configuration of gate electrodes in the semiconductor device of Comparative Example 2. The upper diagram is a top view showing the configuration of gate electrodes 14a to 14c in the semiconductor device 112 of Comparative Example 2. The middle diagram is a diagram showing the distance D in the X direction between two gate electrodes 14a to 14c separated by one gate electrode 14a to 14c relative to the position in the X direction of the semiconductor device 112. The lower diagram is a schematic diagram showing the temperature at the center line 54 in the Y direction of the semiconductor device 112 relative to the position in the X direction.

[0087] like Figure 5 As shown in the upper and middle figures of , the distance DC at the central portion 50 is made greater than the distance DE at the end portions 51 and 52. The distance DC at the central portion 50 is equal to each other in the gate electrodes 14a to 14c, and the distance DE at the end portions 51 and 52 is equal to each other in the gate electrodes 14a to 14c.

[0088] In the unit FET 35b of the central portion 50, the density of the gate electrode 14b in the X direction is low. Therefore, in the unit FET 35b of the central portion 50, the heat generation is small, and the temperature of the unit FET 35b of the central portion 50 can be reduced. The density of the gate electrode 14b in the X direction at the end portion 51 and the end portion 52 is high. The heat generation in the unit FETs 35a to 35c at the end portion 51 and the end portion 52 is large. The unit FET 35b in the region 56 near the central portion 50 of the end portion 51 and the end portion 52 is surrounded by the region 57 with high density of the gate electrodes 14a to 14c in three directions. The remaining one direction is the direction of the central portion 50. Therefore, the heat generated in the unit FET 35b in the region 56 is difficult to diffuse. As a result, as shown in the figure below, the temperature of the unit FET 35b in the region 56 will rise. As a result, the temperature distribution of the unit FETs 35a to 35c will become larger, and the characteristics such as high-frequency characteristics will become non-uniform. As a result, the characteristics as the semiconductor device 112 will deteriorate. Even if an attempt is made to change the distance DC and the distance DE for optimization, it is difficult to reduce the temperature distribution of the unit FET 35 a to the unit FET 35 c .

[0089] [Description of Example 1]

[0090] Figure 6 1 is a diagram showing the configuration of the gate electrodes in the semiconductor device of Example 1. The upper diagram is a top view showing the configuration of the gate electrodes 14a to 14c in the semiconductor device 100 of Example 1. The middle diagram is a diagram showing the distance D in the X direction between two gate electrodes 14a to 14c separated by one gate electrode 14a to 14c relative to the position in the X direction of the semiconductor device 100. The lower diagram is a schematic diagram showing the temperature at the center line 54 in the Y direction of the semiconductor device 100 relative to the position in the X direction.

[0091] like Figure 6As shown in the upper and middle figures of , the distance DC2 of the gate electrode 14b at the central portion 50 is made greater than the distance DC1 and the distance DC3 of the gate electrode 14a and the gate electrode 14c. The distance DE2 and the distance DE5 of the gate electrode 14b at the end portions 51 and 52 are made smaller than the distance DE1, the distance DE3, the distance DE4, and the distance DE6 of the gate electrode 14a and the gate electrode 14c. The heat generated by the unit FET 35a and the unit FET 35c at the end portions 51 and 52 is smaller than the heat generated by the unit FET 35b at the end portions 51 and 52. Therefore, the heat generated in the unit FET 35b at the end portions 51 and 52 is easily diffused in the positive (+) direction and the negative (-) direction in the Y direction as shown by the arrow 58. As a result, as shown in the figure below, the temperature distribution of the unit FET 35a to the unit FET 35c becomes more uniform. As a result, the high-frequency characteristics of the unit FET 35a to the unit FET 35c can be further uniformized, and the degradation of the characteristics as the semiconductor device 100 can be suppressed.

[0092] [Example 2]

[0093] Figure 7 1 and 2 are diagrams showing the arrangement of gate electrodes in the semiconductor device of Example 2. The upper diagram is a plan view showing the arrangement of gate electrodes 14a to 14c in the semiconductor device 101 of Example 2. The lower diagram is a diagram showing the distance D in the X direction between two gate electrodes 14a to 14c separated by one gate electrode 14a to 14c with respect to the position in the X direction of the semiconductor device 101.

[0094] like Figure 7 As shown, in the semiconductor device 101 of the second embodiment, an intermediate portion 51a is provided between the end portion 51 and the central portion 50. An intermediate portion 52a is provided between the end portion 52 and the central portion 50. The distances D between the gate electrode 14a and the gate electrode 14c at the intermediate portion 51a are DM1 to DM3, respectively. The distances D between the gate electrode 14a and the gate electrode 14c at the intermediate portion 52a are DM4 to DM6, respectively. The distance DM2 and the distance DM5 are smaller than the distance DC2 and larger than the distance DE2 and the distance DE5. The distance DM1, the distance DM3, the distance DM4, and the distance DM6 are equal to the distance DC1, the distance DC3, the distance DE1, the distance DE3, the distance DE4, and the distance DE6. The other configurations are the same as those of the first embodiment, and the description thereof is omitted.

[0095] Figure 81 and 12 are diagrams showing the arrangement of gate electrodes in a semiconductor device of Comparative Example 3. The upper diagram is a plan view showing the arrangement of gate electrodes 14a to 14c in a semiconductor device 114 of Comparative Example 3. The lower diagram is a diagram showing the distance D in the X direction between two gate electrodes 14a to 14c separated by one gate electrode 14a to 14c with respect to the position in the X direction of the semiconductor device 114.

[0096] like Figure 8 As shown, in the semiconductor device 114 of Comparative Example 3, the distance D between the gate electrode 14a and the gate electrode 14c at the center portion 50 is DC and is equal to each other. The distance D between the gate electrode 14a and the gate electrode 14c at the end portion 51 and the end portion 52 is DE and is equal to each other. The distance D between the gate electrode 14a and the gate electrode 14c at the middle portion 51a and the middle portion 52a is DM and is equal to each other. The other configurations are the same as those of Example 2.

[0097] [simulation]

[0098] The temperature distribution was simulated for Example 2 and Comparative Example 3. In the simulation, a heat source in parallel with the gate electrodes 14a to 14c was provided on the substrate 10, and a current was passed through the heat source to generate heat. The simulation conditions were as follows.

[0099] Substrate 10a: 100 μm thick silicon carbide substrate

[0100] Semiconductor layer 10b: GaN layer with a thickness of 0.6 μm

[0101] Substrate 10: 3.26 mm width in the X direction, 0.8 mm width in the Y direction

[0102] Size of the heat source: 5μm in width in the X direction, 180μm in width in the Y direction

[0103] Passive regions 13a, 13b: width in the Y direction is 10 μm

[0104] Central portion 50: eight gate electrodes

[0105] Middle parts 51a and 52a: five gate electrodes each

[0106] Ends 51 and 52: six gate electrodes each

[0107] Distance D of Example 2

[0108] DC2=210μm, DM2, DM5=190μm, DE2, DE5=170μm

[0109] DC1, DC3, DM1, DM3, DM4, DM6, DE1, DE3, DE4, DE6 = 190 μm Distance D of Comparative Example 3

[0110] DC=210μm, DM=190μm, DE=170μm

[0111] The values ​​of the distance DC, the distance DM, and the distance DE of Comparative Example 3 are optimized in such a way that the maximum temperature becomes lower. The values ​​of the distance DC2, the distance DM2, the distance DM5, the distance DE2, and the distance DE5 of Example 2 are set to be the same as the values ​​of the distance DC, the distance DM, and the distance DE optimized in Comparative Example 3. The distance DC1, the distance DC3, the distance DM1, the distance DM3, the distance DM4, the distance DM6, the distance DE1, the distance DE3, the distance DE4, and the distance DE6 are set to be equal to each other.

[0112] The following shows the maximum temperature on the substrate 10 in the simulation results in which the heat generation amounts of the heat sources were made the same.

[0113] Example 2: 108.2°C

[0114] Comparative Example 3: 108.9°C

[0115] As described above, the maximum temperature of Example 2 is lower than that of Comparative Example 3 in which the distance DC, the distance DM, and the distance DE are optimized. It can be considered that the temperature distribution in Example 2 is smaller than that in Comparative Example 3. Therefore, in the semiconductor device 101 of Example 2, the characteristics of the unit FETs 35a to 35c can be made uniform compared to the semiconductor device 114 of Comparative Example 3, and the degradation of the characteristics of the semiconductor device 101 can be suppressed.

[0116] [Example 3]

[0117] Embodiment 3 is an example of the source wiring, gate wiring, and drain wiring in Embodiment 1 and Embodiment 2. Fig. 9 It is a top view of the semiconductor device of Example 3. Fig. 9 The plan views of the central portions of Example 1 and Example 2 are shown.

[0118] like Fig. 9 As shown, the distance DC2 is greater than the distance DC1 and the distance DC3. A source wiring 22a, a gate wiring 24a, and a drain wiring 26a are provided on the substrate 10 at the inactive area 13a between the active area 11a and the active area 11b. The source wiring 22a electrically connects the source electrode 12a to the source electrode 12b. The gate wiring 24a electrically connects the gate electrode 14a to the gate electrode 14b. The drain wiring 26a electrically connects the drain electrode 16a to the drain electrode 16b.

[0119] A source wiring 22b, a gate wiring 24b, and a drain wiring 26b are provided on the substrate 10 at the inactive region 13b between the active region 11b and the active region 11c. The source wiring 22b electrically connects the source electrode 12b to the source electrode 12c. The gate wiring 24b electrically connects the gate electrode 14b to the gate electrode 14c. The drain wiring 26b electrically connects the drain electrode 16b to the drain electrode 16c.

[0120] A drain bus bar 27 and a gate bus bar 28 are provided on the substrate 10 via the unit FETs 35a to 35c. The drain bus bar 27 is electrically connected to the drain electrodes 16a to 16c. The gate bus bar 28 is electrically connected to the gate electrodes 14a to 14c.

[0121] The source electrodes 12a to 12c are electrically connected to a metal layer provided on the lower surface of the substrate 10 through vias (not shown) connected to the source electrodes 12a to 12c and penetrating the substrate 10. The source electrodes 12a to 12c may also be electrically connected to a source bus bar.

[0122] As described above, source potential is supplied to source electrodes 12a to 12c from the metal layer provided on the lower surface of substrate 10. Gate potential is supplied to gate electrodes 14a to 14c from gate bus bar 28. Drain potential is supplied to drain electrodes 16a to 16c from drain bus bar 27.

[0123] [Variation 1 of Example 3]

[0124] Modification 1 of Embodiment 3 is an example of the source wiring, gate wiring, and drain wiring in Embodiment 1 and Embodiment 2. Fig.10 It is a top view of a semiconductor device according to a first variation of the third embodiment. Fig.10 The plan views of the central portions of Example 1 and Example 2 are shown.

[0125] like Fig.10 As shown, two source wirings 22a are connected to one source electrode 12a. The two source wirings 22a are respectively connected to the two source electrodes 12b, respectively connected to the two source wirings 22b, and respectively connected to the two source electrodes 12c. A gate wiring 24 is provided between the two source wirings 22a, the two source electrodes 12b, the two source wirings 22b, and the two source electrodes 12c. The negative (-) end of the gate wiring 24 in the Y direction is electrically connected to the gate bus 28. In the inactive region 13a, the gate wiring 25a crosses the source wiring 22a in a non-contact manner to electrically connect the gate wiring 24 to the gate electrode 14a. In the inactive region 13b, the gate wiring 25b crosses the source wiring 22b in a non-contact manner to electrically connect the gate wiring 24 to the gate electrode 14b.

[0126] Thus, the gate potential is directly supplied to the gate electrode 14c from the gate bus bar 28. The gate potential is supplied to the gate electrode 14a and the gate electrode 14b via the gate wiring 24, the gate wiring 25a, and the gate wiring 25b from the gate bus bar 28. By providing the gate wiring 24, the gate resistance can be suppressed.

[0127] The via hole 20 penetrates the substrate 10, and when viewed from the Z direction, the via hole 20 overlaps with the source electrode 12a, and the via hole 20 is electrically connected to the source electrode 12a. Thus, the source potential is supplied from the metal layer provided on the lower surface of the substrate 10 to the source electrode 12a, the source potential is supplied from the source electrode 12a to the source electrode 12b via the source wiring 22a, and the source potential is supplied from the source electrode 12a to the source electrode 12c via the source wiring 22a, the source electrode 12b, and the source wiring 22b. The other configurations are the same as those in Embodiment 3, and the description thereof is omitted.

[0128] [Example 4]

[0129] Fig.11 FIG. 4 is a diagram showing a distance D relative to a position X in a semiconductor device of Example 4. Fig.11 As shown, in the semiconductor device 104 of the fourth embodiment, the distance DC1 and the distance DC3 between the gate electrode 14a and the gate electrode 14c at the center 50 are greater than the distance DE1, the distance DE3, the distance DE4, and the distance DE6 between the gate electrode 14a and the gate electrode 14c at the end 51 and the end 52. The distance DC2 is greater than the distance DC1 and the distance DC3, and the distance DE2 and the distance DE5 are smaller than the distance DE1, the distance DE3, the distance DE4, and the distance DE6. The other structures are the same as those of the first embodiment, and the description is omitted. As in the fourth embodiment, the distance D between the gate electrode 14a and the gate electrode 14c may be different at the center 50 and the end 51 and the end 52.

[0130] [Variation 1 of Example 4]

[0131] Fig.12 FIG. 4 is a diagram showing a distance D relative to a position X in a semiconductor device according to a first variation of the fourth embodiment. Fig.12 As shown, in the semiconductor device 105 of the first variation of the fourth embodiment, the distance D2 of the gate electrode 14b gradually increases from the end E1 and the end E2 to the center. The distance D1 and the distance D3 of the gate electrode 14a and the gate electrode 14c are the distance D0 and are constant. The other configurations are the same as those of the first embodiment, and the description is omitted. As in the first variation of the fourth embodiment, the distance D2 of the gate electrode 14b may gradually change as the position X moves toward the center in the X direction.

[0132] [Variation 2 of Example 4]

[0133] Fig.13FIG. 4 is a diagram showing a distance D relative to a position X in a semiconductor device according to a second variation of the fourth embodiment. Fig.13 As shown, in the semiconductor device 106 of the second variation of the fourth embodiment, the distance D1 and the distance D3 between the gate electrode 14a and the gate electrode 14c gradually increase from the end E1 and the end E2 to the center. At the center 50, the distance D2 is greater than the distance D1 and the distance D3, and at the end 51 and the end 52, the distance D2 is smaller than the distance D1 and the distance D3. The other configurations are the same as those of the first variation of the fourth embodiment, and the description thereof is omitted. As in the second variation of the fourth embodiment, the distance D1 and the distance D3 between the gate electrode 14a and the gate electrode 14c may gradually change as the position X moves toward the center in the X direction.

[0134] [Variation 3 of Example 4]

[0135] Fig.14 FIG. 4 is a diagram showing a distance D relative to a position X in a semiconductor device according to a third variation of the fourth embodiment. Fig.14 As shown, in the semiconductor device 107 of the third variation of the fourth embodiment, the distance D between the gate electrode 14a and the gate electrode 14b is the same as that of the first embodiment. The distance DC3, the distance DE3, and the distance DE6 of the gate electrode 14c are the same as those of the fourth embodiment. The other configurations are the same as those of the first embodiment, and the description thereof is omitted. As in the third variation of the fourth embodiment, the distance D may be different between the gate electrode 14a and the gate electrode 14c.

[0136] [Variation 4 of Example 4]

[0137] Fig.15 1 and 2 are diagrams showing the arrangement of gate electrodes in a semiconductor device according to a fourth variation of the fourth embodiment. The upper diagram is a plan view showing the arrangement of gate electrodes 14a to 14c in a semiconductor device 108 according to a fourth variation of the fourth embodiment. The lower diagram is a diagram showing the distance D in the X direction between two gate electrodes 14a to 14c separated by one gate electrode 14a to 14c with respect to the position in the X direction of the semiconductor device 108.

[0138] like Fig.15 As shown in the above figure, between the gate electrode 14a and the gate electrode 14c, three columns of gate electrodes 14b arranged in the X direction are provided in the Y direction. The distances DC2, DE2, and DE5 of the three columns of unit FETs 35b are the same as each other. The other structures are the same as those in the first embodiment, and the description is omitted. As in the modification 4 of the fourth embodiment, it is also possible to arrange in the Y direction more than two columns of a plurality of unit FETs 35b arranged in the X direction.

[0139] [Variation 5 of Example 4]

[0140] Fig.16 The diagrams show the arrangement of gate electrodes in a semiconductor device according to a fifth variation of the fourth embodiment. The upper diagram is a plan view showing the arrangement of gate electrodes 14a to 14c in a semiconductor device 109 according to a fifth variation of the fourth embodiment. The lower diagram is a diagram showing the distance D in the X direction between two gate electrodes 14a to 14c separated by one gate electrode 14a to 14c with respect to the position in the X direction of the semiconductor device 109.

[0141] like Fig.16 As shown in the above figure, in the Y direction, three columns of gate electrodes 14ba, gate electrodes 14b and gate electrodes 14bb are arranged in the Y direction between the gate electrodes 14a and the gate electrodes 14c. The distances D between the gate electrodes 14ba at the center 50, the end 51 and the end 52 are DC2a, DE2a and DE5a, respectively. The distances D between the gate electrodes 14bb at the center 50, the end 51 and the end 52 are DC2b, DE2b and DE5b, respectively.

[0142] At the center portion 50, the distance DC2a and the distance DC2b are smaller than the distance DC2 and larger than the distance DC1 and the distance DC3. At the end portion 51, the distance DE2a and the distance DE2b are larger than the distance DE2 and smaller than the distance DE1 and the distance DE3. At the end portion 52, the distance DE5a and the distance DE5b are larger than the distance DE5 and smaller than the distance DE4 and the distance DE6. Thus, the temperature can be further uniformed. The other configurations are the same as those of the variation 4 of the embodiment 4, and the description is omitted. As in the variation 5 of the embodiment 4, in the case where two or more columns of a plurality of unit FETs 35b are arranged in the Y direction, the distance DC2a, the distance DC2, and the distance DC2b are different from each other, the distance DE2a, the distance DE2, and the distance DE2b are different from each other, and the distance DE5a, the distance DE5, and the distance DE5b are different from each other.

[0143] According to Embodiments 1 to 4 and their variations, the distance DC2 (first distance) is greater than the distance DE2 (second distance), wherein the distance DC2 is the distance between two gate electrodes 14b separated by one gate electrode 14b at the central portion 50 in the X direction of the unit FET 35a to the unit FET 35c in the X direction, and the distance DE2 is the distance between two gate electrodes 14b separated by one gate electrode 14b at the first end portion 51 in the X direction close to the first end E1 of the unit FET 35a to the unit FET 35c. The distance DE2 is less than the distance DE1 (third distance), wherein the distance DE1 is the distance between two gate electrodes 14a separated by one gate electrode 14a at the first end portion 51. Thus, it is possible to Figure 6As shown in the figure above, heat is dissipated from the region 56 at the end 51 as indicated by arrow 58. Thus, the temperature distribution of the unit FETs 35a to 35c can be made uniform, so the characteristics of the unit FETs 35a to 35c can be made uniform. Thus, the degradation of the characteristics of the semiconductor device can be suppressed.

[0144] The distance DC2 is greater than the distance DC1 (the fourth distance), wherein the distance DC1 is the distance between two gate electrodes 14a separated by one gate electrode 14a at the central portion 50. Thus, the temperature distribution of the unit FETs 35a to 35c can be further uniformized. Thus, the degradation of the characteristics of the semiconductor device can be further suppressed.

[0145] The distance DE2 is smaller than the distance DE3 (fifth distance), wherein the distance DE3 is the distance between two gate electrodes 14c separated by one gate electrode 14c at the end 51. Figure 6 As shown in the figure above, heat is dissipated from the region 56 at the end 51 in the negative (-) direction in the Y direction as shown by arrow 58. Thus, the temperature distribution of the unit FETs 35a to 35c can be made more uniform. Thus, the degradation of the characteristics of the semiconductor device can be suppressed.

[0146] The distance DC2 is greater than the distance DC1 and greater than the distance DC3 (the sixth distance), wherein the distance DC3 is the distance between two gate electrodes 14c separated by one gate electrode 14c at the central portion 50. Thus, the temperature distribution from the unit FET 35a to the unit FET 35c can be further uniformed. Thus, the degradation of the characteristics of the semiconductor device can be further suppressed.

[0147] As in the second embodiment, an intermediate portion 51a is provided between the central portion 50 and the end portion 51 in the X direction. The distance DM2 (the seventh distance) is greater than the distance DE2 and less than the distance DC2, wherein the distance DM2 is the distance between two gate electrodes 14b separated by one gate electrode 14b at the intermediate portion 51a. Thus, the temperature distribution of the unit FETs 35a to 35c can be further uniformized. Thus, the degradation of the characteristics of the semiconductor device can be further suppressed.

[0148] As in the first to fourth embodiments and their variations, the distance DC2 is greater than the distance DE5 (eighth distance), wherein the distance DE5 is the distance between two gate electrodes 14b separated by one gate electrode 14b at the second end portion 52 near the second end E2 opposite to the first end E1. Figure 6 As shown in the upper figure, heat is dissipated from the region 56 at the end 52 as indicated by arrow 58. Thus, the temperature distribution of the unit FETs 35a to 35c can be made more uniform. Thus, the degradation of the characteristics of the semiconductor device can be suppressed.

[0149] The distance DE5 is smaller than the distance DE4 (the ninth distance), wherein the distance DE4 is the distance between two gate electrodes 14a separated by one gate electrode 14a at the second end portion 52. The distance DE5 is smaller than the distance DE6 (the tenth distance), wherein the distance DE6 is the distance between two gate electrodes 14c separated by one gate electrode 14c at the second end portion 52. Figure 6 As shown in the figure above, heat is dissipated from the region 56 at the end 52 in both the positive (+) direction and the negative (-) direction in the Y direction as shown by arrow 58. As a result, the temperature distribution of the unit FETs 35a to 35c can be made more uniform. As a result, the degradation of the characteristics of the semiconductor device can be suppressed.

[0150] The distance DC1 to the distance DC3 are assumed to be the distance D between the gate electrodes 14a and the gate electrodes 14c of the unit FETs 35a to 35c including the centers of the plurality of unit FETs 35a to 35c located in the X direction. The distance DE1 to the distance DE6 are assumed to be the distance D between the gate electrodes 14a and the gate electrodes 14c including the unit FETs 35a to 35c closest to the end E1 or the end E2. At this time, the distance DC2 of the unit FET 35b can be set to be 1.01 times or more of the distance DE2 and the distance DE5, can be set to be 1.05 times or more, and can be set to be 1.1 times or more. When the difference between the distance DC2 and the distance DE2 and the distance DE5 is large, it is difficult to configure the unit FET 35b. From this point of view, the distance DC2 can be set to be 1.5 times or less of the distance DE2 and the distance DE5.

[0151] From the perspective of temperature uniformity, distance DC2 can be set to 1.01 times or more, 1.05 times or more, or 1.1 times or more of distance DC1 and distance DC3. From the perspective of easy configuration, distance DC2 can be set to 1.5 times or less of distance DC1 and distance DC3. From the perspective of temperature uniformity, distance DE2 and distance DE5 can be set to 0.99 times or less, 0.95 times or less, or 0.9 times or less of distance DE1, distance DE3, distance DE4, and distance DE6. From the perspective of easy configuration, distance DE2 and distance DE5 can be set to 0.6 times or more of distance DE1, distance DE3, distance DE4, and distance DE6.

[0152] When the distance D is made different in a plurality of unit FETs 35a and the distance D is made different in a plurality of unit FETs 35c, it is difficult to design the unit FETs 35a and the unit FETs 35c. As in Example 1, Example 2, and Modification 4 and Modification 5 of Example 4, in a plurality of gate electrodes 14a, the distances DC1, DE1, and DE4 at the center 50, the end 51, and the end 52 are the distance D0, which are equal to each other. In a plurality of gate electrodes 14c, the distances DC3, DE3, and DE6 at the center 50, the end 51, and the end 52 are the distance D0, which are equal to each other. Thus, it is easy to design the unit FETs 35a and the unit FETs 35c. It should be noted that the distances D0 being equal to each other (approximately equal) means that manufacturing errors are allowed.

[0153] In addition, the number of unit FETs 35a, the number of unit FETs 35b, and the number of unit FETs 35c are the same. Thus, the source electrodes 12a to the source electrodes 12c of the corresponding unit FETs 35a to 35c can be electrically connected, and the drain electrodes 16a to the drain electrodes 16c of the corresponding unit FETs 35a to 35c can be electrically connected as in the third embodiment and the first variation thereof.

[0154] The unit FET 35a includes a source electrode 12a and a drain electrode 16a via a gate electrode 14a. The unit FET 35b includes a source electrode 12b and a drain electrode 16b via a gate electrode 14b. The unit FET 35c includes a source electrode 12c and a drain electrode 16c via a gate electrode 14c. Thus, the unit FETs 35a to 35c can be configured.

[0155] As in Example 3 and its variation 1, the plurality of source electrodes 12a are connected to the corresponding source electrodes 12b in the inactive region 13a. The plurality of drain electrodes 16a are connected to the corresponding drain electrodes 16b in the inactive region 13a. The plurality of source electrodes 12b are connected to the corresponding source electrodes 12c in the inactive region 13b. The plurality of drain electrodes 16b are connected to the corresponding drain electrodes 16c in the inactive region 13b. Thus, the unit FET 35a and the unit FET 35b, and the unit FET 35b and the unit FET 35c can be electrically connected to each other.

[0156] In the first to fourth embodiments and their variations, examples were described in which 14 or 30 unit FETs 35a to 35c were arranged in the X direction, but a plurality of unit FETs 35a to 35c may be arranged in the X direction. Examples were described in which three or five columns of unit FETs 35a to 35c arranged in the X direction were arranged in the Y direction, but more than three columns of unit FETs 35a to 35c may be arranged in the Y direction.

[0157] The embodiments disclosed herein are illustrative and non-restrictive in all aspects. The scope of the present disclosure is indicated by the claims rather than the above meanings, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Claims

1. A semiconductor device comprising: substrate; a plurality of first FETs, each of which has a plurality of first gate electrodes, wherein the plurality of first FETs are arranged in a first direction on the substrate; a plurality of second FETs, each of which has a plurality of second gate electrodes, wherein the plurality of second FETs are arranged in the first direction; and a plurality of third FETs, each having a plurality of third gate electrodes, the plurality of third FETs being arranged in the first direction, and the plurality of second FETs being arranged between the plurality of third FETs and the plurality of first FETs in a second direction intersecting the first direction, The first distance is greater than the second distance, wherein, The first distance is a distance between two second gate electrodes separated by one second gate electrode among the plurality of second gate electrodes at a central portion in the first direction of the plurality of first FETs, the plurality of second FETs, and the plurality of third FETs, and the second distance is a distance between two second gate electrodes separated by one second gate electrode among the plurality of second gate electrodes at a first end portion in the first direction close to the first end of the plurality of first FETs, the plurality of second FETs, and the plurality of third FETs, The second distance is smaller than a third distance, wherein the third distance is a distance between two first gate electrodes separated by one first gate electrode among the plurality of first gate electrodes at the first end.

2. The semiconductor device according to claim 1, wherein The first distance is greater than a fourth distance, wherein the fourth distance is a distance between two first gate electrodes separated by one first gate electrode among the plurality of first gate electrodes at the central portion.

3. The semiconductor device according to claim 1, wherein The second distance is smaller than a fifth distance, wherein the fifth distance is a distance between two third gate electrodes separated by one third gate electrode among the plurality of third gate electrodes at the first end.

4. The semiconductor device according to claim 3, wherein: The first distance is greater than a fourth distance, wherein the fourth distance is a distance between two first gate electrodes separated by one first gate electrode among the plurality of first gate electrodes at the central portion, The first distance is greater than a sixth distance, wherein the sixth distance is a distance between two third gate electrodes separated by one third gate electrode among the plurality of third gate electrodes at the central portion.

5. The semiconductor device according to any one of claims 1 to 4, wherein: The seventh distance is greater than the second distance and less than the first distance, wherein the seventh distance is the distance between two second gate electrodes separated by one second gate electrode among the plurality of second gate electrodes at the middle portion between the central portion and the first end portion in the first direction.

6. The semiconductor device according to claim 1, wherein The first distance is greater than an eighth distance, wherein the eighth distance is the distance between two second gate electrodes among the multiple second gate electrodes separated by a second gate electrode at a second end portion of the multiple first FETs, the multiple second FETs, and the multiple third FETs that are closer to the central portion and opposite to the first end.

7. The semiconductor device according to claim 4, wherein: The first distance is greater than an eighth distance, wherein the eighth distance is a distance between two second gate electrodes separated by one second gate electrode at a second end portion of the plurality of first FETs, the plurality of second FETs, and the plurality of third FETs that is closer to the second end opposite to the first end than the central portion, The eighth distance is smaller than a ninth distance, wherein the ninth distance is a distance between two first gate electrodes separated by one first gate electrode among the plurality of first gate electrodes at the second end, The eighth distance is smaller than the tenth distance, wherein the tenth distance is a distance between two third gate electrodes separated by one third gate electrode among the plurality of third gate electrodes at the second end.

8. The semiconductor device according to claim 2, wherein: The third distance and the fourth distance are equal to each other.

9. The semiconductor device according to any one of claims 1 to 4, wherein: The number of the plurality of first FETs, the number of the plurality of second FETs, and the number of the plurality of third FETs are the same as each other.

10. The semiconductor device according to any one of claims 1 to 4, wherein: The plurality of first FETs include a plurality of first source electrodes and a plurality of first drain electrodes, and the plurality of first gate electrodes are respectively arranged between one of the plurality of first source electrodes and one of the first drain electrodes in the first direction. The plurality of second FETs include a plurality of second source electrodes and a plurality of second drain electrodes, and the plurality of second gate electrodes are respectively arranged between one of the plurality of second source electrodes and one of the plurality of second drain electrodes in the first direction. The plurality of third FETs include a plurality of third source electrodes and a plurality of third drain electrodes, and the plurality of third gate electrodes are respectively arranged between one of the plurality of third source electrodes and one of the plurality of third drain electrodes in the first direction.

11. The semiconductor device according to claim 10, wherein The substrate comprises: a first active region, a second active region and a third active region; a first inactive region disposed between the first active region and the second active region; and a second inactive region disposed between the second active region and the third active region. The plurality of first FETs are disposed in the first active region, The plurality of second FETs are disposed in the second active region, The plurality of third FETs are disposed in the third active region, The plurality of first source electrodes are respectively connected to corresponding second source electrodes in the first inactive region, The plurality of first drain electrodes are respectively connected to corresponding second drain electrodes in the first inactive region, The plurality of second source electrodes are respectively connected to corresponding third source electrodes in the second inactive region, The plurality of second drain electrodes are respectively connected to corresponding third drain electrodes in the second inactive region.

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