Unidirectional silicon-controlled electrostatic protection device with high maintaining voltage and manufacturing method of unidirectional silicon-controlled electrostatic protection device

Abstract

The invention discloses a unidirectional silicon controlled electrostatic protection device with high maintaining voltage and a manufacturing method thereof, a forward bias diode, an NMOS (N-channel Metal Oxide Semiconductor) with a grounded grid electrode and a reverse bias diode are embedded in a PW (Pseudo Wire), an N + region of the forward bias diode D1 is a drain end N + region of the NMOS with the grounded grid electrode, and an N + region of the reverse bias diode D1 is a drain end N + region of the NMOS with the grounded grid electrode; the N + region of the reverse bias diode D2 is the N + region of the source end of the NMOS of which the grid electrode is grounded; according to the device, a surface ESD current discharge path is additionally arranged on the basis of a traditional unidirectional silicon controlled rectifier electrostatic protection device, shunting is carried out on an SCR path, and the positive feedback effect of the SCR discharge path can be effectively restrained; the silicon controlled rectifier electrostatic discharge device provided by the invention has the characteristics of high maintaining voltage and high failure current, and can realize high protection level while effectively avoiding the latch-up effect.

Description

Technical Field

[0001] The invention relates to the field of electrostatic protection, and in particular to a unidirectional thyristor electrostatic protection device with a high holding voltage and a manufacturing method thereof. Background Art

[0002] With the continuous advancement of semiconductor manufacturing technology, the failure of integrated circuit chips and electronic products caused by ESD (electrostatic discharge) has become more and more serious. ESD protection for electronic products and integrated circuit chips has become one of the main challenges faced by ESD engineers.

[0003] The cross-section diagram of the traditional unidirectional thyristor electrostatic protection device is shown in Figure 1 , its equivalent circuit diagram is shown in Figure 2 . When an ESD pulse is applied to the anode of the unidirectional SCR, the first N-well and the first P-well form a reverse-biased PN junction. When the ESD pulse voltage is higher than the avalanche breakdown voltage of this PN junction, a large amount of avalanche current will be generated inside the device, and the current will flow through the first P-well and flow to the cathode through the parasitic resistance. The voltage drop across the parasitic resistance of the first P-well is equivalent to the base voltage drop of the transistor NPN. When this voltage is higher than the forward conduction voltage of the vertical NPN transistor, the transistor is turned on. After this transistor is turned on, it provides base current for the horizontal PNP transistor. After the horizontal PNP transistor is also turned on, it further provides base current for the vertical NPN transistor, forming a positive feedback mechanism to fully open the SCR path. However, due to its PNPN structure, positive feedback mechanism, high current gain, low parasitic resistance and other factors, its maintenance voltage is too low, resulting in a high latch-up risk when applied to ESD protection of I / O circuits, so it is necessary to increase its maintenance voltage. Summary of the invention

[0004] In order to solve the above technical problems, the present invention provides a unidirectional thyristor electrostatic protection device with a high holding voltage and a manufacturing method thereof, and is applied to the design of an ESD protection network with a 12V working voltage.

[0005] The technical solution of the present invention to solve the above problems is:

[0006] In a first aspect, an embodiment of the present invention provides a high-maintaining voltage unidirectional thyristor electrostatic protection device, comprising a P-type substrate; an N-type buried layer and a P-type epitaxial layer are provided in the P-type substrate; a first high-voltage N-type well and a second high-voltage N-type well are provided above the N-type buried layer; a first N-type deep well is provided above the first high-voltage N-type well; a second N-type deep well is provided above the second high-voltage N-type well; a first N-well is provided on the first N-type deep well; a first P-well is provided on the P-type epitaxial layer; a second N-well is provided on the second N-type deep well; a first N+ injection and a first P+ injection are provided on the first N-well in sequence from left to right; a second P+ injection, a second N+ injection, a first gate, a third N+ injection, a third P+ injection, a fourth N+ injection, and a fourth P+ injection are provided on the first P-well in sequence from left to right; the first gate is between the second N+ injection and the third N+ injection;

[0007] The first N+ injection and the first P+ injection in the first N well are connected together and serve as the anode of the device; the fourth N+ injection and the fourth P+ injection in the first P well are connected together and serve as the cathode of the device; the second P+ and the second N+ injection in the first P well are connected together through a metal wire and are not connected to a potential; the first gate in the first P well is connected to the ground through a metal wire; the third N+ and the third P+ injection in the first P well are connected together through a metal wire and are not connected to a potential.

[0008] Preferably, there are eight field oxygen isolation regions; the first field oxygen isolation region is between the left side of the first N+ injection and the first N-type well, the second field oxygen isolation region is between the first N+ injection and the first P+ injection, the third field oxygen isolation region is between the first P+ injection and the second P+ injection, the fourth field oxygen isolation region is between the second P+ injection and the second N+ injection, the fifth field oxygen isolation region is between the third N+ injection and the third P+ injection, the sixth field oxygen isolation region is between the third P+ injection and the fourth N+ injection, the seventh field oxygen isolation region is between the fourth N+ injection and the fourth P+ injection, and the eighth field oxygen isolation region is between the right side of the fourth P+ injection and the second N-type well.

[0009] Preferably, the first field oxygen isolation region and the second field oxygen isolation region are located on the surface of the first N-well; the third field oxygen isolation region is located on the surface of the first N-well, the surface of the P-type epitaxial layer, and the surface of the first P-well; the fourth field oxygen isolation region, the fifth field oxygen isolation region, the sixth field oxygen isolation region, and the seventh field oxygen isolation region are located on the surface of the first P-well; the eighth field oxygen isolation region is located on the surface of the first P-well, the surface of the P-type epitaxial layer, and the surface of the second N-well.

[0010] Preferably, when a high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, its breakdown surface is between the first N-well and the P-type epitaxial layer and the first P-well; at this time, the second P+ injection and the second N+ injection constitute a forward-biased diode D1, the third N+ injection and the third P+ injection constitute a reverse-biased diode D2, the second N+ injection, the first gate, and the third N+ injection constitute NMOS, and when D1 is turned on, it will constitute an additional shunt path with NMOS and D2.

[0011] Preferably, when a high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the first P+ injection, the first N-well / first deep N-well / first high-voltage N-well / N-type buried layer and the first P-well constitute a parasitic transistor PNP, and the first N-well / first deep N-well / first high-voltage N-well / N-type buried layer, the first P-well and the fourth N+ injection constitute a parasitic transistor NPN. When the voltage drop reaches 0.7V, the parasitic transistor NPN on the right is turned on and provides base current to the parasitic transistor PNP on the left, thereby promoting its conduction. When the parasitic transistor PNP and the parasitic transistor NPN are turned on, a forward SCR path is formed, forming a positive feedback effect. At this time, the device is successfully triggered, and its breakdown surface is between the first N-well and the P-type epitaxial layer and the first P-well.

[0012] Preferably, when a high-voltage ESD pulse reaches the anode of the device and the cathode of the device is at ground potential, after the first N-well / P-type epitaxial layer and the first P-well junction are broken down, the ESD current in the first N-well will converge to the second P+ injection region, flow into the drain N+ region of the NMOS through the forward-biased diode D1, flow out from the source N+ region of the NMOS, and finally flow into the SCR path again through the reverse-biased diode D2; by introducing an additional shunt path, on the one hand, the positive feedback of the SCR can be suppressed, and on the other hand, after D1, NMOS, and D2 form a new shunt path, the hot spots inside the device are dispersed, which can increase the failure current of the device to a certain extent.

[0013] Preferably, the widths S1, S2 and S3 of the second P+ implant are adjustable. When S1 and S2 increase, the sustain voltage increases. When S3 increases, the trigger voltage increases, and the sustain voltage also increases.

[0014] In a second aspect, an embodiment of the present invention provides a method for manufacturing a unidirectional thyristor electrostatic protection device with a high holding voltage, comprising the following steps:

[0015] Step 1: forming an N-type buried layer and a P-type epitaxial layer on a P-type substrate;

[0016] Step 2: generating a first high-voltage N-type well and a second high-voltage N-type well above the N-type buried layer;

[0017] Step 3: generating a first N-type deep well in the first high-voltage N-type well, and generating a second N-type deep well in the second high-voltage N-type well;

[0018] Step 4: generating a first N-well in the first N-type deep well, generating a second N-well in the second N-type deep well, and generating a first P-well in the P-type epitaxial layer;

[0019] Step 5: Generate a first N+ injection and a first P+ injection on the first N well from left to right; generate a second P+ injection, a second N+ injection, a first gate, a third N+ injection, a third P+ injection, a fourth N+ injection, and a fourth P+ injection on the first P well from left to right;

[0020] Step 6: forming a first field oxygen isolation region on the left side of the first N+ injection on the first N well, generating a second field oxygen between the first N+ injection and the first P+ injection on the first N well, generating a third field oxygen between the first P+ injection on the first N well and the second P+ injection on the first P well, generating a fourth field oxygen between the second P+ injection and the second N+ injection on the first P well, generating a fifth field oxygen between the third N+ injection and the third P+ injection on the first P well, generating a sixth field oxygen between the third P+ injection and the fourth N+ injection on the first P well, generating a seventh field oxygen between the fourth N+ injection and the fourth P+ injection on the first P well, and generating an eighth field oxygen on the right side of the fourth P+ injection on the first P well;

[0021] Step 7: Annealing all implanted areas to eliminate the migration of impurities in the implanted areas;

[0022] Step 8: Connect the first N+ injection and the first P+ injection together and use them as the anode of the device, connect the second P+ injection and the second N+ together without connecting any potential, connect the third P+ injection and the third N+ injection together without connecting any potential, and connect the first gate and the fourth N+ injection and the fourth P+ injection together and use them as the cathode of the device.

[0023] Preferably, the forming of an N-type buried layer and a P-type epitaxial layer on a P-type substrate further includes:

[0024] A silicon dioxide film is grown on a P-type substrate, and then a silicon nitride layer is deposited; a photoresist layer is spin-coated on the wafer, and a mask is added to expose and develop it to form an isolation shallow groove; the silicon dioxide, silicon nitride and isolation shallow groove are etched to remove the photoresist layer, a silicon dioxide layer is deposited, and then chemical mechanical polishing is performed until the silicon nitride layer is reached to remove the silicon nitride layer.

[0025] The beneficial effects of the present invention are:

[0026] 1. The present invention can adjust the trigger voltage by adjusting the width of the breakdown surface. Based on the traditional unidirectional thyristor electrostatic protection device, the breakdown surface is changed from the well breakdown between the first N well and the first P well to the well breakdown between the first N well and the P-type epitaxial layer and the first P well. The trigger voltage and the holding voltage can be adjusted by adjusting the width of the breakdown surface.

[0027] 2. In order to further improve the performance of the unidirectional thyristor, the present invention can introduce two diodes and an NMOS structure without increasing the device layout area. The second P+ injection located in the first P well and the second N+ injection together constitute a forward biased diode D1, the third N+ injection located in the first P well and the third P+ injection together constitute a reverse biased diode D2, and the second N+ injection located in the first P well, the first gate, the third N+ injection and the fourth P+ injection constitute an NMOS. When the first N well / P-type epitaxial layer and the first P well junction are broken down, After that, the ESD current in the first N well will converge to the second P+ injection region, flow into the drain N+ region of the NMOS through the forward biased diode D1, flow out from the source N+ region of the NMOS, and finally flow into the SCR path again through the reverse biased diode D2; by introducing an additional shunt path, on the one hand, the positive feedback of the SCR can be suppressed, thereby suppressing the latch effect, thereby increasing the holding voltage of the device; on the other hand, after D1, NMOS, and D2 form a new shunt path, the hot spots inside the device are dispersed, which can increase the failure current of the device to a certain extent.

[0028] 3. The widths S1, S2, and S3 of the second P+ injection of the present invention are adjustable. When S1 and S2 increase, the diode area increases, and the current transmission capability of the path formed by D1, NMOS, and D2 increases, allowing more current to pass through the path. At the same time, the effective base widths of the two parasitic transistors increase, suppressing the positive feedback of the SCR and increasing the maintenance voltage. When S3 increases, the trigger voltage increases, and the maintenance voltage also increases. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a cross-sectional view of a traditional unidirectional SCR electrostatic protection device.

[0030] Figure 2 This is the equivalent circuit diagram of the traditional unidirectional SCR electrostatic protection device.

[0031] Figure 3 It is a cross-sectional view of an embodiment of the present invention.

[0032] Figure 4 2 is an equivalent circuit diagram of an embodiment of the present invention.

[0033] Figure 5A total current density distribution simulation diagram of a unidirectional thyristor electrostatic protection device with a high holding voltage provided by one embodiment of the present invention. DETAILED DESCRIPTION

[0034] The ESD protection design of the I / O port of the 12V DC power interface chip of the present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0035] like Figure 3 As shown, a high-maintaining voltage unidirectional thyristor electrostatic protection device includes a P-type substrate 101; an N-type buried layer 201 and a P-type epitaxial 301 are provided in the substrate; a first high-voltage N-type well 401 and a second high-voltage N-type well 402 are provided above the N-type buried layer 201; a first N-type deep well 501 and a second N-type deep well 502 are provided on the high-voltage N-type wells 401 and 402; a first N-well 601, a first P-well 603, and a second N-well 602 are provided on the N-type deep wells 501 and 502; the first N-well 601 is provided with a first N+ injection 801 and a first P+ injection 802 from left to right in sequence; the first P-well 603 is provided with a second P+ injection 803, a second N+ injection 804, a first gate 901, a third N+ injection 805, a third P+ injection 806, a fourth N+ injection 807, and a fourth P+ injection 808 from left to right in sequence; the first The gate 901 is between the second N+ injection 804 and the third N+ injection 805; the first N+ injection 801 and the first P+ injection 802 in the first N well 601 are connected together and serve as the anode of the device; the first gate 901, the fourth N+ injection 807, and the fourth P+ injection 808 in the first P well 603 are connected together and serve as the cathode of the device; the second P+ injection 803 and the second N+ injection 804 in the first P well are connected together through metal wires without connecting to a potential, and the third N+ injection 805 and the third P+ injection 806 in the first P well are connected together through metal wires without connecting to a potential; in this way, when D1 is turned on, it will form an additional shunt path with NMOS and D2, and part of the current of the SCR path will be discharged through this path, which will suppress the positive feedback effect in the original SCR path, thereby increasing the holding voltage.

[0036] In one embodiment, the high sustaining voltage unidirectional thyristor electrostatic protection device has eight field oxygen isolation regions; the first field oxygen isolation region 701 is between the left side of the first N+ injection 801 and the first N well 601, the second field oxygen isolation region 702 is between the first N+ injection 801 and the first P+ injection 802, the third field oxygen isolation region 703 is between the first P+ injection 802 and the second P+ injection 803, the fourth field oxygen isolation region 704 is between the second P+ injection 803 and the second N+ injection 804, the fifth field oxygen isolation region 705 is between the third N+ injection 805 and the third P+ injection 806, the sixth field oxygen isolation region 706 is between the third P+ injection 806 and the fourth N+ injection 807, the seventh field oxygen isolation region 707 is between the fourth N+ injection 807 and the fourth P+ injection 808, and the eighth field oxygen isolation region 708 is between the right side of the fourth P+ injection 808 and the second N well 602.

[0037] In one embodiment, the first field oxygen isolation region 701 and the second field oxygen isolation region 702 are located on the surface of the first N-well 601; the third field oxygen isolation region 703 is located on the surface of the first N-well 601, the surface of the P-type epitaxial layer 301, and the surface of the first P-well 603; the fourth field oxygen isolation region 704, the fifth field oxygen isolation region 705, the sixth field oxygen isolation region 706, and the seventh field oxygen isolation region 707 are located on the surface of the first P-well 603; the eighth field oxygen isolation region 708 is located on the surface of the first P-well 603, the surface of the P-type epitaxial layer 301, and the surface of the second N-well 602.

[0038] In one embodiment, if Figure 5 As shown, when the high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, its breakdown surface is between the first N well 601 and the P-type epitaxial layer 301 and the first P well 303; at this time, the second P+ injection 803 and the second N+ injection 804 form a forward-biased diode D1, the third N+ injection 805 and the third P+ injection 806 form a reverse-biased diode D2, the second N+ injection 804, the first gate 901, and the third N+ injection 805 form NMOS. When D1 is turned on, it will form an additional shunt path with NMOS and D2.

[0039] When the high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the first P+ injection 802, the first N-well 601 / the first deep N-well 501 / the first high-voltage N-well 401 / the N-type buried layer 201 and the first P-well 603 constitute a parasitic transistor PNP, and the first N-well 601 / the first deep N-well 501 / the first high-voltage N-well 401 / the N-type buried layer 201, the first P-well 603 and the fourth N+ injection 807 constitute a parasitic transistor NPN. When the voltage drop reaches 0.7V, the parasitic transistor NPN on the right is turned on and provides a base current to the parasitic transistor PNP on the left, thereby promoting its conduction. When the parasitic transistor PNP and the parasitic transistor NPN are turned on, a forward SCR path is formed, forming a positive feedback effect. At this time, the device is successfully triggered, and its breakdown surface is between the first N-well 601 and the P-type epitaxial layer 301 and the first P-well 603.

[0040] When a high-voltage ESD pulse reaches the anode of the device and the cathode of the device is grounded, after the junction of the first N-well 601 / P-type epitaxial layer 301 and the first P-well 603 is broken down, the ESD current in the first N-well 601 will converge to the second P+ injection region 803, flow into the drain N+ region 804 of the NMOS through the forward-biased diode D1, flow out from the source N+ region 805 of the NMOS, and finally flow into the SCR path again through the reverse-biased diode D2; by introducing an additional shunt path, on the one hand, the positive feedback of the SCR can be suppressed, and on the other hand, after D1, NMOS, and D2 form a new shunt path, the hot spots inside the device are dispersed, which can increase the failure current of the device to a certain extent.

[0041] This device can be adjusted according to the requirements of the ESD design window in different application scenarios by controlling the width S1 of the second P+ injection 803 and the third P+ injection 806. When S1 increases, the holding voltage increases; the width S2 of the second N+ injection 804 and the third N+ injection 805 is adjustable. Increasing their widths can effectively suppress the current saturation effect and improve the current conduction capacity of NMOS, thereby further improving the holding voltage and failure current, and reducing the on-resistance. As S1 and S2 increase, the base width of the parasitic transistor increases, thereby reducing the current gain coefficient β, thereby increasing the holding voltage. The width of S3 is also adjustable. By adjusting the distance between the first N well 601 and the first P well 603, the trigger voltage can be adjusted. The increase in the width of S3 increases the trigger voltage and the holding voltage.

[0042] The embodiment of the present invention also provides a method for manufacturing a unidirectional thyristor electrostatic protection device with a high holding voltage, comprising the following steps:

[0043] Step 1: forming an N-type buried layer 201 in a P-type substrate 101;

[0044] Step 2: forming a first high-voltage N-type well 401 and a second high-voltage N-type well 402 above the N-type buried layer 201;

[0045] Step 3: generating a first N-type deep well 501 in the first high-voltage N-type well 401 and generating a second N-type deep well 502 in the second high-voltage N-type well 402;

[0046] Step 4: generating a first N-well 601 in the first N-type deep well 501, generating a second N-well 602 in the second N-type deep well 502, and generating a first P-well 603 in the P-type epitaxial layer 301;

[0047] Step 5: Generate a first N+ injection 801 and a first P+ injection 802 from left to right on the first N well 601; generate a second P+ injection 803, a second N+ injection 804, a first gate 901, a third N+ injection 805, a third P+ injection 806, a fourth N+ injection 807, and a fourth P+ injection 808 from left to right on the first P well 603;

[0048] Step 6: Form a first field oxygen isolation region 701 on the left side of the first N+ implant 801 on the first N well 601, generate a second field oxygen isolation region 702 between the first N+ implant 801 and the first P+ implant 802 on the first N well 601, generate a third field oxygen isolation region 703 between the first P+ implant 802 on the first N well 601 and the second P+ implant 803 on the first P well 603, and generate a fourth field oxygen isolation region 704 between the second P+ implant 803 and the second N+ implant 804 on the first P well 603. A fifth field oxygen isolation region 705 is generated between the third N+ implant 805 and the third P+ implant 806 on the first P well 603, a sixth field oxygen isolation region 706 is generated between the third P+ implant 805 and the fourth N+ implant 807 on the first P well 603, a seventh field oxygen isolation region 707 is generated between the fourth N+ implant 807 and the fourth P+ implant 808 on the first P well 603, and an eighth field oxygen isolation region 708 is generated on the right side of the fourth P+ implant 808 on the first P well 603;

[0049] Step 7: Annealing all implanted areas to eliminate the migration of impurities in the implanted areas;

[0050] Step eight: Connect the first N+ injection 801 and the first P+ injection 802 together and use them as the anode of the device, connect the second P+ injection 803 and the second N+ 804 together without connecting any potential, connect the third N+ injection 805 and the third P+ injection 806 together without connecting any potential, and connect the first gate 901 and the fourth N+ injection 807 and the fourth P+ injection 808 together and use them as the cathode of the device.

[0051] The manufacturing method of the high-maintaining-voltage unidirectional thyristor electrostatic protection device of the present invention is simple and easy to operate. In order to further improve the performance of the unidirectional thyristor, the present invention can introduce two diodes and NMOS structures without increasing the device layout area, generating a new shunt path that weakens the positive feedback effect of the SCR path, thereby suppressing the latch effect, and effectively improving the device's protection performance and failure level. The device can be used in the ESD protection design of the I / O port of a 12V DC power interface chip. The example device of the present invention adopts a 0.18μm BCDMOS process.

[0052] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A high-maintaining-voltage unidirectional thyristor electrostatic protection device, characterized in that: include: A P-type substrate; an N-type buried layer and a P-type epitaxial layer are provided in the P-type substrate; a first P-well is provided on the P-type epitaxial layer; A first high-voltage N-type well and a second high-voltage N-type well are provided above the N-type buried layer; a first N-type deep well is provided above the first high-voltage N-type well; and a second N-type deep well is provided above the second high-voltage N-type well; A first N-well is disposed on the first N-type deep well; a second N-well is disposed on the second N-type deep well; a first N-well, a first P-well and a second N-well are disposed on the N-type deep well in sequence from left to right; a first N+ injection and a first P+ injection are disposed on the first N-well in sequence from left to right; The first P well is provided with a second P+ injection, a second N+ injection, a first gate, a third N+ injection, a third P+ injection, a fourth N+ injection, and a fourth P+ injection from left to right; The first gate is between the second N+ injection and the third N+ injection; The first N+ injection and the first P+ injection electrodes in the first N well are connected together and serve as the anode of the device; The fourth N+ injection in the first P well and the fourth P+ injection electrodes are connected together and serve as the cathode of the device; The second P+ and the second N+ injection in the first P well are connected together through a metal wire without connecting the potential; A first gate in the first P well is connected to ground through a metal line; The third N+ and the third P+ implants in the first P well are connected together through a metal wire and are not connected to a potential.

2. The high-maintaining-voltage unidirectional thyristor electrostatic protection device according to claim 1, characterized in that: Also includes: eight field oxygen isolation zones; The first field oxygen isolation zone is between the left side of the first N+ injection and the first N well, the second field oxygen isolation zone is between the first N+ injection and the first P+ injection, the third field oxygen isolation zone is between the first P+ injection and the second P+ injection, the fourth field oxygen isolation zone is between the second P+ injection and the second N+ injection, the fifth field oxygen isolation zone is between the third N+ injection and the third P+ injection, the sixth field oxygen isolation zone is between the third P+ injection and the fourth N+ injection, the seventh field oxygen isolation zone is between the fourth N+ injection and the fourth P+ injection, and the eighth field oxygen isolation zone is between the right side of the fourth P+ injection and the second N well.

3. The high-maintaining-voltage unidirectional thyristor electrostatic protection device according to claim 2, characterized in that: The first field oxygen isolation region and the second field oxygen isolation region are located on the surface of the first N-well; the third field oxygen isolation region is located on the surface of the first N-well, the surface of the P-type epitaxial layer, and the surface of the first P-well; the fourth field oxygen isolation region, the fifth field oxygen isolation region, the sixth field oxygen isolation region, and the seventh field oxygen isolation region are located on the surface of the first P-well; the eighth field oxygen isolation region is located on the surface of the first P-well, the surface of the P-type epitaxial layer, and the surface of the second N-well.

4. The high-maintaining-voltage unidirectional thyristor electrostatic protection device according to claim 1, characterized in that: When the high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, its breakdown surface is between the first N-well and the P-type epitaxial layer and the first P-well; at this time, the second P+ injection and the second N+ injection form a forward-biased diode D1, and the third N+ injection and the third P+ injection form a reverse-biased diode D2. The second N+ injection, the first gate, and the third N+ injection form NMOS. When D1 is turned on, it will form an additional shunt path with NMOS and D2.

5. The high-maintaining-voltage unidirectional thyristor electrostatic protection device according to claim 1, characterized in that: When the high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the first P+ injection, the first N-well / first deep N-well / first high-voltage N-well / N-type buried layer and the first P-well constitute a parasitic transistor PNP, and the first N-well / first deep N-well / first high-voltage N-well / N-type buried layer, the first P-well and the fourth N+ injection constitute a parasitic transistor NPN. When the voltage drop reaches 0.7V, the parasitic transistor NPN on the right is turned on and provides base current to the parasitic transistor PNP on the left, thereby promoting its conduction. When the parasitic transistor PNP and the parasitic transistor NPN are turned on, a forward SCR path is formed, forming a positive feedback effect. At this time, the device is successfully triggered, and its breakdown surface is between the first N-well and the P-type epitaxial layer and the first P-well.

6. The high holding voltage unidirectional thyristor electrostatic protection device according to claim 1, characterized in that: When the high-voltage ESD pulse reaches the anode of the device and the cathode of the device is grounded, after the first N-well / P-type epitaxial layer and the first P-well junction are broken down, the ESD current in the first N-well will converge to the second P+ injection region, flow into the drain N+ region of the NMOS through the forward-biased diode D1, flow out from the source N+ region of the NMOS, and finally flow into the SCR path again through the reverse-biased diode D2; by introducing an additional shunt path, on the one hand, the positive feedback of the SCR can be suppressed, and on the other hand, after D1, NMOS, and D2 form a new shunt path, the hot spots inside the device are dispersed, which can increase the failure current of the device to a certain extent.

7. The high-maintaining-voltage unidirectional thyristor electrostatic protection device according to claim 1, characterized in that: The widths S1, S2, and S3 of the second P+ implant are adjustable. When S1 and S2 increase, the sustaining voltage increases. When S3 increases, the triggering voltage increases, and the sustaining voltage increases.

8. A method for manufacturing a high-maintaining-voltage unidirectional thyristor electrostatic protection device according to any one of claims 1 to 7, comprising the following steps: Step 1: forming an N-type buried layer and a P-type epitaxial layer on a P-type substrate; Step 2: generating a first high-voltage N-type well and a second high-voltage N-type well above the N-type buried layer; Step 3: generating a first N-type deep well in the first high-voltage N-type well, and generating a second N-type deep well in the second high-voltage N-type well; Step 4: generating a first N-well in the first N-type deep well, generating a second N-well in the second N-type deep well, and generating a first P-well in the P-type epitaxial layer; Step 5: Generate a first N+ injection and a first P+ injection on the first N well from left to right in sequence; Generating a second P+ injection, a second N+ injection, a first gate, a third N+ injection, a third P+ injection, a fourth N+ injection, and a fourth P+ injection on the first P well from left to right in sequence; Step 6: forming a first field oxygen isolation region on the left side of the first N+ injection on the first N well, generating a second field oxygen between the first N+ injection and the first P+ injection on the first N well, generating a third field oxygen between the first P+ injection on the first N well and the second P+ injection on the first P well, generating a fourth field oxygen between the second P+ injection and the second N+ injection on the first P well, generating a fifth field oxygen between the third N+ injection and the third P+ injection on the first P well, generating a sixth field oxygen between the third P+ injection and the fourth N+ injection on the first P well, generating a seventh field oxygen between the fourth N+ injection and the fourth P+ injection on the first P well, and generating an eighth field oxygen on the right side of the fourth P+ injection on the first P well; Step 7: Annealing all implanted areas to eliminate the migration of impurities in the implanted areas; Step 8: Connect the first N+ injection and the first P+ injection together and use them as the anode of the device, connect the second P+ injection and the second N+ together without connecting any potential, connect the third P+ injection and the third N+ injection together without connecting any potential, and connect the first gate and the fourth N+ injection and the fourth P+ injection together and use them as the cathode of the device.

9. The method for manufacturing a high-maintaining-voltage unidirectional thyristor electrostatic protection device according to claim 8, characterized in that: The following steps are also included before step one: growing a layer of silicon dioxide film on a P-type substrate, and then depositing a layer of silicon nitride; spin coating a photoresist layer on the wafer, exposing and developing it with a mask to form an isolation shallow groove; etching the silicon dioxide, silicon nitride and the isolation shallow groove to remove the photoresist layer, depositing a layer of silicon dioxide, and then performing chemical polishing until the silicon nitride layer is formed to remove the silicon nitride layer.

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