Electronic device

Abstract

The invention discloses electronic equipment. The electronic equipment comprises a first substrate, a scanning line, a shared electrode line, a first insulating layer, a conductive layer and a second insulating layer, wherein the scanning line and the shared electrode line are arranged on the first substrate, and the shared electrode line is adjacent to the scanning line. The first insulating layer is arranged on the scanning line and the shared electrode line, the conductive layer is arranged on the first insulating layer, and the conductive layer partially overlaps the shared electrode line. The second insulating layer is disposed on the conductive layer. Wherein a top surface of the second insulating layer has a first thickness between a position corresponding to the scanning line and the first substrate, the top surface of the second insulating layer has a third thickness between a position corresponding to the shared electrode line and the first substrate, and the third thickness is greater than the first thickness.

Description

[0001] This application is a divisional application of the invention patent divisional application with application date of May 8, 2018 and application number 201810431878.9 (the name of the invention is "display device"), that is, a divisional application of the invention patent with application number 202210377049.3 (the name of the invention is "electronic device") (based on the first examination opinion notice). Technical Field

[0002] The present invention relates to a display device, in particular to a display device that overcomes the problem of panel light leakage. Background Art

[0003] Flat panel display devices have the characteristics of light weight and thinness, and have gradually become the mainstream products in the display device market. For example, they are used in home TVs, personal computer monitors, and portable electronic products such as mobile phones, digital cameras, and tablet computers. Some flat panel display devices have spacers between substrates to maintain the gap size between the substrates. However, during the press test or panel handling, the panel may be pressed by external force, which may cause the spacers to move, causing damage to the film layer on the surface of the substrate, thereby causing light leakage problems. Summary of the invention

[0004] One embodiment of the present invention discloses an electronic device, which includes a first substrate, a scan line and a shared electrode line arranged on the first substrate, a first insulating layer, a conductive layer and a second insulating layer. The shared electrode line is arranged adjacent to the scan line. The first insulating layer is arranged on the scan line and the shared electrode line, the conductive layer is arranged on the first insulating layer, and the conductive layer partially overlaps the shared electrode line. The second insulating layer is arranged on the conductive layer. A top surface of the second insulating layer has a first thickness between the corresponding scan line and the first substrate, and the top surface of the second insulating layer has a third thickness between the corresponding shared electrode line and the first substrate, wherein the third thickness is greater than the first thickness. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 FIG. 1 is a partial top view of a first embodiment of a display device according to the present invention.

[0006] Figure 2 for Figure 1 The schematic cross-sectional view of the display device is shown along the tangent line AA'.

[0007] Figure 3 FIG. 1 is a partial top view of a second embodiment of a display device of the present invention.

[0008] Figure 4 for Figure 3 The display device is shown in a schematic cross-sectional view along the tangent line BB'.

[0009] Figure 5 FIG. 1 is a partial top view of a third embodiment of a display device of the present invention.

[0010] Figure 6 for Figure 5 The shown schematic cross-sectional view of the display device along the cut line CC'.

[0011] Figure 7 FIG. 4 is a partial top view of a fourth embodiment of a display device according to the present invention.

[0012] Description of reference numerals: 100-display device; 102-first substrate; 104-second substrate; 106-first conductive layer; 1061-first portion; 1062-second portion; 108-first insulating layer; 110-second conductive layer; 112-second insulating layer; 114-light shielding layer; 116-color filter layer; 118-protective layer; 120-second alignment layer; 122-first alignment layer; 130-pixel area; BP1, BP2-bumps; CL-second conductor; CP-conductive pad; D1-first direction; d1-first distance; D2-second direction; d2-second distance; DE-drain; DL-third conductor; DM1-first dummy pad; DM2-second dummy pad; GE-gate; H-spacer height; 0.9H-90% of the spacer height; LC-display medium layer; PS-spacer; R1-first region; R2-second region; R3-third region; R4-fourth region; R5-fifth region; SE-source; SL-first conductor; T1-second thickness; T2-third thickness; Tc-first thickness; Td1-fourth thickness; Td2-fifth thickness; TFT-transistor; TR1, TR2-grooves; W1-spacer width; W2-first width; W3-bottom width. DETAILED DESCRIPTION

[0013] In order to enable those skilled in the art to further understand the present invention, the embodiments of the present invention are listed below, and the components and the effects to be achieved of the present invention are described in detail with the accompanying drawings. It should be noted that the drawings are simplified schematic diagrams, and therefore, only the components and combination relationships related to the present invention are shown to provide a clearer description of the basic architecture or implementation method of the present invention, while the actual components and layout may be more complex. In addition, for the convenience of explanation, the components shown in the various drawings of the present invention are not drawn in proportion to the actual number, shape, and size, and the detailed proportions can be adjusted according to the design requirements.

[0014] In addition, when the terms "including" and / or "having" are used in this specification, they specify the presence of the features, regions, steps, operations and / or components, but do not exclude the presence or addition of one or more other features, regions, steps, operations, components and / or combinations thereof. When a component (or a variation thereof, such as a layer or region) is referred to as "on another component (or a variation thereof)" or "extending onto another component", it can be directly on another component or directly extended onto another component, or there can also be an intervening component between the two. On the other hand, when a component is referred to as "directly on another component (or a variation thereof)" or "directly extending onto another component", there is no intervening component between the two. Furthermore, when a component is referred to as "coupled" to another component (or a variation thereof), it can be directly connected to another component or indirectly connected (e.g., electrically connected) to another component through one or more components.

[0015] It should be noted that the features of the embodiments listed below can be replaced, reorganized, or mixed to complete other embodiments without departing from the spirit of the present invention.

[0016] Please refer to Figure 1 and Figure 2 , Figure 1 is a partial top view of a first embodiment of a display device of the present invention, Figure 2 for Figure 1The cross-sectional schematic diagram of the display device shown along the tangent line A-A'. The present embodiment provides a display device 100, and the display device 100 may include various types of flat display panels, curved display panels or flexible display panels. The present embodiment takes the display device 100 as an example including a liquid crystal material, but is not limited thereto. In other embodiments, the display device 100 may include a light emitting diode (LED), a mini LED, a microLED, a quantum dot (QD), fluorescence, phosphor, or other suitable materials, but is not limited thereto. In one embodiment, the chip size of the light emitting diode is approximately 300 microns (μm) to 10 millimeters (mm), the chip size of the mini LED is approximately 100 microns (μm) to 300 microns (μm), and the chip size of the micro LED is approximately 1 micron (μm) to 100 microns (μm), but is not limited thereto. The display device 100 includes a first substrate 102 and a second substrate 104, and the first substrate 102 and the second substrate 104 are arranged opposite to each other. The materials of the first substrate 102 and the second substrate 104 are, for example, hard substrates such as glass substrates, quartz substrates or sapphire substrates, or plastic substrates such as flexible substrates including polyimide materials (PI), polycarbonate (PC) or polyethylene terephthalate (PET), but are not limited thereto. A display medium layer LC is provided between the first substrate 102 and the second substrate 104. When the display device 100 includes a liquid crystal display panel, the display medium layer LC is, for example, a liquid crystal layer, which includes liquid crystal molecules.

[0017] The display device 100 further includes a first conductive layer 106, a first insulating layer 108, a second conductive layer 110, and a spacer PS. The first conductive layer 106 is disposed on the surface of the first substrate 102 and between the first substrate 102 and the second substrate 104, and includes a first conductive line SL and a first dummy pad DM1. The first conductive line SL extends along a first direction D1. In this embodiment, the first conductive line SL can be used as a scan line of the display device 100 to receive a scan signal, and the first conductive line SL can be electrically connected to a gate GE of a transistor TFT, and the gate GE of the transistor TFT can be formed by the first conductive layer 106, but not limited thereto. The first dummy pad DM1 is disposed adjacent to the first conductive line SL, and the first dummy pad DM1 can be floating or grounded. The first conductive layer 106 of this embodiment can also include a second conductive line CL, which is disposed adjacent to the first conductive line SL and can extend along the first direction D1, and the second conductive line CL is used as a shared electrode line of the display device 100, for example, to receive a shared signal, but not limited thereto. The material of the first conductive layer 106 is, for example, but not limited to, magnesium (Mg), calcium (Ca), aluminum (Al), silver (Ag), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr) or alloys of the above materials. The first insulating layer 108 may cover the first conductive layer 106 and be located between the first conductive layer 106 and the second substrate 104. The first insulating layer 108 may be, for example, a gate dielectric layer of a transistor TFT. The material of the first insulating layer 108 may include, for example, an inorganic insulating material, such as, but not limited to, silicon oxide or silicon nitride. The second conductive layer 110 may be disposed on the first insulating layer 108 and be located between the first insulating layer 108 and the second substrate 104. The second conductive layer 110 includes a conductive pad CP, wherein the conductive pad CP overlaps with the first dummy pad DM1. In one embodiment, the conductive pad CP and the first dummy pad DM1 may partially overlap, but are not limited thereto. It should be noted that the "overlap" here refers to the overlapping parts of the two in the direction along the normal line of the surface of the first substrate 102, or the overlapping parts of the projection patterns of the two on the surface of the first substrate 102. The "partial overlap" or "overlap" mentioned in other places in this article all have similar meanings and are not repeated here. In this embodiment, the conductive pad CP can be electrically connected to the drain DE of the transistor TFT. For example, the conductive pad CP can be used as a drain extension portion extending along the first direction, and the drain DE can be composed of the second conductive layer 110. The length of the conductive pad CP in the first direction D1 of this embodiment can be greater than the length of the first dummy pad DM1 in the first direction D1, but is not limited to this. The second conductive layer 110 of this embodiment also includes a second dummy pad DM2, which is arranged on the second conductive line CL and overlaps or partially overlaps the second conductive line CL, wherein the second dummy pad DM2 can be floating or grounded.The length of the second dummy pad DM2 in the first direction D1 may be less than the length of the second conductive line CL, but is not limited thereto. The second conductive layer 110 may also include a third conductive line DL extending along a second direction D2, wherein the second direction D2 is different from the first direction D1. In this embodiment, the second direction D2 is perpendicular to the first direction D1 as an example. The third conductive line DL may be used as a data line, for example, to receive a data signal. The third conductive line DL may be electrically connected to the source electrode SE of the transistor TFT. In this embodiment, the source electrode SE of the transistor TFT may be formed by the second conductive layer 110. The material of the second conductive layer 110 may be the same as or different from the material of the first conductive layer 106. For example, the material may refer to the introduction of the first conductive layer 106, which will not be repeated. The spacer PS may be arranged between the first substrate 102 and the second substrate 104. The spacer PS in this embodiment is arranged on the surface of the second substrate 104 facing the first substrate 102, forming as follows. Figure 2 In the inverted cone shown, in one embodiment, the top of the spacer PS away from the second substrate 104 may be in an arc shape and may have a highest point, but it is not limited thereto. The spacer PS may have a spacer height H, which refers to the distance from the bottom of the spacer PS (a surface facing the second substrate 104) to the spacer PS farthest from the second substrate 104. In one embodiment, if the spacer PS directly contacts the surface of the second substrate 104, the spacer height H may be the distance from the surface of the second substrate 104 to the spacer PS farthest from the second substrate 104. The spacer height H may be measured along the normal direction of the second substrate 104. The spacer PS may be used to maintain a more stable and uniform thickness between the first substrate 102 and the second substrate 104. According to this embodiment, the display device 100 may include a plurality of spacers PS. The spacer PS may include an inorganic material or an organic material, such as a photosensitive organic photoresist material, but it is not limited thereto.

[0018] The display device 100 may further include a second insulating layer 112 disposed between the spacer PS and the first insulating layer 108 or disposed on the second conductive layer 110. The second insulating layer 112 may include an inorganic or organic insulating material. Figure 2 As shown, the area having the first conductive line SL on the surface of the first substrate 102 may be defined as a first region R1. A first thickness Tc may be present between the top surface of the second insulating layer 112 in the first region R1 (the surface of the second insulating layer 112 away from the first substrate 102) and the surface of the first substrate 102, and the first thickness Tc may be measured along the normal direction of the first substrate 102. In other words, the first thickness Tc is the distance between a top surface of the second insulating layer 112 and the first substrate 102 at a location corresponding to the first conductive line SL. Figure 2The first substrate 102 in the left area may have a bump BP1 formed by a first dummy pad DM1, a first insulating layer 108, a conductive pad CP and a second insulating layer 112 arranged in sequence. The area on the surface of the first substrate 102 having the first dummy pad DM1 may be defined as a second region R2, and the bump BP1 may be arranged corresponding to the second region R2. There may be a second thickness T1 between the top surface of the second insulating layer 112 in the second region R2 (the surface of the second insulating layer 112 away from the first substrate 102) and the surface of the first substrate 102, and the second thickness T1 may be measured along the normal direction of the first substrate 102. In other words, the distance between the top surface of the second insulating layer 112 and the first substrate 102 at the location corresponding to the first dummy pad DM1 is defined as the second thickness T1. Similarly, Figure 2 The first substrate 102 in the right region may have a bump BP2 formed by the second conductive line CL, the first insulating layer 108, the second dummy pad DM2 and the second insulating layer 112 arranged in sequence. The region on the surface of the first substrate 102 having the second conductive line CL may be defined as a third region R3, and the bump BP2 may be arranged corresponding to the third region R3. A third thickness T2 may be provided between the top surface of the second insulating layer 112 in the third region R3 (the surface of the second insulating layer 112 away from the first substrate 102) and the surface of the first substrate 102, and the third thickness T2 may be measured along the normal direction of the first substrate 102. In other words, the distance between the top surface of the second insulating layer 112 and the first substrate 102 at the position corresponding to the second conductive line CL is defined as the third thickness T2. According to the present embodiment, the second thickness T1 may be greater than the first thickness Tc, and the third thickness T2 may be greater than the first thickness Tc.

[0019] In one embodiment, a fourth region R4 may be defined between the first conductive line SL and the first dummy pad DM1, and a fourth thickness Td1 may be provided between the top surface of the second insulating layer 112 in the fourth region R4 (the surface of the second insulating layer 112 away from the first substrate 102) and the surface of the first substrate 102, that is, a fourth thickness Td1 may be provided between the top surface of the second insulating layer 112 and the first substrate 102 at the corresponding groove TR1. The first thickness Tc in this embodiment may be greater than the fourth thickness Td1, or the second thickness T1 may be greater than the fourth thickness Td1. Similarly, a fifth region R5 may be defined between the first conductive line SL and the second conductive line CL, and a fifth thickness Td2 may be provided between the top surface of the second insulating layer 112 in the fifth region R5 (the surface of the second insulating layer 112 away from the first substrate 102) and the surface of the first substrate 102, that is, a fifth thickness Td2 may be provided between the top surface of the second insulating layer 112 and the first substrate 102 at the corresponding groove TR2. In this embodiment, the first thickness Tc may be greater than the fifth thickness Td2, or the third thickness T2 may be greater than the fifth thickness Td2. Under this design, the bump BP1 and the bump BP2 may serve as stops for the spacer PS. If the display device 100 is subjected to external pressure, such as pressing, which causes the spacer PS to move toward the two sides of the first conductive line SL, even if the spacer PS moves toward the first dummy pad DM1, the probability of moving toward the outer side will be reduced due to the larger thickness of the bump BP1; similarly, if the spacer PS moves toward the second conductive line CL, the probability of moving toward the outer side will be reduced due to the larger thickness of the bump BP2. In addition, it can be seen from the above that since the fourth thickness Td1 is smaller than the second thickness T1 and the first thickness Tc on both sides thereof, a concave groove TR1 may be formed on the surface of the second insulating layer 112 in the fourth region R4, that is, a groove TR1 may be formed between the first conductive line SL and the first dummy pad DM1. Similarly, since the fifth thickness Td2 is smaller than the third thickness T2 and the first thickness Tc on both sides thereof, a concave trench TR2 may be formed on the surface of the second insulating layer 112 in the fifth region R5, that is, a trench TR2 may be formed between the first conductive line SL and the second conductive line CL. Figure 2As shown, the spacer PS is, for example, in an inverted trapezoid, and the surface of the spacer PS facing the first substrate 102 may have a spacer width W1 in the second direction D2, wherein the second direction D2 may be perpendicular to the extension direction of the first conductive line SL. The spacer width W1 in this embodiment may be smaller than a first distance d1 between the first dummy pad DM1 and the first conductive line SL, and the first distance d1 may be the minimum distance between the first dummy pad DM1 and the first conductive line SL. Similarly, the spacer width W1 in this embodiment may be smaller than a second distance d2 between the second conductive line CL and the first conductive line SL, and the second distance d2 may be the minimum distance between the second conductive line CL and the first conductive line SL. The first distance d1 and the second distance d2 may be measured along the second direction D2. Therefore, even if the spacer PS moves left and right due to external force, the spacer PS may be located in one of the grooves on both sides, and it is difficult to move further outward, which can reduce the light leakage problem. In another embodiment of the present invention, the first distance d1 is not limited to be greater than the spacer width W1. However, a first width W2 may be provided in the second direction D2 at a height of 90% of the spacer height H (0.9H in the figure), and the ratio of the first distance d1 to the first width W2 may be between greater than or equal to 0.2 and less than or equal to 2. In addition, the bottom of the spacer PS (the surface facing the second substrate 104) may have a bottom width W3 in the second direction D2. This embodiment takes the bottom width W3 as greater than the first width W2 and the spacer width W1 as an example, but is not limited thereto. On the other hand, in a variant embodiment, the second distance d2 is not limited to be greater than the spacer width W1, but the ratio of the second distance d2 to the first width W2 may be between greater than or equal to 0.2 and less than or equal to 2. Alternatively, in this embodiment, the ratio of the first distance d1 to the first width W2 may be designed to be between greater than or equal to 0.8 and less than or equal to 1.2, or the ratio of the second distance d2 to the first width W2 may be designed to be between greater than or equal to 0.8 and less than or equal to 1.2. The above design allows at least a portion of the spacer PS to be located in the trench TR1 of the fourth region R4 or in the trench TR2 of the fifth region R5 when the spacer PS moves toward the two sides of the first conductive line SL, and is less likely to move to the outside, thereby reducing light leakage.

[0020] The display device 100 of this embodiment further includes a light shielding layer 114 on the surface of the second substrate 104, which may be, for example, a black matrix layer or other light-shielding materials, but is not limited thereto. The light shielding layer 114 may be disposed in an area outside the pixel area 130 (or opening area) in the display device 100 to reduce the light in the pixel area 130 from being shielded by the light shielding layer 114. In one embodiment, the pixel area 130 may be an area where a pixel (or sub-pixel) emits light, or the pixel area 130 may be an area defined by the light shielding layer 114. In this embodiment, the light shielding layer 114 may be disposed corresponding to the first wire SL, the first dummy pad DM1, the second dummy pad DM2 and / or the transistor TFT, that is, the light shielding layer 114 may cover the bump BP1, the bump BP2, the first area R1, the second area R2, the third area R3, the fourth area R4 and / or the fifth area R5, but is not limited thereto. The display device 100 may further include a color filter layer 116 and a protective layer 118 disposed sequentially on the surface of the light shielding layer 114. When the display device 100 is a liquid crystal display device, the display device 100 may further include a first alignment layer 122 and a second alignment layer 120, which are respectively arranged corresponding to the first substrate 102 and the second substrate 104. For example, the first alignment layer 122 may cover the surface of the second insulating layer 112, and the second alignment layer 120 may cover the surface of the protective layer 118 and the spacer PS. In the present embodiment, the first alignment layer 122 is arranged between the spacer PS and the second insulating layer 112, and the second alignment layer 120 is arranged between the spacer PS and the first alignment layer 122, but the present invention is not limited thereto. The first alignment layer 122 and the second alignment layer 120 may provide a function of aligning the liquid crystal molecules. In the present embodiment, the design of the groove TR1, the groove TR2, the bump BP1 and / or the bump BP2 may make it less likely for the spacer PS to move outward to the outside of the bump BP1 and / or the bump BP2 and scratch the film layer (for example, the first alignment layer 122) on both sides of the first conductive line SL, so that the liquid crystal molecules may be effectively aligned and arranged, thereby reducing the occurrence of light leakage problems.

[0021] Please refer to Figures 3 to 7In another variant embodiment of the present invention, the bump BP1 or the bump BP2 may be provided only in the vicinity of one of the two sides of the first conductive line SL, that is, the bump BP1 or the bump BP2 does not need to be provided at the same time, that is, the first dummy pad DM1 and the second dummy pad DM2 do not necessarily need to exist at the same time, and the direction in which the spacer PS is more likely to be displaced when pressed by an external force can be determined according to the positions of the first conductive line SL and the spacer PS on the display device 100, so as to determine whether to provide the bump BP1 or the bump BP2 to block the displacement of the spacer PS. In addition, the aforementioned embodiment takes the overlap of the spacer PS and the first conductive line SL as an example, however, in some embodiments, the overlapped portion of the spacer PS and the first conductive layer 106 may not have a conductive line function. Therefore, the present embodiment may also be regarded as the spacer PS at least partially overlapping a first portion 1061 of the first conductive layer 106, and the first conductive layer 106 may also include a second portion 1062, which is provided adjacent to the first portion 1061, and the bump BP1 or the bump BP2 is formed at the position of the second portion 1062. In other words, the display device 100 of this embodiment can be explained as comprising a first substrate 102, a second substrate 104, a first conductive layer 106, a first insulating layer 108, a second conductive layer 110, and a spacer PS. The first conductive layer 106 comprises a first portion 1061 (e.g., a first conductive line SL) and a second portion 1062 (e.g., a first dummy pad DM1 or a second conductive line CL, and the first dummy pad DM1 is taken as an example here), the first portion 1061 and the second portion 1062 are disposed adjacent to each other, and there may be a distance between the first portion 1061 and the second portion 1062, such as a first distance d1 (or a second distance d2). The first insulating layer 108 is disposed on the first conductive layer 106, and the second conductive layer 110 is disposed on the first insulating layer 108 and overlaps the second portion 1062. The spacer PS is disposed between the first substrate 102 and the second substrate 104 and overlaps the first portion 1061. The spacer PS has a first width W2 at a height of 0.9H which is 90% of the spacer height, wherein the ratio of the first distance d1 (or the second distance d2) to the first width W2 may range between greater than or equal to 0.2 and less than or equal to 2. In addition, as described above, in the present embodiment, when the first portion 1061 is used as a part of the scan line, the first portion 1061 may receive a scan signal, when the second portion 1062 is used as the first dummy pad DM1, it may be floating or grounded, and when the second portion 1062 is used as the second conductive line CL, it may receive a shared signal. The second dummy pad DM2 of the second conductive layer 110 may overlap with the second portion 1062, wherein the second dummy pad DM2 may be floating or grounded.The top surface of the second insulating layer 112 has a first thickness Tc between the first portion 1061 and the first substrate 102, and the top surface of the second insulating layer 112 has a second thickness T1 (or a third thickness T2) between the second portion 1062 and the first substrate 102, wherein the second thickness T1 (or the third thickness T2) is greater than the first thickness Tc. In addition, a trench TR1 (or a trench TR2) may be formed between the first portion 1061 and the second portion 1062, and the top surface of the second insulating layer 112 has a fourth thickness Td1 (or a fifth thickness Td2) between the first substrate 102 and the corresponding trench TR1 (or trench TR2), wherein the fourth thickness Td1 (or the fifth thickness Td2) is less than the first thickness Tc.

[0022] Please refer to Figure 3 and Figure 4 , Figure 3 is a partial top view of a second embodiment of a display device of the present invention, Figure 4 for Figure 3 The cross-sectional view of the display device shown is taken along the tangent line BB'. The difference between this embodiment and the first embodiment is that the third region R3 may not have the second dummy pad DM2, so the third thickness T2 of the bump BP2 is slightly smaller than the second thickness T1 of the bump BP1. According to this embodiment, when the setting condition (e.g., setting position) of the spacer PS makes it easier for the spacer PS to move toward one side of the first conductive line SL (e.g., Figure 4 When the first conductor SL is offset to the left side, it is not necessary to Figure 4 The second dummy pad DM2 is additionally provided on the second conductive line CL (on the right side in FIG. 1 ), and the thickness of the bump on the offset side of the spacer PS is increased, for example, Figure 4 The second thickness T1 of the middle bump BP1 is greater than the first thickness Tc, so that the bump BP1 can form a barrier to reduce the probability of the spacer PS further shifting beyond the bump BP1. In this embodiment, the third thickness T2 may be approximately the same as the first thickness Tc, but is not limited thereto.

[0023] Please refer to Figure 5 and Figure 6 , Figure 5 is a partial top view of a third embodiment of a display device of the present invention, Figure 6 for Figure 5 The cross-sectional view of the display device shown is taken along the cut line CC'. The difference between this embodiment and the first embodiment is that the second region R2 may not have the first dummy pad DM1, so the second thickness T1 of the bump BP1 is slightly smaller than the third thickness T2 of the bump BP2. According to this embodiment, when the setting condition (e.g., setting position) of the spacer PS makes it easier for the spacer PS to move toward one side of the first conductive line SL (e.g., Figure 6When the first conductor SL is offset to the right side, it is not necessary to Figure 6 The first dummy pad DM1 is additionally provided under the conductive pad CP on the left side of the figure. It is only necessary to increase the bump thickness on the offset side of the spacer PS. For example, Figure 6 The third thickness T2 of the middle bump BP2 is greater than the first thickness Tc, so that the bump BP2 can form a barrier to reduce the probability of the spacer PS further shifting beyond the bump BP2. In this embodiment, the second thickness T1 may be approximately the same as the first thickness Tc, but is not limited thereto.

[0024] Please refer to Figure 7 , Figure 7 1 is a partial top view of a fourth embodiment of the display device of the present invention. The main difference between this embodiment and the previous embodiment is that the conductive pad CP is not connected to the drain DE, that is, the conductive pad CP can be floating. In addition, the shape of the dummy pad is not limited to a rectangle or a strip, and can be various suitable shapes, and the shapes of the dummy pads do not need to be exactly the same. For example, the first dummy pad DM1 of this embodiment is "U"-shaped, and the second dummy pad DM2 is arc-shaped, but it is not limited to this.

[0025] As can be seen from the above, since the present invention simultaneously sets a conductive pad and a first dummy pad, and / or a second conductive wire and a second dummy pad with the first conductive layer and the second conductive layer near the spacer, a bump can be formed on one side or both sides of the spacer, and / or a groove of a specific size can be formed between the spacer and the bump, thereby blocking the displacement amplitude of the spacer, overcoming the problem of the spacer scratching the surface film layer of the substrate due to displacement, or overcoming the light leakage problem caused by scratching the film layer. Under this design, the overall pressure resistance of the display device can be increased, or the display effect of the product can be improved.

[0026] The above description is only an embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An electronic device, characterized in that: include: a first substrate; A scan line and a common electrode line are arranged on the first substrate, and the common electrode line is arranged adjacent to the scan line; a first insulating layer, disposed on the scan line and the common electrode line; a conductive layer disposed on the first insulating layer, wherein the conductive layer partially overlaps the common electrode line; and a second insulating layer disposed on the conductive layer; A top surface of the second insulating layer has a first thickness between the scanning line and the first substrate, and a top surface of the second insulating layer has a third thickness between the shared electrode line and the first substrate, wherein the third thickness is greater than the first thickness.

2. The electronic device according to claim 1, wherein: The part where the conductive layer overlaps with the common electrode line is a dummy pad, and the dummy pad is floating or grounded.

3. The electronic device according to claim 1, wherein: The overlapping part of the conductive layer and the common electrode line is a dummy pad, and the dummy pad has an arc shape.

4. The electronic device according to claim 1, wherein: It also includes another dummy pad disposed adjacent to the scan line, and the conductive layer also includes a conductive pad partially overlapping the other dummy pad, wherein the scan line is located between the other dummy pad and the shared electrode line.

5. The electronic device according to claim 4, characterized in that: The other dummy pad is floating or grounded, and the conductive pad is floating.

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