Memory array, storage and calculation integrated circuit, control method of storage and calculation integrated circuit, chip and electronic equipment

Abstract

The invention provides a memory array, a storage and calculation integrated circuit, a control method of the storage and calculation integrated circuit, a chip and electronic equipment. Relates to the technical field of memory design. The memory array comprises a plurality of memory units arranged in an array; the first end of each storage unit is connected with a first word line and a first double-bit line, and the second end of each storage unit is connected with a second word line and a second double-bit line; the first double-bit line is provided with a first switch module, and the first switch module is used for controlling the number of bit lines connected to the storage unit in the first double-bit line; the second double-bit line is provided with a second switch module, and the second switch module is used for controlling the number of bit lines connected to the storage unit in the second double-bit line. According to the embodiment of the invention, the problem that the existing SRAM device cannot realize the balance between the unit array area and the logic function can be solved in a targeted manner.

Description

Technical Field

[0001] The present application relates to the field of memory design technology, and in particular to a memory array, a storage-computing integrated circuit and a control method thereof, a chip and an electronic device. Background Art

[0002] SRAM (Static Random-Access Memory) is a high-speed semiconductor memory used to store data. The 6T SRAM-CIM (Computing-in-Memory) device is an integrated circuit that combines traditional 6TSRAM storage cells with computing power. It has the advantages of small size, high speed, and easy refresh.

[0003] However, the bit line voltage swing of 6T SRAM-CIM devices is limited by read disturbance and small signal tolerance, which may affect the accuracy of data, and the logical operations that can be achieved by 6T-SRAM are limited. In order to solve the problems of 6T SRAM-CIM devices, the related art has developed non-6T SRAM cell structures, such as 8T or 9T SRAM. Non-6T SRAM structures reduce read disturbance by adding additional transistors and provide greater noise tolerance. Although these improvements help improve performance and reliability, they also lead to an increase in cell and array area.

[0004] That is, existing SRAM devices cannot achieve a balance between cell array area and logic functions.

[0005] It should be noted that the above statements are only used to provide background technical information related to the present application and do not necessarily constitute prior art. Summary of the invention

[0006] In view of this, the purpose of this application is to propose a memory array, a storage-computing integrated circuit and its control method, a chip and an electronic device. This application can specifically solve the problem that existing SRAM devices cannot achieve a balance between unit array area and logical function.

[0007] Based on the above purpose, in a first aspect, the present application proposes a memory array, which includes a plurality of memory cells arranged in an array; a first end of each memory cell is connected to a first word line and a first double bit line, and a second end of each memory cell is connected to a second word line and a second double bit line; the first double bit line is provided with a first switch module, and the first switch module is used to control the number of bit lines in the first double bit line connected to the memory cell; the second double bit line is provided with a second switch module, and the second switch module is used to control the number of bit lines in the second double bit line connected to the memory cell.

[0008] In some embodiments, the first double bit line includes a main bit line and a first auxiliary bit line, the main bit line, the first switch module and the first auxiliary bit line are connected in series, when the first switch module is disconnected, the main bit line is connected to the memory cell, when the first switch module is closed, the main bit line and the first auxiliary bit line are both connected to the memory cell.

[0009] In some embodiments, the second double bit line includes a complementary bit line and a second auxiliary bit line, the complementary bit line, the second switch module and the second auxiliary bit line are connected in series, when the second switch module is disconnected, the complementary bit line is connected to the storage unit, when the second switch module is closed, the complementary bit line and the second auxiliary bit line are both connected to the storage unit.

[0010] In some embodiments, the storage unit includes a 6T-SRAM storage unit, and the 6T-SRAM storage unit includes a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube and a sixth switch tube; the second end of the first switch tube and the second end of the second switch tube are both connected to a power supply, and the first end of the first switch tube, the third end of the second switch tube, the first end of the third switch tube and the second end of the fourth switch tube are all connected through a first node; the third end of the first switch tube, the first end of the second switch tube, the second end of the third switch tube and the first end of the fourth switch tube are all connected through a second node; the third end of the third switch tube and the third end of the fourth switch tube are grounded; wherein, the first end of the fifth switch tube is connected to the first word line, the second end of the fifth switch tube is connected to the first double bit line, and the third end of the fifth switch tube is connected to the second node; the first end of the sixth switch tube is connected to the second word line, the second end of the sixth switch tube is connected to the second double bit line, and the third end of the sixth switch tube is connected to the first node.

[0011] In the second aspect, a storage and computing integrated circuit is also provided, which includes a control circuit, a readout circuit and the memory array described in any one of the first aspect; the control circuit is connected to the first word line, the second word line, the first switch module and the second switch module of the memory array, the control circuit is used to input a control signal to the target memory cell through the first word line and the second word line, and the control circuit is used to control the opening or closing of the first switch module and the second switch module; the readout circuit is connected to each memory cell of the memory array, and is used to output data of the target memory cell.

[0012] In the third aspect, a control method for a storage-computation integrated circuit is also provided, and the method is applied to the storage-computation integrated circuit according to claim 5, and the method includes: controlling the first switch module and the second switch module of the storage array in the storage-computation integrated circuit to be in a closed state; inputting a control signal 1 to a target storage unit through any one of the first word line and the second word line, and writing target data through the first double bit line and the second double bit line, so that the target storage unit performs one of an OR operation and a NOR operation; and outputting the operation result of the target storage unit through the read circuit.

[0013] In some embodiments, the method also includes: controlling the first switch module and the second switch module of the memory array in the storage-computation integrated circuit to be in a disconnected state; inputting a control signal 1 to the target storage unit through the first word line and the second word line at the same time, and writing target data through the main bit line and the complement bit line, so that the target storage unit performs one of an AND operation and a NAND operation; and outputting the operation result of the target storage unit through the read circuit.

[0014] In a fourth aspect, a chip is also provided, wherein the chip includes the storage and computing integrated circuit provided in the second aspect.

[0015] In a fifth aspect, an electronic device is also provided, wherein the electronic device comprises the chip described in the fourth aspect.

[0016] In general, this application has at least the following beneficial effects:

[0017] The embodiment of the present application proposes a memory array, wherein the first end of each memory cell is connected to a first word line and a first double bit line, and the second end of each memory cell is connected to a second word line and a second double bit line; and the first double bit line is provided with a first switch module, and the second double bit line is provided with a second switch module, thereby changing the switching states of the first switch module and the second switch module, and thereby changing the number of bit lines connected to the memory cell in the first double bit line and the number of bit lines connected to the memory cell in the second double bit line, thereby changing the operation logic of the memory array, and without increasing the number of transistors in the memory cell, multiple logic operations can be realized, thereby achieving a balance between the area of ​​the memory cell array and the logic function.

[0018] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in the present application and should not be regarded as limiting the scope of the present application. In addition, the same reference numerals are used to represent the same parts in all the drawings.

[0020] Figure 1 A schematic diagram showing the structure of a memory array provided by an embodiment of the present application is shown;

[0021] Figure 2 A schematic diagram of the structure of a storage unit provided in an embodiment of the present application is shown;

[0022] Figure 3 A schematic diagram showing the structure of a storage-computation-in-one circuit provided in an embodiment of the present application is shown;

[0023] Figure 4 A schematic diagram showing the structure of a readout circuit according to an embodiment of the present application is shown;

[0024] Figure 5 A schematic diagram of the structure of a chip provided by an embodiment of the present application is shown;

[0025] Figure 6 A schematic structural diagram of an electronic device provided in one embodiment of the present application is shown. DETAILED DESCRIPTION

[0026] The following embodiments of the technical solution of the present application are described in detail in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application, and are therefore only used as examples, and cannot be used to limit the scope of protection of the present application.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" in the specification and claims of this application and the above-mentioned figure descriptions and any variations thereof are intended to cover non-exclusive inclusions.

[0028] In the description of the embodiments of the present application, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined.

[0029] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0030] In the description of the embodiments of the present application, the term "and / or" is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0031] In the description of the embodiments of the present application, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0032] In the description of the embodiments of the present application, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, which are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the embodiments of the present application.

[0033] In the description of the embodiments of the present application, unless otherwise clearly specified and limited, technical terms such as "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the internal connection of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0034] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0035] As the gap between processor and memory process improvement widens, the storage wall gap under the von Neumann architecture continues to increase, and the memory access power consumption wall problem becomes increasingly prominent. At the same time, with the rapid increase in computing volume, frequent data exchange brings challenges in speed and power consumption, becoming one of the key bottlenecks of computing efficiency. In order to solve the problems of storage wall and power consumption wall, the storage-computing integrated architecture is proposed. SRAM (Static Random-Access Memory) is the closest memory to the CPU. The storage-computing integrated technology based on SRAM has the advantages of fast read and write speed, low power consumption, strong reliability, and high scalability. It has gradually become the mainstream intelligent computing architecture of the new generation. The 6T SRAM-CIM (Computing-in-Memory) device is an integrated circuit that combines traditional 6T SRAM storage cells with computing power. It has the advantages of small size, high speed, and easy refresh. However, the bit line voltage swing of the 6T SRAM-CIM device is limited by read interference and small signal tolerance, which may affect the accuracy of the data, and the logical operations that can be realized by 6T-SRAM are limited. In order to solve the problem of 6T SRAM-CIM devices, the related art has developed non-6T SRAM cell structures, such as 8T or 9T SRAM. The non-6T SRAM structure reduces read interference by adding additional transistors and provides greater noise margin. Although these improvements help improve performance and reliability, they also lead to an increase in cell and array area. In other words, existing SRAM devices cannot achieve a balance between cell array area and logic function.

[0036] Therefore, in order to solve the above problems, the present embodiment proposes a memory array, a storage-computation integrated circuit and a control method thereof, a chip and an electronic device, wherein the first end of each memory cell is connected to a first word line and a first double bit line, and the second end of each memory cell is connected to a second word line and a second double bit line; and the first double bit line is provided with a first switch module, and the second double bit line is provided with a second switch module, and then by changing the switching state of the first switch module and the second switch module, the number of bit lines connected to the memory cell in the first double bit line and the number of bit lines connected to the memory cell in the second double bit line can be changed, thereby changing the operation logic of the memory array, and multiple logic operations can be realized without increasing the number of transistors in the memory cell, thereby achieving a balance between the area of ​​the memory cell array and the logic function.

[0037] Figure 1 A schematic diagram of the structure of a memory array provided by an embodiment of the present application is shown as follows: Figure 1As shown, a memory array 10 provided in this embodiment includes: a plurality of memory cells 101 arranged in an array, a first end of each memory cell 101 is connected to a first word line WLL and a first double bit line, and a second end of each memory cell 101 is connected to a second word line WLR and a second double bit line; a first switch module 102 is provided for the first double bit line, and the first switch module 102 is used to control the number of bit lines connected to the memory cell 101 in the first double bit line; a second switch module 103 is provided for the second double bit line, and the second switch module 103 is used to control the number of bit lines connected to the memory cell 101 in the second double bit line.

[0038] The first word line WLL and the second word line WLR are used to transmit a control signal input by a user, so as to open the first word line WLL or the second word line WLR under the control of the control signal, and then store data in the target memory cell 101 .

[0039] In the present embodiment, the first double bit line is provided with a first switch module 102, and the first switch module 102 is used to control the number of bit lines in the first double bit line connected to the memory cell 101. For example, when the first switch module 102 is closed, both bit lines in the first double bit line are connected to the memory cell 101, the parasitic resistance on the bit line is small, and the data on the bit line can be easily written into the memory cell 101. Therefore, as long as one of the first word line WLL and the second word line WLR is opened, the data on the bit line can be written.

[0040] Similarly, the second double bit line is provided with a second switch module 103, and the second switch module 103 is used to control the number of bit lines in the second double bit line connected to the memory cell 101. When the second switch module 103 is closed, both bit lines in the second double bit line are connected to the memory cell 101, the parasitic resistance on the bit line is small, and the data on the bit line can be written into the memory cell 101 more easily. Therefore, as long as one of the first word line WLL and the second word line WLR is opened, the data on the bit line can be written.

[0041] When the first switch module 102 is disconnected, only one bit line of the first dual bit line is connected to the memory cell 101, the parasitic resistance on the bit line is large, and the data on the bit line is difficult to write into the SRAM cell. Therefore, the first word line WLL and the second word line WLR need to be turned on at the same time so that the data on the bit line can be written. Similarly, when the second switch module 103 is disconnected, only one bit line of the second dual bit line is connected to the memory cell 101, the parasitic resistance on the bit line is large, and the data on the bit line is difficult to write into the SRAM cell. Therefore, the first word line WLL and the second word line WLR need to be turned on at the same time so that the data on the bit line can be written.

[0042] Based on the structure and principle of the memory array 10 , the operation logic of the memory cell 101 can be changed by changing the switch states of the first switch module 102 and the second switch module 103 .

[0043] Figure 2 A schematic diagram of the structure of a storage unit 101 provided in an embodiment of the present application is shown. Figure 2 As shown, specifically, the first dual bit line includes a main bit line BL and a first auxiliary bit line AUX-BL, the main bit line BL, the first switch module 102 and the first auxiliary bit line AUX-BL are connected in series, when the first switch module 102 is disconnected, the main bit line BL is connected to the memory cell 101, and the first auxiliary bit line AUX-BL is disconnected from the memory cell 101. When the first switch module 102 is closed, both the main bit line BL and the first auxiliary bit line AUX-BL are connected to the memory cell 101.

[0044] The second double bit line includes a complementary bit line BLB and a second auxiliary bit line AUX-BLB. The complementary bit line BLB, the second switch module 103 and the second auxiliary bit line AUX-BLB are connected in series. When the second switch module 103 is disconnected, the complementary bit line BLB is connected to the memory cell 101, and the second auxiliary bit line AUX-BLB is disconnected from the memory cell 101. When the second switch module 103 is closed, the complementary bit line BLB and the second auxiliary bit line AUX-BLB are both connected to the memory cell 101.

[0045] The main bit line BL and the complementary bit line BLB are used to transmit write data, so that the storage unit 101 performs a logic operation based on the write data, obtains the data after the operation and stores it. The first auxiliary bit line AUX-BL and the second auxiliary bit line AUX-BLB provide additional verification information to ensure that no error occurs during the storage and reading process of the data, and at the same time, they are connected in parallel or serially to improve the efficiency of data transmission.

[0046] like Figure 2 As shown, the memory cell 101 includes a 6T-SRAM memory cell 101, and the 6T-SRAM memory cell 101 includes a first switch tube M1, a second switch tube M2, a third switch tube M3, a fourth switch tube M4, a fifth switch tube M5, and a sixth switch tube M6. The memory cell 101 includes the 6T-SRAM memory cell 101, so that the memory array can increase the logic operation mode while maintaining the array area of ​​6T-SRAM.

[0047] The second end of the first switch tube M1 and the second end of the second switch tube M2 are both connected to the power supply V DDThe first end of the first switch tube M1, the third end of the second switch tube M2, the first end of the third switch tube M3 and the second end of the fourth switch tube M4 are all connected through a first node QB; the third end of the first switch tube M1, the first end of the second switch tube M2, the second end of the third switch tube M3 and the first end of the fourth switch tube M4 are all connected through a second node Q; the third end of the third switch tube M3 and the third end of the fourth switch tube M4 are grounded V SS .

[0048] Among them, the first end of the fifth switch tube M5 is connected to the first word line, the second end of the fifth switch tube M5 is connected to the first double bit line, and the third end of the fifth switch tube M5 is connected to the second node QB; the first end of the sixth switch tube M6 is connected to the second word line, the second end of the sixth switch tube M6 is connected to the second double bit line, and the third end of the sixth switch tube M6 is connected to the first node Q.

[0049] In one example, the first switch module 102 may include a switch module such as a transistor or a switch circuit or a switch control module that can realize the conduction or disconnection between the main bit line BL and the first auxiliary bit line AUX-BL. The second switch module 103 may also include a switch module such as a transistor or a switch circuit or a switch control module that can realize the conduction or disconnection between the complementary bit line BLB and the second auxiliary bit line AUX-BLB. No specific limitation is made here.

[0050] The main bit line BL and the complementary bit line BLB are also connected to a readout circuit, and the readout circuit is used to output the data calculated and stored in the storage unit 101.

[0051] The above embodiment provides a memory array 10, wherein the first end of each memory cell 101 is connected to a first word line and a first double bit line, and the second end of each memory cell 101 is connected to a second word line and a second double bit line; and the first double bit line is provided with a first switch module 102, and the second double bit line is provided with a second switch module 103, and then by changing the switch states of the first switch module 102 and the second switch module 103, the number of bit lines connected to the memory cell 101 in the first double bit line and the number of bit lines connected to the memory cell 101 in the second double bit line can be changed, thereby changing the operation logic of the memory array 10, and multiple logic operations can be realized without increasing the number of transistors in the memory cell 101, thereby achieving a balance between the array area and the logic function of the memory cell 101.

[0052] Moreover, the memory array 10 of this embodiment can directly write the calculation results into the storage unit 101 on the basis of realizing the data read and write operations, thereby saving the write cycle of writing data into the storage unit 101 and reducing the system delay. It can improve the operation rate, reduce the operation power consumption of the circuit and system, and alleviate the problems of the storage wall and the power consumption wall.

[0053] This embodiment provides a storage and computing integrated circuit. Figure 3 A schematic diagram of a storage-computation integrated circuit provided in an embodiment of the present application is shown. Figure 3 As shown, the storage-computation integrated circuit includes a control circuit 20, a readout circuit 30, and a memory array 10. The memory array 10 is the memory array 10 provided in the above embodiment. Figure 1 and Figure 2 A memory array 10 is shown.

[0054] Among them, the control circuit 20 is connected to the first word line, the second word line, the first switch module 102 and the second switch module 103 of the memory array 10, and the control circuit 20 is used to input a control signal to the target memory cell 101 through the first word line and the second word line, and the control circuit 20 is used to control the opening or closing of the first switch module 102 and the second switch module 103; the read-out circuit 30 is connected to each memory cell 101 of the memory array 10, and is used to output data of the target memory cell 101.

[0055] The target storage unit 101 may be determined according to a target instruction input according to actual needs, and the target instruction is used to indicate the location of the target storage unit 101 .

[0056] One end of the control circuit 20 can be connected to the signal input end, and the other end is connected to the memory array 10, and is used to input a control signal to the target memory cell 101 through the first word line and the second word line. The control signal is, for example, a voltage signal A and a voltage signal B for controlling the logic calculation of the target memory cell 101, wherein the voltage signal A can be transmitted through the first word line WLL, and the voltage signal B can be transmitted through the second word line WLR.

[0057] The control circuit 20 can also control the opening or closing of the first switch module 102 and the second switch module 103. For example, the control circuit 20 sends a switch closing control signal to the first switch module 102 and the second switch module 103, and the first switch module 102 and the second switch module 103 are in a closed state, or the control circuit 20 sends a switch opening control signal to the first switch module 102 and the second switch module 103, and the first switch module 102 and the second switch module 103 are in a disconnected state. The working mode of the storage unit 101 can be determined, and the working mode of the storage unit 101 includes an OR operation and an OR-NOR operation mode, that is, an OR / NOR mode, and an AND operation and an AND-NAND operation mode, that is, an AND / NAND mode.

[0058] In one example, the readout circuit 30 is as follows Figure 4As shown, the readout circuit 30 includes an amplifier 301 and an inverter INV. The amplifier 301 is used to amplify the voltage difference between BL and BLB, thereby accelerating the read operation and improving the accuracy of data reading. The inverter INV is used to output an out2 signal that is opposite to out1.

[0059] The working logic and process of the above-mentioned storage and computing integrated circuit are explained below:

[0060] 1. Initialization: close the first switch module 102 and the second switch module 103, set BL=0, BLB=1, open the word lines WLL and WLR, and initialize the data stored in the SRAM cell to 0.

[0061] 2. Write data, input control signals of the first switch module 102 and the second switch module 103, determine the operation logic of the target storage unit 101, preset BL to "1", preset BLB to "0", and prepare to write data "1" to the unit.

[0062] 3. Calculate and store, input WLL and WLR, perform calculations, and store the calculation results in the selected target unit.

[0063] 4. Data readout: The calculation result is outputted through the readout circuit 30. The readout circuit 30 can read out AND / NAND results at the same time, or read out OR / NOR results at the same time.

[0064] Specifically, when the first switch module 102 and the second switch module 103 are closed, the OR / NOR mode is entered. Since the first switch module 102 and the second switch module 103 are closed, data can be written if one of WLL and WLR is turned on, that is, after the data of the SRAM cell is initialized to 0, when WLL=1 or WLR=0, in the above calculation process example step 3, the stored data will be rewritten to 1. That is, the OR operation result of WLL and WLR is written into the selected SRAM cell. The OR / NOR result can be output simultaneously by the readout circuit 30.

[0065] The following results are obtained in Table 1:

[0066] Table 1:

[0067]

[0068] When the first switch module 102 and the second switch module 103 are disconnected, the AND / NAND mode is entered. Since the first switch module 102 and the second switch module 103 are disconnected, data can be written only when WLL and WLR are turned on at the same time, that is, after the data of the SRAM storage unit 101 is initialized to 0, only when WLL=1 and WLR=1, in the above operation example step 3, the storage data Q can be rewritten to 1. That is, the AND operation result of WLL and WLR is written to the selected SRAM unit. The AND / NAND result can be outputted simultaneously by the readout circuit 30. The results shown in Table 2 below can be obtained.

[0069] Table 2:

[0070]

[0071] As described above, the integrated storage and calculation circuit of this embodiment can realize the operation of multiple logical operations such as OR / NOR and AND / NAND without adding additional transistors, thereby achieving a balance between the array area and logical function of the storage unit 101.

[0072] Based on the above-mentioned storage-computation integrated circuit, this embodiment proposes a control method for the storage-computation integrated circuit, which is applied to the above-mentioned storage-computation integrated circuit. The method includes: controlling the first switch module 102 and the second switch module 103 of the storage array in the storage-computation integrated circuit to be in a closed state; inputting a control signal 1 to the target storage unit 101 through any one of the first word line and the second word line, and writing target data through the first double bit line and the second double bit line, so that the target storage unit 101 performs one of an OR operation and a NOR operation; and outputting the operation result of the target storage unit 101 through the read circuit 30.

[0073] Specifically, the first switch module 102 and the second switch module 103 are controlled to be closed, and the OR / NOR mode is entered. Since the first switch module 102 and the second switch module 103 are closed, data can be written if one of WLL and WLR is turned on, that is, after the data of the SRAM storage unit 101 is initialized to 0, when WLL=1 or WLR=0, in the above calculation process example step 3, the stored data will be rewritten to 1. That is, the OR operation result of WLL and WLR is written to the selected SRAM storage unit 101. The OR / NOR result can be outputted simultaneously by the readout circuit 30, and the result shown in the above Table 1 can be obtained.

[0074] The method also includes: controlling the first switch module 102 and the second switch module 103 of the memory array in the storage-computation integrated circuit to be in the disconnected state; inputting a control signal 1 to the target storage unit 101 through the first word line and the second word line at the same time, and writing the target data through the main bit line and the complement bit line, so that the target storage unit 101 performs one of an AND operation and a NAND operation; and outputting the operation result of the target storage unit 101 through the read circuit 30.

[0075] Specifically, the first switch module 102 and the second switch module 103 are controlled to be disconnected to enter the AND / NAND mode. Since the first switch module 102 and the second switch module 103 are disconnected, data can be written only when WLL and WLR are turned on at the same time, that is, after the data of the SRAM cell is initialized to 0, only when WLL=1 and WLR=1, in the above operation example step 3, the stored data Q can be rewritten to 1. That is, the AND operation result of WLL and WLR is written into the selected SRAM cell. The AND / NAND result can be outputted simultaneously by the readout circuit 30. The result shown in Table 2 above can be obtained.

[0076] The control method of the storage-computing integrated circuit provided in the above-mentioned embodiment of the present application is based on the same application concept as the memory array 10 provided in the embodiment of the present application, and has the same beneficial effects as the method adopted, run or implemented by the application program stored therein.

[0077] The above description of various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced to each other, and for the sake of brevity, they will not be repeated herein.

[0078] Figure 5 A schematic diagram of the structure of a chip provided in this embodiment is shown. Figure 5 As shown, a chip 50 includes the storage-computation integrated circuit 40 of the above embodiment, and the storage-computation integrated circuit 40 is as shown in FIG. Figure 3 shown.

[0079] The chip provided in the above-mentioned embodiment of the present application and the memory array 10 provided in the embodiment of the present application are based on the same application concept and have the same beneficial effects as the methods adopted, run or implemented by the application programs stored therein.

[0080] Figure 6 A schematic diagram of the structure of an electronic device provided by this embodiment is shown. Figure 6 As shown, an electronic device 60 includes Figure 5 Chip 50 is shown.

[0081] The electronic device provided by the above-mentioned embodiment of the present application and the memory array 10 provided by the embodiment of the present application are based on the same application concept and have the same beneficial effects as the methods adopted, run or implemented by the application programs stored therein.

[0082] It should be noted that:

[0083] In the above text, the term "comprises", "includes" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be noted that the scope of the method and device in the embodiment of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0084] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for a terminal (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0085] The embodiments of the present application are described above in conjunction with the accompanying drawings, which are only specific implementation modes of the present application. However, the present application is not limited to the above-mentioned specific implementation modes. The above-mentioned specific implementation modes are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A memory array, characterized in that: The memory array includes a plurality of memory cells arranged in an array; A first end of each memory cell is connected to a first word line and a first double bit line, and a second end of each memory cell is connected to a second word line and a second double bit line; The first double bit line is provided with a first switch module, and the first switch module is used to control the number of bit lines in the first double bit line connected to the storage unit; The second dual bit line is provided with a second switch module, and the second switch module is used to control the number of bit lines in the second dual bit line connected to the storage unit.

2. The memory array according to claim 1, wherein: The first double bit line includes a main bit line and a first auxiliary bit line. The main bit line, the first switch module and the first auxiliary bit line are connected in series. When the first switch module is disconnected, the main bit line is connected to the storage unit. When the first switch module is closed, the main bit line and the first auxiliary bit line are both connected to the storage unit.

3. The memory array according to claim 1, wherein: The second double bit line includes a complementary bit line and a second auxiliary bit line. The complementary bit line, the second switch module and the second auxiliary bit line are connected in series. When the second switch module is disconnected, the complementary bit line is connected to the storage unit. When the second switch module is closed, the complementary bit line and the second auxiliary bit line are both connected to the storage unit.

4. The memory array according to any one of claims 1 to 3, characterized in that: The storage unit includes a 6T-SRAM storage unit, and the 6T-SRAM storage unit includes a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube and a sixth switch tube; The second end of the first switch tube and the second end of the second switch tube are both connected to a power source; the first end of the first switch tube, the third end of the second switch tube, the first end of the third switch tube and the second end of the fourth switch tube are all connected through a first node; the third end of the first switch tube, the first end of the second switch tube, the second end of the third switch tube and the first end of the fourth switch tube are all connected through a second node; the third end of the third switch tube and the third end of the fourth switch tube are grounded; Wherein, a first end of the fifth switch tube is connected to the first word line, a second end of the fifth switch tube is connected to the first double bit line, and a third end of the fifth switch tube is connected to the second node; A first end of the sixth switch tube is connected to the second word line, a second end of the sixth switch tube is connected to the second double bit line, and a third end of the sixth switch tube is connected to the first node.

5. A storage and computing integrated circuit, characterized in that: The storage-computation integrated circuit comprises a control circuit, a readout circuit and a memory array according to any one of claims 1 to 4; The control circuit is connected to the first word line, the second word line, the first switch module and the second switch module of the memory array, the control circuit is used to input a control signal to the target memory cell through the first word line and the second word line, and the control circuit is used to control the opening or closing of the first switch module and the second switch module; The readout circuit is connected to each memory cell of the memory array and is used for outputting data of a target memory cell.

6. A control method for a storage-computation integrated circuit, characterized in that: The method is applied to the storage-computation-in-one circuit according to claim 5, and the method comprises: Controlling the first switch module and the second switch module of the storage array in the storage-computation integrated circuit to be in a closed state; Input a control signal 1 to a target memory cell through any one of the first word line and the second word line, and write target data through the first double bit line and the second double bit line, so that the target memory cell performs one of an OR operation and a NOR operation; The operation result of the target storage unit is outputted through the read circuit.

7. The control method according to claim 6, characterized in that: The method further comprises: Controlling the first switch module and the second switch module of the storage array in the storage-computation integrated circuit to be in an off state; Input a control signal 1 to a target memory cell simultaneously through the first word line and the second word line, and write target data through the main bit line and the complement bit line, so that the target memory cell performs one of an AND operation and a NAND operation; The operation result of the target storage unit is outputted through the read circuit.

8. A chip, characterized in that: The chip includes the storage and computing integrated circuit as described in claim 5.

9. An electronic device, characterized in that: The electronic device comprises the chip according to claim 8.

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