Packaging structure and method for interconnection of multiple layers of wafers

Abstract

The invention relates to the technical field of chip packaging, in particular to a packaging structure and method for multilayer wafer interconnection. Comprising a plurality of stacked wafers, the distribution of bonding pads on each wafer is the same, the bonding pads of the adjacent wafers are arranged in a staggered mode, through holes are formed in the wafers, one ends of the through holes are flush with the surface of the wafer on the outermost side, the other ends of the through holes fall on the bonding pads of the wafer on the innermost side, insulating layers are arranged in the through holes, and conductive columns are arranged in the insulating layers. And the bonding pads of the adjacent wafers are electrically connected through the conductive columns. Compared with the prior art, the bonding pads are exposed in a stepped mode through dislocation bonding, holes are uniformly filled after the insulating layers on the surfaces of the bonding pads are removed, and then electrical interconnection between wafers can be achieved. Unified via technology with efficient electrical interconnection is achieved. Therefore, the complicated steps of drilling, depositing and filling holes of multiple layers of wafers are avoided, the overall manufacturing process is simplified, and the production efficiency is remarkably improved.

Description

Technical Field

[0001] The invention relates to the technical field of chip packaging, in particular to a packaging structure and method for interconnecting multiple layers of wafers. Background Art

[0002] With the advancement of technology, people's performance requirements for electronic devices continue to increase, including an urgent need for low latency, low power consumption, and high bandwidth transmission. In this context, effective interconnection between wafers has become a key factor in improving overall system performance. Through tightly interconnected wafers, the data transmission path can be shortened, thereby reducing latency, increasing transmission rates, and enhancing the overall data processing capabilities of the system.

[0003] TSV (Through-Silicon Via) technology is a key process method for achieving efficient vertical electrical connections between wafers or wafers. It greatly improves the efficiency of wafer interconnection by creating vertical conductive channels inside the chip or wafer. In the current wafer interconnection process achieved by TSV technology, each layer of wafer needs to undergo a series of precise drilling, deposition and hole filling steps, and then the wafers are combined together through a precisely aligned bonding process to finally form a three-dimensional structure with multiple layers of wafer interconnection. However, these complicated processes have greatly increased the number of steps in the production process and the technical difficulty of the operation, resulting in a significant extension of the overall production cycle from product design to finished product.

[0004] It is a very simplified and efficient solution to directly align and bond multi-layer wafers accurately, and then perform drilling, deposition and filling steps uniformly. However, this solution has a key problem: the insulating layer is between the pad and the conductive deep hole, which hinders the electrical interconnection between the two. Therefore, this solution cannot achieve true TSV technology. In order to achieve effective electrical interconnection, more precise process control is required to ensure the interconnection between the pad and the conductive deep hole.

[0005] The Chinese patent application number CN201621491243.0 discloses a new type of wafer silicon through-hole interconnected stacked 3D package. First, the individual wafer layers are thinned and stacked, and then the silicon through-holes are completed at one time using ultraviolet lasers. Then, copper is plated in the entire stacked silicon through-holes, and finally the stacked 3D package is completed. However, in actual use, after vertical drilling, a thinner insulating layer will be deposited on the hole wall, and finally the hole will be filled with conductive material. This results in the conductive material that is finally filled not having direct contact with the wafer, and electrical interconnection cannot be achieved. Summary of the invention

[0006] In order to overcome the deficiencies of the prior art, the present invention provides a packaging structure and method for multi-layer wafer interconnection.

[0007] To achieve the above purpose, a packaging structure for multi-layer wafer interconnection is designed, including several stacked wafers, the distribution of pads on each wafer is the same, the pads of adjacent wafers are staggered, a through hole is provided in the wafer, one end of the through hole is flush with the surface of the outermost wafer, and the other end of the through hole falls on the pad of the innermost wafer, an insulating layer is provided in the through hole, a conductive column is provided in the insulating layer, and the pads of adjacent wafers are electrically connected through the conductive column.

[0008] Preferably, the horizontal distance between the pads at the same position on adjacent wafers is 1-5 um.

[0009] Preferably, there is an area without an insulating layer on the surface of the pad, and the side surface of the pad is covered by an insulating layer.

[0010] Preferably, the pad is located on the functional layer of the wafer, and the functional layer of each wafer faces the outermost wafer or the functional layer of each wafer faces the outermost wafer.

[0011] To achieve the above object, a packaging method for multi-layer wafer interconnection is designed, comprising the following steps: S1, stacking a plurality of wafers, with pads of adjacent wafers arranged in a staggered manner, to form a wafer stack; S2, drilling holes uniformly on the wafer stack, the through holes are stepped, and the bottom of the holes at the steps falls on the surface of the pad; S3, uniformly depositing in the through hole to form an insulating layer, the insulating layer is in contact with the surface and side of the pad; S4, removing part of the insulating layer on the surface of the pad; S5, filling a conductive column in the through hole, wherein one end of the conductive column is electrically connected to the pad; S6, forming an electrical connection structure at the other end of the conductive column.

[0012] Preferably, in step S4, the insulating layer on the surface of the pad is removed by etching once, the pad material is selected from one of metal aluminum, copper or titanium, and the etching gas is a fluorine-based gas with a high selectivity for the insulating layer, and the selectivity is 10-20.

[0013] Preferably, in step S4, the insulating layer on the surface of the pad is accurately removed through multiple etching processes, and each etching and removal process avoids the pad to protect the pad from damage.

[0014] Preferably, before step S2, a mask layer is formed on the outermost wafer surface, and after step S5, the mask layer is removed, an insulating layer is deposited, and a CMP treatment is performed.

[0015] Preferably, the specific method of step S1 is as follows: S11, providing a first wafer, and forming a bonding layer on a pad surface of the first wafer; S12, providing a second wafer with a pad facing downward, and bonding the wafer to a carrier through a bonding layer; S13, grinding the other side of the second wafer; S14, flipping the second wafer so that the pad surface faces upward, and staggered bonding the second wafer to the surface of the first wafer, so that the bonding layers of the two wafers are bonded; S15, removing the carrier of the second wafer; S16, depositing a bonding layer on the pad surface of the second wafer; S17, repeating steps S12 to S16 until a plurality of layers of wafer stacks with offset stacking are formed; S18, trimming the edges of the wafer stack to make the edges smooth.

[0016] Preferably, the specific method of step S1 is as follows: S11, providing a first wafer, wherein the pad surface of the first wafer faces downward and is bonded to a carrier; S12, grinding the other side of the first wafer; S13, forming a bonding layer on the surface of the first wafer; S14, providing a second wafer, with the pad surface of the second wafer facing downward, and staggered bonding to the surface of the first wafer, so that the bonding layers of the two wafers are bonded; S15, grinding the other side of the second wafer and depositing a bonding layer; S16, repeating step S14 to step S15 until a plurality of layers of wafer stacks with offset stacking are formed; S17, trimming the edges of the wafer stack to make the edges smooth.

[0017] Compared with the prior art, the present invention uses staggered bonding to expose the pads in a stepped manner, and then uniformly fills the holes after removing the insulating layer on the pad surface, thereby achieving electrical interconnection between wafers. A unified through-hole technology with effective electrical interconnection is achieved. This avoids the complicated steps of drilling, depositing and filling holes in multi-layer wafers, simplifies the overall manufacturing process, and significantly improves production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a structural diagram of embodiment 1 of the present invention.

[0019] Figure 2 This is a schematic diagram of the process of Embodiment 1 of the present invention.

[0020] Figure 3 It is a structural diagram of embodiment 2 of the present invention.

[0021] Figure 4 This is a flow chart of the second embodiment of the present invention. DETAILED DESCRIPTION

[0022] The present invention will be further described below with reference to the accompanying drawings. Embodiment 1

[0023] like Figure 1 As shown, among several stacked wafers 1, the distribution of pads 2 on each wafer 1 is the same, the pads of adjacent wafers 1 are staggered, a through hole 3 is provided in the wafer 1, one end of the through hole 3 is flush with the surface of the outermost wafer 1, and the other end of the through hole 3 falls on the pad 2 of the innermost wafer 1, an insulating layer 4 is provided in the through hole 3, and a conductive column 5 is provided in the insulating layer 4, and the pads 2 of adjacent wafers are electrically connected through the conductive column 5. The through hole 3 passes through other wafers 1 except the innermost wafer 1.

[0024] The horizontal distance between the pads 2 at the same position of adjacent wafers is 1-5 um.

[0025] There is an area without the insulating layer 4 on the surface of the pad 2, which ensures that the pad 2 can be electrically connected to the pad 2 of other wafers 1 through the conductive pillar 5. The side surface of the pad 2 is covered by the insulating layer 4.

[0026] One end of the outermost wafer 1 is connected to the rewiring layer 6, and the rewiring layer 6 is connected to the bump 7. The rewiring layer 6 and the bump 7 form an electrical connection structure with an external device.

[0027] In this embodiment, the wafer on the side electrically connected to the outside through the rewiring layer 6 and the bump 7 is defined as the outermost wafer 1, and the wafer on the side away from the rewiring layer 6 and the bump 7 is defined as the innermost wafer.

[0028] In this embodiment, the pads 2 are located on the functional layers of the wafers 1 , and the functional layer of each wafer 1 faces the outermost wafer 1 .

[0029] like Figure 2 As shown, the packaging method of the multi-layer wafer interconnection includes the following steps: S1, stacking a plurality of wafers 1, with pads 2 of adjacent wafers arranged in a staggered manner, to form a wafer stack 8; S2, uniformly drilling the wafer stack 8, the through hole 3 is stepped, and the bottom of the hole at the step falls on the surface of the pad 2; S3, uniformly depositing in the through hole 3 to form an insulating layer, the insulating layer 4 is in contact with the surface of the pad 2 and the side of the pad 2; S4, removing part of the insulating layer 4 on the surface of the pad 2; S5, filling the conductive column 5 in the through hole 3, one end of the conductive column 5 is electrically connected to the pad 2; S6, forming a rewiring layer 6 and a bump 7 at the other end of the conductive pillar 5; S7, thinning the innermost wafer 1; S8, cutting.

[0030] After the unified drilling in step S2, part of the pads 2 of each layer of wafer 1 will be exposed, and the insulating layer 4 uniformly deposited in step S3 will cover all the exposed parts of the pads 2. Therefore, step S4 needs to remove the insulating layer 4 on the surface of these pads 2, and then uniformly fill the holes, so as to achieve electrical interconnection between the filled conductive deep holes and the pads of each layer of wafers. At the same time, the insulating layer 4 on the side of the pad 2 is not processed.

[0031] In specific use, step S4 can be implemented by etching once or multiple times. The details are as follows: In step S4, the insulating layer 4 on the surface of the pad 2 is removed by one etching. The pad 2 is made of one of metal aluminum, copper or titanium. The etching gas is a fluorine-based gas with a high selectivity for the insulating layer 4, and the selectivity is 10-20.

[0032] In step S4, the insulating layer on the surface of the pad 2 is accurately removed through multiple etching processes, and each etching and removal process avoids the pad 2 to protect the pad 2 from being damaged.

[0033] Before step S2, a mask layer 9 is formed on the outermost wafer 1 surface, and after step S5, the mask layer 9 is removed, an insulating layer 4 is deposited, and a CMP process is performed. When used specifically, a photoresist is deposited on the uppermost wafer 1 surface, and a mask layer is formed by exposure and development.

[0034] The specific method of step S1 in this embodiment is as follows: S11, provide a first wafer 1-1, and form a bonding layer 11 on the pad surface of the first wafer 1-1; S12, provide a second wafer 1-2, with the pad surface facing down, and bonded to the carrier 12 through the bonding layer 11; S13, grind the other side of the second wafer 1-2; S14, flip the second wafer 1-2 to face the pad surface upward, and staggered bond it to the surface of the first wafer 1-1, and the bonding layers 11 of the two wafers 1 are bonded to each other; S15, remove the carrier of the second wafer 1-2; S16, deposit a bonding layer 11 on the pad surface of the second wafer 1-2; S17, repeat steps S12 to S16 until a plurality of layers of staggered stacked wafer stacks 8 are formed; S18, trim the edges of the wafer stack 8 to make the edges smooth.

[0035] The staggered bonding process of the present invention still involves vertical drilling, but the pad material has a high selectivity and is not completely etched away, so the hole presents a step morphology. A thinner insulating layer is deposited on the hole wall, and we propose to remove these portions of the insulating layer on the step surface of the pad, and finally fill the hole with a conductive material, which can directly contact the pad surface in the hole, thereby achieving electrical interconnection. Embodiment 2

[0036] This embodiment only describes the differences from the first embodiment, and the similarities are not described again.

[0037] The difference between this embodiment and the first embodiment is that Figure 3 As shown, in this embodiment, the pad 2 is located on the functional layer of the wafer 1 , and the functional layer of each wafer 1 faces away from the outermost wafer 1 .

[0038] like Figure 4 As shown, in this embodiment, the specific method of step S1 is as follows: S11, provide a first wafer 1-1, with the pad surface of the first wafer 1-1 facing downward and bonded to the carrier 12; S12, grind the other side of the first wafer 1-1; S13, form a bonding layer 11 on the surface of the first wafer 1-1; S14, provide a second wafer 1-2, with the pad surface of the second wafer 1-2 facing downward and offset-bonded to the surface of the first wafer 1-1, and the bonding layers 11 of the two wafers 1 are bonded to each other; S15, grind the other side of the second wafer 1-2 and deposit the bonding layer 11; S16, repeat steps S14 to S15 until a plurality of layers of offset-stacked wafer stacks 8 are formed; S17, trim the edges of the wafer stack 8 to make the edges smooth.

[0039] In step S7 , since the innermost first wafer 1 - 1 is still bonded to the carrier 12 , the carrier 12 is ground and then cut in step S8 .

[0040] In this embodiment, bonding is performed first and then grinding, and the second wafer 1-2 no longer needs to be temporarily bonded to the carrier during grinding, thus saving costs.

[0041] The pads on the wafer of the present invention are evenly distributed in a uniform pattern, and multiple wafers are stacked by regular misalignment to form an orderly interlayer misalignment. The pads also present a corresponding misaligned arrangement between the layers. After uniform drilling, part of the pads of each layer of wafers will be exposed, and the uniformly deposited insulating layer 4 will cover all the exposed partial pads 1. After removing the insulating layer 4 on the surface of these pads 2, the holes are uniformly filled, thereby realizing the electrical interconnection between the filled conductive deep holes and the pads of each layer of wafers 1. The present invention designs a structure and process method for wafer misalignment bonding because the insulating layer hinders the interconnection between the pads and the conductive deep holes, realizes a unified through-hole technology with effective electrical interconnection, thereby avoiding the complicated steps of drilling, depositing and filling holes for multiple layers of wafers, simplifying the overall manufacturing process, and significantly improving production efficiency.

Claims

1. A multi-layer wafer interconnect packaging structure, characterized in that: The invention comprises a plurality of stacked wafers, wherein the distribution of pads (2) on each wafer (1) is the same, and the pads of adjacent wafers (1) are arranged in a staggered manner. A through hole (3) is provided in the wafer (1), one end of the through hole (3) is flush with the surface of the outermost wafer (1), and the other end of the through hole (3) falls on the pad (2) of the innermost wafer (1), an insulating layer (4) is provided in the through hole (3), and a conductive column (5) is provided in the insulating layer (4), and the pads (2) of adjacent wafers are electrically connected via the conductive column (5).

2. The multi-layer wafer interconnect packaging structure according to claim 1, characterized in that: The horizontal distance between the pads (2) at the same position of adjacent wafers is 1-5 um.

3. The multi-layer wafer interconnect packaging structure according to claim 1, characterized in that: There is an area on the surface of the soldering pad (2) without the insulating layer (4), and the side surface of the soldering pad (2) is covered by the insulating layer (4).

4. The multi-layer wafer interconnect packaging structure according to claim 1, characterized in that: The pad (2) is located on the functional layer of the wafer (1), and the functional layer of each wafer (1) faces the outermost wafer (1) or the functional layer of each wafer (1) faces the outermost wafer (1).

5. A packaging method for multi-layer wafer interconnection, characterized in that: The steps include: S1, stacking a plurality of wafers (1), with pads (2) of adjacent wafers arranged in a staggered manner, to form a wafer stack (8); S2, drilling the wafer stack (8) uniformly, wherein the through hole (3) is in a stepped shape, and the bottom of the hole at the stepped portion falls on the surface of the pad (2); S3, uniformly depositing in the through hole (3) to form an insulating layer, wherein the insulating layer (4) is in contact with the surface of the pad (2) and the side of the pad (2); S4, removing a portion of the insulating layer (4) on the surface of the pad (2); S5, filling a conductive column (5) in the through hole (3), wherein one end of the conductive column (5) is electrically connected to the pad (2); S6, forming an electrical connection structure at the other end of the conductive column (5).

6. The packaging method of multi-layer wafer interconnection according to claim 5, characterized in that: In the step S4, the insulating layer (4) on the surface of the pad (2) is removed by etching once, the pad (2) is made of a material selected from the group consisting of metal aluminum, copper or titanium, and the etching gas is a fluorine-based gas having a high selectivity for the insulating layer (4), the selectivity being 10 to 20.

7. The packaging method of multi-layer wafer interconnection according to claim 5, characterized in that: In the step S4, the insulating layer on the surface of the pad (2) is accurately removed through multiple etching processes, and each etching and removal process avoids the pad (2) to protect the pad (2) from damage.

8. The packaging method for multi-layer wafer interconnection according to claim 5, characterized in that: Before step S2, a mask layer (9) is formed on the surface of the outermost wafer (1), and after step S5, the mask layer (9) is removed, an insulating layer (4) is deposited, and a CMP treatment is performed.

9. The packaging method of multi-layer wafer interconnection according to claim 5, characterized in that: The specific method of step S1 is as follows: S11, providing a first wafer (1-1), and forming a bonding layer (11) on a pad surface of the first wafer (1-1); S12, providing a second wafer (1-2), with the pad facing downward, and bonding it to a carrier board (12) via a bonding layer (11); S13, grinding the other side of the second wafer (1-2); S14, flipping the second wafer (1-2) so that the pad surface faces upward, and staggered bonding it to the surface of the first wafer (1-1), so that the bonding layers (11) of the two wafers (1) are bonded to each other; S15, removing the carrier of the second wafer (1-2); S16, depositing a bonding layer (11) on the pad surface of the second wafer (1-2); S17, repeating steps S12 to S16 until a plurality of layers of staggered stacked wafer stacks (8) are formed; S18, trimming the edges of the wafer stack (8) to make the edges smooth.

10. The packaging method of multi-layer wafer interconnection according to claim 5, characterized in that: The specific method of step S1 is as follows: S11, providing a first wafer (1-1), wherein the pad surface of the first wafer (1-1) faces downward and is bonded to a carrier board (12); S12, grinding the other side of the first wafer (1-1); S13, forming a bonding layer (11) on a surface of the first wafer (1-1); S14, providing a second wafer (1-2), wherein the pad surface of the second wafer (1-2) faces downward and is offset-bonded to the surface of the first wafer (1-1), and the bonding layers (11) of the two wafers (1) are bonded to each other; S15, grinding the other side of the second wafer (1-2) and depositing a bonding layer (11); S16, repeating step S14 to step S15 until a plurality of layers of staggered stacked wafer stacks (8) are formed; S17, trimming the edges of the wafer stack (8) to make the edges smooth.

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