Constant on low dropout regulator for coin battery based wireless local area network devices

Abstract

Techniques and apparatus for operating a low dropout (LDO) regulator during cold start and different sleep mode scenarios of a device including the LDO regulator that is always on. The LDO regulator may be provided in, for example, a wireless local area network (WLAN) device powered by a coin battery. One example apparatus may be an integrated circuit (IC), which may be disposed in such a WLAN device and / or may be a power management unit (PMU). The IC generally includes a first port for coupling to a battery, a second port, a switched mode power supply (SMPS) including a power input coupled to the second port, and an LDO regulator including a power input selectively coupled to the first port or an output of the SMPS.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Non-Provisional Application No. 18 / 446,338, filed on August 8, 2023, which claims the benefit of and priority to U.S. Provisional Application No. 63 / 370,883, filed on August 9, 2022, and U.S. Provisional Application No. 63 / 491,692, filed on March 22, 2023, all of which are hereby expressly incorporated herein by reference as if fully set forth below and for all applicable purposes. Technical Field

[0003] Certain aspects of the present disclosure relate generally to electronic circuits and, more particularly, to a low dropout (LDO) voltage regulator that may be included in a wireless local area network (WLAN) device powered by a coin cell battery. Background Art

[0004] A voltage regulator provides a constant direct current (DC) output voltage regardless of changes in load current or input voltage. Voltage regulators can be classified as linear regulators or switching regulators. Although linear regulators are small and compact, many applications can benefit from the improved efficiency of switching regulators. For example, linear regulators can be implemented by low dropout (LDO) regulators. Switching regulators can be implemented by switch mode power supplies (SMPS) such as buck converters, boost converters, buck-boost converters, or charge pumps.

[0005] For example, a buck converter is a type of SMPS that typically includes: (1) a high-side switch coupled between a relatively high voltage rail and a switch node, (2) a low-side switch coupled between the switch node and a relatively low voltage rail, (3) and an inductor coupled between the switch node and a load (e.g., represented by a shunt capacitor element). The high-side switch and the low-side switch may be implemented using transistors, but the low-side switch may also be implemented using a diode.

[0006] A power management unit (PMU) is used to manage the power requirements of a host system and may include and / or control one or more voltage regulators (e.g., LDO and / or SMPS). A PMU may be used in battery-powered devices such as mobile phones, tablets, laptops, wearable devices, etc. to control the flow and direction of power in the device. The PMU may perform various functions for the device, such as DC to DC conversion (e.g., using a voltage regulator as described above), battery charging, power source selection, voltage scaling, power sequencing, etc. Summary of the invention

[0007] The systems, methods, and devices of the present disclosure each have several aspects, no single one of which is solely responsible for its desirable characteristics. Without limiting the scope of the present disclosure as expressed in the appended claims, some features are briefly discussed. After considering this discussion, and particularly after reading the section entitled "Detailed Description of the Invention," one will understand how the features of the present disclosure provide the advantages described herein.

[0008] Certain aspects of the present disclosure are generally directed to a wireless local area network (WLAN) device that includes an always-on low dropout (LDO) voltage regulator and a coin cell battery coupled to the LDO voltage regulator and configured to power the same.

[0009] Certain aspects of the present disclosure generally relate to techniques for operating an always-on low dropout (LDO) regulator during cold start and sleep modes of a device including the low dropout (LDO) regulator. The LDO regulator may be provided, for example, in a WLAN device powered by a coin cell battery.

[0010] Certain aspects of the present disclosure provide an integrated circuit (IC) for power management. The IC generally includes a first port for coupling to a battery, a second port, a switching mode power supply (SMPS) including a power input coupled to the second port, and an LDO regulator including a power input selectively coupled to the first port or an output of the SMPS.

[0011] Certain aspects of the present disclosure provide a WLAN device including the IC described herein.

[0012] Certain aspects of the present disclosure provide a method for managing power in an IC. The IC generally includes an LDO regulator and an SMPS. The method generally includes: during a cold start of the IC, coupling a power input of the LDO regulator to a battery input of the IC so that the LDO regulator is powered by the battery for cold start; and after a cold start of the IC, coupling the power input of the LDO regulator to an output of the SMPS so that the LDO regulator is powered by the SMPS.

[0013] Certain aspects of the present disclosure provide a non-transitory computer-readable medium encoding logic, which, when executed by at least one processor of a device, causes the device to perform a method for managing power in an IC, the IC including an LDO regulator and an SMPS. The method generally includes: during a cold start of the IC, coupling a power input of the LDO regulator to a battery input of the IC so that the LDO regulator is powered by the battery for the cold start; and after a cold start of the IC, coupling the power input of the LDO regulator to an output of the SMPS so that the LDO regulator is powered by the SMPS.

[0014] To achieve the aforementioned and related purposes, one or more aspects include the features fully described below and particularly pointed out in the claims. The following description and the accompanying drawings set forth in detail certain exemplary features of the one or more aspects. However, these features indicate only some of the various ways in which the principles of the various aspects can be employed. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to be able to understand in detail the manner in which the above-mentioned features of the present disclosure are achieved, a more specific description briefly summarized above can be obtained by reference to various aspects, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only certain typical aspects of the present disclosure and are therefore not to be considered as limiting the scope thereof, as the specification may admit to other equally effective aspects.

[0016] Figure 1 is a block diagram of an example device including a battery coupled to a power management unit (PMU), in accordance with certain aspects of the present disclosure.

[0017] Figure 2 is a block diagram of an example PMU powered by a coin cell battery, according to certain aspects of the present disclosure.

[0018] Figure 3 and Figure 4 Different sleep mode scenarios for an always-on low dropout (AON LDO) voltage regulator are illustrated in accordance with certain aspects of the present disclosure.

[0019] Figure 5 is a block diagram of an example circuit for operating an AON LDO in a discontinuous conduction mode (DCM), according to certain aspects of the present disclosure.

[0020] Figure 6 is a flow chart depicting example operations for managing power in an integrated circuit (IC) including an LDO and a switch mode power supply (SMPS), in accordance with certain aspects of the present disclosure.

[0021] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one aspect may be beneficially utilized on other aspects without specific recitation. DETAILED DESCRIPTION

[0022] The various aspects of the present disclosure are described more fully below with reference to the accompanying drawings. However, the present disclosure can be embodied in many different forms, and should not be interpreted as being limited to any specific structure or function presented throughout the present disclosure. On the contrary, these aspects are provided so that the present disclosure will be thorough and complete, and the scope of the present disclosure will be fully conveyed to those skilled in the art. Based on the teachings of this article, it should be understood by those skilled in the art that the scope of the present disclosure is intended to cover any aspect of the disclosure disclosed herein, whether it is implemented independently or in combination with any other aspect of the present disclosure. For example, any number of aspects set forth herein can be used to implement a device or practice method. In addition, the scope of the present disclosure is intended to cover such a device or method that is practiced using other structures, functions, or structures and functions in addition to or different from the various aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein can be embodied by one or more elements of the claims.

[0023] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0024] As used herein, the term "connected with" in various tenses of the verb "connect" may mean that element A is directly connected to element B or that other elements may be connected between element A and element B (i.e., element A is indirectly connected to element B). In the context of electronic components, the term "connected with" may also be used herein to mean that wires, traces, or other conductive materials are used to electrically connect element A and element B (and any components electrically connected therebetween).

[0025] Example Device

[0026] It should be understood that various aspects of the present disclosure can be used for various applications. Although the present disclosure is not limited in this respect, the circuits disclosed herein can be used in any of a variety of suitable devices, such as power supplies, battery charging circuits or power management circuits for communication systems, video codecs, audio equipment (such as music players and microphones), televisions, camera equipment, and / or test equipment (such as oscilloscopes). By way of example only, communication systems intended to be included within the scope of the present disclosure include cellular radiotelephone communication systems, satellite communication systems, two-way radio communication systems, one-way pagers, two-way pagers, personal communication systems (PCS), personal digital assistants (PDAs), Internet of Things (IoT) devices, etc.

[0027] Figure 1An example device 100 is illustrated in which aspects of the present disclosure may be implemented. Device 100 may be a battery-driven device such as a cellular phone, a PDA, a handheld device, a wireless device, a laptop, a tablet computer, a smart phone, a wearable device, an augmented reality device, or the like.

[0028] The device 100 may include a processor 104 that controls the operation of the device 100. The processor 104 may also be referred to as a central processing unit (CPU). A memory 106, which may include both read-only memory (ROM) and random access memory (RAM), provides instructions and data to the processor 104. A portion of the memory 106 may also include non-volatile random access memory (NVRAM). The processor 104 typically performs logical and arithmetic operations based on program instructions stored in the memory 106.

[0029] In some aspects, the device 100 may also include a housing 108, which may include a transmitter 110 and a receiver 112 to allow data to be sent and received between the device 100 and a remote location. For some aspects, the transmitter 110 and the receiver 112 may be combined into a transceiver 114. One or more antennas 116 may be attached to or otherwise mechanically coupled to the housing 108 and electrically coupled to the transceiver 114. The device 100 may also include (not shown) multiple transmitters, multiple receivers, and / or multiple transceivers.

[0030] The device 100 may also include a signal detector 118, which may be used to detect and quantify the signal level received by the transceiver 114. The signal detector 118 may detect signal parameters such as total energy, energy per subcarrier per symbol, and power spectral density and other signal parameters. The device 100 may also include a digital signal processor (DSP) 120 for processing signals.

[0031] Device 100 may also include a battery 122 for powering various components of device 100. For certain aspects, battery 122 may be a coin cell style battery, such as a CR2032 battery, which is a round lithium battery and may be capable of delivering 220 milliamp hours (mAh).

[0032] The device 100 may also include a power management unit (PMU) 123 for managing power from a battery to various components of the device 100. At least a portion of the PMU 123 may be implemented in one or more power management integrated circuits (power management ICs or PMICs). The PMU 123 may perform various functions for the device 100, such as DC to DC conversion, battery charging, power source selection, voltage scaling, power sequencing, etc. For example, the PMU 123 may include a battery charging circuit (e.g., a master-slave battery charging circuit) for charging the battery 122. The PMU 123 may include one or more power supply circuits, which may include at least one low dropout (LDO) voltage regulator 124 and / or at least one switch mode power supply (SMPS) 125. The switch mode power supply may be implemented by any of a variety of suitable switch mode power supply circuit topologies, such as a buck converter, a boost converter, a buck-boost converter, or a charge pump.

[0033] The various components of the device 100 may be coupled together via a bus system 126, which may include a power bus, a control signal bus, and / or a status signal bus in addition to a data bus. Additionally or alternatively, various combinations of components of the device 100 may be coupled together via one or more other suitable technologies.

[0034] Example device with always-on LDO

[0035] Micro-power Wi-Fi technology (e.g., under the IEEE 802.11 family of standards, such as IEEE 802.11n) enables Wi-Fi devices to operate on coin cell batteries (e.g., CR2032 batteries) and achieve usable battery life. For certain aspects, such micro-power Wi-Fi technology can be used for extended personal area network (XPAN) applications.

[0036] In the case of micropower Wi-Fi, a wireless local area network (WLAN) integrated circuit (IC) may be powered by a single coin cell battery. It may be desirable to provide the device with a regulated voltage (e.g., from a PMU) that is always on during various sleep mode conditions. This regulated voltage may be used primarily to maintain the state of multiple logic gates in the WLAN IC (e.g., a system on chip (SoC)) and the PMU to provide fast switching of the device from sleep mode. Ideally, the always-on regulator that provides this voltage should have minimal current consumption.

[0037] Figure 22 is a block diagram of an example PMU 200 powered by a coin cell battery 202, according to certain aspects of the present disclosure. The PMU 200 may include at least one switch mode power supply (e.g., a first switch mode power supply (SMPS) 204 labeled “SMPS1” and a second SMPS 206 labeled “SMPS2”). SMPS1 and SMPS2 may each be configured to generate a regulated voltage based on power from the coin cell battery 202. The PMU 200 may also include an always-on low dropout regulator (AON LDO) 208, an oscillator low dropout (LDO) regulator 210 (labeled “OSC LDO”), an oscillator 212 (labeled “OSC”), and logic 226. The oscillator 212 may be used as a sleep mode clock source, powered by a regulated voltage generated by the oscillator LDO regulator 210, and configured to generate a clock signal (e.g., for sleep mode).

[0038] The PMU 200 may include a first port 214, a second port 216, and a third port 218. Figure 2 As shown, each of the ports 214, 216, 218 is coupled to the positive terminal of the coin cell battery 202. In some cases, the first port 214 and the second port 216 can be the same port, while in other cases, these ports 214, 216 can be shorted outside of the PMU 200, as shown. The negative terminal of the coin cell battery 202 can be coupled to a reference potential node 234 (e.g., electrical ground). The SMPS 204 can have a power input coupled to the second port 216, and the SMPS 206 can have a power input coupled to the third port 218.

[0039] The AON LDO 208 may include a first switch S1, a second switch S2, a pass transistor M1, and an amplifier 236 (e.g., an error amplifier). As shown, switch S1 may be a single-pole double-throw (SPDT) switch. Switch S1 may alternatively be implemented in various other suitable ways. Transistor M1 may be a metal oxide semiconductor field effect transistor (MOSFET), which may be a p-type transistor (as shown) or an n-type transistor. Switch S2 may be referred to as a bypass switch and may be configured to bypass transistor M1. Alternatively, switch S2 may not be included in the AON LDO 208, and the functionality of switch S2 may be implemented by clamping the gate voltage of transistor M1 to a higher voltage. The AON LDO 208 may have a power input 228 that effectively includes or is implemented by switch S1, such as Figure 2The switch S1 may include a first terminal 220 coupled to the first port 214 (having a battery voltage labeled “VBAT” from the coin cell battery 202 ), coupled to an output terminal of the SMPS 204 (e.g., labeled “VDD RF The third terminal 222 of the switch S1 can be configured to selectively couple to the first port 214 via the first terminal 220 or to the output of the SMPS1 via the second terminal 224.

[0040] Also referred to as a "pass transistor" of the AON LDO 208, the transistor M1 may have a source coupled to the third terminal 222 of the switch S2 and the first terminal 230. The transistor M1 may also have a gate coupled to the output of the amplifier 236 and a positive input coupled to the amplifier 236 and the output of the AON LDO 208 (e.g., labeled "VDD AON ” output rail voltage). As shown, the output of AON LDO 208 can be coupled to oscillator LDO regulator 210 and oscillator 212. The negative input of amplifier 236 can be coupled to a reference voltage node (labeled “V REF ”).

[0041] Logic 226 may be configured to provide control signals to switches (e.g., switch S1 and switch S2) and / or control other aspects of PMU 200. Logic 226 may also provide enable signals 236 (e.g., an enable signal labeled "En1") to various components such as amplifiers, SMPS1, and SMPS2.

[0042] The AON LDO 208 may be specified to operate under a variety of input power conditions while consuming minimal, or at least reduced, current. In some cases, during a cold start (e.g., of the WLAN IC), the AON LDO 208 may use a battery supply voltage (e.g., from the coin cell battery 202 and labeled “VBAT”) directly because that voltage may be the only available voltage source. For example, the switch S1 may be controlled to select the first terminal 220, and the power input 228 may receive the battery supply voltage at the first terminal 220, such that the AON LDO 208 is powered by the coin cell battery 202. During a cold start, one or more of the SMPS 204 and the SMPS 206 may be enabled (e.g., by an enable signal, not shown) after the AON LDO 208 is enabled (e.g., by an En1 signal).

[0043] In some aspects, PMU 200 can be configured to enter a sleep mode of the device. To enter sleep mode when the RF circuit power rail voltage from SMPS 204 is available, power input 228 of AON LDO 208 can be coupled to the output of SMPS 204 (e.g., via switch S1), switch S2 (e.g., controlled by logic 226) can be closed to bypass transistor M1, and AON LDO 208 can be disabled (e.g., via En1 signal). In some cases, when entering sleep mode, switch S2 can be closed after a delay. In some cases, to enter sleep mode, SMPS 204 can boost its output voltage (VDD) before switch S2 is closed. RF ), and SMPS 204 may then enter a low power mode (eg, for the duration of the sleep mode).

[0044] In some aspects, to exit the sleep mode of the device, switch S2 can be opened (e.g., controlled by logic 226) and AON LDO 208 can be enabled (e.g., enabled by En1 signal). In some cases, switch S2 can be opened after a delay. To exit the sleep mode, SMPS 204 can exit from the low power mode before switch S2 is opened and enter a pulse frequency modulation (PFM) mode or a pulse width modulation (PWM) mode.

[0045] During sleep mode, AON LDO 208 may consume as little current as possible, regardless of whether other on-chip regulators are enabled, and regardless of whether a sleep clock signal (eg, from oscillator 212) is enabled. For example, the target current consumption may be approximately 100 nA.

[0046] According to certain aspects of the present disclosure, to meet these design specifications during cold start, AON LDO 208 and the VDD RF regulator (e.g., SMPS1). Once the cold start is complete, the power input 228 of the AON LDO 208 can be switched from the coin cell battery voltage (e.g., via the first terminal 220 of the switch S1) to the output voltage of the SMPS1 (e.g., via the second terminal 224 of the switch S1) using the switch S1. That is, the AON LDO 208 can be configured to use the switch S1 (e.g., controlled by the logic 226) to couple the source of the pass transistor to the output of the SMPS1 and begin using the regulated voltage from the SMPS1 to reduce the battery reference power consumption. That is, the third terminal 222 of the switch S1 can be coupled to the second terminal 224, and the power input 228 can receive the regulated voltage VDD RF, so that AON LDO 208 is powered by SMPS1. For the operations described herein, both hardware-based and software-based control are available.

[0047] Entering sleep mode may involve two different scenarios: (1) VDD RF and system sleep clock available, and (2) VDD RF The sources of the SMPS1 and system clocks (eg, SMPS1 and oscillator 212, respectively) are powered down.

[0048] Figure 3 is an example diagram 300 of a first sleep mode scenario (labeled “Scene 1”) according to certain aspects of the present disclosure, wherein VDD RF and sleep clocks are available. Before entering sleep mode, the SMPS1 can operate in pulse frequency modulation (PFM) mode or pulse width modulation (PWM) mode to regulate VDD RF In this scenario, to enter sleep mode, the AON LDO transmission gate (e.g., transistor M1) can be bypassed (e.g., by closing switch S2), and the controller of AON LDO 208 (e.g., amplifier 236) can be disabled, so that the output terminal (VDD AON ) can effectively short to the output of SMPS1 (VDD RF ). For some aspects, SMPS1 can reduce VDD before the switch is closed. RF Additionally or alternatively, for some aspects, the transmission gate may be bypassed after a delay of Δt1, which may start immediately when the sleep mode entry is triggered (or when VDD is raised from SMPS1). RF )

[0049] During sleep mode, the SMPS1 may enter a low power mode where the output voltage is below VDD RF Furthermore, the AON LDO 208 may consume only leakage current during sleep mode.

[0050] To exit sleep mode, SMPS1 may exit from low power mode and begin ramping up its output voltage VDD RF For example, SMPS1 may enter a pulse frequency modulation (PFM) mode or a pulse width modulation (PWM) mode. In addition, AON LDO 208 may be enabled (e.g., by the En1 signal at amplifier 236), and switch S2 may be opened (e.g., controlled by logic 226). In some cases, switch S2 may be switched from VDD to VDD. RF Once switch S2 is turned off, the output of AON LDO 208 (VDDAON ) is no longer effectively shorted to the output of SMPS1 (VDD RF ), and the two signals have different voltage levels as shown.

[0051] Before entering sleep mode, parameters related to sleep transition (e.g. Figure 3 ΔV1, Δt1, and Δt2) shown can be adjusted by software, which can improve the design robustness.

[0052] Figure 4 is an exemplary diagram 400 of a second sleep mode scenario (labeled “Scene 2”) according to certain aspects of the present invention, wherein VDD RF The sources of the SMPS1 and system clock (e.g., SMPS1 and oscillator 212, respectively) are powered down during sleep mode. Curve 400 shows that upon initially entering sleep mode, the PMU may operate in a similar manner as in curve 300. However, in curve 400, SMPS1 and oscillator LDO regulator 210 are powered down at time t a Power is lost, causing VDD RF The oscillator 212 is ramped down (eg, as a capacitor (not shown) at the output of the SMPS 1 discharges) and effectively disables the oscillator 212, thereby stopping the clock signal during the sleep mode. Also at time t a At , the AON LDO 208 begins operating directly from the battery voltage from the coin cell battery 202. For certain aspects, the power input 228 of the AON LDO 208 is switched to VBAT (eg, the third terminal 222 of the switch S1 is coupled to the first terminal 220).

[0053] From time t a Initially, the AON LDO 208 may be operated in a discontinuous conduction mode (DCM). To operate in DCM, two low power comparators (e.g., Figure 5 The thresholds of the two comparators may be slightly skewed, and the two comparator output bits may be used to set the LDO output (e.g., VDD AON ) is limited within a voltage window set by the two thresholds (e.g., two offset reference voltages Vref_h and Vref_1). For certain aspects, transistor M3 is enabled during sleep mode when the LDO output is about to fall below a lower threshold (e.g., Vref_1). For certain aspects, AON LDO 208 may be idle when the LDO output is about to rise above a higher threshold (e.g., Vref_h). For example, the length of the time window when the pass transistor is enabled may be adjusted by software.

[0054] To exit sleep mode, SMPS1 can be powered up and at time t b The output voltage VDD starts to rise RF . At VDD RF After reaching its low power mode voltage level, the comparator (and / or Figure 5 ) can be disabled so that the AON LDO 208 exits DCM, and the switch S2 can be switched on at time t c The output of AON LDO 208 and the output of SMPS1 are effectively shorted together (eg, VDD AON Tracking VDD RF ), similar to the first sleep mode scenario. After a delay, SMPS1 may exit its low power mode, AON LDO 208 may be enabled (e.g., by the En1 signal at amplifier 236), and switch S2 may be opened (e.g., controlled by logic 226). In some cases, switch S2 may be switched off from VDD RF After a delay (eg, delay Δt2) from ramping back from low power mode, switch S2 is turned off. Once switch S2 is turned off, the output terminal (VDD AON ) is no longer effectively shorted to the output of SMPS1 (VDD RF ), and the two signals have different voltage levels as shown.

[0055] Figure 5 is a block diagram of an example circuit 500 for operating the AON LDO 208 in a discontinuous conduction mode (DCM) according to certain aspects of the present disclosure. The circuit 500 may include an ultra-low power (ULP) bias circuit 502, low power comparators 504, 506, logic 508, 510, a pulse generator 512 (labeled "OneShot"), transistor M2, transistor M3, and a capacitive element 514. The ULP bias circuit 502 may be implemented as a low power bandgap reference (e.g., part of the PMU 200), which may generate two offset reference voltages: Vref_h and Vref_l. The ULP bias circuit 502 may have a control input (e.g., labeled "SEL_INDEFINITE__DEEPSLEEP") that may be used to enable or disable the two reference voltages (e.g., Vref_h and Vref_l) generated by the ULP bias circuit 502. Vref_h is slightly higher than Vref_l (e.g., tens to hundreds of millivolts). Two low power comparators 504, 506 can be used to adjust the regulated output voltage (Vreg, where Vreg = VDD) of the AON LDO 208. AON) is compared with the two reference voltages and generates two one-bit outputs (Comp_h and Comp_l) as shown. The pulse generator 512 may be implemented as a one-shot pulse generator or any other suitable pulse generator and may have a programmable pulse width.

[0056] The transistor M2 (implemented by a p-type field effect transistor (PFET)) may have a source coupled to the first port 214 of the PMU 200 and a source coupled to the AON LDO 208 (VDD AON ). Transistor M3 (implemented by a PFET) may also have a source coupled to the first port 214 of PMU 200 and a drain coupled to the output of AON LDO 208. Transistor M3 may have a tunable transistor size.

[0057] Comparator 504 may have a first input coupled to a first reference voltage node having a higher reference voltage Vref_h from ULP bias circuit 502, and an output coupled to AON LDO 208 (at Figure 5 506 may have a first input coupled to a second reference voltage node having a lower reference voltage Vref_1 from the ULP bias circuit 502, and an output terminal coupled to the AON LDO 208 (Vreg=VDD). AON ). Logic 510, which may be implemented as a NAND gate, may have a first input coupled to the output of comparator 506 (labeled “Comp_1”) and a second input coupled to an enable node (configured to receive the En_loop signal). Logic 510 may have an output coupled to the gate of transistor M3. Comparators 504, 506 may each have a control input (labeled “En_comp”) that may be controlled by logic 226 to enable and disable the comparator.

[0058] Capacitive element 514 may be coupled between the output of AON LDO 208 and a reference potential node 516 (eg, electrical ground). For example, capacitive element 514 may be implemented by one or more capacitors having a total capacitance of approximately 1 μF capacitor.

[0059] In the second sleep mode scenario, as described above Figure 4As described above, SMPS1 can be disabled, and VDD at the output of the AON LDO 208 AON can be higher than the first reference voltage (Vref_h) on the first reference voltage node. In this case, the AON LDO 208 can be configured to be idle. That is, if Vreg > Vref_h, then (Comp_h, Comp_l) = (0, 0), and the AON LDO 208 is idle (e.g., there is substantially no current consumption in the AON LDO 208 except for the low-power comparators 504, 506).

[0060] In another case, during the second sleep mode scenario, SMPS1 can be disabled, and VDD AON can be lower than the first reference voltage (Vref_h), but higher than the second reference voltage (Vref_l) on the second reference voltage node. In this case, Comp_h is logic high, Comp_l is logic low, and the logic 508 can be configured to trigger the pulse generator 512 to generate an output pulse that instantaneously turns on the transistor M2 within a time interval Δt3 (e.g., the time length of the pulse) to charge the capacitive element 514 from the coin cell battery 202 (e.g., through the voltage node labeled "VBAT") during the time interval Δt3, and increase the voltage at the output of the AON LDO 208. That is, if Vref_l < Vreg < Vref_h, then (Comp_h, Comp_l) = (1, 0), and the transistor M2 driven by the pulse from the pulse generator 512 can be briefly activated to charge the capacitive element 514 and increase Vreg (= VDD AON ).

[0061] In yet another case, during the second sleep mode scenario, SMPS1 can be disabled, and VDD AON can be lower than the second reference voltage (Vref_l). In this case, Comp_h is logic high, Comp_l is logic high, and the logic 510 can be configured to turn on the transistor M3 to charge the capacitive element 514 from the coin cell battery 202 (e.g., through the voltage node labeled "VBAT"), and increase the voltage at the output of the AON LDO 208. The capacitive element 514 can be continuously charged until VDD AON (= Vreg) increases above the second reference voltage (Vref_l). That is, when (Comp_h, Comp_l) = (1, 1), the transistor M3 driven by the logic 510 supplies most of the charge to the capacitive element 514.

[0062] In certain aspects, PMU 200 (e.g., logic 226 in PMU 200) may be configured to determine the length of a time period that AON LDO 208 is configured to idle during a sleep mode of the IC, and adjust the length of the time interval based on the length of the time period. PMU 200 may be configured to count the number of falling edges or rising edges of a clock signal (e.g., a clock signal from oscillator 212) associated with the sleep mode of the IC while AON LDO 208 is configured to idle during the sleep mode of the IC. In these aspects, PMU 200 may be configured to adjust the length of the time interval based on the count of falling edges or rising edges of the clock signal.

[0063] Using these techniques described above for certain aspects of the present disclosure, after a cold start, the AON LDO 208 consumes minimal or at least reduced current throughout different system configurations (including two sleep mode scenarios). In particular, in the second sleep mode scenario, operation in an event-driven manner results in very low power consumption (e.g., a typical current consumption including the bandgap circuit is 0.3 μA) without the need for a system sleep clock. In addition, functionality can be maintained over a wide battery voltage range between 3.6V and 1.8V.

[0064] According to certain aspects, when the system sleep clock is available, the system sleep clock can be used to count the time period during the sleep duration when (Comp_h, Comp_l) = (0,0). The result of the counting (e.g., the count value) can be used to adjust the pulse width of the pulse generator (e.g., pulse generator 512) for the next sleep cycle. For example, for a given load current of AON LDO208, when the count value is large, this indicates that the current pulse generator pulse width is too large, which may result in a large Vreg ripple. By reducing the pulse width of the pulse generator, the Vreg ripple can be reduced in the next sleep cycle. For another example, when the count value of the load current of the AON LDO is small or zero, this indicates that the current pulse generator pulse width is too small, which may result in a lower average AON LDO output voltage (e.g., a smaller margin for robust AON LDO function). In this case, the pulse generator pulse width can be increased in the next sleep cycle.

[0065] Example Power Management Operations

[0066] Figure 6 6 is a flow chart depicting example operations 600 for managing power in an integrated circuit (IC) according to certain aspects of the present disclosure. The IC includes an LDO regulator (e.g., AON LDO 208) and an SMPS (e.g., SMPS1 204). Operations 600 may be performed by a PMU (e.g., PMU 200) included in the IC.

[0067] Operations 600 may begin at box 602, where during a cold start of the IC, the IC couples a power input of an LDO regulator (e.g., power input 228 or the source of transistor M1) to a battery input of the IC (e.g., first port 214) such that the LDO regulator is powered by a battery (e.g., coin cell battery 202) for a cold start.

[0068] At block 604, after a cold start of the IC, the IC may couple the power supply input of the LDO regulator to the output of the SMPS (eg, VDD RF ), so that the LDO regulator is powered by the SMPS.

[0069] According to certain aspects, operation 600 may also include entering a sleep mode of the IC. In these aspects, when the output voltage (e.g., VDD) from the SMPS is RF ) is available, entering the sleep mode may include coupling the power input of the LDO regulator to the output of the SMPS, closing a switch (e.g., switch S2) to bypass the pass transistor (e.g., transistor M1) of the LDO regulator, and disabling the LDO regulator (e.g., via the En1 signal). In some cases, entering the sleep mode of the IC may also include boosting the output voltage from the SMPS before closing the switch, and after boosting, causing the SMPS to enter a low power mode for the duration of the sleep mode. In some aspects, operation 600 also includes exiting the sleep mode of the IC. Exiting the sleep mode of the IC may include disconnecting the switch and enabling the LDO regulator. In some cases, exiting the sleep mode of the IC may also include exiting the SMPS from the low power mode and entering a pulse frequency modulation (PFM) mode or a pulse width modulation (PWM) mode before disconnecting the switch.

[0070] In some aspects, during a sleep mode of the IC, if the SMPS is disabled and the voltage at the output of the LDO regulator (e.g., the output rail voltage VDD AOD) is: (i) above a first reference voltage (e.g., Vref_h), the LDO regulator is configured to be idle; (ii) below the first reference voltage but above a second reference voltage (e.g., Vref_1), a capacitive element (e.g., capacitive element 514) coupled to the output of the LDO regulator is charged from a battery during a time interval (e.g., time interval Δt3) to increase a voltage at the output of the LDO regulator; or (iii) below the second reference voltage, the capacitive element is charged from a battery to increase a voltage at the output of the LDO regulator. In these aspects, the second reference voltage is lower than the first reference voltage. In certain aspects, operation 600 may also include determining a length of a time period during which the LDO regulator is configured to be idle during a sleep mode of the IC, and adjusting a length of the time interval based on the length of the time period. In some aspects, operation 600 may also include counting a number of falling edges or rising edges of a clock signal associated with a sleep mode of the IC (e.g., generated from the output of oscillator 212) when the LDO regulator is configured to be idle during the sleep mode of the IC, and adjusting the length of the time interval based on the count of the falling edges or rising edges of the clock signal.

[0071] Example aspects

[0072] In addition to the above-mentioned aspects, specific combinations of the aspects are also within the scope of the present disclosure, and the details of some of the specific combinations are as follows:

[0073] Aspect 1: An integrated circuit (IC) for power management, the IC comprising: a first port for coupling to a battery; a second port; a switch mode power supply (SMPS), the switch mode power supply (SMPS) comprising a power input coupled to the second port; and a low dropout (LDO) regulator, the low dropout (LDO) regulator comprising a power input selectively coupled to the first port or an output of the SMPS.

[0074] Aspect 2: According to the IC of Aspect 1, the IC also includes a switch, the switch includes a first terminal coupled to the first port, a second terminal coupled to the output end of the SMPS, and a third terminal coupled to the power input end of the LDO regulator, wherein the switch is configured to selectively couple the first terminal or the second terminal to the third terminal.

[0075] Aspect 3: The IC of aspect 2, wherein during a cold start of the IC, the switch is configured to couple the first terminal to the third terminal such that the LDO regulator is configured to be powered by the battery.

[0076] Aspect 4: The IC of aspect 3, wherein during the cold start of the IC, the SMPS is configured to be enabled after the LDO regulator is enabled.

[0077] Aspect 5: The IC of aspect 3 or 4, wherein after the cold start of the IC, the switch is configured to couple the second terminal to the third terminal such that the LDO regulator is configured to be powered by the SMPS.

[0078] Aspect 6: The IC of aspect 1, wherein the LDO regulator comprises: a transistor; and a switch comprising a first terminal coupled to a source of the transistor and a second terminal coupled to a drain of the transistor.

[0079] Aspect 7: An IC according to Aspect 6, wherein in order to enter a sleep mode of the IC, when the output voltage from the SMPS is available, the power input terminal of the LDO regulator is coupled to the output terminal of the SMPS, the switch is configured to close to bypass the transistor, and the LDO regulator is configured to be disabled.

[0080] Aspect 8: The IC of aspect 7, wherein to enter the sleep mode of the IC, the switch is configured to close after a delay.

[0081] Aspect 9: An IC according to Aspect 8, wherein in order to enter the sleep mode of the IC, the SMPS is configured to: boost the output voltage from the SMPS before the switch is configured to close; and enter a low power mode for the duration of the sleep mode after boosting the output voltage from the SMPS.

[0082] Aspect 10: The IC of aspect 6, wherein to exit a sleep mode of the IC, the switch is configured to be open and the LDO regulator is configured to be enabled.

[0083] Aspect 11: The IC of aspect 10, wherein to exit the sleep mode of the IC, the switch is configured to open after a delay.

[0084] Aspect 12: An IC according to Aspect 10 or 11, wherein to exit the sleep mode of the IC, the SMPS is configured to exit from a low power mode and enter a pulse frequency modulation (PFM) mode or a pulse width modulation (PWM) mode before the switch is configured to be disconnected.

[0085] Aspect 13: According to any one of Aspects 1 to 4, the IC further includes: a transistor having a source coupled to the first port and a drain coupled to the output of the LDO regulator; a second transistor having a source coupled to the first port and a drain coupled to the output of the LDO regulator; a first comparator having a first input coupled to a first reference voltage node and a second input coupled to the output of the LDO regulator; a first logic coupled between the output of the first comparator and the gate of the first transistor; a second comparator having a first input coupled to a second reference voltage node and a second input coupled to the output of the LDO regulator, wherein the first reference voltage node is configured to have a higher voltage than the second reference voltage node; and a second logic coupled between the output of the second comparator and the gate of the second transistor.

[0086] Aspect 14: An IC according to Aspect 13, wherein the first logic includes: a logic "AND" gate, the logic "AND" gate having a first input terminal coupled to the output terminal of the first comparator and a second input terminal coupled to an enable node; and a pulse generator, the pulse generator having an input terminal coupled to the output terminal of the logic "AND" gate and an output terminal coupled to the gate of the first transistor.

[0087] Aspect 15: The IC of aspect 14, wherein the pulse generator is configured to output pulses having a programmable pulse width.

[0088] Aspect 16: An IC according to any one of Aspects 13 to 15, wherein the second logic includes a logic "NAND" gate, the logic "NAND" gate having a first input terminal coupled to the output terminal of the second comparator, a second input terminal coupled to an enable node, and an output terminal coupled to the gate of the second transistor.

[0089] Aspect 17: The IC of any of Aspects 13 to 16, wherein the second transistor has a tunable transistor size.

[0090] Aspect 18: An IC according to any one of Aspects 13 to 17, wherein the IC also includes a capacitive element coupled to the output terminal of the LDO regulator, wherein during a sleep mode of the IC, if the SMPS is disabled and the voltage at the output terminal of the LDO regulator is: higher than a first reference voltage on the first reference voltage node, the LDO regulator is configured to be idle; lower than the first reference voltage but higher than a second reference voltage on the second reference voltage node, the first logic is configured to turn on the first transistor within a time interval to charge the capacitive element from the battery during the time interval and increase the voltage at the output terminal of the LDO regulator; or lower than the second reference voltage, the second logic is configured to turn on the second transistor to charge the capacitive element from the battery and increase the voltage at the output terminal of the LDO regulator.

[0091] Aspect 19: An IC according to aspect 18, wherein the IC is configured to: determine the length of a time period during which the LDO regulator is configured to be idle during the sleep mode of the IC; and adjust the length of the time interval based on the length of the time period.

[0092] Aspect 20: An IC according to Aspect 18 or 19, wherein the IC is configured to: count the number of falling edges or rising edges of a clock signal associated with the sleep mode of the IC when the LDO regulator is configured to be idle during the sleep mode of the IC; and adjust the length of the time interval based on the count of the falling edges or the rising edges of the clock signal.

[0093] Aspect 21: The IC of any one of aspects 1 to 20, wherein the second port is the same as the first port.

[0094] Aspect 22: A method of using, operating or forming an IC or a device according to any one of aspects 1 to 21.

[0095] Aspect 23: A method for managing power in an integrated circuit (IC) including a low dropout (LDO) regulator and a switch mode power supply (SMPS), the method comprising: during a cold start of the IC, coupling a power input terminal of the LDO regulator to a battery input terminal of the IC so that the LDO regulator is powered by the battery for the cold start; and after the cold start of the IC, coupling the power input terminal of the LDO regulator to an output terminal of the SMPS so that the LDO regulator is powered by the SMPS.

[0096] Aspect 24: According to the method of Aspect 23, the method also includes entering a sleep mode of the IC, wherein when the output voltage from the SMPS is available, entering the sleep mode includes: coupling the power input terminal of the LDO regulator to the output terminal of the SMPS; closing a switch to bypass the pass transistor of the LDO regulator; and disabling the LDO regulator.

[0097] Aspect 25: The method of aspect 24, wherein entering the sleep mode of the IC further comprises: boosting the output voltage from the SMPS before closing the switch; and after the boosting, causing the SMPS to enter a low power mode for a duration of the sleep mode.

[0098] Aspect 26: The method according to aspect 24 or 25, the method further comprising exiting the sleep mode of the IC, wherein exiting the sleep mode of the IC comprises: turning off the switch; and enabling the LDO regulator.

[0099] Aspect 27: The method according to Aspect 26, wherein exiting the sleep mode of the IC further comprises causing the SMPS to exit a low power mode and enter a pulse frequency modulation (PFM) mode or a pulse width modulation (PWM) mode before turning off the switch.

[0100] Aspect 28: A method according to any one of Aspects 23 to 27, wherein during a sleep mode of the IC, if the SMPS is disabled and the voltage at the output of the LDO regulator is: higher than a first reference voltage, the LDO regulator is configured to be idle; lower than the first reference voltage but higher than a second reference voltage, a capacitive element coupled to the output of the LDO regulator is charged from the battery during a time interval to increase the voltage at the output of the LDO regulator; or lower than the second reference voltage, the capacitive element is charged from the battery to increase the voltage at the output of the LDO regulator, wherein the second reference voltage is lower than the first reference voltage.

[0101] Aspect 29: The method according to Aspect 28, further comprising: determining the length of a time period during which the LDO regulator is configured to be idle during the sleep mode of the IC; and adjusting the length of the time interval based on the length of the time period.

[0102] Aspect 30: The method according to Aspect 28 or 29 further includes: when the LDO regulator is configured to be idle during the sleep mode of the IC, counting the number of falling edges or rising edges of the clock signal associated with the sleep mode of the IC; and adjusting the length of the time interval based on the count of the falling edges or the rising edges of the clock signal.

[0103] Additional considerations

[0104] The various operations of the above method can be performed by any suitable component capable of performing the corresponding function. The component may include various hardware and / or software components and / or modules, including but not limited to circuits, application specific integrated circuits (ASICs) or processors. Generally, where there are operations illustrated in the accompanying drawings, those operations may have corresponding corresponding components plus functional components with similar numbers.

[0105] As used herein, the term "determine" encompasses a wide variety of actions. For example, "determine" may include calculating, computing, processing, deriving, investigating, searching (e.g., searching in a table, a database, or another data structure), ascertaining, etc. In addition, "determine" may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), etc. In addition, "determine" may include resolving, selecting, choosing, establishing, etc.

[0106] As used herein, a phrase referring to "at least one of" a list of items refers to any combination of those items (including single members). For example, "at least one of a, b, or c" is intended to cover: a, b, c, ab, ac, bc, and abc, as well as any combination with multiple of the same elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc or any other ordering of a, b, and c).

[0107] The methods disclosed herein include one or more steps or actions for implementing the described methods. The steps and / or actions of the methods may be interchangeable with each other without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and / or use of specific steps and / or actions may be modified without departing from the scope of the claims.

[0108] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. An integrated circuit (IC) for power management, the IC comprising: a first port for coupling to a battery; Second port; a switch mode power supply (SMPS) comprising a power input coupled to the second port; and A low dropout (LDO) regulator includes a power supply input selectively coupled to the first port or an output of the SMPS.

2. The IC of claim 1 , further comprising a switch comprising a first terminal coupled to the first port, a second terminal coupled to the output of the SMPS, and a third terminal coupled to the power input of the LDO regulator, wherein the switch is configured to selectively couple the first terminal or the second terminal to the third terminal.

3. The IC of claim 2, wherein during a cold start of the IC, the switch is configured to couple the first terminal to the third terminal such that the LDO regulator is configured to be powered by the battery. 4 . The IC of claim 3 , wherein during the cold start of the IC, the SMPS is configured to be enabled after the LDO regulator is enabled. 5 . The IC of claim 3 , wherein after the cold start of the IC, the switch is configured to couple the second terminal to the third terminal such that the LDO regulator is configured to be powered by the SMPS.

6. The IC of claim 1 , wherein the LDO regulator comprises: transistor; and A switch includes a first terminal coupled to the source of the transistor and a second terminal coupled to the drain of the transistor.

7. The IC of claim 6, wherein to enter a sleep mode of the IC, when an output voltage from the SMPS is available, the power input of the LDO regulator is coupled to the output of the SMPS, the switch is configured to close to bypass the transistor, and the LDO regulator is configured to be disabled.

8. The IC of claim 7, wherein to enter the sleep mode of the IC, the switch is configured to close after a delay.

9. The IC of claim 8, wherein to enter the sleep mode of the IC, the SMPS is configured to: before the switch is configured to close, boosting the output voltage from the SMPS; and After boosting the output voltage from the SMPS, a low power mode is entered for the duration of the sleep mode.

10. The IC of claim 6, wherein to exit a sleep mode of the IC, the switch is configured to be open and the LDO regulator is configured to be enabled.

11. The IC of claim 10, wherein to exit the sleep mode of the IC, the switch is configured to open after a delay.

12. The IC of claim 10, wherein to exit the sleep mode of the IC, the SMPS is configured to exit from a low power mode and enter a pulse frequency modulation (PFM) mode or a pulse width modulation (PWM) mode before the switch is configured to open.

13. The IC of claim 1, further comprising: a first transistor having a source coupled to the first port and having a drain coupled to an output of the LDO regulator; a second transistor having a source coupled to the first port and having a drain coupled to the output of the LDO regulator; a first comparator having a first input coupled to a first reference voltage node and having a second input coupled to the output of the LDO regulator; a first logic coupled between an output of the first comparator and a gate of the first transistor; a second comparator having a first input coupled to a second reference voltage node and having a second input coupled to the output of the LDO regulator, wherein the first reference voltage node is configured to have a higher voltage than the second reference voltage node; and A second logic is coupled between an output of the second comparator and a gate of the second transistor.

14. The IC of claim 13, wherein the first logic comprises: a logic AND gate having a first input coupled to the output of the first comparator and a second input coupled to an enable node; and A pulse generator having an input coupled to the output of the logic AND gate and an output coupled to the gate of the first transistor.

15. The IC of claim 14, wherein the pulse generator is configured to output pulses having a programmable pulse width.

16. The IC of claim 13, wherein the second logic comprises a logic NAND gate having a first input coupled to the output of the second comparator, having a second input coupled to an enable node, and having an output coupled to the gate of the second transistor.

17. The IC of claim 13, wherein the second transistor has a tunable transistor size.

18. The IC of claim 13, further comprising a capacitive element coupled to the output of the LDO regulator, wherein during a sleep mode of the IC, if the SMPS is disabled and the voltage at the output of the LDO regulator is: is higher than a first reference voltage on the first reference voltage node, the LDO regulator is configured to be idle; is lower than the first reference voltage but higher than a second reference voltage on the second reference voltage node, the first logic is configured to turn on the first transistor for a time interval to charge the capacitive element from the battery during the time interval and increase the voltage at the output terminal of the LDO regulator; or is lower than the second reference voltage, the second logic is configured to turn on the second transistor to charge the capacitive element from the battery and increase the voltage at the output terminal of the LDO regulator.

19. The IC of claim 18, wherein the IC is configured to: determining a length of a period of time that the LDO regulator is configured to be idle during the sleep mode of the IC; and A length of the time interval is adjusted based on the length of the time period.

20. The IC of claim 18, wherein the IC is configured to: When the LDO regulator is configured to idle during the sleep mode of the IC, counting a number of falling edges or rising edges of a clock signal associated with the sleep mode of the IC; and The length of the time interval is adjusted based on the count of the falling edges or the rising edges of the clock signal.

21. The IC of claim 1, wherein the second port is the same as the first port.

22. A method for managing power in an integrated circuit (IC) including a low dropout (LDO) regulator and a switch mode power supply (SMPS), the method comprising: During a cold start of the IC, coupling a power input of the LDO regulator to a battery input of the IC so that the LDO regulator is powered by the battery for the cold start; as well as After the cold start of the IC, the power input of the LDO regulator is coupled to the output of the SMPS so that the LDO regulator is powered by the SMPS.

23. The method of claim 22, further comprising entering a sleep mode of the IC, wherein when the output voltage from the SMPS is available, entering the sleep mode comprises: coupling the power input of the LDO regulator to the output of the SMPS; closing a switch to bypass a pass transistor of the LDO regulator; as well as Disable the LDO regulator.

24. The method of claim 23, wherein entering the sleep mode of the IC further comprises: boosting the output voltage from the SMPS before closing the switch; as well as After the boosting, the SMPS is caused to enter a low power mode for a duration of the sleep mode.

25. The method of claim 23, further comprising exiting the sleep mode of the IC, wherein exiting the sleep mode of the IC comprises: disconnecting the switch; as well as Enable the LDO regulator.

26. The method of claim 25, wherein exiting the sleep mode of the IC further comprises causing the SMPS to exit a low power mode and enter a pulse frequency modulation (PFM) mode or a pulse width modulation (PWM) mode before opening the switch.

27. The method of claim 22, wherein during a sleep mode of the IC, if the SMPS is disabled and the voltage at the output of the LDO regulator is: is higher than the first reference voltage, the LDO regulator is configured to be idle; is lower than the first reference voltage but higher than a second reference voltage, charging a capacitive element coupled to the output terminal of the LDO regulator from the battery during a time interval to increase the voltage at the output terminal of the LDO regulator; or If the second reference voltage is lower than the second reference voltage, the capacitive element is charged from the battery to increase the voltage at the output terminal of the LDO regulator, wherein the second reference voltage is lower than the first reference voltage.

28. The method according to claim 27, further comprising: determining a length of a period of time that the LDO regulator is configured to be idle during the sleep mode of the IC; as well as A length of the time interval is adjusted based on the length of the time period.

29. The method according to claim 27, further comprising: when the LDO regulator is configured to be idle during the sleep mode of the IC, counting a number of falling edges or rising edges of a clock signal associated with the sleep mode of the IC; as well as The length of the time interval is adjusted based on the count of the falling edges or the rising edges of the clock signal.

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