SMD (Surface Mount Device) ceramic electronic component suitable for low-voltage power grid voltage and manufacturing method

Abstract

The invention discloses a surface-mounted ceramic electronic component suitable for low-voltage power grid voltage and a manufacturing method. The surface-mounted ceramic electronic component comprises N surface-mounted electronic ceramic chips, a conductive connecting assembly and an insulating wrapping layer, wherein N is greater than or equal to 1; the N surface-mounted electronic ceramic chips are mutually stacked to form a laminated surface-mounted component; each surface-mounted electronic ceramic chip comprises a ceramic body, a first electrode and a second electrode; the first side surface and the second side surface are arranged between the upper end surface and the lower end surface, the first electrode covers part of the upper end surface and at least part of the first side surface, and the second electrode covers part of the lower end surface and at least part of the second side surface; the conductive connection assembly is connected with the side electrodes of the N surface-mounted electronic ceramic chips, and the N surface-mounted electronic ceramic chips are connected in parallel and fixed in position. And packaging by using an insulating material, and only exposing the end of the connecting electrode, and bending and forming to serve as the end electrode of the surface-mounted ceramic electronic component.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic ceramic components including varistors, and in particular to a patch-type ceramic electronic component suitable for low-voltage power grid voltage and a manufacturing method thereof. Background Art

[0002] Low-voltage power grid refers to the power supply line for short-distance transmission and direct connection to electrical appliances. For AC power, the transmission line with a voltage lower than 1000V is called low-voltage power grid. The most commonly used low-voltage power grid voltages are 110V, 220V and 380V.

[0003] In the current electronic manufacturing industry, the surface mount technology (SMT) using patch components has become the mainstream production process, occupying 80% to 90% of the market share of printed circuit board (PCB) processing. However, in a few fields such as power modules, some components have slowed down their patch structure due to their electrical characteristics, and they are mainly processed by traditional lead insertion welding. Varistors are one of them. In low-voltage power grids, high-energy surges caused by lightning induction or heavy-load equipment operation often occur. Due to instantaneous overcurrent, varistors need to withstand large surge current impacts. The varistor's current tolerance capacity is proportional to the electrode end surface area. The large-area varistor patch structure has great technical difficulties.

[0004] At present, there are multilayer varistors that have realized the chip structure. They are mainly embodied in a chip multilayer varistor with the same structure and process as the multilayer ceramic capacitor (MLCC). The varistor ceramic green film layer is generated by the casting process, with a typical thickness of several microns, and then the electrode is printed on it, and then the film layer is cast. After repeated stacking, the blocks are cut and dried, and then sintered together at high temperature. During the sintering process, the organic additives in the ceramic blank and the electrode slurry are vaporized and volatilized, and the low-melting-point inorganic components (glass phase) are melted and bonded into a whole, also known as a "monolithic" structure, to form the main body of the multilayer chip varistor. Since the ceramic green film layer generated by the casting process cannot be too thick, the operating voltage of this multilayer chip varistor will not be very high, and it is difficult to exceed 50 volts. And because it has been sintered to form a whole, the ability to withstand the thermal shock stress caused by the surge is insufficient, which affects the surge shock tolerance of the component and can only absorb a few joules to a few joules of surge energy. It is widely used in the external jacks of battery-powered mobile electronic devices such as laptops and mobile phones to absorb electrostatic induction surges with relatively small surge energy and operational overvoltage surges caused by hot plugging.

[0005] It can be seen from this that the chip-type multilayer ceramic electronic components produced by the casting method cannot be used in low-voltage power grid voltages, such as AC 220V, because the ceramic green film layer cannot be made thicker, the operating voltage is low, and the energy tolerance is too low.

[0006] At present, there are single-layer varistors with SMD structures and single-layer medium and high voltage capacitors with similar manufacturing processes. For example: the rectangular strip varistor device disclosed in the Chinese patent application number 2013203516840; it is first made into a rectangular porcelain body (ceramic body) of the varistor, and then metal electrodes are coated on the two end faces, and a thin copper strip is welded to the metal end face electrodes, and then the ceramic body coated with electrodes is insulated and packaged with resin, and the exposed lead copper strip is shaped to form a lead terminal, which is convenient for surface mounting welding. Since the porcelain body of the SMD varistor with this structure can be made thicker, a product that can be used in low-voltage power grid voltages - for example, AC 220V voltage can be obtained. However, considering the high working voltage and the need to withstand the instantaneous pulses of high voltage and high current caused by strong surges such as lightning surges, the bending and forming of the lead-out copper strip at the end part must fully consider sufficient insulation space to ensure that there is no short circuit and no high-voltage arc discharge breakdown when discharging surges. This leads to the disadvantages of complex structure of the end lead-out part, excessive space occupation, and the inability to stack ceramic pieces in parallel. Since the end face electrode area of ​​the single-layer porcelain body is limited and the allowable flow rate is too small, if the flow rate needs to be increased, the end face electrode area needs to be increased, thereby increasing the length and width of the component, which is inconsistent with the requirements of small size and high performance of modern electronic technology. Therefore, the current single-layer SMD varistor has been greatly limited in its application range in the field of low-voltage power grid voltage. In the field of low-voltage power grid voltage applications, traditional lead plug-in welding products are still the mainstream. Summary of the invention

[0007] The purpose of the present invention is to overcome the problems that the existing multilayer chip varistor / capacitor ceramic green body film layer cannot be made thicker, the working voltage is low, and the energy tolerance is low; the existing single-layer chip varistor / capacitor electrical parameter capacity is too small and cannot be applied to low-voltage grid voltage application scenarios, and provide a chip-type ceramic electronic component and method suitable for low-voltage grid voltage. The stacked chip-type ceramic electronic component provided by the present invention includes a plurality of single-piece formed chip-type electronic ceramic chips, and a plurality of chip-type electronic ceramic chips are stacked on each other and fixed in parallel and then packaged to form a stacked chip-type ceramic electronic component. In actual use environments, varistors and capacitors may be used in parallel at the same time. The stacked chip-type ceramic electronic component provided by the present invention can combine varistors and capacitors into an integrated component, effectively reducing the number of plug-ins and costs.

[0008] In order to achieve the above-mentioned object of the invention, the present invention provides the following technical solutions:

[0009] A surface-mount ceramic electronic component suitable for low-voltage power grid voltage, characterized by comprising:

[0010] N surface-mount electronic ceramic chips, conductive connection components and insulating encapsulation layers; wherein N ≥ 1;

[0011] N said patch-type electronic ceramic chips are stacked on each other to form a laminated patch assembly, said laminated patch assembly is fixedly connected to a conductive connection assembly, and said insulating encapsulation layer is used to encapsulate the fixedly connected assembly;

[0012] The surface mount electronic ceramic chip comprises: a ceramic body and an electrode group, wherein the electrode group is arranged on the outer surface of the ceramic body, and the electrode group comprises: a first electrode and a second electrode; the ceramic body has an upper and lower end surface and a side surface between the upper and lower end surfaces, wherein the side surface comprises at least a first side surface and a second side surface, and the first electrode covers a portion of the upper end surface and at least a portion of the first side surface to form an end surface electrode portion and a side surface electrode portion of the first electrode; the second electrode covers a portion of the lower end surface and at least a portion of the second side surface to form an end surface electrode portion and a side surface electrode portion of the second electrode;

[0013] The overlapping surface of the laminated patch component is the end surface of the patch-type electronic ceramic chip, and the patch-type electronic ceramic chip is stacked and arranged according to the symmetrical relationship between the end surface electrodes adjacent to the overlapping surface; the laminated patch component includes: a third electrode and a fourth electrode, the third electrode is jointly formed by the N side electrodes on the same side of the stacked N patch-type electronic ceramic chips, and the fourth electrode is jointly formed by the N side electrodes on the other side of the stacked N patch-type electronic ceramic chips; the conductive connection component is connected to the third and fourth electrodes to realize parallel connection of the N patch-type electronic ceramic chips and fix the positions of the N patch-type electronic ceramic chips;

[0014] The insulating encapsulation layer is used to encapsulate the laminated patch assembly and part of the conductive connection assembly, and the remaining unencapsulated part of the conductive connection assembly is the terminal electrode.

[0015] According to a specific implementation, in the above-mentioned SMD ceramic electronic component applicable to low-voltage grid voltage, the conductive connection component includes: a first lead-out electrode and a second lead-out electrode;

[0016] The first lead electrode is welded to the third electrode of the stacked patch assembly, and the second lead electrode is welded to the fourth electrode of the stacked patch assembly;

[0017] The insulating encapsulating material encapsulates the stacked patch assembly after the lead electrodes are welded, and the first lead electrode and the second lead electrode are respectively extended out of a portion of the insulating encapsulating layer to form terminal electrodes.

[0018] According to a specific embodiment, in the above-mentioned chip-type ceramic electronic component suitable for low-voltage grid voltage, the first lead electrode and the second lead electrode are sheet electrodes, which pass through the extension section of the insulating encapsulation layer and are bent tightly against the surface of the insulating encapsulation layer to serve as end electrodes of the chip-type ceramic electronic component.

[0019] It should be noted that the sheet-shaped lead-out electrode extension section that passes through the insulating encapsulation layer is already useful when it does not need to be bent and formed. Insert the electrode extension section directly into the welding socket of the printed circuit board, and then process and weld it in the traditional way. This installation method is more suitable for certain occasions where the component size is oversized and the weight is overweight due to the super-large electrical parameter capacity. It can be connected more firmly and has stronger vibration resistance. At this point, except that it cannot be classified as a surface-mount component, it already has all the other technical features of the present invention. Compared with the use of N independent lead-inserted components in parallel, it has the advantages of occupying a smaller installation area and lower cost due to the shared lead-out electrode and insulating encapsulation layer.

[0020] According to a specific embodiment, in the above-mentioned patch-type ceramic electronic component suitable for low-voltage grid voltage, the conductive connection component is in the shape of a cap, and the third and fourth electrode ends of the laminated patch component are respectively inserted into the bottom of the cap of the conductive connection component and welded to the conductive connection component; a gap is left between the inner surface of the raised edge of the cap-shaped conductive connection component and the periphery of the laminated patch component;

[0021] The laminated chip assembly to which the conductive connection component is welded is encapsulated with an insulating encapsulating material. The encapsulating material should fill the gap and completely wrap the remaining surface of the laminated chip assembly, leaving only the outer surface of the cap-shaped conductive connection component exposed as the terminal electrode of the patch-type ceramic electronic component.

[0022] This method makes the bottom of the cap also serve as part of the encapsulation layer, which can shorten the length of the patch-type ceramic electronic components without affecting the size of the built-in laminated patch components. Filling the gap with insulating encapsulation material is to avoid the raised edge of the cap-shaped conductive connection component from contacting and short-circuiting the built-in laminated patch component, and to ensure sufficient insulation withstand voltage strength. The gap width must be greater than 0.3mm. In this way, only the bottom inner surface of the cap-shaped conductive connection component is welded to the third and fourth electrodes of the laminated patch component, and the raised outer surface of the cap edge represents the welding of the terminal electrode to the copper foil solder joint of the printed circuit board. The raised outer surface can increase the welding area with the circuit board and improve welding reliability.

[0023] According to a specific implementation, in the above-mentioned surface-mount ceramic electronic component suitable for low-voltage power grid voltage, the first electrode and the second electrode of the electrode group of the surface-mount electronic ceramic chip are formed at one time by a sputtering process, the thickness of the first electrode and the second electrode are uniform, the electrode thickness is in the range of 2um to 15um, and the nominal thickness error rate does not exceed a preset value, and the preset value range is [-15%, 15%]; the end surface electrode edge of the first electrode is at a distance d from the second side surface, and the end surface electrode edge of the second electrode is also at a distance d from the first side surface.

[0024] The electrodes manufactured by the sputtering process have the advantages of no oxidation, high material purity, compact structure, uniform thickness, strong adhesion, and high conductivity. By setting the deposition direction of the electrode particles and the placement angle of the ceramic workpiece, the end face and side face of the electrode can be processed at one time. The conductive connection component only needs to be connected to the side face of the electrode and does not need to extend to the end face. It will not reduce the electrical performance of the electronic component and can realize the function of the electronic component without attenuation. Connecting only the conductive connection component to the side face of the electrode is a necessary condition for implementing the scheme of the present invention, connecting N SMD electronic ceramic chips in parallel, and fixing the positions of the N SMD electronic ceramic chips.

[0025] Setting the partition d between the electrodes at the edge of the end face of the ceramic body can maximize the effective end face electrode area, thereby maximizing the electrical parameter value of the monolithic surface-mount electronic ceramic chip.

[0026] According to a specific implementation, in the above-mentioned SMD ceramic electronic component suitable for low-voltage grid voltage, the stacked SMD assembly is composed of N SMD electronic ceramic chips with the same function. The SMD electronic ceramic chips with the same function can be varistor chips; the SMD electronic ceramic chips with the same function can also be capacitor chips.

[0027] The operating voltage of electronic components suitable for low-voltage power grid voltage is several hundred volts. At this time, the thickness of varistor chips / capacitor chips is at the millimeter level. The ceramic green film layer manufactured by the tape casting method cannot reach this thickness. Therefore, multi-layer electronic components manufactured by the tape casting method cannot be used in the field of low-voltage power grid voltage. However, the use of traditional pressing and sintering ceramic processes can easily achieve millimeter-level ceramic chips. In addition, after N chips with the same function are overlapped and connected in parallel, the electrical parameters are doubled compared to single-layer SMD components, expanding the application range of SMD components in the field of low-voltage power grid voltage.

[0028] According to a specific implementation, in the above-mentioned SMD ceramic electronic component suitable for low-voltage grid voltage, the N SMD electronic ceramic chips of the stacked SMD assembly include at least two SMD electronic ceramic chips with different functions. The SMD electronic ceramic chips with different functions may include both varistor chips and capacitor chips.

[0029] In some applications, it is necessary to use two or more electronic components with different functions in parallel, such as connecting a varistor and a capacitor in parallel. The present invention can achieve this purpose by simply selecting patch-type electronic ceramic chips with different functions to overlap and connect them in parallel. The length of the selected chips must be consistent so that they can be welded in parallel with the conductive connection components after overlapping and aligning, and the position is fixed. The width is best kept consistent, and the thickness can be inconsistent, as long as the respective performance requirements are met. In this way, one component can be equivalent to two independent components in parallel. However, due to the shared conductive connection electrode and the insulating encapsulation layer, the implementation product of the present invention has a smaller installation footprint and lower manufacturing cost.

[0030] According to a specific implementation, in the above-mentioned SMD ceramic electronic component suitable for low-voltage grid voltage, gaps are left on the overlapping surfaces of the N SMD electronic ceramic chips of the stacked SMD assembly.

[0031] The gap can be formed naturally by utilizing the unevenness of the chip end faces when stacking the SMD electronic ceramic chips, or can be formed by positioning with a special fixture when assembling and welding the stacked chip components, or can be formed by coating the chip end faces with soft insulating materials such as paraffin wax, silicone rubber, etc. and then overlapping. The gap width is preferably less than 0.1mm, so that when the surge absorption components such as varistor chips are subjected to surge impact and heat and expand in size, the overlapping chips will not squeeze each other to generate stress, so as not to reduce the component's surge impact resistance performance and the component's service life.

[0032] Another aspect of the present invention provides a method for manufacturing the above-mentioned surface-mount ceramic electronic component suitable for low-voltage grid voltage, the method comprising:

[0033] Processing N of the surface-mount electronic ceramic chips, and stacking the N surface-mount electronic ceramic chips on each other to form a laminated surface-mount component;

[0034] Welding the laminated patch assembly and the conductive connection assembly together;

[0035] Encapsulating the welded components with insulating encapsulation materials;

[0036] The reserved electrode material extending out of the insulating encapsulation layer is formed into a terminal electrode of a surface-mount ceramic electronic component.

[0037] Compared with the prior art, the present invention has the following beneficial effects:

[0038] 1. The laminated SMD ceramic electronic component provided in the embodiment of the present invention comprises N SMD electronic ceramic chips, wherein all the SMD electronic ceramic chips are connected in parallel, which can improve the electrical parameters by several times compared with the single-layer SMD ceramic electronic component; since the individually manufactured SMD electronic ceramic chips can be easily made into ceramic pieces with a thickness of millimeters, which is several orders of magnitude thicker than the ceramic green film layer of the tape casting method, the operating voltage can be increased to several hundred volts; and no connection measures are taken on the overlapping surfaces of the overlapping SMD electronic ceramic chips, when the temperature of the ceramic pieces rises sharply due to the impact of a surge, causing the ceramic body to expand, each ceramic piece has space for expansion, thereby eliminating the harmful stress caused by the extrusion of the ceramic body, and will not lead to the disadvantages of reduced surge tolerance and shortened component life. This feature is very important for surge absorption components such as varistors.

[0039] 2. The energy tolerance of the multilayer chip varistor using the technical solution can reach hundreds of joules; therefore, the multilayer chip ceramic electronic component provided by the embodiment of the present invention is very suitable for replacing traditional lead-inserted components and is used in the field of low-voltage power grid voltage.

[0040] 3. The production of electronic ceramic chips is standard parts production. Based on the laminated SMD ceramic electronic components provided by the present invention, standard parts can be selected for flexible combination and stacking during production to form electronic components with specified parameters, thereby reducing processing costs.

[0041] 4. In addition, the present invention also provides a solution for connecting SMD electronic ceramic chips with different functions in parallel to form a stacked SMD ceramic electronic component, which is equivalent to connecting two or more independent components with different functions in parallel, but has more advantages in reducing the installation area and reducing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A schematic diagram of a stacked structure of surface mount ceramic electronic chips according to an exemplary embodiment of the present invention;

[0043] Figure 2 A first structural schematic diagram of a surface-mount electronic ceramic chip according to an exemplary embodiment of the present invention;

[0044] Figure 3 A first structural schematic diagram of a surface-mount ceramic electronic chip connected to a sheet-shaped conductive connection component according to an exemplary embodiment of the present invention;

[0045] Figure 4 A schematic diagram of the structure of the connection between the surface-mount ceramic electronic chip and the lead-out electrode according to an exemplary embodiment of the present invention;

[0046] Figure 5 The insulation encapsulation layer of the exemplary embodiment of the present invention is Figure 3 , Figure 4 A schematic diagram of the structure of packaging the components shown;

[0047] Figure 6 It is a schematic structural diagram of a cap-shaped conductive connection component according to an exemplary embodiment of the present invention;

[0048] Figure 7 The insulation encapsulation layer of the exemplary embodiment of the present invention is Figure 6 A schematic diagram of the structure of connecting and packaging the components shown;

[0049] Figure 8 A schematic diagram of a top view of a surface-mount ceramic electronic chip according to an exemplary embodiment of the present invention;

[0050] Fig. 9 A second structural schematic diagram of a surface-mount ceramic electronic chip according to an exemplary embodiment of the present invention;

[0051] Fig.10 It is a schematic structural diagram of a deposited electrode metal material according to an exemplary embodiment of the present invention;

[0052] Figure numerals: 100 - SMD electronic ceramic chip, 101 - first electrode, 102 - second electrode; 103 - ceramic body, 105 - partition, 200 - conductive connection component, 201 - first lead electrode, 202 - second lead electrode, 203 - terminal electrode, 300 - insulating encapsulation layer, 400 - laminated SMD component. DETAILED DESCRIPTION

[0053] The present invention is further described in detail below in conjunction with test examples and specific implementation methods. However, this should not be understood as the scope of the above subject matter of the present invention being limited to the following embodiments, and all technologies realized based on the content of the present invention belong to the scope of the present invention.

[0054] Example 1

[0055] A surface-mount ceramic electronic component suitable for low-voltage grid voltage, characterized in that it comprises: N surface-mount electronic ceramic chips 100, a conductive connection component 200 and an insulating encapsulation layer 300; wherein N≥1;

[0056] like Figure 1 As shown, three (N=3) surface mount electronic ceramic chips 100 are stacked on top of each other to form a stacked surface mount component 400 .

[0057] like Figure 2As shown, the surface mount electronic ceramic chip 100 includes: a ceramic body 103 and an electrode group, the ceramic body 103 is rectangular, the electrode group is arranged on the outer surface of the ceramic body, and the electrode group includes: a first electrode 101 and a second electrode 102; the ceramic body 103 has an upper and lower end surface and a side surface between the upper and lower end surfaces, the side surface at least includes a first side surface and a second side surface, the first electrode 101 covers part of the upper end surface and at least part of the first side surface, forming the end surface electrode part and the side surface electrode part of the first electrode 101. The second electrode 102 covers part of the lower end surface and at least part of the second side surface, forming the end surface electrode part and the side surface electrode part of the second electrode 102.

[0058] like Figure 1 As shown, the overlapping surface of the laminated patch assembly is the end surface of the patch-type electronic ceramic chip 100, and the patch-type electronic ceramic chip 100 is stacked and arranged according to the symmetrical relationship between the end surface electrodes adjacent to the overlapping surface. The third electrode of the laminated patch assembly is jointly formed by the side electrodes on the same side of the stacked three patch-type electronic ceramic chips 100, and the fourth electrode of the laminated patch assembly is jointly formed by the side electrodes on the other side of the stacked three patch-type electronic ceramic chips 100.

[0059] The three SMD electronic ceramic chips 100 that make up the stacked SMD assembly can all be varistor chips, or all be capacitor chips, or have both varistor chips and capacitor chips. The lengths of the chips must be consistent so that they can be overlapped and aligned and welded in parallel with the conductive connection components to fix their positions. It is best to keep the width consistent, and the thickness can be different as long as the respective electrical performance requirements are met. Depending on the different voltages of the low-voltage power grid in the application scenario, the single-chip thickness of the SMD electronic ceramic chip 100 is between 0.5mm and 5mm.

[0060] like Figure 3 , Figure 4 As shown, the conductive connection component 200 is connected to the third and fourth electrodes of the laminated patch component. The conductive connection component includes: a first lead electrode 201 and a second lead electrode 202. The first lead electrode 201 is welded to the third electrode of the laminated patch component 400, and the second lead electrode 202 is welded to the fourth electrode of the laminated patch component 400, and the three patch-type electronic ceramic chips 100 are connected in parallel and the positions of the three patch-type electronic ceramic chips 100 are fixed. A gap is left on the overlapping surface of the fixed chip, and the gap is naturally formed by utilizing the unevenness of the chip end surface when the patch-type electronic ceramic chips 100 are stacked.

[0061] The laminated patch assembly after welding the sheet-shaped lead electrodes is encapsulated with a hot injection insulating material to form an insulating encapsulation layer 300 , and the first lead electrode 201 and the second lead electrode 202 are respectively extended out of the insulating encapsulation layer for a section to make the terminal electrode 203 .

[0062] like Figure 5 As shown, the extension section of the first lead electrode 201 passing through the insulating encapsulation layer and the extension section of the second lead electrode 202 passing through the insulating encapsulation layer 300 are bent and formed close to the outer surface of the insulating encapsulation layer to serve as the terminal electrodes of the surface-mount ceramic electronic component. The sheet-shaped lead electrodes 201 and 202 are made of copper metal, and can also be made of other conductive metals or alloys that are easy to weld.

[0063] Example 2

[0064] A surface-mount ceramic electronic component suitable for low-voltage grid voltage, characterized in that it comprises: N surface-mount electronic ceramic chips 100, a conductive connection component 200 and an insulating encapsulation layer 300; wherein N≥1;

[0065] like Figure 1 As shown, three (N=3) surface mount electronic ceramic chips 100 are stacked on top of each other to form a stacked surface mount component.

[0066] like Figure 2 As shown, the surface mount electronic ceramic chip 100 includes: a ceramic body 103 and an electrode group, the ceramic body 103 is rectangular, the electrode group is arranged on the outer surface of the ceramic body, and the electrode group includes: a first electrode 101 and a second electrode 102; the ceramic body 103 has an upper and lower end surface and a side surface between the upper and lower end surfaces, the side surface at least includes a first side surface and a second side surface, the first electrode 101 covers part of the upper end surface and at least part of the first side surface, forming the end surface electrode part and the side surface electrode part of the first electrode 101. The second electrode 102 covers part of the lower end surface and at least part of the second side surface, forming the end surface electrode part and the side surface electrode part of the second electrode 102.

[0067] like Figure 1 As shown, the overlapping surface of the laminated patch assembly is the end surface of the patch-type electronic ceramic chip 100, and the patch-type electronic ceramic chip 100 is stacked and arranged according to the symmetrical relationship between the end surface electrodes adjacent to the overlapping surface. The third electrode of the laminated patch assembly is jointly formed by the side electrodes on the same side of the stacked three patch-type electronic ceramic chips 100, and the fourth electrode of the laminated patch assembly is jointly formed by the side electrodes on the other side of the stacked three patch-type electronic ceramic chips 100.

[0068] The three SMD electronic ceramic chips 100 that make up the stacked SMD assembly can all be varistor chips, or all be capacitor chips, or have both varistor chips and capacitor chips. The lengths of the chips must be consistent so that they can be overlapped and aligned and welded in parallel with the conductive connection components to fix their positions. It is best to keep the width consistent, and the thickness can be different as long as the respective electrical performance requirements are met. Depending on the different voltages of the low-voltage power grid in the application scenario, the single-chip thickness of the SMD electronic ceramic chip 100 is between 0.5mm and 5mm.

[0069] The conductive connection component is connected to the third and fourth electrodes of the laminate patch component. Figure 6 The cap shape is shown, which is made by stamping thin copper sheets, and can also be made of other conductive metals or alloys that are easy to weld. In this embodiment, the cap thickness is 0.3mm. The third and fourth electrode ends of the laminated patch component 400 are respectively inserted into the bottom of the cap of the conductive connection component, and are welded and connected to the conductive connection component to connect three patch-type electronic ceramic chips 100 in parallel and fix the positions of the three patch-type electronic ceramic chips 100. A gap is left on the overlapping surface of the fixed chip, and the gap is naturally formed by utilizing the unevenness of the chip end surface when the patch-type electronic ceramic chips 100 are stacked. A gap is left between the inner surface of the raised edge of the cap-shaped conductive connection component and the periphery of the laminated patch component. In this embodiment, the gap width is 0.7mm.

[0070] like Figure 7 As shown, the laminated chip assembly to which the conductive connection assembly is welded is encapsulated using a hot injection molding insulating material, the hot-melt liquid encapsulation material fills the gap and completely wraps the remaining surface of the laminated chip assembly, leaving only the outer surface of the cap-shaped conductive connection assembly exposed as the terminal electrode of the patch-type ceramic electronic component.

[0071] This method makes the bottom of the cap also serve as part of the encapsulation layer, which can shorten the length of the patch-type ceramic electronic components without affecting the size of the built-in laminated patch components. Filling the gap with insulating encapsulation material is to avoid the raised edge of the cap-shaped conductive connection component from contacting and short-circuiting with the built-in laminated patch component, and to ensure sufficient insulation withstand voltage strength. In this way, only the bottom inner surface of the cap-shaped conductive connection component is welded to the third and fourth electrodes of the laminated patch component, and the raised outer surface of the cap edge represents the welding of the terminal electrode to the copper foil solder joint of the printed circuit board. The raised outer surface can increase the welding area with the circuit board and improve welding reliability.

[0072] Example 3

[0073] like Figure 8 , Fig. 9A surface mount electronic ceramic chip 100 shown includes: a ceramic body 103 and an electrode group, the ceramic body 103 is rectangular; the electrode group is arranged on the outer surface of the ceramic body, and the electrode group includes: a first electrode 101 and a second electrode 102; the ceramic body 103 has upper and lower end faces and side faces between the upper and lower end faces, the side faces at least include a first side face and a second side face, the first electrode 101 covers part of the upper end face and at least part of the first side face, forming the end face electrode part and the side face electrode part of the first electrode 101. The second electrode 102 covers part of the lower end face and at least part of the second side face, forming the end face electrode part and the side face electrode part of the second electrode 102;

[0074] The first electrode and the second electrode of the surface-mount electronic ceramic chip 100 are formed by one-time sputtering process, and the sputtering target material is copper metal, and other metals or alloys that are easy to weld can also be selected. The thickness of the first electrode 101 and the second electrode 102 is uniform, and the electrode thickness is in the range of 2 microns to 15 microns. The nominal thickness error rate does not exceed the preset value, and the preset value range is [-15%, 15%]; the end surface electrode edge of the first electrode 101 is separated from the second side surface by a gap 105 (length d), and the end surface electrode edge of the second electrode 102 is also separated from the first side surface by a distance d.

[0075] The electrodes manufactured by sputtering process have the advantages of no oxidation, high material purity, compact structure, uniform thickness, strong adhesion and high conductivity. By setting the electrode atom deposition direction and the placement angle of the ceramic workpiece, such as Fig.10 As shown, the end face and side face of the electrode can be processed at one time. At the corners of the end face and side face of the ceramic body, the chamfering can be smoothed to make the electrode thickness at the corner more uniform. The conductive connection component only needs to be connected to the side face of the electrode, and does not need to extend to the end face, and will not reduce the electrical performance of the electronic component, so the function of the electronic component can be realized without attenuation. Connecting only the conductive connection component to the side face of the electrode is a necessary condition for implementing the scheme of the present invention, connecting N SMD electronic ceramic chips 100 in parallel, and fixing the positions of the N SMD electronic ceramic chips 100.

[0076] Setting the partition d between the electrodes at the edge of the end surface of the ceramic body can maximize the effective end surface electrode area, thereby maximizing the electrical parameter value of the single-chip surface-mount electronic ceramic chip 100.

[0077] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A chip-type ceramic electronic component suitable for low-voltage grid voltage, characterized in that: include: N surface-mount electronic ceramic chips (100), a conductive connection component (200) and an insulating encapsulation layer (300); wherein N≥1; N patch-type electronic ceramic chips (100) are stacked on top of each other to form a laminated patch assembly (400), the laminated patch assembly (400) is fixedly connected to a conductive connection assembly (200), and the insulating encapsulation layer (300) is used to encapsulate the fixedly connected assembly; The surface-mount electronic ceramic chip (100) comprises: a ceramic body and an electrode group, wherein the electrode group is arranged on the outer surface of the ceramic body, and the electrode group comprises: a first electrode (101) and a second electrode (102); the ceramic body (103) has an upper and lower end surface and a side surface between the upper and lower end surfaces, wherein the side surface comprises at least a first side surface and a second side surface, and the first electrode (101) covers a portion of the upper end surface and at least a portion of the first side surface, forming an end surface electrode portion and a side surface electrode portion of the first electrode; the second electrode (102) covers a portion of the lower end surface and at least a portion of the second side surface, forming an end surface electrode portion and a side surface electrode portion of the second electrode; The overlapping surface of the laminated patch component is the end surface of the patch-type electronic ceramic chip (100), and the patch-type electronic ceramic chips (100) are stacked and arranged according to the symmetrical relationship between the end surface electrodes adjacent to the overlapping surface; the laminated patch component comprises: a third electrode and a fourth electrode, the third electrode being jointly formed by N side electrodes on the same side of the stacked N patch-type electronic ceramic chips (100), and the fourth electrode being jointly formed by N side electrodes on the other side of the stacked N patch-type electronic ceramic chips (100); the conductive connection component (200) is connected to the third and fourth electrodes to realize parallel connection of the N patch-type electronic ceramic chips (100) and to fix the positions of the N patch-type electronic ceramic chips (100); The insulating encapsulating layer (300) is used to encapsulate the laminated patch assembly (400) and part of the conductive connection assembly (200), and the remaining unencapsulated part of the conductive connection assembly (200) is a terminal electrode.

2. The chip-type ceramic electronic component suitable for low-voltage grid voltage according to claim 1, characterized in that: The conductive connection assembly comprises: a first lead-out electrode (201) and a second lead-out electrode (202); The first lead electrode (201) is connected to the third electrode of the stacked patch assembly (400) by welding, and the second lead electrode (202) is connected to the fourth electrode of the stacked patch assembly (400) by welding; The insulating encapsulating layer (300) encapsulates the stacked patch assembly after the lead electrodes are welded, and the first lead electrode (201) and the second lead electrode (202) are respectively extended out of a portion of the insulating encapsulating layer (300) to form the terminal electrode (203).

3. The surface-mount ceramic electronic component suitable for low-voltage grid voltage according to claim 2, characterized in that: The first lead electrode (201) and the second lead electrode (202) are sheet electrodes, extending out of an extension section of the insulating encapsulating layer (300), being bent and shaped closely against a surface of the insulating encapsulating layer (300), and serving as terminal electrodes (203) of the surface-mount ceramic electronic component.

4. The surface-mount ceramic electronic component suitable for low-voltage grid voltage according to claim 1, characterized in that: The conductive connection component (200) is in the shape of a cap, and the third and fourth electrode ends of the laminated patch component (400) are respectively inserted into the bottom of the cap of the conductive connection component (200) and are welded to the conductive connection component; a gap is left between the inner surface of the raised edge of the cap-shaped conductive connection component and the periphery of the laminated patch component; The insulating encapsulation layer (300) encapsulates the laminated patch component (400) to which the conductive connection component (200) is welded, and the encapsulation material fills the gap and completely encapsulates the remaining surface of the laminated patch component (400), leaving only the outer surface of the cap-shaped conductive connection component exposed to the outside, serving as the terminal electrode (203) of the patch-type ceramic electronic component.

5. The chip-type ceramic electronic component suitable for low-voltage grid voltage according to claim 1, characterized in that: The electrode group includes the first electrode (101) and the second electrode (102) which are formed by one-step processing using a sputtering process; the thickness of the first electrode (101) and the second electrode (102) are uniform, the electrode thickness is within the range of 2um to 15um, and the nominal thickness error rate does not exceed a preset value, and the preset value range is [-15%, 15%]; A distance d is left between the end surface electrode edge of the first electrode (101) and the second side surface, and a distance d is also left between the end surface electrode edge of the second electrode (102) and the first side surface.

6. The surface-mount ceramic electronic component suitable for low-voltage grid voltage according to any one of claims 1 to 4, characterized in that: The laminated patch assembly (400) is composed of N patch-type electronic ceramic chips (100) having the same function.

7. The chip-type ceramic electronic component suitable for low-voltage grid voltage according to claim 6, characterized in that: The SMD electronic ceramic chip (100) having the same function is a varistor chip.

8. The surface-mount ceramic electronic component suitable for low-voltage grid voltage according to claim 6, characterized in that: The surface-mount electronic ceramic chip (100) having the same function is a capacitor chip.

9. The surface-mount ceramic electronic component suitable for low-voltage grid voltage according to any one of claims 1 to 4, characterized in that: The N SMD electronic ceramic chips (100) of the stacked SMD component include at least two SMD electronic ceramic chips (100) with different functions.

10. The chip-type ceramic electronic component suitable for low-voltage grid voltage according to claim 9, characterized in that: The two surface-mount electronic ceramic chips (100) with different functions are a varistor chip and a capacitor chip.

11. The chip-type ceramic electronic component suitable for low-voltage grid voltage according to any one of claims 1 to 10, characterized in that: Gaps are left on the overlapping surfaces of the N surface-mount electronic ceramic chips (100) of the stacked surface-mount assembly (400).

12. A method for manufacturing a surface-mount ceramic electronic component suitable for low-voltage grid voltage as claimed in any one of claims 1 to 11, characterized in that: The method comprises: Processing N of the surface mount electronic ceramic chips (100), and stacking the N surface mount electronic ceramic chips (100) on top of each other to form a laminated surface mount assembly (400); Welding the laminated patch assembly (400) and the conductive connection assembly (200) together; Using an insulating encapsulation material to encapsulate the welded components to form an insulating encapsulation layer (300); The reserved electrode extending out of the insulating encapsulation layer (300) is formed into a terminal electrode of a patch-type ceramic electronic component.

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