Class II superlattice infrared detector chip with optimized lower electrode structure and preparation method thereof

Abstract

The invention provides a type-II superlattice infrared detector chip with an optimized lower electrode structure and a preparation method of the type-II superlattice infrared detector chip, and belongs to the technical field of infrared detector preparation. The problems that the distances between pixels and lower electrodes in the middle and edge positions of a focal plane array are unequal, and the response uniformity is poor are solved. According to the technical scheme, the array comprises a plurality of units arranged on a focal plane array in an array mode, each unit comprises at least one lower electrode and an upper electrode array composed of at least three upper electrodes, and the lower electrodes are located in the centers of the upper electrode arrays; the method is applied to preparation of infrared detectors with large area arrays and small pixels.

Description

Technical Field

[0001] The invention provides a type II superlattice infrared detector chip with an optimized lower electrode structure and a preparation method thereof, belonging to the technical field of infrared detector preparation. Background Art

[0002] With the popularization of "large array, small pixel" infrared detectors, the chip response uniformity is getting worse and worse. Figure 1 As shown, the photogenerated carriers generated in the absorption region 4 need to be transmitted to the lower electrode 7 through the lower contact layer 3 for collection, especially the photogenerated carriers generated in the absorption region 4 of the central table of the array need to reach the lower electrode 7 through a longer transmission distance, and during the transmission process, the carriers will be recombined and annihilated at the defects of the epitaxial material of the lower contact layer 3, which will affect the carrier lifetime and reduce the signal strength of the focal plane chip; at the same time, since the photogenerated carriers generated in the absorption region 4 of the table at different positions of the focal plane chip are transmitted to the lower electrode 7 at different distances, the signal strengths of different focal plane chip areas received by the lower electrode 7 will be different, which will affect the response uniformity of the focal plane chip and ultimately affect the comprehensive performance of the focal plane chip.

[0003] like Figure 2 As shown, since there are more upper electrodes 6, the pixels in the middle and at the edge of the focal plane array have different distances from the lower electrode 7. The farther away from the lower electrode 7, the higher the probability of encountering epitaxial material defect composite annihilation, and the smaller the signal strength.

[0004] Another technical solution is Figure 2 Improvements based on Figure 5 As shown, the position of the existing lower electrode 7 is kept unchanged, and the lower electrodes 7 on all sides are connected together using a gold electrode grid, but this solution is limited by the size of the focal plane array. When the focal plane array 8 is small, this solution can improve this problem to a certain extent, but the larger the focal plane array 8 is, the more limited the effect of this solution will be. Figure 5 In the arrangement scheme, the etching depth of the isolation groove of the mesa 13 is less than the etching depth of the lower electrode 7. Since the area of ​​the lower electrode 7 is large, the etching depth is greater when the mesa 13 is subjected to ICP etching, so that the etching depth of the isolation groove of the mesa 13 is less than the etching depth of the lower electrode 7. When the focal plane array 8 is further enlarged, the etching depth difference will be further enlarged. At this time, in order to ensure the etching depth of the isolation groove of the mesa 13 (to avoid short circuit between two mesas), the etching depth of the lower electrode 7 may exceed the theoretical etching depth. Summary of the invention

[0005] In order to solve the problem of unequal distances between pixels and lower electrodes at the middle and edge positions of a focal plane array and poor response uniformity, the present invention proposes a type II superlattice infrared detector chip with an optimized lower electrode structure and a preparation method thereof.

[0006] The technical solution adopted by the present invention is: a type II superlattice infrared detector chip with an optimized lower electrode structure, comprising a plurality of units arranged in an array on a focal plane array, each unit comprising at least one lower electrode and an upper electrode array consisting of at least three upper electrodes, and the lower electrode is located at the center of the upper electrode array.

[0007] Furthermore, when the upper electrode array provided in each unit is an odd-numbered array, a lower electrode is provided at the center position of the upper electrode array.

[0008] Further, when the upper electrode array provided in each unit is an even-numbered array, four lower electrodes are provided at the center position of the upper electrode array.

[0009] Furthermore, a compensation algorithm is used to compensate for blind pixels appearing in the discontinuous upper electrode.

[0010] Furthermore, the compensation algorithm adopts one or more of the adjacent pixel replacement method, the neighborhood interpolation method, the compensation algorithm based on statistical characteristics, and the median filtering method.

[0011] A method for preparing a type II superlattice infrared detector chip with an optimized lower electrode structure comprises the following steps: S1: Clean the sample for later use: the sample is a wafer on which an epitaxial buffer layer of a type II superlattice material is grown on a substrate; S2: Plate mark lithography: making plate marks on the sample surface; S3: plate logo etching; S4: cleaning and degumming; S5: Hard mask film formation: SiO2 with a set thickness is grown on the sample surface as a hard mask for subsequent mesa etching; S6: mesa photolithography: remove impurities from the grown SiO2 sample and then perform mesa photolithography; S7: Hard mask etching: using photoresist as a mask, etching SiO2 to form a hard mask mesa pattern; S8: degumming and cleaning; S9: Mesa ICP etching: Mesa etching is performed using ICP dry etching technology with SiO2 as a hard mask; S10: wet etching: etching the superlattice material; S11: Passivation layer film formation: After the mesa etching is completed, silicon oxide is deposited as a passivation layer; S12: Opening holes in the passivation layer: opening holes according to the positions of the upper and lower electrodes; S13: gold electrode fabrication; S14: Indium electrode production, dicing, flip-chip interconnection, glue dispensing, grinding and polishing.

[0012] Furthermore, in step S2, a binder is applied to the surface of the sample, and then the sample is subjected to a process of spinning, pre-baking, exposure, development, and hardening to obtain a plate mark.

[0013] Furthermore, in both steps S1 and S3, cleaning is performed by sequentially using acetone, ethanol, and isopropanol solutions.

[0014] Furthermore, the implementation process of step S8 is: removing the surface photoresist by heating in an acetone water bath for 10-20 minutes, and then cleaning the material surface with anhydrous ethanol and deionized water in sequence.

[0015] Furthermore, in step S10, a mixed solution of phosphoric acid, citric acid and hydrogen peroxide is used to corrode the superlattice material.

[0016] The beneficial effects of the present invention compared with the prior art are as follows: the upper and lower electrode position arrangement structure provided by the present invention can reduce the distance difference between each upper electrode and lower electrode, thereby improving the response uniformity of the focal plane array and improving the comprehensive performance of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The present invention will be further described below in conjunction with the accompanying drawings: Figure 1 It is a structural schematic diagram of an existing infrared detector focal plane chip; Figure 2 It is a schematic diagram of the electrode arrangement structure of the existing infrared detector focal plane chip; Figure 3 for Figure 2 A cross-sectional view of the upper electrode in the middle; Figure 4 for Figure 2 Cross-sectional view of the lower electrode at B in the middle; Figure 5 For Figure 2 A schematic diagram of the structure of the improved lower electrode arrangement based on the present invention; Figure 6 This is a schematic diagram of the structure of placing upper and lower electrodes in a unit array according to Embodiment 1 of the present invention; Figure 7 Based on Figure 6 A schematic diagram of the local structure of the electrode arrangement on the entire infrared detector focal plane chip obtained by the arrangement method; Figure 8 A schematic diagram of the structure of placing upper and lower electrodes in a unit array according to Embodiment 2 of the present invention; Fig. 9 Based on Figure 8 A schematic diagram of the local structure of the electrode arrangement on the entire infrared detector focal plane chip obtained by the arrangement method; Fig.10 for Fig. 9 The cross section at C in the middle Figure 1 ; Fig.11 for Fig. 9 The cross section at C in the middle Figure 2 ; Fig.12 A schematic diagram of the structure of placing upper and lower electrodes in a unit array according to Embodiment 3 of the present invention; Fig.13 Based on Fig.12 A schematic diagram of the local structure of the electrode arrangement on the entire infrared detector focal plane chip obtained by the arrangement method; In the figure: 1 is the substrate, 2 is the epitaxial buffer layer, 3 is the lower contact layer, 4 is the absorption region, 5 is the upper contact layer, 6 is the upper electrode, 7 is the lower electrode, 8 is the focal plane array, 9 is the hard mask, 10 is the gold electrode, 11 is the indium electrode, 12 is the passivation layer, and 13 is the table. DETAILED DESCRIPTION

[0018] like Figures 6 to 13 As shown, the present invention provides a type II superlattice infrared detector chip with an optimized lower electrode structure, changes the arrangement of the lower electrode 7, reduces the distance difference between the upper electrode 6 (pixel) and the lower electrode 7 at different positions, and improves the response non-uniformity.

[0019] The present invention mainly combines multiple upper electrodes 6 and one lower electrode 7 into corresponding units, so that the lower electrode 7 in each unit is located at the center of the multiple upper electrodes 6, thereby ensuring that the distance difference between each upper electrode 6 and the lower electrode 7 is basically the same or the difference is small.

[0020] The structure of the present invention is described below based on specific embodiments.

[0021] Example 1 Each 3*3 upper electrodes 6 is a unit, the middle position of each unit is set as the lower electrode 7, and the unit array is arranged according to the number of area array pixels. Figure 6 and 7 shown.

[0022] Example 2 Each 5*5 upper electrodes 6 is a unit, the middle position of each unit is set as the lower electrode 7, and the unit array is arranged according to the number of area array pixels. Figure 8 and 9 shown.

[0023] Since there are many pixels on each chip, taking 640*512 resolution as an example, there are 327680 pixels. Figure 7 and 9 It is only a partial location.

[0024] The number of pixels in the unit can be changed according to the number of rows / columns and the actual compensation algorithm requirements. The pixel array in the unit is recommended to be (2n+1)*(2n+1), that is, the rows / columns are all odd numbers, so that the lower electrode 7 is placed in the middle of the unit, and the distance from the upper electrode 6 to the lower electrode 7 can be made as equal as possible, which is convenient for the compensation algorithm calculation.

[0025] Fig.10 and 11 The cross-sectional effect is shown, with the left side of the figure showing the effect of the position of the upper electrode 6 and the right side showing the effect of the position of the lower electrode 7. Fig.10 The passivation layer 12 at the position of the lower electrode 7 on the middle right side is completely removed. Fig.11 At the position of the lower electrode 7 on the middle right side, the passivation layer 12 is removed only at the position in the groove that needs to be electrically connected to the lower contact layer 3.

[0026] Example 3 If the pixel array in the unit is 2n*2n, it is possible to consider setting the lower electrode 7 to a size of 2*2 mesas 13. Fig.12 and 13 The cross-sectional view of the upper electrode 6 and the lower electrode 7 of this embodiment is the same as above and will not be described here.

[0027] It is necessary that, since the present invention implants the lower electrode 7 into the upper electrode 6 area, the upper electrode 6 will be discontinuous and regular "blind pixels" will appear, which requires the use of a compensation algorithm in the later stage, such as 1) adjacent pixel replacement method, using the grayscale value of one pixel among the 4, 8... adjacent pixels around the blind pixel to replace the grayscale value here; 2) neighborhood interpolation method, by calculating the average grayscale value of each point in the neighborhood of the blind pixel to replace the grayscale value here; 3) compensation algorithm based on statistical characteristics, by analyzing the statistical characteristics of the entire image or local area (such as grayscale histogram, mean, variance, etc.) to estimate and compensate the value of the blind pixel, there are other median filtering methods and so on.

[0028] The present invention also proposes a method for preparing a type II superlattice infrared detector chip with an optimized lower electrode structure, and the structures of Examples 1, 2, and 3 are prepared, and the specific steps are as follows: S1: Cleaning the sample: Use acetone, ethanol, and isopropanol to clean the sample in sequence for later use, wherein the sample is a wafer having an epitaxial buffer layer 2 of a type II superlattice material grown on a substrate 1.

[0029] S2: Plate marking photolithography: Apply adhesive on the sample surface, then go through the steps of spinning, pre-baking, exposure, development, and hardening to make the plate marking.

[0030] S3: Plate marking etching: Etching materials using plasma formed by chlorine-based gases in an inductively coupled plasma (ICP) system.

[0031] S4: Cleaning and degumming: Use acetone, ethanol and isopropanol in sequence to clean and degummed the etched sample.

[0032] S5: Hard mask film formation: Use plasma enhanced chemical vapor deposition (PECVD) to grow a certain thickness of SiO2 on the sample surface as a hard mask for subsequent mesa etching 9. The thickness of SiO2 depends on the required etching depth of the device and the etching ratio of the mask to the material by different ICP gas combinations. Usually, 200-300nm is added to the required thickness to prevent over-etching.

[0033] S6: table photolithography: put the sample after growing SiO2 into a plasma glue machine without a metal cover to remove impurities attached to the surface; put it into HMDS to coat the adhesive to increase the adhesion between the material surface and the photoresist and avoid the phenomenon of no glue sticking during the glue spinning process; use the glue spinning machine to spread the glue, the first version uses positive glue AZ6130 with a glue thickness of 1.5-2μm, put it on the heating plate, 95℃, pre-bake for 10min to remove moisture on the sample surface; exposure, the time is set according to the glue thickness; the sample is placed in a tetramethylammonium hydroxide solution with a concentration of 2.38% for development; after development, use nitrogen to blow dry, put it on the heating plate, select temperature points between 95℃-110℃ for gradient hardening, each for 10min, and finally harden at 120℃ for 20-30min; put it in a plasma glue machine with a metal cover to remove the residual photoresist at the edge of the pattern.

[0034] S7: Hard mask etching: Using photoresist as a mask, inductively coupled plasma (ICP) technology is used to etch SiO2 to form a hard mask mesa pattern. The process gas used is 5sccm chlorine, 12sccm methane, 5sccm argon, vacuum 5mTorr, substrate 1 temperature is 200℃, ICP power is 600W, and RF power is 35W.

[0035] S8: Degumming and cleaning: Heat in an acetone water bath for 10-20 minutes to remove the surface photoresist, and then use anhydrous ethanol and deionized water to clean the material surface in turn.

[0036] S9: Terrane ICP etching: The terrace 13 is etched using ICP dry etching technology with SiO2 as the hard mask 9.

[0037] S10: Wet etching: The superlattice material is corroded using a mixed solution of phosphoric acid, citric acid, and hydrogen peroxide (H3PO4, C6H8O7, H2O2).

[0038] S11: Passivation layer film formation: After the etching of the mesa 13 is completed, 30-60 nm silicon oxide is deposited using an atomic layer deposition (ALD) method, and 100-300 nm silicon oxide is deposited using a plasma enhanced chemical vapor deposition process as a composite passivation layer 12.

[0039] S12: Opening holes in the passivation layer: Performing photolithography of opening holes in the passivation layer 12, leaving the area where the hole is required, and covering the other areas with photoresist, the parameters are consistent with the mesa photolithography of the upper electrode 6 in step S6, and then using ICP to etch the passivation layer 12; The opening positions of the passivation layer 12 of the upper and lower electrodes are quite different. The upper electrode 6 is opened normally, and the isolation grooves around the lower electrode 7 need to be opened synchronously to ensure that the lower electrode 7 can maintain electrical connection with the lower contact layer 3.

[0040] S13: Preparation of gold electrode: Use negative photoresist L300 to perform 10-photolithography of gold electrode, then use electron beam evaporation technology to evaporate Ti / Pt / Au metal with thickness of 50 / 50 / 300nm respectively. Put the evaporated metal sample into acetone, wait for 1~2 hours, and then use acetone to blow off the surface of the material to complete the metal stripping. After the metal is stripped clean, wash the sample with anhydrous ethanol and deionized water in turn, blow dry with nitrogen, and the preparation of the unit detector chip is officially completed.

[0041] S14: Indium electrode 11 is manufactured, sliced, flip-chip interconnected, glued, and ground and polished.

[0042] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A type II superlattice infrared detector chip with an optimized lower electrode structure, characterized in that: It comprises a plurality of units arranged in an array on a focal plane array, each unit comprises at least one lower electrode and an upper electrode array composed of at least three upper electrodes, and the lower electrode is located at the center of the upper electrode array.

2. A type II superlattice infrared detector chip with an optimized lower electrode structure according to claim 1, characterized in that: When the upper electrode array arranged in each unit is an odd-numbered array, a lower electrode is arranged at the center position of the upper electrode array.

3. The type II superlattice infrared detector chip with optimized lower electrode structure according to claim 1, characterized in that: When the upper electrode array arranged in each unit is an even-numbered array, four lower electrodes are arranged at the center position of the upper electrode array.

4. A type II superlattice infrared detector chip with an optimized lower electrode structure according to claim 2 or 3, characterized in that: A compensation algorithm is used to compensate for the blind pixels that appear in the discontinuous upper electrode.

5. The type II superlattice infrared detector chip with optimized lower electrode structure according to claim 4, characterized in that: The compensation algorithm adopts one or more of the adjacent pixel replacement method, the neighborhood interpolation method, the compensation algorithm based on statistical characteristics, and the median filtering method.

6. A method for preparing a type II superlattice infrared detector chip having an optimized lower electrode structure as claimed in any one of claims 1 to 5, characterized in that: The following steps are involved: S1: Clean the sample for later use: the sample is a wafer on which an epitaxial buffer layer of a type II superlattice material is grown on a substrate; S2: Plate mark lithography: making plate marks on the sample surface; S3: plate logo etching; S4: cleaning and degumming; S5: Hard mask film formation: SiO2 with a set thickness is grown on the sample surface as a hard mask for subsequent mesa etching; S6: mesa photolithography: remove impurities from the grown SiO2 sample and then perform mesa photolithography; S7: Hard mask etching: using photoresist as a mask, etching SiO2 to form a hard mask mesa pattern; S8: degumming and cleaning; S9: Mesa ICP etching: Mesa etching is performed using ICP dry etching technology with SiO2 as a hard mask; S10: wet etching: etching the superlattice material; S11: Passivation layer film formation: After the mesa etching is completed, silicon oxide is deposited as a passivation layer; S12: Opening holes in the passivation layer: opening holes according to the positions of the upper and lower electrodes; S13: gold electrode fabrication; S14: Indium electrode production, dicing, flip-chip interconnection, glue dispensing, grinding and polishing.

7. The method for preparing a type II superlattice infrared detector chip with an optimized lower electrode structure according to claim 6, characterized in that: In step S2, a binder is applied to the surface of the sample, and then the sample is subjected to a process of spinning, pre-baking, exposure, development, and hardening to obtain a plate mark.

8. The method for preparing a type II superlattice infrared detector chip with an optimized lower electrode structure according to claim 6, characterized in that: In both steps S1 and S3, cleaning is performed by sequentially using acetone, ethanol, and isopropanol solutions.

9. The method for preparing a type II superlattice infrared detector chip with an optimized lower electrode structure according to claim 6, characterized in that: The implementation process of step S8 is: remove the surface photoresist by heating in an acetone water bath for 10-20 minutes, and then use anhydrous ethanol and deionized water to clean the material surface in sequence.

10. The method for preparing a type II superlattice infrared detector chip with an optimized lower electrode structure according to claim 6, characterized in that: In step S10, a mixed solution of phosphoric acid, citric acid and hydrogen peroxide is used to corrode the superlattice material.

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