A data access method, processor and CXL controller

Abstract

The application discloses a data access method, a processor and a CXL controller, relates to the technical field of computing, and can reduce the critical path length in the process of CPU processing data access and improve access speed. The method comprises the following steps: in response to a read request of a first program, determining a storage space where to-be-read data is located; the to-be-read data is data to be read by the read request; in the case that the storage space where the to-be-read data is located is located at a remote storage device, instructing a direct memory access (DMA) controller to process the read request, so that the DMA controller controls migration of the to-be-read data from the remote storage device to a CXL storage device; and receiving a message fed back by the DMA controller that the read request is successfully processed, and reading the to-be-read data from the CXL storage device.

Description

Technical Field

[0001] This application relates to the field of computing technology, and in particular to a data access method, a processor, and a CXL controller. Background Technology

[0002] With the development of technologies such as cloud computing, artificial intelligence, and high-performance computing, data centers are increasingly demanding higher computing power from processors, leading to a surge in processor core counts and consequently, a greater need for memory resources. To meet the demands of data center computing devices (such as servers) for large-capacity and high-bandwidth memory, a disaggregated storage system is proposed. Computing devices access the storage space provided by this system through remote direct memory access (RDMA) technology. Two key challenges remain in building a disaggregated storage system: providing application-independent memory infrastructure at the OS level and achieving extremely low access latency to support CPU synchronous instructions.

[0003] In some related technical solutions, the central processing unit (CPU) of a computing device accesses a remote storage system by triggering a page fault interrupt. In this solution, after the CPU triggers a page fault interrupt, it needs to perform actions such as locking the faulty page table, acquiring the page table entry (PTE), requesting a page frame, and requesting a page cache before sending an access request to the remote storage system to the network card (NIC) with RDMA capabilities. This series of actions results in an excessively long critical path for accessing the remote storage system, impacting access speed. Summary of the Invention

[0004] This application provides a data access method, processor, and CXL controller that can reduce the critical path length during CPU data access and improve access speed.

[0005] To achieve the above technical objectives, the embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, embodiments of this application provide a data access method applied to the CPU of a computing device. The CPU is connected to a CXL storage device via a CXL bus, and the CXL storage device is connected to a remote storage device via a network. The method includes: in response to a read request from a first program, determining the storage space where the data to be read is located; the data to be read is the data to be read by the read request; if the storage space where the data to be read is located is on a remote storage device, instructing a DMA controller to process the read request, so that the DMA controller controls the data to be read to be migrated from the remote storage device to the CXL storage device; receiving a message from the DMA controller indicating that the read request has been successfully processed, and reading the data to be read from the CXL storage device.

[0007] Understandably, in the above process, after the CPU receives a read request from the application, it only needs to determine the location of the data to be read before handing the read request over to the DMA controller for processing. This reduces the number of CPU processing steps, thus decreasing the critical path in the CPU's processing and improving access speed. Furthermore, this method involves two steps: the first step is a synchronous foreground process where the CPU determines the storage space where the data to be read is located; the second step involves the DMA controller asynchronously processing the read request, preventing the CPU from being suspended. The simultaneous execution of the foreground synchronous process and the background asynchronous process improves the efficiency of data access.

[0008] In one possible implementation, the read request carries the target logical address of the storage space where the data to be read is located. Determining the storage space where the data to be read is located includes: when there is an indicator flag in the address mapping table where the target logical address is located, determining that the storage space where the data to be read is located is located in a remote storage device; wherein, the address mapping table includes a mapping relationship between the target logical address and the target bus address, and the indicator flag is used to indicate that the storage space indicated by the bus address corresponding to the logical address is located in a remote storage device.

[0009] Understandably, this method triggers an error interrupt by setting an indicator flag, so that the CPU executes subsequent instructions to the DMA controller to process the read request. This method is simple to implement and easy to manage, and compared with related technologies, the CPU's processing path is shortened.

[0010] In another possible implementation, after receiving a message from the DMA controller indicating that the read request was successfully processed, the method further includes: deleting the indicator flag in the entry of the target logical address in the address mapping table; reading the data to be read from the CXL storage device, including: reading the data to be read from the storage space indicated by the target bus address; wherein the storage space indicated by the target bus address is the storage space of the CXL storage device.

[0011] It is understandable that since the indicator flag is used to indicate that the data to be read is located on a remote storage device, deleting the indicator flag after the data to be read is migrated to the local CXL storage device is beneficial for subsequent reading of the data to be read from the CXL storage device and completing the read request.

[0012] In another possible implementation, the read request carries the target logical address of the storage space where the data to be read is located; instructing the DMA controller to process the read request, including: obtaining the target bus address corresponding to the target logical address, modifying the target logical address carried in the read request to the target bus address, and adding the read request carrying the target bus address to the task queue to instruct the DMA controller to obtain and process the read request carrying the target bus address from the task queue.

[0013] Understandably, by setting up a task queue for the DMA controller in the CPU, the CPU can send all the tasks that need to be processed to the task queue, avoiding waiting for the DMA controller to finish processing one task before sending the next task. Therefore, after setting up the task queue, the CPU can send tasks to the DMA controller in batches, improving task processing efficiency.

[0014] In another possible implementation, after instructing the DMA controller to process the read request, the method further includes: switching from a first program to a second program in response to scheduling by the task scheduler; and after receiving a message from the DMA controller indicating that the read request was successfully processed, the method further includes: switching from the second program to the first program.

[0015] Understandably, during the process of the DMA controller processing a read request, the CPU switches from the first program to the second program. After the DMA controller finishes processing, the CPU switches back from the second program to the first program. During this process, the CPU does not need to wait for the DMA controller to process the read request. Instead, the task scheduler schedules the CPU to execute other programs to improve CPU utilization.

[0016] Secondly, embodiments of this application provide a data access method applied to a DMA controller of a computing device. The CPU of the computing device is connected to a CXL storage device via a CXL bus, and the CXL storage device is connected to a remote storage device via a network. The method includes: obtaining a read request from a task queue; tasks in the task queue are issued by the CPU, and the read request is used to read data to be read from the storage space indicated by the target bus address; sending the read request to the CXL storage device, so that the CXL controller of the CXL storage device migrates the data to be read from the remote storage device to the CXL storage device when the storage space indicated by the target bus address is the storage space of the remote storage device; after receiving a message from the CXL controller indicating that the migration of the data to be read is successful, sending a message to the CPU indicating that the read request has been successfully processed, so that the CPU reads the data to be read from the CXL storage device.

[0017] Understandably, during this process, the DMA controller asynchronously processes read requests under the CPU's instructions, enabling batch processing of tasks issued by the CPU and preventing the CPU from being suspended. This asynchronous processing, combined with the CPU's foreground synchronization process, improves the efficiency of data access.

[0018] Thirdly, embodiments of this application provide a data access method applied to a CXL controller of a CXL storage device. The CXL storage device is connected to the CPU of a computing device via a CXL bus, and the CXL storage device is connected to a remote storage device via a network. The method includes: receiving a read request sent by a DMA controller of the computing device; the read request is used to request reading data to be read from a storage space indicated by a target bus address; if the storage space indicated by the bus address is a first storage space in the CXL storage device, sending a message to the DMA controller indicating successful migration of the data to be read; if the storage space indicated by the target bus address is a second storage space in a remote storage device, migrating the data in the second storage space to the CXL storage device, and sending a message to the DMA controller indicating successful migration of the data to be read.

[0019] Understandably, in this method, after receiving a read request, the CXL controller further determines the location of the data to be read, which can ensure the accuracy of the storage space indicated by the target bus address and improve the success rate of reading the data.

[0020] In one possible implementation, the CXL storage device stores the mapping relationship between the storage bus address and the physical address of the storage space of the CXL storage device, or the mapping relationship between the CXL storage device's storage bus address and the physical address of the storage space of a remote storage device. After receiving a read request sent by the DMA controller of the computing device, the method further includes: determining the storage space indicated by the target bus address; when the mapping address corresponding to the target bus address is the address of a first storage space, the storage space indicated by the target bus address is the first storage space; when the mapping address corresponding to the target bus address is the address of a second storage space, the storage space indicated by the target bus address is the second storage space.

[0021] It is understood that the method proposed in the embodiments of this application can quickly determine the storage space indicated by the target bus address and the specific location where the data to be read is stored.

[0022] In another possible implementation, before migrating the data in the second storage space to the CXL storage device, the method further includes: when the storage capacity of the available storage space of the CXL storage device is less than the required storage capacity, migrating the data in the third storage space of the CXL storage device to a remote storage device, so that the storage capacity of the currently available storage space of the CXL storage device is greater than or equal to the required storage capacity; wherein, the required storage capacity is the storage capacity required to store the data to be read, and the currently available storage space is the sum of the storage capacity of the third storage space and the storage capacity of the available storage space; migrating the data in the second storage space to the CXL storage device includes: migrating the data in the second storage space to the fourth storage space of the CXL storage device; the fourth storage space is part or all of the storage space in the currently available storage space.

[0023] It is understandable that when the available storage space of the CXL storage device is insufficient, some of the data is migrated to a remote storage device in order to leave enough storage space for the data to be read to be migrated to the CXL storage device, so that the data to be read can be read from the CXL storage device later.

[0024] In another possible implementation, the method also includes: storing the mapping relationship between the target bus address and the physical address of the fourth memory space.

[0025] It is understandable that the CXL controller stores the mapping relationship between the target bus address and the physical address of the fourth memory space in the target address mapping table. When the CPU reads the data in the memory space indicated by the target bus address, it can determine the mapped address corresponding to the target bus address as the physical address of the fourth memory space from the mapping relationship, thereby improving data reading efficiency.

[0026] Fourthly, embodiments of this application provide a processor, wherein the processor is applied to various modules of the data access method of the first aspect or any possible implementation of the first aspect.

[0027] Fifthly, embodiments of this application provide a DMA controller, wherein the DMA controller is applied to various modules of the data access method of the second aspect or any possible implementation of the second aspect.

[0028] In a sixth aspect, embodiments of this application provide a CXL controller, wherein the CXL controller is applied to various modules of the data access method of the third aspect or any possible implementation thereof.

[0029] In a seventh aspect, embodiments of this application provide a processor coupled to a memory for storing programs or instructions. When the program or instructions are executed by the processor, the processor performs a data access method as described in the first aspect and any possible implementation thereof.

[0030] Eighthly, embodiments of this application provide a CXL controller, including a processor coupled to a memory for storing programs or instructions. When the programs or instructions are executed by the processor, the CXL controller is applied to various modules of the data access method of the third aspect or any possible implementation of the third aspect.

[0031] Ninthly, embodiments of this application provide a computer-readable storage medium including computer instructions. When the computer instructions are executed on a processor, the processor performs a data access method as described in the first aspect and any possible implementation thereof; or, when the computer instructions are executed on a CXL controller, the CXL controller performs a data access method as described in the third aspect and any possible implementation thereof.

[0032] In a tenth aspect, embodiments of this application provide a computer program product comprising computer instructions. When the computer instructions are executed on a processor, the processor performs a data access method as described in the first aspect and any possible implementation thereof; or, when the computer instructions are executed on a CXL controller, the CXL controller performs a data access method as described in the third aspect and any possible implementation thereof.

[0033] For a detailed description of aspects four through ten and their various implementations in the embodiments of this application, please refer to the detailed descriptions in aspects one, two, or three and their various implementations; and for a detailed description of the beneficial effects of aspects three through ten and their various implementations, please refer to the beneficial effect analyses in aspects one, two, or three and their various implementations, which will not be repeated here.

[0034] These or other aspects of the embodiments of this application will become more apparent in the following description. Attached Figure Description

[0035] Figure 1 This is a system architecture diagram proposed in an embodiment of this application;

[0036] Figure 2 A flowchart illustrating a data access method provided in an embodiment of this application;

[0037] Figure 3 A flowchart illustrating another data access method provided in this application embodiment;

[0038] Figure 4 A flowchart illustrating another data access method provided in this application embodiment;

[0039] Figure 5 A schematic diagram of a processor provided in an embodiment of this application;

[0040] Figure 6 This is a schematic diagram of the structure of a DMA controller provided in an embodiment of this application;

[0041] Figure 7 This is a schematic diagram of the structure of a CXL controller provided in an embodiment of this application. Detailed Implementation

[0042] For ease of understanding, the relevant terms used in the embodiments of this application will be briefly introduced below:

[0043] (1) Memory Management Unit (MMU): A type of computer hardware responsible for handling CPU memory access requests. Its functions include virtual address to physical address translation (i.e., virtual memory management), memory protection, control of the CPU cache, and in simpler computer architectures, bus arbitration and memory switching.

[0044] (2) Compute Express Link (CXL): A protocol for interconnecting the CPU with other devices. This protocol supports a unified memory space for the CPU and peripherals to maintain memory consistency.

[0045] (3) Translation lookaside buffer (TLB): a technique to accelerate page table lookups.

[0046] (4) Direct memory access (DMA): The data transfer capability provided by the computer bus can support data to be transferred directly from external devices to memory.

[0047] (5) RDMA: A network technology in which a processor with RDMA capability can access the memory of a remote device without the CPU of the remote device being involved.

[0048] Hereinafter, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," or "third," etc., may explicitly or implicitly include one or more of that feature.

[0049] In the description of the embodiments in this application, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. "And / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, "at least one" refers to one or more, and "multiple" refers to two or more.

[0050] To address two main problems associated with computing devices accessing discrete storage systems, relevant technologies propose several solutions. In some solutions, the computing device's CPU accesses the remote storage system by triggering a page fault interrupt. In this approach, after triggering the interrupt, the CPU must first perform actions such as locking the faulty page table, acquiring the Page Entity Transfer (PTE), allocating page frames, and allocating page caches before sending an access request to the remote storage system to the network interface card (NIC) with RDMA capabilities. This allows the NIC to complete the access. Furthermore, these CPU actions result in an excessively long critical path for accessing the remote storage system, impacting access speed.

[0051] Based on this, this application proposes a data access method, which is mainly applied to a computing device reading data from a remote storage device. In this method, after the application (first program) initiates a read request, the CPU of the computing device first determines the storage space where the data to be read is located. If the data to be read is in a remote storage device, the CPU instructs the DMA controller to handle the read request. After the DMA controller successfully migrates the data to be read from the remote storage device to the local CXL storage device, the CPU then reads the data to be read from the CXL storage device.

[0052] Understandably, after the CPU receives a read request from the application, it only needs to determine the location of the data to be read before handing the read request over to the DMA controller for processing. In this process, the number of CPU processing steps is reduced, which reduces the critical path in the CPU processing and thus improves the access speed.

[0053] Furthermore, this method involves two steps. The first step is a synchronous process where the CPU in the foreground determines the storage space where the data to be read resides. In the second step, the DMA controller asynchronously processes the read request, preventing the CPU from being suspended. The simultaneous execution of the foreground synchronous process and the background asynchronous process improves the efficiency of data access.

[0054] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0055] Please refer to Figure 1 This diagram illustrates a system architecture involved in the data access method provided in an embodiment of this application. Figure 1 As shown, the system architecture may include: computing device 110, CXL storage device 120 and remote storage device 130.

[0056] CXL storage device 120 is connected to computing device 110 via the CXL physical bus. Specifically, CXL controller 120 is connected to the CPU of computing device 110. Remote storage device 130 is connected to computing device 110 via a network.

[0057] Computing device 110 is a computing device with data processing, logical operation, and storage functions. For example, computing device 110 may include computing devices such as servers, tablets, desktop computers, laptops, or netbooks. The server may be a rack server, blade server, or tower server, among other different types. A server may include one or more computing nodes, each computing node including at least one CPU 111. When a server includes multiple computing nodes, the multiple CPUs 111 in the multiple computing nodes share a single operating system.

[0058] The CPU 111 of the computing device 110 includes a memory management unit (MMU) 113 and multiple DMA controllers 112.

[0059] MMU113 is responsible for handling memory access requests from CPU111 and managing PTEs. PTEs include the mapping relationship between logical addresses and physical addresses. MMU113 is used to translate logical addresses into physical addresses.

[0060] The DMA controller 112 supports high-speed data transfer between the computing device 110 and its peripherals (e.g., CXL storage device 120) or between the peripherals (e.g., CXL storage device 120) and the memory of the computing device 110. This transfer process does not require the participation of the CPU 111, thus saving CPU 111 resources. Each DMA controller 112 is connected to the internal memory (e.g., RAM) of the computing device 110 or the external storage device (e.g., CXL storage device 120) of the computing device via a bus.

[0061] In this embodiment of the application, the DMA controller receives and processes tasks issued by the CPU 111, such as read / write data requests.

[0062] In one embodiment, a task queue is set up for each CPU 111 of the computing device 110. The task queue is used to cache tasks issued by the CPU 111 to the DMA controller 112. The DMA controller 112 retrieves the tasks issued by the CPU 111 from the task queue in sequence and processes them.

[0063] CXL storage device 120 is used to provide directly accessible storage space to computing device 110, provide the physical address of the storage space to computing device 110, query available storage space, and perform data migration, etc.

[0064] CXL storage device 120 includes CXL controller 121 and CXL memory 122.

[0065] The CXL controller 121 can write data to or read data from the CXL memory 122 under the instruction of the CPU 111 or DMA controller 112 of the computing device 110. Additionally, the CXL controller 121 has RDMA functionality, enabling it to access remote memory 132. The CXL controller 121 is also known as a CXL memory expander controller or a CXL memory expander pooling chip. The CXL controller 121 can take various forms; for example, it can be a processor or a data processing unit (DPU).

[0066] CXL memory 122 provides storage space for fast data read / write for computing device 110.

[0067] For example, the CXL memory 122 may include one or more dual inline memory modules (DIMMs), one or more storage devices with dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), solid state disk (SSD), storage devices with NAND flash memory, and / or persistent memory (PMEM). This application embodiment does not limit the media type, quantity, or deployment method of the CXL memory 122.

[0068] Remote storage device 130, a device with storage space, can provide storage space for computing device 110 to transfer data across a network.

[0069] The remote storage device 130 includes a remote controller 131 and a remote memory 132. The remote controller 131 is used to communicate with the CXL controller 121 and, under the instruction of the CXL controller 121, to acquire data from the remote memory 132.

[0070] The remote storage device 130 can be a computing device such as a server, tablet computer, desktop computer, laptop computer, notebook computer or netbook, or the remote storage device 130 can be a distributed storage cluster, and the remote controller 131 can be a data processing unit (DPU).

[0071] The remote memory 132 is the physical carrier for storing data in the remote storage device 130.

[0072] For example, the remote storage 132 may include one or more dual inline memory modules (DIMMs), one or more storage devices with dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), solid state disk (SSD), storage devices with NAND flash memory, and / or persistent memory (PMEM). This application embodiment does not limit the media type, quantity, or deployment method of the remote storage 132.

[0073] In this embodiment, the number of computing devices 110 can be one or more. When there is only one computing device 110, it can be directly connected to the CXL storage device 120 via the CXL physical bus. When there are multiple computing devices, each computing device 110 can be connected to the CXL storage device 120 via a multi-head expansion device.

[0074] In one application scenario, an application running on computing device 110 initiates a read request. Based on this read request, CPU 111 determines the storage space where the data to be read is located. If the data to be read is located in CXL storage device 120, CPU 111 reads the data from CXL storage device 120. If the data to be read is located in remote storage device 130, CPU 111 instructs DMA controller 112 to process the read request. DMA controller 112 sends the read request to CXL controller 121, causing CXL controller 121 to migrate the data from remote storage device 130 to CXL storage device 120. Then, CPU 111 continues to read the data from CXL storage device 120.

[0075] The data access method provided in the embodiments of this application will be described below:

[0076] Please refer to Figure 2 This is a flowchart illustrating a data access method provided in an embodiment of this application. The method is applied to... Figure 1 The CPU 111 in the computing device 110 shown is, for example Figure 2 As shown, the method may include S101-S107.

[0077] S101: The CPU responds to the read request from the first program and determines the storage space where the data to be read is located.

[0078] The data to be read is the data that the read request wants to read. For example, a read request is a read instruction in a load / store command.

[0079] If the storage space where the data to be read is located is located on a remote storage device, execute S102;

[0080] If the storage space where the data to be read is located is a CXL storage device, execute S107.

[0081] The first type of program is the user-mode program running in the CPU's operating system, such as cloud computing programs and artificial intelligence programs.

[0082] Determine the storage space where the data to be read is located, that is, determine whether the data to be read is stored on a remote storage device or on a CXL storage device.

[0083] In one implementation, for determining the storage space where the data to be read is located in S101, a specific implementation process is proposed: the MMU in the CPU determines whether there is an indicator flag in the table entry where the target logical address is located based on the address mapping table.

[0084] If the table entry containing the target logical address has an indicator flag, the MMU determines that the data to be read is stored in the remote storage device; if the table entry containing the target logical address does not have an indicator flag, the MMU determines that the data to be read is stored in the CXL storage device.

[0085] The target logical address is the logical address of the storage space where the data to be read carried by the read request is located.

[0086] Address mapping tables are used to record the mapping relationship between logical addresses and bus addresses, such as page table entries (PTEs). A logical address is the virtual physical address of the memory space allocated by the CPU to an application, plus an offset. A bus address is the actual physical address of the computing device's memory space, which includes the memory space of CXL storage devices and remote storage devices.

[0087] The bus address is the address obtained by the computing device through unified addressing of all storage spaces of the computing device. All storage spaces of the computing device include the storage space provided by the remote storage device and the storage space provided by the CXL storage device. Therefore, there is a correspondence between the bus address and the physical address of the remote storage device and the physical address of the CXL storage device.

[0088] The address mapping table contains indicator tags that indicate that the memory space indicated by the bus address is the memory space of the remote storage device.

[0089] For example, when an inaccessible flag is indicated, the MMU marks the entry in the address mapping table where the bus address indicates a remote storage device as inaccessible. The MMU then checks whether the entry in the address mapping table containing the target logical address contains this inaccessible flag. As shown in Table 1, Table 1 is the address mapping table maintained by the MMU, which includes multiple logical addresses and their corresponding bus addresses. Table 1 includes "Indicator Flag", "Logical Address", and "Bus Address".

[0090] Table 1

[0091] Indicator Marker Logical address Bus address Inaccessible A1 B1 Inaccessible A2 B2 -- A3 B3 -- A4 B4

[0092] As can be seen from the indicator marks shown in Table 1 above, the bus addresses of the entries containing the indicator marks are B1 and B2. It can be assumed that the storage space indicated by B1 and B2 is the storage space of the remote device.

[0093] The above implementation can be achieved using a Page Fault Entry (PTE) maintained by the MMU. When an indicator flag (which can be called a page fault flag) exists in a PTE entry, the memory space indicated by the bus address in that entry is considered inaccessible. This triggers a page fault interrupt, and the CPU jumps from the user-mode program to the interrupt handling unit of the kernel-mode program. In this embodiment, a processing branch can be set in the interrupt handling unit for the data access method proposed in this embodiment, for example, defined as a numa fault branch. Based on the indicator flag contained in the PTE, after jumping to the interrupt handling unit, the CPU further jumps to the numa fault branch to handle the read request.

[0094] The following S102 describes the processing procedure after the CPU jumps to the numa fault branch.

[0095] S102: The CPU instructs the DMA controller to process the read request so that the DMA controller can control the migration of the data to be read from the remote storage device to the CXL storage device.

[0096] In one implementation, the specific execution process of S102 may include: S102a-S102c.

[0097] S102a: The CPU obtains the target bus address corresponding to the target logical address.

[0098] In one implementation, the CPU obtains the target bus address corresponding to the target logical address from the address mapping table maintained by the MMU.

[0099] S102b: The CPU modifies the target logical address carried in the read request to the target bus address.

[0100] The bus address is the address uniformly assigned to all memory spaces of a computing device, including those of remote storage devices. Therefore, there is a correspondence between the bus address and the physical address of the remote storage device. Since the correspondence between the target logical address and the target bus address is maintained by the MMU in the CPU, to subsequently determine the physical address of the remote storage device corresponding to the target bus address, the CPU can change the target logical address carried in the read request to the target bus address before sending the task to the DMA controller. This avoids the DMA controller repeatedly maintaining the address mapping table in the MMU, reducing resource waste.

[0101] S102c: The CPU adds a read request carrying the target bus address to the task queue, instructing the DMA controller to retrieve and process the read request carrying the target bus address from the task queue.

[0102] In one implementation, a task queue is set up for the DMA controller. The CPU sends tasks that need to be processed by the DMA controller to the task queue through a pre-defined asynchronous data transfer interface. Subsequently, the DMA controller can retrieve tasks from the task queue to process read requests sent by the CPU.

[0103] S102c is one implementation of the CPU instructing the DMA controller to process a read request. Optionally, the CPU can also send the read request to the DMA controller via the bus so that the DMA controller can process the read request.

[0104] In this embodiment, a task queue is set up in the CPU for the DMA controller. The CPU can send all the tasks that need to be processed to the task queue, avoiding waiting for the DMA controller to finish processing one task before sending the next task. Therefore, after setting up the task queue, the CPU can send tasks to the DMA controller in batches, improving task processing efficiency.

[0105] For details on how the DMA controller handles read requests, see S201-S208.

[0106] S103 (optional): The CPU returns to the user-mode program.

[0107] In one implementation, a preset signal (e.g., "put_cpu") is set in the kernel-mode program, and the CPU can receive this preset signal through a signal interface (e.g., send_sig). After the CPU adds the read request to the task queue, it returns from the kernel-mode program to the user-mode program under the instruction of the preset signal.

[0108] In this implementation method, a preset signal is used to instruct the CPU to return from the kernel-mode program to the user-mode program. By setting the preset signal in the kernel-mode program, the CPU can quickly return to the user-mode program and continue processing other programs, thereby improving CPU utilization.

[0109] In one implementation, the CPU returns from the kernel-mode program to the task scheduler in the user-mode program.

[0110] The task scheduler is used to schedule the CPU to execute user-mode programs. Since the first program is currently experiencing a page fault, it needs to wait for the DMA controller to complete processing the read request. If the CPU returns to the first program at this time, it will repeatedly switch back and forth between user-mode and kernel-mode programs until the DMA controller completes processing the read request. Therefore, in order to avoid the overhead caused by the CPU switching back and forth between user-mode and kernel-mode programs, the CPU is set to return to the task scheduler. While the DMA controller is processing the read request, the task scheduler schedules the CPU to execute other programs to improve CPU utilization.

[0111] Optionally, when the CPU switches from a user-mode program to a kernel-mode program, the CPU cache will be cleared once each time it switches, which will cause the CPU cache to become contaminated. Therefore, returning the CPU to the task scheduler can reduce the degree of CPU cache contamination.

[0112] The following S104 describes the process by which the task scheduler schedules the CPU to execute other programs after the CPU returns to the task scheduler.

[0113] S104: The CPU responds to the task scheduler's scheduling and switches from the first program to the second program.

[0114] The second program is a program that runs in user mode, such as a thread or a coroutine within a thread.

[0115] In one implementation, the task scheduler provides a standard interface (e.g., pthread) for user-mode programs. When a page fault occurs in a user-mode program (the first program), the task scheduler schedules the CPU to switch to the second program.

[0116] S105: The CPU receives a message from the DMA controller indicating that the read request has been successfully processed, and switches from the second program to the first program.

[0117] When the DMA controller successfully processes a read request, it means that the data to be read has been migrated from the remote storage device to the CXL storage device. At this point, the DMA controller sends a message to the CPU that the read request has been successfully processed.

[0118] In one implementation, after the CPU receives a message from the DMA controller indicating that the read request has been successfully processed, the task scheduler switches the CPU from the second program to the first program.

[0119] S106: The CPU deletes the indicator flag from the entry containing the target logical address in the address mapping table.

[0120] After the CPU switches to the first program, due to a page fault in the address mapping table of the first program, the CPU jumps from the user-mode program to the interrupt handling unit of the kernel-mode program again. At this time, the CPU deletes the indicator mark in the entry of the target logical address in the address mapping table, indicating that the data to be read already exists in the CXL storage device.

[0121] For example, as shown in Table 1, if the target logical address is A1, the CPU deletes the "inaccessible" indicator from the entry where A1 is located. At this time, the entry where A1 is located can be accessed normally, and the CPU can read and write the memory space indicated by the target bus address corresponding to A1.

[0122] S107: The CPU reads data from the CXL storage device.

[0123] Specifically, the CPU reads the data to be read from the storage space indicated by the target bus address; where the storage space indicated by the target bus address is the storage space of the CXL storage device.

[0124] For example, the target bus address indicates the storage space in the CXL storage device. The MMU in the CPU translates the target bus address into the physical address of the storage space in the CXL storage device and reads the data to be read from that physical address.

[0125] In the method proposed in this application, after receiving a read request, the CPU hands the read request over to the DMA controller for execution. The CPU can then switch to other programs, avoiding being suspended during DMA controller execution and thus preventing resource waste. Furthermore, compared to related technologies, the CPU execution path no longer requires steps such as locking the page table, acquiring the Page Entrance Table (PTE), allocating page frames, and allocating page caches, thus shortening the processing path and improving data access efficiency.

[0126] like Figure 3 As shown, the CPU's execution process in the above process mainly includes steps one through three:

[0127] Step 1: The CPU responds to the read request from the first program and determines the storage space where the data to be read is located.

[0128] Step 2: When the storage space containing the data to be read is located on a remote storage device, the CPU instructs the DMA controller to process the read request, so that the DMA controller controls the migration of the data to be read from the remote storage device to the CXL storage device.

[0129] Step 3: The CPU receives a message from the DMA controller indicating that the read request has been successfully processed, and then reads the data to be read from the CXL storage device.

[0130] The following describes the process by which the DMA controller handles read requests under the instruction of the CPU, such as... Figure 4 As shown, Figure 4 A flowchart of the process for the DMA controller to process read requests, which includes: S201-S208.

[0131] S201: The DMA controller obtains a read request from the queue of pending tasks.

[0132] Tasks in the pending task queue can be issued by the CPU, and read requests are used to read data from the memory space indicated by the target bus address.

[0133] For example, the read request obtained by the DMA controller includes: the target bus address and the length of the data to be read.

[0134] S202: The DMA controller sends a read request to the CXL storage device, and correspondingly, the CXL controller of the CXL storage device receives the read request sent by the DMA controller of the computing device.

[0135] The purpose of the DMA controller sending a read request to the CXL storage device is to enable the CXL controller of the CXL storage device to migrate the data to be read from the remote storage device to the CXL storage device when the storage space indicated by the target bus address is the storage space of the remote storage device.

[0136] In one implementation, the CXL controller has RDMA functionality, enabling it to directly read data from the storage space of a remote storage device. Upon receiving a read request, the CXL controller parses the target bus address and the length of the data to be read from the request.

[0137] S203: The CXL controller determines the memory space indicated by the target bus address.

[0138] If the target bus address indicates that the storage space is the first storage space in the CXL storage device, then S207 is executed.

[0139] If the target bus address indicates that the storage space is the second storage space in the remote storage device, then S204 is executed.

[0140] Regarding S203, this application embodiment proposes a specific method for determining the storage space indicated by the target bus address, including: the CXL controller determining the mapping address corresponding to the target bus address.

[0141] When the mapped address corresponding to the target bus address is the address of the first storage space, the storage space indicated by the target bus address is the first storage space;

[0142] When the mapped address corresponding to the target bus address is the address of the second storage space, the storage space indicated by the target bus address is the second storage space.

[0143] In one implementation, the CXL controller maintains a target address mapping table to store the mapping relationship between bus addresses and the physical addresses of the storage space of the CXL storage device, or the mapping relationship between bus addresses and the physical addresses of the storage space of a remote storage device. Based on the target address mapping table, the CXL controller determines the mapped address corresponding to the target bus address.

[0144] For example, as shown in Table 2, Table 2 illustrates a target address mapping table that includes a mapping relationship between "bus address" and "physical address". The physical address includes the physical address of the storage space of the CXL storage device and the physical address of the storage space of the remote storage device.

[0145] Table 2

[0146] Bus address physical address B1 C1 (the physical address of the storage space of the CXL storage device) B2 C2 (the physical address of the storage space of the CXL storage device) B3 D1 (The physical address of the storage space on the remote storage device) B4 D2 (Physical address of the storage space on the remote storage device)

[0147] After receiving a read request from the computing device, the CXL controller looks up the physical address corresponding to the target bus address in the target address mapping table. After finding the physical address corresponding to the target bus address, it further confirms whether the physical address belongs to the storage space of the CXL storage device or the storage space of the remote storage device.

[0148] For example, if the target bus address is B1 in Table 2, then the physical address corresponding to the target bus address is confirmed to be C1, which is the physical address of the first storage space of the CXL storage device. If the target bus address is B3 in Table 2, then the physical address corresponding to the target bus address is confirmed to be D1, which is the physical address of the second storage space of the remote storage device.

[0149] In another implementation, the CXL controller maintains in two address mapping tables the mapping relationship between the bus address and the physical address of the storage space of the CXL storage device, and the mapping relationship between the bus address and the physical address of the storage space of the remote storage device.

[0150] After receiving a read request from the computing device, the CXL controller first checks the address mapping table, which maps storage bus addresses to the physical addresses of CXL storage devices, to see if the target bus address is included. If the target bus address is included, it means that the physical address corresponding to the target bus address indicates the first storage space of the CXL storage device. If the target bus address is not included, the controller continues to check the address mapping table, which maps storage bus addresses to the physical addresses of remote storage devices, to see if the target bus address is included. If the target bus address is included, it means that the physical address corresponding to the target bus address indicates the second storage space of the remote storage device.

[0151] In the first implementation, a single address mapping table simultaneously maps the bus address to the physical address of the CXL storage device's storage space and the bus address to the physical address of the remote storage device's storage space. The CXL controller only needs to query one table, reducing operations and improving query efficiency. In the second implementation, two separate address mapping tables store the mappings between the bus address and the physical address of the CXL storage device's storage space, and between the bus address and the physical address of the remote storage device's storage space, allowing for clearer management of these two mapping relationships.

[0152] During this process, after receiving a read request, the CXL controller reconfirms the storage space indicated by the target bus address carried in the read request. This ensures the accuracy of the storage space indicated by the target bus address, preventing errors in the indication markers in Table 1 that could lead to failure in reading the data to be read, and improving the success rate of reading the data to be read.

[0153] S204: The CXL controller determines whether the available storage capacity of the CXL storage device is less than the required storage capacity.

[0154] If the available storage capacity of the CXL storage device is less than the required storage capacity, then execute S205 first, and then execute S206.

[0155] If the available storage capacity of the CXL storage device is greater than or equal to the required storage capacity, then execute S206.

[0156] Available storage space is the unused storage space in the CXL storage device, and required storage capacity is the storage capacity needed to store the data to be read.

[0157] In one implementation, the CXL controller records the usage status of the CXL storage device's storage space, including whether it is used or unused, as well as the physical address and storage capacity of the used storage space, and the physical address and storage capacity of the unused storage space. "Used" indicates that the storage space has stored data, while "unused" indicates that the storage space does not store data. Based on the recorded storage space usage status of the CXL storage device, the CXL controller determines whether the storage capacity of the unused (i.e., usable) storage space is less than the required storage capacity.

[0158] For example, as shown in Table 3, Table 3 shows the usage of the storage space of the CXL storage device recorded by the CXL controller. Table 3 includes: "physical address", "storage capacity" and "usage status", where "physical address" is the physical address of the storage space of the CXL storage device, "storage capacity" is the storage capacity of the storage space corresponding to the "physical address", and "usage status" is the usage status of the storage space corresponding to the "physical address", including whether it is used or not.

[0159] Table 3

[0160]

[0161] As shown in Table 3, the total storage capacity of the CXL storage device is 2GB, of which 1GB + 512MB is used and 512MB is unused. If the storage capacity required to store the data to be read is less than or equal to 512MB, then the available storage capacity of the CXL storage device is greater than or equal to the required storage capacity. Conversely, if the storage capacity required to store the data to be read is greater than or equal to 512MB, then the available storage capacity of the CXL storage device is less than the required storage capacity.

[0162] S205: The CXL controller migrates data from the third storage space of the CXL storage device to a remote storage device so that the storage capacity of the currently available storage space of the CXL storage device is greater than or equal to the required storage capacity.

[0163] The currently available storage space is the sum of the storage capacity of the third storage space and the storage capacity of the available storage space.

[0164] In one implementation, if the sum of the storage capacity of multiple storage spaces and the available storage capacity in the CXL storage device is greater than or equal to the required storage capacity, the CXL controller can select any one of the storage spaces as the third storage space, or select the storage space with the lowest data access frequency, or whose data access frequency is less than or equal to a frequency threshold, as the third storage space. The access frequency includes the frequency at which the computing device reads data, for example, once a day.

[0165] In one implementation, the CXL controller maintains a data access frequency list, which includes the access frequency of data stored in each storage space of the CXL storage device. The CXL controller periodically updates the data access frequency list based on the least recently used (LRU) algorithm and determines the third storage space of the CXL storage device.

[0166] The LRU algorithm is a memory eviction algorithm. The principle of this algorithm is to evict the least recently used data in memory when the memory space is below a threshold.

[0167] For example, as shown in Table 4, Table 4 is a list of data access frequencies maintained by the CXL controller. This list includes: "physical address", "storage capacity" and "data access frequency", where "data access frequency" is the access frequency of the data stored in the storage space corresponding to the "physical address".

[0168] Table 4

[0169] physical address Storage capacity Data access frequency C1 1G Once a day C2 1G Once every two days C3 2G once every three days C4 3G Once a week

[0170] As can be seen from the data access frequency shown in Table 4 above, the storage space indicated by C4 has the lowest access frequency. Therefore, C4 can be identified as the third storage space.

[0171] The data access frequency list shown in Table 4 above is only an example, and the actual implementation is not limited to this.

[0172] After migrating data from the third storage space to the remote storage device, the CXL controller updates the maintained data access frequency list. In this embodiment, the data access frequency list is maintained by the CXL controller. Compared to the related technology where the CPU maintains the list, this further reduces the length of the critical path during CPU processing and further reduces CPU overhead.

[0173] Optionally, in one implementation, the CXL controller migrates data from the third storage space of the CXL storage device to the fifth storage space of the remote storage device, and the CXL controller establishes a mapping relationship between the bus address corresponding to the physical address of the third storage space and the physical address of the fifth storage space.

[0174] Optionally, after migrating data from the third storage space to the fifth storage space of the remote storage device, the CXL controller removes the mapping between the physical address of the third storage space and the bus address corresponding to that third storage space. For example, the CXL controller deletes the mapping between the physical address of the third storage space and the bus address corresponding to that third storage space from the address mapping table.

[0175] The fifth storage space is part or all of the available storage space in a remote storage device.

[0176] For example, as shown in Table 2, if the third storage space is the storage space indicated by C2 in Table 2, then the bus address corresponding to the third storage space is B2 in Table 2. After the CXL controller migrates the data in the storage space indicated by C2 to the storage space indicated by D3 of the remote storage device (the fifth storage space), it stores the mapping relationship between the bus address B2 corresponding to the third storage space and the physical address D3 of the fifth storage space in the target address mapping table shown in Table 2, and deletes the mapping relationship between the third storage space C2 and the bus address B2 corresponding to the third storage space. Table 2 is then updated to Table 5 accordingly.

[0177] Table 5

[0178] Bus address physical address B1 C1 (the physical address of the storage space of the CXL storage device) B2 D3 (Physical address of the storage space of the CXL storage device) B3 D1 (The physical address of the storage space on the remote storage device) B4 D2 (Physical address of the storage space on the remote storage device)

[0179] It is understandable that by establishing a mapping relationship between the bus address corresponding to the physical address of the third storage space and the physical address of the fifth storage space, when a computing device needs to read this part of the data, it can quickly find the data in the fifth storage space of the remote storage device through this mapping relationship, thereby improving the efficiency of reading data and reducing waiting time.

[0180] S206: The CXL controller migrates data from the second storage space to the CXL storage device.

[0181] Specifically, the CXL controller migrates the data to be read to the fourth storage space of the CXL storage device; the fourth storage space is part or all of the currently available storage space.

[0182] Optionally, the CXL controller stores the mapping between the target bus address and the physical address of the fourth memory space.

[0183] The CXL controller stores the mapping relationship between the target bus address and the physical address of the fourth memory space in the target address mapping table. When the CPU subsequently reads data from the memory space indicated by the target bus address, it can determine the mapped address corresponding to the target bus address as the physical address of the fourth memory space from this mapping relationship. For example, in S107, when the CPU reads data from the memory space indicated by the target bus address, it can read the data from the fourth memory space of the CXL storage device through this mapping relationship between the target bus address and the physical address of the fourth memory space. Therefore, storing the mapping relationship between the target bus address and the physical address of the fourth memory space can improve data reading efficiency.

[0184] S207: The CXL controller sends a message to the DMA controller that the data to be read has been successfully migrated.

[0185] S208: After receiving the message from the CXL controller that the migration of the data to be read was successful, the DMA controller sends a message to the CPU that the read request was successfully processed, so that the CPU can read the data to be read from the CXL storage device.

[0186] Specifically, the DMA controller sends a feedback message to the CPU via an interrupt, indicating that the read request has been successfully processed. Upon receiving this message, the CPU stops the currently executing program and jumps from the user-mode program to the kernel-mode program to read the data to be read.

[0187] Optionally, the task queue includes multiple tasks to be processed. After the DMA controller processes multiple tasks, it sends a feedback message to the CPU via an interrupt to indicate that the task has been successfully processed. Upon receiving the message, the CPU jumps from the user-mode program to the kernel-mode program to process the multiple data access requests in a unified manner.

[0188] In this optional approach, the DMA controller can send a task processing success feedback message to the CPU after processing a portion of the tasks in batches, thereby reducing the number of times the CPU switches back and forth between user-mode and kernel-mode programs, reducing program switching overhead, and saving CPU resources.

[0189] In a data access method proposed in this application embodiment, after the application (first program) initiates a read request, the CPU first determines the storage space where the data to be read is located. If the data to be read is in a remote storage device, the CPU instructs the DMA controller to handle the read request. After the DMA controller successfully migrates the data to be read from the remote storage device to the local CXL storage device, the CPU then reads the data from the CXL storage device. It can be understood that in this process, after receiving the read request from the application, the CPU only needs to determine the location of the data to be read before handing the read request over to the DMA controller for processing. This reduces the number of CPU processing steps, thereby reducing the critical path in the CPU processing and improving access speed. Furthermore, the method includes two steps: the first step is a synchronous process in the CPU foreground to determine the storage space where the data to be read is located; the second step involves the DMA controller asynchronously processing the read request, which reduces CPU overhead. The simultaneous execution of the foreground synchronous process and the background asynchronous process improves access efficiency.

[0190] The foregoing primarily describes the solutions provided by the embodiments of this application from a methodological perspective. To achieve the aforementioned functions, it includes corresponding hardware structures and / or software modules for executing each function. Those skilled in the art should readily recognize that, in conjunction with the units and algorithm steps of the various examples described in the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0191] This application embodiment also provides a processor 200, for example Figure 1 CPU111 in the example. Figure 5 The diagram shown is a structural schematic of a processor 200 provided in an embodiment of this application.

[0192] The processor 200 includes: a processing unit 201, configured to, in response to a read request from a first program, determine the storage space where the data to be read is located; the data to be read is the data to be read by the read request; and, if the storage space where the data to be read is located is a remote storage device, instruct the DMA controller to process the read request so that the DMA controller controls the data to be read to be migrated from the remote storage device to the CXL storage device; and a receiving unit 202, configured to receive a message from the DMA controller indicating that the read request has been successfully processed, and read the data to be read from the CXL storage device.

[0193] In some implementations, the read request carries the target logical address of the storage space where the data to be read is located. The processing unit 201 is specifically used to determine that the storage space where the data to be read is located is located in a remote storage device when there is an indication flag in the entry of the target logical address in the address mapping table. The address mapping table includes a mapping relationship between the target logical address and the target bus address, and the indication flag is used to indicate that the storage space indicated by the bus address corresponding to the logical address is located in a remote storage device.

[0194] In some embodiments, the processing unit 201 is further configured to, after receiving a message from the DMA controller indicating that the read request has been successfully processed, delete the indicator flag in the entry where the target logical address is located in the address mapping table; and read the data to be read from the storage space indicated by the target bus address; wherein the storage space indicated by the target bus address is the storage space of the CXL storage device.

[0195] In some implementations, the read request carries the target logical address of the storage space where the data to be read is located; the processing unit 201 is specifically used to obtain the target bus address corresponding to the target logical address, modify the target logical address carried in the read request to the target bus address, and add the read request carrying the target bus address to the task queue to instruct the DMA controller to obtain and process the read request carrying the target bus address from the task queue.

[0196] In some embodiments, the processing unit 201 is further configured to, after instructing the DMA controller to process the read request, switch from the first program to the second program in response to the scheduling of the task scheduler; and after receiving a message from the DMA controller that the read request processing was successful, switch from the second program to the first program.

[0197] This application also provides a DMA controller 300, for example... Figure 1 The DMA controller 112 in the middle. For example... Figure 6 The diagram shown is a structural schematic of a controller 300 provided in an embodiment of this application.

[0198] The DMA controller 300 includes: a processing unit 301, used to obtain read requests from a task queue; the tasks in the task queue are issued by the CPU, and the read requests are used to read data to be read from the storage space indicated by the target bus address; a sending unit 302, used to send read requests to the CXL storage device, so that the CXL controller of the CXL storage device migrates the data to be read from the remote storage device to the CXL storage device when the storage space indicated by the target bus address is the storage space of the remote storage device; and a receiving unit 303, used to receive a message from the CXL controller indicating that the migration of the data to be read was successful, and then send a message to the CPU indicating that the read request was successfully processed, so that the CPU reads the data to be read from the CXL storage device.

[0199] This application also provides a CXL controller 400, for example... Figure 1 The CXL controller 121 in the example. Figure 7 The diagram shown is a structural schematic of a CXL controller 400 provided in an embodiment of this application.

[0200] The CXL controller 400 includes: a receiving unit 401, used to receive a read request sent by the DMA controller of the computing device; the read request is used to request to read data to be read from the storage space indicated by the target bus address; a sending unit 402, used to send a message to the DMA controller that the data to be read has been successfully migrated when the storage space indicated by the bus address is the first storage space in the CXL storage device; and a processing unit 403, used to migrate the data in the second storage space to the CXL storage device when the storage space indicated by the target bus address is the second storage space in the remote storage device, and send a message to the DMA controller that the data to be read has been successfully migrated.

[0201] In some implementations, the CXL storage device stores the mapping relationship between the storage bus address and the physical address of the storage space of the CXL storage device, or the mapping relationship between the CXL storage device's storage bus address and the physical address of the storage space of the remote storage device. After receiving a read request sent by the DMA controller of the computing device, the processing unit 403 is further configured to determine the storage space indicated by the target bus address; when the mapping address corresponding to the target bus address is the address of the first storage space, the storage space indicated by the target bus address is the first storage space; when the mapping address corresponding to the target bus address is the address of the second storage space, the storage space indicated by the target bus address is the second storage space.

[0202] In some embodiments, before migrating the data in the second storage space to the CXL storage device, the processing unit 403 is further configured to migrate the data in the third storage space of the CXL storage device to a remote storage device when the storage capacity of the available storage space of the CXL storage device is less than the required storage capacity, so that the storage capacity of the currently available storage space of the CXL storage device is greater than or equal to the required storage capacity; wherein, the required storage capacity is the storage capacity required to store the data to be read, and the currently available storage space is the sum of the storage capacity of the third storage space and the storage capacity of the available storage space; specifically, the processing unit 403 is configured to migrate the data in the second storage space to the fourth storage space of the CXL storage device; the fourth storage space is part or all of the storage space in the currently available storage space.

[0203] In some implementations, the processing unit 403 is also used to store the mapping relationship between the target bus address and the physical address of the fourth memory space.

[0204] Of course, the processor 200, DMA controller 300 or CXL controller 400 provided in the embodiments of this application include, but are not limited to, the above-mentioned modules.

[0205] Another embodiment of this application provides a processor coupled to a memory; the memory stores computer program code, which includes computer instructions. When the processor executes the computer instructions, it performs the steps of the data access method shown in the above-described method embodiments.

[0206] Another embodiment of this application provides a computer-readable storage medium storing computer instructions that, when executed on a processor, cause the processor to perform various steps of the data access method flow shown in the above method embodiment.

[0207] Another embodiment of this application provides a chip system applied to a processor. The chip system includes one or more interface circuits. The interface circuits and the processor are interconnected via lines. The interface circuits are used to receive signals from memory coupled to the processor and to send signals to the processor, the signals including computer instructions stored in the memory. When the processor executes the computer instructions, the processor performs the various steps of the data access method flow shown in the above method embodiments.

[0208] In another embodiment of this application, a computer program product is also provided, which includes computer instructions that, when executed on a processor, cause the processor to perform the various steps of the data access method flow shown in the above method embodiments.

[0209] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any combination thereof. When implemented using software programs, the above embodiments can be implemented, in whole or in part, as a computer program product. This computer program product includes one or more computer instructions. When these computer instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a server, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device containing one or more servers, data centers, etc., that can be integrated with the medium. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state disks, SSDs).

[0210] The above description is merely a specific embodiment of this application. Any variations or substitutions conceived by those skilled in the art based on the specific embodiments provided in this application should be covered within the protection scope of this application.

Claims

1. A data access method, characterized in that, A central processing unit (CPU) applied to a computing device, the CPU being connected to a CXL storage device via a Compute Interconnect Protocol (CXL) bus, the CXL storage device being connected to a remote storage device via a network, the method comprising: In response to a read request from the first program, the storage space where the data to be read is located is determined; the data to be read is the data to be read by the read request. If the storage space containing the data to be read is located on a remote storage device, instruct the Direct Memory Access (DMA) controller to process the read request so that the DMA controller controls the migration of the data to be read from the remote storage device to the CXL storage device; The system receives a message from the DMA controller indicating that the read request has been successfully processed, and then reads the data to be read from the CXL storage device.

2. The method according to claim 1, characterized in that, The read request carries the target logical address of the storage space where the data to be read is located, and determining the storage space where the data to be read is located includes: When an indicator flag exists in the entry of the target logical address in the address mapping table, it is determined that the storage space where the data to be read is located is located in the remote storage device; wherein, the address mapping table includes a mapping relationship between the target logical address and the target bus address, and the indicator flag is used to indicate that the storage space indicated by the bus address corresponding to the logical address is located in the remote storage device.

3. The method according to claim 2, characterized in that, After receiving the message from the DMA controller indicating that the read request was successfully processed, the method further includes: Delete the indicator flag in the entry containing the target logical address in the address mapping table; Reading the data to be read from the CXL storage device includes: The data to be read is read from the storage space indicated by the target bus address; wherein the storage space indicated by the target bus address is the storage space of the CXL storage device.

4. The method according to claim 1, characterized in that, The read request carries the target logical address of the storage space where the data to be read is located; The instruction to the DMA controller to process the read request includes: Obtain the target bus address corresponding to the target logical address, modify the target logical address carried in the read request to the target bus address, and add the read request carrying the target bus address to the task queue to instruct the DMA controller to obtain and process the read request carrying the target bus address from the task queue.

5. The method according to any one of claims 1 to 4, characterized in that, After instructing the DMA controller to process the read request, the method further includes: In response to the scheduling of the task scheduler, switch from the first program to the second program; After receiving the message from the DMA controller indicating that the read request was successfully processed, the method further includes: Switch from the second program to the first program.

6. A data access method, characterized in that, A direct memory access (DMA) controller for a computing device, wherein the central processing unit (CPU) of the computing device is connected to a CXL storage device via a compute interconnect protocol (CXL) bus, and the CXL storage device is connected to a remote storage device via a network, the method comprising: A read request is obtained from the task queue to be processed; the tasks in the task queue to be processed are issued by the CPU, and the read request is used to read the data to be read from the storage space indicated by the target bus address; Send the read request to the CXL storage device so that the CXL controller of the CXL storage device will migrate the data to be read from the remote storage device to the CXL storage device if the storage space indicated by the target bus address is the storage space of the remote storage device. After receiving a message from the CXL controller indicating that the migration of the data to be read was successful, the CPU sends a message indicating that the read request was successfully processed, so that the CPU can read the data to be read from the CXL storage device.

7. A data access method, characterized in that, A CXL controller applied to a Compute Interconnect Protocol (CXL) storage device, wherein the CXL storage device is connected to the central processing unit (CPU) of a computing device via a CXL bus, and the CXL storage device is connected to a remote storage device via a network, the method comprising: The system receives a read request sent by the Direct Memory Access (DMA) controller of the computing device; the read request is used to request the reading of data to be read from the storage space indicated by the target bus address. If the storage space indicated by the bus address is the first storage space in the CXL storage device, a message indicating that the migration of the data to be read has been successfully sent to the DMA controller; If the storage space indicated by the target bus address is the second storage space in the remote storage device, the data in the second storage space is migrated to the CXL storage device, and a message indicating that the migration of the data to be read is successful is sent to the DMA controller.

8. The method according to claim 7, characterized in that, The method further includes, after receiving a read request sent by the DMA controller of the computing device, the mapping relationship between the CXL storage device's storage bus address and the physical address of the CXL storage device's storage space, or the mapping relationship between the CXL storage device's storage bus address and the physical address of the remote storage device's storage space: Determine the storage space indicated by the target bus address; When the mapped address corresponding to the target bus address is the address of the first storage space, the storage space indicated by the target bus address is the first storage space; When the mapped address corresponding to the target bus address is the address of the second storage space, the storage space indicated by the target bus address is the second storage space.

9. The method according to claim 7 or 8, characterized in that, Prior to migrating the data in the second storage space to the CXL storage device, the method further includes: When the available storage capacity of the CXL storage device is less than the required storage capacity, the data in the third storage space of the CXL storage device is migrated to the remote storage device so that the current available storage capacity of the CXL storage device is greater than or equal to the required storage capacity; wherein, the required storage capacity is the storage capacity required to store the data to be read, and the current available storage space is the sum of the storage capacity of the third storage space and the storage capacity of the available storage space; The step of migrating data from the second storage space to the CXL storage device includes: The data in the second storage space is migrated to the fourth storage space of the CXL storage device; the fourth storage space is part or all of the currently available storage space.

10. The method according to claim 9, characterized in that, The method further includes: The mapping relationship between the target bus address and the physical address of the fourth memory space is stored.

11. A processor, characterized in that, The processor is coupled to a memory for storing programs or instructions that, when executed by the processor, cause the processor to perform the method as described in any one of claims 1 to 5.

12. A Computational Interconnect Protocol (CXL) controller, characterized in that, The system includes a processor coupled to a memory for storing programs or instructions that, when executed by the processor, cause the CXL controller to perform the method as described in any one of claims 7 to 10.

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