Pixel and pixel driving method

Abstract

The present invention relates to a pixel and a driving method thereof, the pixel including: a first transistor electrically connected between a first power supply and a fourth node, and including a gate electrode electrically connected to the first node; a second transistor electrically connected between the third node and the data line, and turned on in response to a scan signal of the first polarity applied to the first scan line; a third transistor electrically connected between the first node and a fourth node and turned on in response to a scan signal of a second polarity applied to a third scan line, where the second polarity is opposite to the first polarity; a fourth transistor electrically connected between the second node and the initialization voltage, and turned on in response to a scan signal applied to a second scan line; a light emitting diode connected between the second node and a second power supply, and including an anode electrode electrically connected to the second node; a first capacitor connected between the third node and the first node; and a second capacitor connected between the first node and the second node.

Description

[0001] This application is a divisional application of a patent application with an application date of November 8, 2019, application number 201980096193.6, and invention name “Pixel, display device including pixels, and driving method for display device”. Technical Field

[0002] The present disclosure relates to a pixel, a display device including the pixel, and a method of driving the display device. Background Art

[0003] The display device includes pixels connected to data lines and scan lines. The pixels generally include a light emitting element and a driving transistor for controlling the amount of current flowing to the light emitting element. The driving transistor controls the amount of current flowing from a first driving power source through the light emitting element to a second driving power source in response to a data signal. In this case, the light emitting element generates light of a specific brightness corresponding to the amount of current from the driving transistor.

[0004] Currently, a method of achieving high brightness by setting the voltage of the second driving power supply to a low level or minimizing power consumption by driving the display device at a low frequency is used. However, when the second driving power supply is set to a low level or the display device is driven at a low frequency, a certain leakage current is generated from the gate electrode of the driving transistor. In this case, the voltage of the data signal cannot be maintained for a single frame, and therefore, an image with a desired brightness cannot be displayed. Summary of the invention

[0005] Technical issues The present disclosure relates to a pixel that can display an image with desired brightness by minimizing a leakage current from a gate electrode of a driving transistor, a display device including the pixel, and a method of driving the display device.

[0006] The present disclosure also relates to a pixel that can prevent degradation of a light emitting element and brightness deviation due to an IR drop of a driving power source, a display device including the pixel, and a method of driving the display device.

[0007] Technical Solution According to an embodiment of the present disclosure, a pixel includes: a first transistor connected between a first power supply and a fourth node and having a gate electrode connected to the first node; a second transistor connected between a third node and a data line and turned on in response to a scan signal supplied to an i-th first scan line, wherein i is a natural number; a third transistor connected between the first node and a fourth node and turned on in response to a scan signal supplied to an i-th third scan line; a fourth transistor connected between the second node and an initialization voltage and turned on in response to a scan signal supplied to an i-th second scan line; a first capacitor connected between the third node and the first node; a second capacitor connected between the first node and the second node; and an organic light emitting diode connected between the second node and the second power supply, wherein the third transistor may be an N-type transistor.

[0008] At least one of the second transistor and the fourth transistor may be an N-type transistor.

[0009] The fourth transistor may be an N-type transistor, and the i-th second scan line may be the same as the (i+1)-th third scan line.

[0010] The second transistor may be an N-type transistor, and the i-th first scan line may be the same as the i-th third scan line.

[0011] The fourth transistor may be an N-type transistor, and the i-th second scan line may be the same as the (i+1)-th third scan line.

[0012] The i-th second scan line may be the same as the (i+1)-th first scan line.

[0013] The pixel may further include: a fifth transistor connected between the reference voltage and the third node and turned on in response to a light emitting signal supplied to the light emitting control line; and a sixth transistor connected between the fourth node and the second node and turned on in response to the light emitting signal supplied to the light emitting control line.

[0014] The second transistor and the third transistor may be turned on in a first period, and the fourth transistor may be turned on in a second period after the first period.

[0015] The second transistor and the third transistor may be turned on in a first period, the fourth transistor may be turned on in a second period after the first period, and the fifth transistor and the sixth transistor may be turned on in an emission period after the second period.

[0016] According to an embodiment of the present disclosure, a display device includes: pixels connected to scan lines and data lines; a scan driver that supplies scan signals to the scan lines; and a data driver that supplies data signals to the data lines, wherein at least one of the pixels located on the i-th horizontal line includes (where i is a natural number): a first transistor connected between a first power supply and a fourth node and having a gate electrode connected to the first node; a second transistor connected between a third node and the data line and turned on in response to a scan signal supplied to an i-th first scan line, wherein i is a natural number; a third transistor connected between the first node and the fourth node and turned on in response to a scan signal supplied to an i-th third scan line; a fourth transistor connected between the second node and an initialization voltage and turned on in response to a scan signal supplied to an i-th second scan line; a first capacitor connected between the third node and the first node; a second capacitor connected between the first node and the second node; and an organic light emitting diode connected between the second node and the second power supply, wherein the third transistor may be an N-type transistor.

[0017] The scan driver may supply scan signals having one of a first polarity and a second polarity opposite to the first polarity to the i-th first to i-th third scan lines.

[0018] The display device may further include: an emission driver that supplies a light-emitting signal to the light-emitting control line, and the at least one pixel may further include: a fifth transistor that is connected between the reference voltage and the third node and is turned on in response to the light-emitting signal supplied to the light-emitting control line; and a sixth transistor that is connected between the fourth node and the second node and is turned on in response to the light-emitting signal supplied to the light-emitting control line.

[0019] The scan driver may set scan signals supplied to the i-th first scan line and the i-th third scan line to an on level in a first period, and set a scan signal supplied to the i-th second scan line to an on level in a second period after the first period.

[0020] The scan driver can set the scan signal supplied to the i-th first scan line and the i-th third scan line to an on-level in a first time period, set the scan signal supplied to the i-th second scan line to an on-level in a second time period after the first time period, and set the light-emitting signal to an on-level in an emission time period after the second time period.

[0021] According to an embodiment of the present disclosure, a method for driving a display device including a plurality of pixels, wherein at least one pixel located on an i-th horizontal line among the plurality of pixels includes (where i is a natural number): a first transistor connected between a first power supply and a fourth node and having a gate electrode connected to the first node; a second transistor connected between a third node and a data line and turned on in response to a scan signal supplied to an i-th first scan line, wherein i is a natural number; a third transistor connected between a first node and a fourth node and turned on in response to a scan signal supplied to an i-th third scan line; a fourth transistor connected between a second node and an initialization voltage and turned on in response to a scan signal supplied to an i-th second scan line; a first capacitor connected between the third node and the first node; a second capacitor connected between the first node and the second node; and an organic light emitting diode connected between the second node and the second power supply, the method comprising: turning on the second transistor and the third transistor in a first time period; and turning on the fourth transistor in a second time period after the first time period.

[0022] The third transistor may be an N-type transistor.

[0023] The at least one pixel may further include: a fifth transistor connected between the reference voltage and the third node and turned on in response to a light emitting signal supplied to the light emitting control line; and a sixth transistor connected between the fourth node and the second node and turned on in response to the light emitting signal supplied to the light emitting control line, and the method may further include: turning on the fifth transistor and the sixth transistor in an emission period after the second period.

[0024] Beneficial Effects According to the present disclosure, a pixel, a display device including the pixel, and a method of driving the display device can improve driving reliability and power consumption by minimizing leakage current from a gate electrode of a driving transistor.

[0025] In addition, a pixel, a display device including the pixel, and a method of driving the display device can improve degradation of a light emitting element and brightness deviation due to an IR drop of a driving power source. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a block diagram of a display device according to an embodiment of the present disclosure.

[0027] Figure 2 yes Figure 1 Schematic diagram of the scan driver shown in .

[0028] Figure 3 Shows from Figure 1 An example of a scan signal output by a scan driver is shown in FIG.

[0029] Figure 4 is a circuit diagram of a pixel according to the first embodiment of the present disclosure.

[0030] Figure 5 is a diagram for describing a high-frequency operation of a display device according to an embodiment of the present disclosure.

[0031] Figure 6 is a diagram for describing a low frequency operation according to an embodiment of the present disclosure.

[0032] Figure 7 is a timing chart showing a method of driving a display device according to a first embodiment of the present disclosure.

[0033] Figures 8 to 12 According to the embodiment of the present disclosure Figure 7 : The equivalent circuit of the pixel in each period of the timing diagram shown in .

[0034] Fig.13 is a circuit diagram of a pixel according to a second embodiment of the present disclosure.

[0035] Fig.14 is a timing diagram showing a method of driving a display device according to a second embodiment of the present disclosure.

[0036] Fig.15 is a circuit diagram of a pixel according to a third embodiment of the present disclosure.

[0037] Fig.16 is a timing diagram showing a method of driving a display device according to a third embodiment of the present disclosure.

[0038] Fig.17 is a circuit diagram of a pixel according to a fourth embodiment of the present disclosure.

[0039] Fig.18 is a timing diagram showing a method of driving a display device according to a fourth embodiment of the present disclosure.

[0040] Fig.19 is a circuit diagram of a pixel according to a fifth embodiment of the present disclosure.

[0041] Fig. 20 is a timing diagram showing a method of driving a display device according to a fifth embodiment of the present disclosure.

[0042] Fig.21 is a circuit diagram of a pixel according to a sixth embodiment of the present disclosure.

[0043] Fig. 22 is a timing diagram showing a method of driving a display device according to a sixth embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] Embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The same or similar reference numerals are used for the same elements in the accompanying drawings.

[0045] Figure 1 is a block diagram of a display device according to an embodiment of the present disclosure.

[0046] Reference Figure 1 , the display device 1 according to an embodiment of the present disclosure may include a timing controller 10 , a data driver 20 , a scan driver 30 , an emission driver 40 , and a display 50 .

[0047] The timing controller 10 can provide grayscale values ​​and control signals to the data driver 20 to adapt to the specifications of the data driver 20. The timing controller 10 can also provide a clock signal, a start scan signal, etc. to the scan driver 30 to adapt to the specifications of the scan driver 30. The timing controller 10 can also provide a clock signal, a stop light emission signal, etc. to the emission driver 40 to adapt to the specifications of the emission driver 40.

[0048] The data driver 20 may generate data voltages to be supplied to the data lines D1 to Dm using the grayscale values ​​and control signals received from the timing controller 10. For example, the data driver 20 may sample the grayscale values ​​using the clock signal and apply data voltages corresponding to the grayscale values ​​to the data lines D1 to Dm in units of pixel rows. m may be a natural number.

[0049] The scan driver 30 may receive a clock signal, a start scan signal, etc. from the timing controller 10 to generate scan signals to be supplied to the scan lines S11 to S1n, S21 to S2n, and S31 to S3n. n may be a natural number.

[0050] For example, the scan driver 30 may be configured in the form of a shift register, and may generate a scan signal in such a manner that a turn-on level pulse of a start scan signal is sequentially transmitted to a next stage under the control of a clock signal.

[0051] In various embodiments of the present disclosure, the scan driver 30 may provide a scan signal having a pulse of opposite polarity. The term polarity may refer to a logic level of a pulse. For example, the scan driver 30 may provide a scan signal having a first polarity to at least some of the first to third scan lines S11 to S1n, S21 to S2n, and S31 to S3n, and provide a scan signal having a second polarity opposite to the first polarity to some other scan lines. To this end, the scan driver 30 may have a first stage for providing a first polarity scan signal and a second stage for providing a second polarity scan signal.

[0052] In an embodiment, the first polarity scan signals provided to at least some of the first to third scan lines S11 to S1n, S21 to S2n, and S31 to S3n may have the same or different waveforms. Alternatively, the first polarity scan signals may have a time lag relationship.

[0053] In an embodiment, the second polarity scan signals provided to other ones of the first to third scan lines S11 to S1n, S21 to S2n, and S31 to S3n may have a phase opposite to that of one of the first polarity scan signals.

[0054] When the pulse has the first polarity, the pulse may have a gate-on voltage at a low level. When the gate-on voltage of the first polarity pulse is supplied to the gate electrode of the P-type transistor, the P-type transistor may be turned on. Assume that a voltage at a sufficiently high level compared to the gate electrode is applied to the source electrode of the P-type transistor. For example, the P-type transistor may be a P-channel metal oxide semiconductor (PMOS).

[0055] When the pulse has the second polarity, the pulse may have a gate-on voltage at a high level. When the gate-on voltage of the second polarity pulse is supplied to the gate electrode of the N-type transistor, the N-type transistor may be turned on. It is assumed that a voltage at a sufficiently low level compared to the gate electrode is applied to the source electrode of the N-type transistor. For example, the N-type transistor may be an N-channel metal oxide semiconductor (NMOS).

[0056] The emission driver 40 may receive a clock signal, a stop light emission signal, etc. from the timing controller 10 to generate a light emission signal to be provided to the light emission control lines E1 to En. For example, the emission driver 40 may sequentially provide a light emission signal having an off-level pulse to the light emission control lines E1 to En. For example, the emission driver 40 may be configured in the form of a shift register, and may generate a light emission signal in a manner of sequentially transmitting an off-level pulse of a stop light emission signal to a next light emission stage under the control of a clock signal.

[0057] The display 50 includes pixels PX. For example, the pixels PX may be connected to corresponding data lines, first to third scan lines S11 to S1n, S21 to S2n, and S31 to S3n, and a light emitting control line En.

[0058] Despite Figure 1, n first to third scan lines S11 to S1n, S21 to S2n, and S31 to S3n and n light emission control lines E1 to En are shown, but the present disclosure is not limited thereto. For example, in various embodiments of the present disclosure, according to the circuit structure of the pixel PX, the pixel located on the current horizontal line can be additionally connected to the scan line located on the previous horizontal line or the next horizontal line. To this end, a dummy scan line and / or a dummy light emission control line (not shown) can be additionally formed for the display 50.

[0059] Despite Figure 1 , the first scan lines S11 to S1n, the second scan lines S21 to S2n, and the third scan lines S31 to S3n are shown, but the disclosed technical concept is not limited thereto. For example, in various embodiments, only one or two of the first scan lines S11 to S1n, the second scan lines S21 to S2n, and the third scan lines S31 to S3n may be arranged for the display device 1 according to the circuit structure of the pixel PX.

[0060] In addition, despite the Figure 1 , the light emitting control lines E1 to En are shown, but the present disclosure is not limited thereto. For example, in various embodiments, an inverted light emitting control line (not shown) may be additionally formed according to the circuit structure of the pixel PX. The inverted light emitting control line may receive an inverted light emitting signal that is inverted to the light emitting signal.

[0061] Figure 2 yes Figure 1 The schematic diagram of the scan driver is shown in FIG. Figure 3 Shows from Figure 1 An example of a scan signal output by a scan driver is shown in FIG. Figure 2 and Figure 3 For example, n (n is a natural number equal to or greater than 2) stages ST are included in the scan driver 30. Although an embodiment in which the scan driver 30 supplies first scan signals SS11 to SS1n having a first polarity to the first scan lines S11 to S1n will now be described, the following description will also apply to other embodiments in which the scan driver 30 supplies second scan signals having a first polarity and third scan signals having a second polarity to the second scan lines S21 to S2n and the third scan lines S31 to S3n, respectively.

[0062] Reference Figure 2 In an embodiment of the present disclosure, the scan driver 30 includes a plurality of stages ST1 to STn. Each of the stages ST1 to STn is connected to one of the first scan lines S11 to S1n to supply the first scan signals SS11 to SS1n to the first scan lines S11 to S1n in response to the start scan signal GSP. Here, the i-th (i is a natural number) stage STi may supply the first scan signal SS1i to the i-th first scan line S1i.

[0063] The first stage ST1 supplies the first scan signal SS11 to the first scan line S11 connected to the first stage ST1 in response to the start scan signal GSP. The other stages ST2 to STn supply the scan signals SS12 to SS1n to the first scan lines (one of the first scan lines S12 to S1n) connected to the other stages ST2 to STn in response to the output signal (i.e., the first scan signal) supplied from their previous stage. For example, the i-th stage STi may supply the first scan signal SS1i to the i-th first scan line S1i in response to the first scan signal SS1i-1 supplied from the i-1-th stage STi-1.

[0064] Scan driver 30 may receive clock signals CLK1 and CLK2. Figure 2 An example of supplying the first clock signal CLK1 and the second clock signal CLK2 is shown in FIG. 3 , but the present disclosure is not limited thereto, and according to an embodiment, there may be more than two clock signals supplied to the scan driver 30 .

[0065] The first clock signal CLK1 and the second clock signal CLK2 are supplied to different stages ST. For example, the first clock signal CLK1 can be supplied to odd-numbered stages, and the second clock signal CLK2 can be supplied to even-numbered stages. The opposite is also possible. The first clock signal CLK1 and the second clock signal CLK2 can be supplied to the first scan lines S11 to S1n as the first scan signals SS11 to SS1n.

[0066] The first clock signal CLK1 and the second clock signal CLK2 are set as square wave signals that repeat a gate-on voltage (e.g., a low level) and a gate-off voltage (e.g., a high level). In a single cycle of the first clock signal CLK1 and the second clock signal CLK2, the gate-on voltage period may be set to be shorter than the gate-off voltage period. The gate-on voltage period may correspond to the width of the first scanning signals SS11 to SS1n, and the width of the first scanning signals SS11 to SS1n may be set differently according to the circuit structure of the pixel PX.

[0067] The first clock signal CLK1 and the second clock signal CLK2 may be set to signals having the same period (e.g., 2H) and phase shift. For example, the first clock signal CLK1 and the second clock signal CLK2 may be set to have phases in which one phase is shifted by half a period from the earlier clock signal. Specifically, when the first clock signal CLK1 and the second clock signal CLK2 are sequentially supplied, the phase of the second clock signal CLK2 may be shifted by half a period from the first clock signal CLK1.

[0068] As described above, in an embodiment of the present disclosure, the gate-on voltage period of the first clock signal CLK1 and the second clock signal CLK2 may be set to be shorter than the gate-off voltage period. For example, when the first clock signal CLK1 and the second clock signal CLK2 are set to have a period of 2H, the gate-on voltage period of the first clock signal CLK1 and the second clock signal CLK2 may be shorter than 1H. In the present embodiment, the first clock signal CLK1 and the second clock signal CLK2 may be set to be phase-shifted by half a period. Based on the clock signals CLK1 and CLK2 set as described above, the first scan signal SS1i output to the i-th first scan line S1i and the first scan signal SS1i+1 output to the i+1-th first scan line S1i+1 have the following characteristics: Figure 3 The waveform shown in .

[0069] For example, in various embodiments, when the gate-on voltage period is set equal to the gate-off voltage period in the first clock signal CLK1 and the second clock signal CLK2, the rising edge of the first scan signal SS1i output to the i-th first scan line S1i is in phase with the falling edge of the first scan signal SS1i+1 output to the i+1-th first scan line S1i+1.

[0070] In the following embodiments, it is assumed that the first scan signals SS11 to SS1n output to the first scan lines S11 to S1n have the following characteristics: Figure 3 However, the present invention is not limited thereto, and as will be described later, the waveform of the scanning line may be variously changed to the extent that it does not depart from the scope of the present disclosure.

[0071] Figure 4 is a circuit diagram of a pixel according to a first embodiment of the present disclosure. Figure 4 In the figure, for the convenience of explanation, the pixel PX located on the i-th horizontal line and connected to the j-th data line Dj is taken as an example.

[0072] Reference Figure 4 , the pixel PX includes first to sixth transistors T1 to T6, first and second capacitors C1 and C2, and an organic light emitting diode OLED.

[0073] The first transistor T1 is connected between the first driving power source ELVDD and the terminal of the sixth transistor T6 (i.e., the fourth node N4). The gate electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 can be turned on according to the voltage applied to the first node N1 to control the amount of current flowing from the first driving power source ELVDD to the organic light emitting diode OLED through the sixth transistor T6. In various embodiments of the present disclosure, the first transistor T1 can be referred to as a driving transistor.

[0074] The second transistor T2 is connected between the third node N3 and the data line Dj. The gate electrode of the second transistor T2 is connected to the i-th first scan line S1i. The second transistor T2 may be turned on in response to the first scan signal applied to the i-th first scan line S1i. When the second transistor T2 is turned on, the data signal applied to the data line Dj may be supplied to the third node N3.

[0075] The third transistor T3 is connected between the first node N1 and the fourth node N4. A gate electrode of the third transistor T3 is connected to the i-th third scan line S3i. The third transistor T3 may be turned on in response to a third scan signal applied to the i-th third scan line S3i.

[0076] The fourth transistor T4 is connected between the second node N2 and the initialization voltage Vint. The gate electrode of the fourth transistor T4 is connected to the i-th second scan line S2i. The fourth transistor T4 may be turned on in response to the second scan signal applied to the i-th second scan line S2i. When the fourth transistor T4 is turned on, the initialization voltage Vint may be applied to the second node N2 (i.e., the anode electrode of the organic light emitting diode OLED).

[0077] In various embodiments of the present disclosure, the initialization voltage Vint may have a voltage value lower than that of the second driving power source ELVSS. For example, the initialization voltage Vint may be -3.5V, but is not limited thereto.

[0078] The fifth transistor T5 is connected between the reference voltage Vref and the third node N3. The gate electrode of the fifth transistor T5 is connected to the light emission control line Ei. The fifth transistor T5 may be turned on in response to the light emission signal supplied to the light emission control line Ei. When the fifth transistor T5 is turned on, the reference voltage Vref may be applied to the third node N3. When the reference voltage Vref is applied to the third node N3, even when the first capacitor C1 floats, the voltage at the third node N3 may be stably maintained, and as a result, the gate voltage of the first transistor T1 (i.e., the voltage at the first node N1) may be stably maintained in combination with the second capacitor C2.

[0079] In various embodiments of the present invention, the reference voltage Vref may have a positive voltage value or a negative voltage value, but is not particularly limited to a specific value.

[0080] The sixth transistor T6 is connected between the fourth node N4 and the second node N2. The gate electrode of the sixth transistor T6 is connected to the light emission control line Ei. The sixth transistor T6 may be turned on in response to a light emission signal supplied to the light emission control line Ei. When the sixth transistor T6 is turned on, the fourth node N4 and the second node N2 may be electrically connected to each other.

[0081] The first capacitor C1 is connected between the first node N1 and the third node N3. The first capacitor C1 can store a voltage corresponding to the voltage difference between the first node N1 and the third node N3. In other words, the first capacitor C1 can control the voltage across the first node N1 and the third node N3. In various embodiments of the present disclosure, the first capacitor C1 can be referred to as a storage capacitor.

[0082] The second capacitor C2 is connected between the first node N1 and the second node N2. The second capacitor C2 may store a voltage corresponding to a voltage difference between the first node N1 and the second node N2. In other words, the second capacitor C2 may control the voltage across the first node N1 and the second node N2.

[0083] In various embodiments of the present disclosure, the second capacitor C2 can control the voltage at the second node N2 to correspond to the threshold voltage of the organic light emitting diode OLED, and control the voltage at the first node N1 together with the first capacitor C1 according to the voltage at the second node N2 being controlled. The threshold voltage of the organic light emitting diode OLED increases as the organic light emitting diode OLED deteriorates, and therefore, the amount of current required for the organic light emitting diode OLED to emit light with uniform brightness increases. In various embodiments of the present disclosure, the second capacitor C2 can control the voltages at the two terminals (the first node N1 and the second node N2) to correspond to the threshold voltage of the organic light emitting diode OLED during the data writing period as will be described later, and allows the voltage at the first node N1 to be controlled by reflecting the threshold voltage of the organic light emitting diode OLED during the emission period. Then, the gate-source voltage Vgs of the first transistor T1 is controlled, so that the amount of current flowing to the organic light emitting diode OLED can be controlled. Therefore, in the present disclosure, the degradation of the organic light emitting diode OLED is compensated, and the organic light emitting diode OLED can emit light with a desired brightness.

[0084] The organic light emitting diode OLED has an anode electrode connected to the second node N2 and a cathode electrode connected to the second driving power ELVSS. The second driving power ELVSS may be set to be lower than the first driving power ELVDD. In various embodiments of the present disclosure, the second driving power ELVSS may be set to -2.6V, but is not limited thereto.

[0085] The organic light emitting diode OLED may include an internal parasitic capacitor Coled (hereinafter, referred to as an organic capacitor). When the initialization voltage Vint is applied to the anode electrode of the organic light emitting diode OLED through the fourth transistor T4, the organic capacitor Coled is discharged, thereby improving the black representation capability of the pixel PX.

[0086] Specifically, the organic capacitor Coled is charged with a certain voltage corresponding to the current supplied for the previous frame period. Once the organic capacitor Coled is charged, the organic light emitting diode OLED can easily emit light even at a low current.

[0087] At the same time, a black data signal can be supplied to the pixel PX during the current frame period. When a black data signal is supplied, ideally, current should not be applied to the organic light emitting diode OLED. However, in the pixel PX composed of transistors, even if a black data signal is supplied, a certain leakage current is supplied to the organic light emitting diode OLED. In this case, when the organic capacitor Coled is in a charged state, the organic light emitting diode OLED emits very little light, thereby reducing the black performance capability.

[0088] On the other hand, as in the present disclosure, when the organic capacitor Coled is discharged by the initialization voltage Vint, even if a leakage current is applied to the organic light emitting diode OLED, the organic light emitting diode OLED is set to a non-emitting state. Therefore, in the present disclosure, the initialization voltage Vint can be used to discharge the organic capacitor Coled, thereby improving the black performance capability.

[0089] In such Figure 4 In the embodiment shown in , the pixel PX includes an oxide semiconductor thin film transistor and a low temperature polysilicon (LTPS) thin film transistor.

[0090] The oxide semiconductor thin film transistor includes a gate electrode, a source electrode and a drain electrode. The oxide semiconductor thin film transistor has an active layer formed with an oxide semiconductor. The oxide semiconductor can be set as an amorphous oxide semiconductor or a crystalline oxide semiconductor. The oxide semiconductor thin film transistor can be formed by an N-type transistor. The oxide semiconductor thin film transistor can be processed at low temperatures and has a lower charge mobility than the LTPS thin film transistor. The oxide semiconductor thin film transistor has good cut-off current characteristics.

[0091] The LTPS thin film transistor includes a gate electrode, a source electrode and a drain electrode. The LTPS thin film transistor may have an active layer formed of polysilicon. The LTPS thin film transistor may be formed of a P-type thin film transistor or an N-type thin film transistor. In the embodiments of the present disclosure, it is assumed that the LTPS thin film transistor is formed of a P-type transistor. The LTPS thin film transistor has high electron mobility and therefore has fast driving characteristics.

[0092] exist Figure 4 In the embodiment of the present invention, the third transistor T3 is formed by an oxide semiconductor thin film transistor, and the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are formed by LTPS thin film transistors. Figure 4 In the embodiment of the present invention, the first scan signal and the second scan signal supplied to the gate electrodes of the second transistor T2 and the fourth transistor T4 have the first polarity, and the third scan signal supplied to the third transistor T3 has the second polarity.

[0093] In various embodiments of the present disclosure, the third transistor T3 is formed of a semiconductor thin film transistor (ie, an N-type transistor) having good cut-off current characteristics. Therefore, when the first transistor T1 is driven to apply current from the first driving power source ELVDD to the organic light emitting diode OLED via the sixth transistor T6, leakage current generated through the third transistor T3 can be effectively prevented.

[0094] However, the present disclosure is not limited thereto, and transistors of the pixel PX may be variously arranged, and a signal supplied to the pixel PX may be changed accordingly.

[0095] Figure 5 is a diagram for describing a high-frequency operation of a display device according to an embodiment of the present disclosure, and Figure 6 is a diagram for describing a low frequency operation according to an embodiment of the present disclosure.

[0096] When the display device operates in a high-frequency driving method, the display device can be expressed as being in a first driving mode. In addition, when the display device operates in a low-frequency driving method, the display device can be expressed as being in a second driving mode.

[0097] The first driving mode may be a normal driving mode. Specifically, when a user uses the display device, frames may be displayed at 20 Hz or higher (eg, 60 Hz).

[0098] The second driving mode may be a low power driving mode. For example, when the user is not using the display device, the frame may be displayed at less than 20 Hz (e.g., 1 Hz). For example, a situation where only the time and date are displayed in the "always-on mode" of the business model may correspond to the second driving mode.

[0099] In the first driving mode, a cycle may include a plurality of frames. For comparison with the second driving mode, a cycle is an arbitrarily defined period of time. A cycle may refer to the same time interval in the first driving mode and the second driving mode.

[0100] In the first driving mode, each frame may include a data writing period WP and an emission period EP.

[0101] In the second driving mode, the first frame in one cycle includes a data writing period WP and an emission period EP, and the other frames in one cycle each include an emission period EP. The pixel PX can display the same image during one cycle based on the data voltage applied during the data writing period WP of the first frame in one cycle.

[0102] Refer to Figure 4 During the data writing period WP in the first driving mode and the second driving mode, the first to third scan signals may be supplied to the i-th first to third scan lines S1i, S2i, and S3i, the data signal may be supplied to the data line Dj, and in response, the voltages for the first to third nodes N1 to N3 and the first and second capacitors C1 and C2 may be set. During the emission period EP in the first driving mode and the second driving mode, the light emission signal is supplied to the light emission control line Ei, and the organic light emitting diode OLED may emit light based on the voltages of the first to third nodes N1 to N3 and the first and second capacitors C1 and C2 set during the data writing period WP.

[0103] Figure 7 is a timing diagram showing a method of driving a display device according to a first embodiment of the present disclosure, and Figures 8 to 12 According to the embodiment of the present disclosure Figure 7 : The equivalent circuit of the pixel in each period of the timing diagram shown in .

[0104] exist Figures 7 to 12 In the figure, it is shown that Figure 5 The high frequency operation shown in Figure 6 The operation in any frame including the data writing period WP and the transmission period EP in the low frequency operation shown in . The arbitrary frame may be one of a plurality of frames constituting one cycle in the high frequency operation or the first frame of a plurality of frames constituting one cycle in the low frequency operation.

[0105] In addition, Figures 7 to 12 In the example, the driver Figure 4 The method of the pixel PX located on the i-th horizontal line and connected to the j-th data line Dj shown in FIG. 1 is taken as a representative example. Figure 7 , scan signals supplied to the i-th first scan line to the i-th third scan line S1i, S2i, and S3i, a light emitting signal supplied to the light emitting control line Ei, and a data signal supplied to the data line Dj are shown as examples. In the first embodiment of the present disclosure, a scan signal having a first polarity may be supplied to the i-th first scan line S1i and the i-th second scan line S2i, and a scan signal having a second polarity may be supplied to the i-th third scan line S3i.

[0106] In various embodiments of the present disclosure, the data write period WP may include a first period P1, a second period P2, a third period P3, and a fourth period P4. In various embodiments, a voltage corresponding to a data signal and a voltage for compensating for a threshold voltage of the organic light emitting diode OLED may be written to the pixel PX in the first period P1. During the third period P3, a voltage of an anode of the organic light emitting diode OLED may be initialized. During the emission period EP, the organic light emitting diode OLED may emit light based on the data voltage written in the data write period WP and the threshold voltage compensation value for the organic light emitting diode OLED.

[0107] The driving method in the data writing period WP and the emission period EP will now be described in detail.

[0108] Refer to Figure 4 , Figure 7 and Figure 8 During the first period P1, a low-level first scan signal is supplied to the i-th first scan line S1i, and a high-level second scan signal and a third scan signal are supplied to the i-th second scan line S2i and the i-th third scan line S3i, respectively. In response to the first scan signal and the third scan signal, the second transistor T2 and the third transistor T3 are turned on, respectively, and in response to the second scan signal, the fourth transistor T4 is turned off.

[0109] In addition, during the first period P1, a light emitting signal of a high level is supplied through the light emitting control line Ei. The fifth transistor T5 and the sixth transistor T6 are then turned off in response to the light emitting signal.

[0110] According to the above, the pixel PX in the first period P1 can be Figure 8 The equivalent circuit shown in is represented. During the first period P1, since the second transistor T2 is turned on, the data signal DATA in the current frame is supplied through the data line Dj, and the third node N3 is set to have a voltage Vdata corresponding to the data signal DATA.

[0111] During the first period P1, the first transistor T1 remains in the on state and is diode-connected, so current is applied from the first driving power ELVDD to the fourth node N4. The first node N1 is then set to have a voltage dropped from the voltage of the first driving power ELVDD by the threshold voltage Vth of the first transistor T1.

[0112] The second node N2 is set to have a voltage increased from the voltage of the second driving power source ELVSS by the threshold voltage Voled,th of the organic light emitting diode OLED.

[0113] According to the above, during the first period P1, the voltage VN1 of the first node N1, the voltage VN2 of the second node N2, and the voltage VN3 of the third node N3 may be expressed as follows: [Equation 1]

[0114] [Equation 2]

[0115] [Equation 3]

[0116] Then, refer to Figure 4 , Figure 7 and Fig. 9 During the second period P2, a high-level scan signal is supplied to the i-th first scan line S1i and the i-th second scan line S2i, and a low-level scan signal is supplied to the i-th third scan line S3i. In response to the first scan signal converted to a high level, the second transistor T2 is turned off, and in response to the third scan signal converted to a low level, the third transistor T3 is turned off.

[0117] According to the above, the pixel PX in the second period P2 can be Fig. 9 During the second period P2, the first to third nodes N1 to N3 may stably maintain the voltage set in the first period P1 due to the first capacitor C1 and the second capacitor C2.

[0118] Next, let’s refer to Figure 4 , Figure 7 and Fig.10 During the third period P3, the first scan signal of high level is supplied to the i-th first scan line S1i, and the second scan signal and the third scan signal of low level are supplied to the i-th second scan line S2i and the i-th third scan line S3i, respectively. The fourth transistor T4 is then turned on in response to the second scan signal converted to a low level.

[0119] According to the above content, the pixel PX in the third period P3 can be Fig.10 The equivalent circuit shown in is represented. Since the fourth transistor T4 is turned on during the third period P3, the initialization voltage Vint is applied to the second node N2. The voltage of the second node N2 is then changed from the voltage maintained by the second capacitor C2 in the previous period to the initialization voltage Vint. Therefore, during the third period P3, the voltage VN2 of the second node N2 and the voltage change ΔVN2 at the second node N2 can be expressed as the following equations 4 and 5: [Equation 4]

[0120] [Equation 5]

[0121] As the voltage of the second node N2 changes, the voltages at the first node N1 and the third node N3 may also change. Specifically, during the third period P3, the first transistor T1, the first capacitor C1, and the second capacitor C2 are in a floating state, so that when the voltage at the second node N2 changes, the voltages at the first node N1 and the third node N3 may also change from the voltage maintained by the first capacitor C1 in the previous period by as much as the change in the voltage at the second node N2. Therefore, during the second period P2, the voltage VN1 of the first node N1 and the voltage VN3 of the third node N3 may be expressed as in the following equations 6 and 7: [Equation 6]

[0122] [Equation 7]

[0123] Meanwhile, when the initialization voltage Vint is applied to the second node N2, the organic capacitor Coled of the organic light emitting diode OLED may be discharged. The organic capacitor Coled is discharged during the data writing period WP, ​​thereby improving the black representation capability of the pixel PX in the subsequent emission period EP.

[0124] Then, refer to Figure 4 , Figure 7 and Fig.11 During the fourth period P4, the first scan signal and the second scan signal of high level are respectively supplied to the i-th first scan line S1i and the i-th second scan line S2i, and the third scan signal of low level is supplied to the i-th third scan line S3i. The fourth transistor T4 is then turned off in response to the second scan signal converted to a high level.

[0125] Fig.11 denoted an equivalent circuit of the fourth period P4. During the fourth period P4, the first to third nodes N1 to N3 may stably maintain the voltage set by the first and second capacitors C1 and C2 in the third period P3.

[0126] Then, refer to Figure 4 , Figure 7 and Fig.12During the emission period EP, a first scan signal and a second scan signal of a high level are respectively supplied to the i-th first scan line S1i and the i-th second scan line S2i, and a third scan signal of a low level is supplied to the i-th third scan line S3i. In response to the first scan signal to the third scan signal, the second transistor T2, the third transistor T3 and the fourth transistor T4 are turned off.

[0127] In addition, during the emission period EP, a light emitting signal of a low level is supplied through the light emitting control line Ei. The fifth transistor T5 and the sixth transistor T6 are then turned on in response to the light emitting signal.

[0128] The pixels PX in the emission period EP can be used Fig.12 The equivalent circuit shown in . Since the fifth transistor T5 is turned on during the emission period EP, the reference voltage Vref is applied to the third node N3, and the voltage at the third node N3 changes to the reference voltage Vref. Therefore, during the emission period EP, the voltage VN3 of the third node N3 and the voltage change ΔVN3 at the third node N3 can be expressed as the following equations 8 and 9: [Equation 8]

[0129] [Equation 9]

[0130] As the voltage of the third node N3 changes, the voltages at the first node N1 and the second node N2 may also change. Specifically, since the first capacitor C1 and the second capacitor C2 are connected in series during the emission period EP, the change in the voltage at the third node N3 is allocated to the first capacitor C1 and the second capacitor C2, and the voltage at the first node N1 may change according to the change in the voltage allocated to the first capacitor C1. Therefore, the voltage of the first node N1 during the emission period EP is expressed as the following equation 10: [Equation 10]

[0131] Here, Cst represents the capacitance of the first capacitor C1, and Cself represents the capacitance of the second capacitor C2.

[0132] When such a voltage is applied to the first node N1, a current corresponding to the voltage difference (i.e., gate-source voltage Vgs) between the first driving power source ELVDD and the first node N1 may flow through the first transistor T1. The current flowing through the first transistor T1 is supplied to the organic light emitting diode OLED via the sixth transistor T6 in a turned-on state. The organic light emitting diode OLED may then emit light having a brightness corresponding to the amount of the supplied current.

[0133] When the voltage VN1 of the first node N1 is controlled as in Equation 10, the current Ioled flowing to the organic light emitting diode OLED is expressed as in Equation 11 below.

[0134] [Equation 11]

[0135] where μ P represents the carrier mobility of the first transistor T1, C ox represents the gate oxide capacitance of the first transistor T1, and represents the ratio of the width to the length of the first transistor T1.

[0136] Referring to Equation 11, it can be seen that the current Ioled supplied to the organic light emitting diode OLED during the emission period EP is not affected by the IR drop according to the first driving power source ELVDD and increases by considering the threshold voltage Voled,th of the organic light emitting diode OLED.

[0137] At the same time, the third transistor T3 remains in the off state during the emission period EP. In various embodiments of the present disclosure, the third transistor T3 is formed by an N-type transistor having good off-current characteristics. Therefore, some of the driving current flowing from the first driving power source ELVDD through the first transistor T1 can be prevented from leaking through the third transistor T3 during the emission period EP.

[0138] Preventing leakage of driving current during the emission period EP can improve driving characteristics in a low-frequency driving mode (eg, a "normally on mode" of the display device 1). In addition, preventing leakage of driving current can lead to improvements in the ability to express black grayscale, color bleeding, or crosstalk.

[0139] Despite Figure 7 In the embodiment of FIG. 1 , the data writing period WP is shown as having a first period P1 to a fourth period P4, but the present disclosure is not limited thereto. For example, as described above in conjunction with Figure 2 and Figure 3 As described, in an embodiment in which the gate-on voltage period of the clock signal for generating the scan signal is set to be the same as the gate-off voltage period, the data writing period WP may not include the second period P2 and the fourth period P4.

[0140] Fig.13 is a circuit diagram of a pixel according to a second embodiment of the present disclosure, and Fig.14 is a timing diagram showing a method of driving a display device according to a second embodiment of the present disclosure.

[0141] exist Fig.13In the figure, for the convenience of description, the pixel PX_1 located on the i-th horizontal line and connected to the j-th data line Dj is taken as an example.

[0142] Reference Fig.13 , the pixel PX_1 according to the disclosed second embodiment includes first to sixth transistors T1 to T6, first and second capacitors C1 and C2, and an organic light emitting diode OLED. In addition to the fourth transistor T4_1 being formed of an N-type transistor, the pixel PX_1 according to the disclosed second embodiment may be similar to the following. Figure 4 The pixels PX shown in FIG. 1 are substantially the same. Fig.13 In the Figure 4 , and their detailed description will not be repeated.

[0143] In the second embodiment of the present disclosure, the fourth transistor T4_1 is connected between the second node N2 and the initialization voltage Vint. The gate electrode of the fourth transistor T4_1 is connected to the i-th second scan line S2i_1. The fourth transistor T4_1 may be turned on in response to the second scan signal applied to the i-th second scan line S2i_1. When the fourth transistor T4_1 is turned on, the initialization voltage Vint may be applied to the second node N2 (i.e., the anode electrode of the organic light emitting diode OLED).

[0144] In the present embodiment of the present disclosure, the i th first scan line S1 i may be supplied with a scan signal having a first polarity, and the i th second scan line S2 i_1 and the i th third scan line S3 i may be supplied with a scan signal having a second polarity.

[0145] exist Fig.14 In the figure, it is shown that Figure 5 The high frequency operation shown in Figure 6 The operation in any frame including the data writing period WP and the transmission period EP in the low frequency operation shown in . The arbitrary frame may be one of a plurality of frames constituting one cycle in the high frequency operation or the first frame of a plurality of frames constituting one cycle in the low frequency operation.

[0146] In addition, Fig.14 In the example, the driver Fig.13 The method of the pixel PX_1 located on the i-th horizontal line and connected to the j-th data line Dj shown in FIG. 1 is taken as a representative example. Fig.14 , scan signals supplied to the i-th first to i-th third scan lines S1i, S2i_1, and S3i, a light emitting signal supplied to the light emitting control line Ei, and a data signal supplied to the data line Dj are shown as examples.

[0147] Reference Fig.14 , except according to Fig.13 In addition to changing the second scan signal supplied to the i-th second scan line S2i_1 into a second polarity signal, the method for driving the display device according to the second embodiment of the present disclosure is combined with the above Figure 7 The described method of driving the display device is substantially the same, and thus a repeated description thereof will not be repeated.

[0148] Fig.15 is a circuit diagram of a pixel according to a third embodiment of the present disclosure, and Fig.16 is a timing diagram showing a method of driving a display device according to a third embodiment of the present disclosure.

[0149] exist Fig.15 In the figure, for the convenience of description, the pixel PX_2 located on the i-th horizontal line and connected to the j-th data line Dj is taken as an example.

[0150] Reference Fig.15 , the pixel PX_2 includes the first transistor T1 to the sixth transistor T6, the first capacitor C1 and the second capacitor C2, and the organic light emitting diode OLED. In addition to the gate electrode of the fourth transistor T4_2 being connected to the i+1 third scan line S3i+1, the pixel PX_2 can be connected to the following example: Fig.13 The pixel PX_1 shown in FIG. 1 is substantially the same. Therefore, in Fig.15 In the Fig.13 , and their detailed description will be omitted.

[0151] In a third embodiment of the present disclosure, the fourth transistor T4_2 is connected between the second node N2 and the initialization voltage Vint. The gate electrode of the fourth transistor T4_2 is connected to the i+1th third scan line S3i+1. The fourth transistor T4_2 may be turned on in response to the third scan signal applied to the i+1th third scan line S3i+1. When the fourth transistor T4_2 is turned on, the initialization voltage Vint may be applied to the second node N2 (i.e., the anode electrode of the organic light emitting diode OLED).

[0152] In the present embodiment, the i-th first scan line S1i may be supplied with a scan signal having a first polarity, and the i-th third scan line S3i and the (i+1)-th third scan line S3i+1 may be supplied with a scan signal having a second polarity.

[0153] exist Fig.16 In the figure, it is shown that Figure 5 The high frequency operation shown in Figure 6The operation in any frame including the data writing period WP and the transmission period EP in the low frequency operation shown in . The arbitrary frame may be one of a plurality of frames constituting one cycle in the high frequency operation or the first frame of a plurality of frames constituting one cycle in the low frequency operation.

[0154] In addition, Fig.16 In the example, the driver Fig.15 The method of the pixel PX_2 located on the i-th horizontal line and connected to the j-th data line Dj shown in FIG. 1 is taken as a representative example. Fig.16 In the figure, scan signals supplied to the i-th first scan line S1i and the i-th third scan line S3i, a scan signal supplied to the i+1-th third scan line S3i+1, a light emitting signal supplied to the light emitting control line Ei, and a data signal supplied to the data line Dj are shown as examples.

[0155] Reference Fig.16 , except according to Fig.15 The pixel structure applies the third scan signal to the gate electrode of the fourth transistor T4_2 through the i+1 third scan line S3i+1. The method for driving the display device according to the third embodiment of the present disclosure is combined with the above Fig.14 The described method of driving the display device is substantially the same, and thus a repeated description thereof will not be repeated.

[0156] like Fig.15 and Fig.16 As shown in, in the third embodiment of the present disclosure, the pixel PX_2 can be connected to the i-th first scan line S1i and the i-th third scan line S3i and driven based on the first scan signal and the third scan signal. Compared with the first and second embodiments of the present disclosure, the scan driver 30 does not need to have a stage for generating a second scan signal, and the i-th second scan line S2i does not need to be arranged for the display 50. As a result, in the third embodiment of the present disclosure, the size of the scan driver 30 and the display 50 can be reduced, and the driving of the display device 1 can become easier.

[0157] Fig.17 is a circuit diagram of a pixel according to a fourth embodiment of the present disclosure, and Fig.18 is a timing diagram showing a method of driving a display device according to a fourth embodiment of the present disclosure.

[0158] exist Fig.17 In the figure, for the convenience of description, the pixel PX_3 located on the i-th horizontal line and connected to the j-th data line Dj is taken as an example.

[0159] Reference Fig.17, the pixel PX_3 includes first to sixth transistors T1 to T6, first and second capacitors C1 and C2, and an organic light emitting diode OLED. In addition to the second transistor T2_1 being formed of an N-type transistor, the pixel PX_3 according to the fourth embodiment of the present disclosure may be similar to the following. Fig.13 The pixel PX_1 shown in FIG. 1 is substantially the same. Therefore, in Fig.17 In the Fig.13 , and their detailed description will be omitted.

[0160] In a fourth embodiment of the present disclosure, the second transistor T2_1 is connected between the third node N3 and the data line Dj. The gate electrode of the second transistor T2_1 is connected to the i-th third scan line S3i. The second transistor T2_1 may be turned on in response to the third scan signal applied to the i-th third scan line S3i. When the second transistor T2_1 is turned on, the data signal applied to the data line Dj may be supplied to the third node N3.

[0161] In the present embodiment, the scan signal having the first polarity may be supplied to the i-th first scan line S1i, and the scan signal having the second polarity may be supplied to the i-th third scan line S3i.

[0162] exist Fig.18 In the figure, it is shown that Figure 5 The high frequency operation shown in Figure 6 The operation in any frame including the data writing period WP and the transmission period EP in the low frequency operation shown in . The arbitrary frame may be one of a plurality of frames constituting one cycle in the high frequency operation or the first frame of a plurality of frames constituting one cycle in the low frequency operation.

[0163] In addition, Fig.18 In the example, the driver Fig.17 The method of the pixel PX_3 located on the i-th horizontal line and connected to the j-th data line Dj shown in FIG. 1 is taken as a representative example. Fig.18 , a scan signal supplied to an i-th second scan line S2i_1, a scan signal supplied to an i-th third scan line S3i, a light emitting signal supplied to a light emitting control line Ei, and a data signal supplied to a data line Dj are shown as examples.

[0164] Reference Fig.18 , except according to Fig.17 In addition to supplying the third scan signal to both the gate electrode of the second transistor T2_1 and the gate electrode of the third transistor T3 through the i-th third scan line S3i, the method for driving the display device according to the fourth embodiment of the present disclosure is combined with the above Fig.14 The described method of driving the display device is substantially the same, and thus a repeated description thereof will not be repeated.

[0165] Despite Fig.17 The fourth transistor T4_1 formed of an N-type transistor is shown in the embodiment of the present disclosure, but the present disclosure is not limited thereto. For example, in the fourth embodiment of the present disclosure, the fourth transistor T4_1 may be formed of a P-type transistor. In this case, the second scan signal supplied to the i-th second scan line S2i_1 is set to have a value such as Figure 7 The second polarity shown in .

[0166] Despite Fig.17 In the embodiment of the present disclosure, the gate electrode of the fourth transistor T4_1 is connected to the i-th second scan line S2i_1, but the present disclosure is not limited thereto. For example, in the fourth embodiment of the present disclosure, the gate electrode of the fourth transistor T4_1 may be connected to the i-th second scan line S2i_1. Fig.15 . In the present embodiment, the pixel PX_3 can be connected to the i-th third scan line S3i, and is basically driven using only the third scan signal. Therefore, in the present embodiment of the present disclosure, the scan driver 30 does not need to have a stage for generating the first scan signal and the second scan signal, and it is not necessary to arrange the i-th first scan line S1i and the i-th second scan line S2i for the display 50. As a result, in the third embodiment of the present disclosure, the size of the scan driver 30 and the display 50 can be reduced, and the driving of the display device 1 can become easier.

[0167] Fig.19 is a circuit diagram of a pixel according to a fifth embodiment of the present disclosure, and Fig. 20 is a timing diagram showing a method of driving a display device according to a fifth embodiment of the present disclosure.

[0168] exist Fig.19 In the figure, for the convenience of description, the pixel PX_4 located on the i-th horizontal line and connected to the j-th data line Dj is taken as an example.

[0169] Reference Fig.19 , the pixel PX_4 includes first to sixth transistors T1 to T6, first and second capacitors C1 and C2, and an organic light emitting diode OLED. In addition to the gate electrode of the fourth transistor T4_3 being connected to the i+1 first scan line S1i+1, the pixel PX_4 according to the disclosed fifth embodiment can be connected to the organic light emitting diode OLED. Figure 4 The pixels PX shown in FIG. 1 are substantially the same. Fig.19 In the Figure 4 , and their detailed description will be omitted.

[0170] In a fifth embodiment of the present disclosure, the fourth transistor T4_3 is connected between the second node N2 and the initialization voltage Vint. The gate electrode of the fourth transistor T4_3 is connected to the i+1th first scan line S1i+1. The fourth transistor T4_3 may be turned on in response to the first scan signal applied to the i+1th first scan line S1i+1. When the fourth transistor T4_3 is turned on, the initialization voltage Vint may be applied to the second node N2 (i.e., the anode electrode of the organic light emitting diode OLED).

[0171] In the present embodiment, the scan signal having the first polarity may be supplied to the i-th first scan line S1i and the i+1-th first scan line S1i+1, and the scan signal having the second polarity may be supplied to the i-th third scan line S3i.

[0172] exist Fig. 20 In the figure, it is shown that Figure 5 The high frequency operation shown in Figure 6 The operation in any frame including the data writing period WP and the transmission period EP in the low frequency operation shown in . The arbitrary frame may be one of a plurality of frames constituting one cycle in the high frequency operation or the first frame of a plurality of frames constituting one cycle in the low frequency operation.

[0173] In addition, Fig. 20 In the example, the driver Fig.19 The method of the pixel PX_4 located on the i-th horizontal line and connected to the j-th data line Dj shown in FIG. 1 is taken as a representative example. Fig. 20 In the figure, scan signals supplied to the i-th first scan line S1i and the i-th third scan line S3i, scan signals supplied to the i+1-th first scan line S1i+1, light emitting signals supplied to the light emitting control line Ei, and data signals supplied to the data line Dj are shown as examples.

[0174] Reference Fig. 20 , except according to Fig.19 The pixel structure applies the first scan signal to the gate electrode of the fourth transistor T4_3 through the i+1th first scan line S1i+1. The method for driving the display device according to the fifth embodiment of the present disclosure is combined with the above Figure 7 The described method of driving the display device is substantially the same, and thus a repeated description thereof will not be repeated.

[0175] Fig.21 is a circuit diagram of a pixel according to a sixth embodiment of the present disclosure, and Fig. 22 is a timing diagram showing a method of driving a display device according to a sixth embodiment of the present disclosure.

[0176] exist Fig.21In the figure, for the convenience of description, the pixel PX_5 located on the i-th horizontal line and connected to the j-th data line Dj is taken as an example.

[0177] Reference Fig.21 , the pixel PX_5 includes first to fourth transistors T1 to T4, first and second capacitors C1 and C2, and an organic light emitting diode OLED. Except for omitting the fifth and sixth transistors T5 and T6, the pixel PX_5 may be configured as follows: Figure 4 The pixels PX shown in FIG. 1 are substantially the same.

[0178] In other words, the pixel PX_5 according to the sixth embodiment of the present disclosure corresponds to Figure 4 In the pixel PX shown in FIG. , the light emitting signal is always kept at the cut-off level, so that the fifth transistor T5 and the sixth transistor T6 are cut off. Therefore, Fig.21 The pixel PX_5 shown in FIG. Figure 7 The data writing period WP is driven in the same manner as shown in the timing diagram. Fig.21 and Fig. 22 The pixel PX_5 is configured to perform an operation for setting voltages with respect to the first to third nodes N1 to N3 during the data writing period WP.

[0179] Although various exemplary embodiments have been described above, it will be appreciated by those skilled in the art that various modifications, additions and substitutions are possible without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed in this specification are for illustrative purposes only and are not intended to limit the technical spirit of the present disclosure. The scope of the present disclosure must be limited by the appended claims.

Claims

1. A pixel, comprising: a first transistor electrically connected between the first power source and the fourth node and including a gate electrode electrically connected to the first node; a second transistor electrically connected between the third node and the data line and turned on in response to a scan signal of a first polarity applied to the first scan line; a third transistor electrically connected between the first node and the fourth node and turned on in response to a scan signal of a second polarity applied to a third scan line, wherein the second polarity is opposite to the first polarity; a fourth transistor electrically connected between the second node and the initialization voltage and turned on in response to a scan signal applied to the second scan line; a light emitting diode connected between the second node and a second power source and including an anode electrode electrically connected to the second node; a first capacitor connected between the third node and the first node; and The second capacitor is connected between the first node and the second node.

2. The pixel according to claim 1, wherein: The fourth transistor is turned on in response to the scan signal of the first polarity applied to the second scan line.

3. The pixel according to claim 1, wherein: The fourth transistor is turned on in response to the scan signal of the second polarity applied to the second scan line.

4. The pixel according to claim 1, wherein: The first polarity is a low level, and the second polarity is a high level.

5. The pixel according to claim 1, wherein: The second transistor and the third transistor are turned on during a first period, and the fourth transistor is turned on during a second period after the first period.

6. A pixel, comprising: a first transistor electrically connected between the first power source and the fourth node and including a gate electrode electrically connected to the first node; a second transistor electrically connected between the third node and the data line and turned on in response to a scan signal of a first polarity applied to the first scan line; a third transistor electrically connected between the first node and the fourth node and turned on in response to a scan signal of the first polarity applied to a third scan line; a fourth transistor electrically connected between the second node and the initialization voltage and turned on in response to a scan signal applied to the second scan line; a light emitting diode connected between the second node and a second power source and including an anode electrode electrically connected to the second node; a first capacitor connected between the third node and the first node; as well as The second capacitor is connected between the first node and the second node.

7. The pixel according to claim 6, wherein: The first polarity is a high level.

8. The pixel according to claim 7, wherein: The fourth transistor is turned on in response to a scan signal of a second polarity applied to the second scan line.

9. The pixel according to claim 8, wherein: The second polarity is a low level.

10. A method for driving a pixel, wherein: The pixels include: a first transistor electrically connected between the first power source and the fourth node and including a gate electrode electrically connected to the first node; a second transistor electrically connected between the third node and the data line and turned on in response to a scan signal of a first polarity applied to the first scan line; a third transistor electrically connected between the first node and the fourth node and turned on in response to a scan signal of a second polarity applied to a third scan line; a fourth transistor electrically connected between the second node and the initialization voltage and turned on in response to a scan signal applied to the second scan line; a light emitting diode connected between the second node and a second power source and including an anode electrode electrically connected to the second node; a first capacitor connected between the third node and the first node; and a second capacitor connected between the first node and the second node, and Wherein, the driving method of the pixel includes: turning on the second transistor and the third transistor during a first period; and The fourth transistor is turned on during a second period after the first period.

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