Chip packaging method and packaging structure
By using the same material plastic sealing substrate and plastic sealing adapter layer in the 2.5D fan-out package, the problems of complex process and inconsistent stress of silicon adapter boards are solved, and higher chip packaging reliability and cost savings are achieved.
Patent Information
- Application Number
- CN202510130881.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-06
- Publication Date
- 2025-03-25
AI Technical Summary
The silicon adapter plates in the existing 2.5D fan-out packages have complex processes and high costs. Due to the different materials of the substrate and silicon adapter plates, the stress is inconsistent, which affects the reliability of the chip package.
A plastic sealing substrate and a plastic sealing adapter layer are used to form a plastic sealing adapter layer electrically connected to the plastic sealing substrate, and a plastic sealing body covering the chip is formed on the side where the plastic sealing adapter layer is away from the plastic sealing substrate. The plastic seal substrate and the plastic seal adapter layer use materials with the same characteristics to simplify the process flow and reduce costs.
It effectively avoids the problem of stress inconsistency caused by different expansion coefficients, improves the reliability of chip packaging, especially when assembling highly trusted product groups, meets its reliability packaging requirements, simplifies the process flow, and saves costs.
Smart Images
Figure CN119694902A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present disclosure belong to the field of semiconductor packaging technology, and specifically relate to a chip packaging method and packaging structure. Background Art
[0002] The silicon adapter in the existing 2.5D fan-out package is mainly connected between the chip and the substrate, and the silicon adapter has the function of re-layout of the circuit. The existing 2.5D fan-out package has the following problems:
[0003] 1) The process of forming the silicon adapter plate is complicated and the cost is high.
[0004] 2) Since the substrate and the silicon adapter are made of different materials and have different expansion coefficients, the different expansion coefficients lead to inconsistent stress and delamination. When the silicon adapter is placed on the substrate, the reliability of the chip package will be affected due to delamination, especially when assembling a highly trusted product group, and the reliability packaging requirements cannot be met.
[0005] In view of the above problems, it is necessary to propose a chip packaging method and packaging structure that are reasonably designed and effectively solve the above problems. Summary of the invention
[0006] The embodiments of the present disclosure aim to solve at least one of the technical problems existing in the prior art and provide a chip packaging method and packaging structure.
[0007] An aspect of an embodiment of the present disclosure provides a chip packaging method, characterized in that the method includes:
[0008] forming a plastic encapsulation substrate;
[0009] Forming a plastic transfer layer electrically connected to the plastic substrate on the plastic substrate;
[0010] Fixing the chip module to the plastic packaging transfer layer so that the chip module is electrically connected to the plastic packaging transfer layer;
[0011] A plastic packaging body wrapping the chip is formed on a side of the plastic packaging transfer layer away from the plastic packaging substrate.
[0012] Optionally, forming the plastic encapsulation substrate includes:
[0013] forming a circuit layer of a plastic-encapsulated substrate;
[0014] Forming a first plastic packaging layer wrapping the circuit layer of the plastic packaging substrate;
[0015] The first plastic packaging layer is thinned to expose the plastic packaging substrate circuit layer.
[0016] Optionally, forming a circuit layer of a plastic-encapsulated substrate includes:
[0017] Providing a metal plate, and fixing the metal plate to a temporary carrier;
[0018] Patterning the metal plate to form a first circuit layer;
[0019] forming a second circuit layer on the first circuit layer;
[0020] Removing the temporary carrier; wherein,
[0021] The step of thinning the first plastic packaging layer to expose the plastic packaging substrate circuit layer comprises:
[0022] The first plastic packaging layer is thinned to expose the second circuit layer.
[0023] Optionally, the step of forming a plastic transfer layer electrically connected to the plastic substrate on the plastic substrate includes:
[0024] forming a second plastic encapsulation layer on the surface of the plastic encapsulation substrate;
[0025] Patterning the second plastic encapsulation layer to form a plurality of through holes penetrating the thickness of the second plastic encapsulation layer;
[0026] forming a conductive column in the through hole electrically connected to the plastic package substrate;
[0027] A wiring layer is formed on the surface of the second plastic packaging layer away from the plastic packaging substrate and the surface of the conductive column, and the wiring layer is electrically connected to the conductive column; wherein,
[0028] The step of fixing the chip module to the plastic packaging transfer layer includes:
[0029] The chip module is fixed to the wiring layer, and the electrical connection between the chip module and the plastic packaging transfer layer is achieved through the wiring layer.
[0030] Optionally, the plastic encapsulation substrate, the plastic encapsulation transfer layer and the plastic encapsulation material in the plastic encapsulation body have the same properties.
[0031] Optionally, after forming a plastic packaging body wrapping the chip module on a side of the plastic packaging transfer layer away from the plastic packaging substrate, the method further includes:
[0032] A plurality of solder balls are formed on a side of the plastic encapsulation substrate away from the plastic encapsulation transfer layer.
[0033] Another aspect of the disclosed embodiment provides a chip packaging structure, including a plastic package substrate, a plastic package transfer layer, a chip module and a plastic package body;
[0034] The plastic encapsulation transfer layer is arranged on the surface of the plastic encapsulation substrate and is electrically connected to the plastic encapsulation substrate;
[0035] The chip module is arranged on the plastic packaging transfer layer and is electrically connected to the plastic packaging transfer layer;
[0036] The plastic packaging body is arranged on a surface of the plastic packaging transfer layer away from the plastic packaging substrate, and wraps the chip module.
[0037] Optionally, the plastic encapsulation substrate includes a plastic encapsulation substrate circuit layer and a first plastic encapsulation layer wrapping the plastic encapsulation substrate circuit layer.
[0038] Optionally, the plastic encapsulation transfer layer includes a second plastic encapsulation layer, a plurality of conductive pillars and a wiring layer;
[0039] The second plastic encapsulation layer is disposed on the surface of the plastic encapsulation substrate;
[0040] A plurality of the conductive pillars are arranged at intervals along the thickness direction of the second plastic packaging layer, wherein the conductive pillars are electrically connected to the plastic packaging substrate;
[0041] The wiring layer is arranged on a surface of the second plastic packaging layer away from the plastic packaging substrate and a surface of the conductive pillar, wherein the wiring layer is electrically connected to the chip module.
[0042] Optionally, the plastic encapsulation substrate, the plastic encapsulation transfer layer and the plastic encapsulation body are made of the same plastic encapsulation material.
[0043] The chip packaging method and packaging structure of the disclosed embodiments, in the chip packaging method, a plastic packaging transfer layer is formed on the surface of a plastic packaging substrate, the signal of the chip module is amplified and connected to the plastic packaging substrate through the plastic packaging transfer board, the plastic packaging substrate and the plastic packaging transfer layer are made of materials with the same characteristics and have similar expansion coefficients, which can effectively avoid the problem of stratification caused by inconsistent stress due to different expansion coefficients, improve the connection reliability between the plastic packaging substrate and the plastic packaging transfer board, especially when assembling a highly trusted product group, it can meet its reliability packaging requirements; the plastic packaging transfer layer is formed by a plastic packaging process, which simplifies the process flow and saves costs; the plastic packaging substrate and the plastic packaging transfer layer are used to replace the original substrate and silicon transfer board, the cracking phenomenon caused by warping is weak, and the reliability is high; the plastic packaging substrate and the plastic packaging transfer layer are both made of plastic packaging materials, saving material costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0044] Figure 1 A schematic diagram of a chip packaging method according to an embodiment of the present disclosure;
[0045] Figures 2 to 20 A schematic diagram of a chip packaging method according to another embodiment of the present disclosure;
[0046] Fig.21This is a schematic structural diagram of a chip packaging structure according to an embodiment of the present disclosure;
[0047] Fig. 22 It is a structural schematic diagram of a chip packaging structure of another embodiment of the present disclosure. DETAILED DESCRIPTION
[0048] In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the embodiments of the present disclosure are further described in detail below in conjunction with the accompanying drawings and specific implementation methods.
[0049] like Figure 1 As shown, one aspect of an embodiment of the present disclosure provides a chip packaging method S100, the chip packaging method S100 comprising:
[0050] S110, forming a plastic packaging substrate.
[0051] In this embodiment, the specific process of forming the plastic encapsulation substrate 110 in step S110 can be
[0052] As follows:
[0053] like Figures 2 to 8 As shown, a plastic encapsulation substrate circuit layer is formed. The specific process of forming the plastic encapsulation substrate circuit layer 111 can be as follows:
[0054] like Figure 2 As shown, a metal plate 111a is provided, wherein the metal plate 111a may be a copper plate, and the metal plate 111a is fixed to a temporary carrier plate 111b.
[0055] like Figure 3 As shown, a first photoresist layer 111c is formed on the surface of the metal plate 111a, and the first photoresist layer 111c is exposed and developed to form a plurality of first openings 111d on the first photoresist layer 111c. Figure 4 As shown, the metal plate 111a is etched along the first opening 111d, and the metal plate 111a is patterned to form the first circuit layer 111. After the first circuit layer 111 is formed, the remaining first photoresist layer 111c is removed.
[0056] like Figure 5 As shown, a second photoresist layer 112a is formed on the surface of the temporary carrier 111b and the first circuit layer 111. Figure 6 As shown, the second photoresist layer 112a is exposed and developed to form a plurality of second openings 112b on the second photoresist layer 112a. Figure 7 As shown, a process such as electroplating can be used to electroplating in the second opening 112b to form a second circuit layer 112 connected to the first circuit layer 111. Figure 8As shown, after the second wiring layer 112 is formed, the remaining second photoresist layer 112a is removed.
[0057] like Figure 8 As shown, in this embodiment, the first circuit layer 111 is arranged flatly, and the second circuit layer 112 is distributed vertically.
[0058] like Fig. 9 As shown, a first plastic packaging layer 113 is formed on the temporary carrier 111b to wrap the circuit layer of the plastic packaging substrate.
[0059] like Fig. 9 As shown, the first plastic encapsulation layer 113 is thinned to expose the plastic encapsulation circuit layer. In other words, the first plastic encapsulation layer 113 is thinned to expose the second circuit layer 112.
[0060] like Fig.10 As shown, the temporary carrier 111b is removed to obtain a plastic encapsulation substrate 110, which includes a first circuit layer 111, a second circuit layer 112 connected to the first circuit layer 111, and a first plastic encapsulation layer 113 wrapping the first circuit layer 111 and the second circuit layer 112.
[0061] S120, forming a plastic packaging transfer layer electrically connected to the plastic packaging substrate on the plastic packaging substrate.
[0062] like Figures 11 to 16 As shown, a plastic transfer layer 120 electrically connected to the plastic substrate 110 is formed on the plastic substrate 110. That is, the formed plastic transfer layer 120 is electrically connected to the plastic circuit layer of the plastic substrate 110.
[0063] The specific process of forming the plastic transfer layer 120 in step S120 may be as follows:
[0064] like Fig.11 As shown, a second plastic encapsulation layer 121 is formed on the surface of the plastic encapsulation substrate 110 by using a plastic encapsulation mold.
[0065] like Fig.12 As shown, a third photoresist layer 121a is formed on the surface of the second plastic encapsulation layer 121, and the third photoresist layer 121a is exposed and developed to form a plurality of third openings on the third photoresist layer 121a.
[0066] like Fig.13 As shown, the second plastic encapsulation layer 121 is etched along the third opening to pattern the second plastic encapsulation layer 121 to form a plurality of through holes 122 penetrating the thickness of the second plastic encapsulation layer 121 .
[0067] like Fig.14As shown, a conductive column 123 electrically connected to the plastic package substrate 110 can be formed in the through hole 122 by electroplating or other processes. The conductive column 123 can be made of metal copper material. The conductive column 123 is electrically connected to the circuit layer of the plastic package substrate.
[0068] like Fig.15 As shown, a wiring layer 124 is formed on the surface of the second plastic encapsulation layer 121 away from the plastic encapsulation substrate 110 and the surface of the conductive pillar 123, and the wiring layer 124 is electrically connected to the conductive pillar 123, thereby forming Fig.15 In the present embodiment, the wiring layer 124 may be as follows: Fig.15 The wiring layer 124 in the plastic transfer layer 120 can realize high-density interconnection of the chip module 130.
[0069] It should be noted that after forming the wiring layer 124, the connection bumps 125 may be further formed on the wiring layer 124 according to the requirements of chip packaging. The specific process of forming the connection bumps 125 may be as follows:
[0070] like Fig.16 As shown, a fourth photoresist layer is formed on the surface of the wiring layer 124, and the fourth photoresist layer is exposed and developed to form a plurality of fourth openings on the fourth photoresist layer.
[0071] like Fig.16 As shown, a metal bump is formed at the fourth opening by electroplating or other processes, and the metal bump is reflowed to form a connection bump 125 electrically connected to the wiring layer 124. In other words, the plastic encapsulation transfer layer 120 may also include a connection bump 125. The connection bump 125 may be used to realize the mounting of the flip chip and the plastic encapsulation transfer layer 120.
[0072] S130, fixing the chip module to the plastic packaging transfer layer, so that the chip module is electrically connected to the plastic packaging transfer layer.
[0073] like Fig.17 and Fig.19 As shown, the chip module 130 is fixed to the plastic transfer layer 120, so that the chip module 130 is electrically connected to the plastic transfer layer 120. The plastic transfer layer 120 is used to realize the re-layout of the circuit.
[0074] Specifically, that is to say, the chip module 130 is fixed to the wiring layer 124 , and the chip module 130 is electrically connected to the plastic packaging transfer layer 120 through the wiring layer 124 .
[0075] It should be noted that the chip module 130 may include one chip or multiple chips, and the chip may be a high-performance chip. The specific structural features of the chip module 130 are specifically defined in this embodiment and may be selected according to actual needs. Fig.17 As shown, in one embodiment, a plurality of chips may be stacked sequentially on the plastic transfer layer 120, and the chips may be electrically connected to the wiring layer 124 of the plastic transfer layer 120 via bonding wires. Fig.19 As shown, in another embodiment, a plurality of chips can be arranged flat on the surface of the plastic transfer layer 120. A plurality of chips can be arranged flip-chip on the plastic transfer layer 120 and electrically connected to the connection bumps 125 of the plastic transfer layer 120.
[0076] S140, forming a plastic packaging body wrapping the chip module on a side of the plastic packaging transfer layer away from the plastic packaging substrate.
[0077] like Fig.18 and Fig. 20 As shown, a plastic encapsulation process is used to form a plastic encapsulation body 140 that wraps the chip module 130 on the side of the plastic encapsulation transfer layer 120 that is away from the plastic encapsulation substrate 110. The plastic encapsulation body 140 protects the chip module 130.
[0078] In this embodiment, the properties of the plastic materials in the plastic substrate 110, the plastic transfer layer 120 and the plastic body 140 are the same. In this way, there will be no delamination problem due to different expansion coefficients causing inconsistent stress between the plastic substrate 110 and the plastic transfer layer 120, and between the plastic transfer layer 120 and the plastic body 140, further improving the reliability of chip packaging.
[0079] It should be noted that, in this embodiment, the plastic encapsulation materials in the plastic encapsulation substrate 110, the plastic encapsulation transfer layer 120 and the plastic encapsulation body 140 are selected from plastic encapsulation materials with higher reliability. Among them, the plastic encapsulation materials used in this embodiment include epoxy resin, curing agent, release agent, catalyst, filler and other substances. Among them, the filler accounts for the majority, accounting for about 78%, and the epoxy resin accounts for about 10% to 15%. The appropriate plastic encapsulation materials used in this embodiment are matched to obtain better reliability.
[0080] Exemplarily, after forming a plastic packaging body wrapping the chip module on a side of the plastic packaging transfer layer away from the plastic packaging substrate, the method further includes:
[0081] like Fig.18 and Fig. 20 As shown, a plurality of solder balls 150 are formed on the side of the plastic encapsulation substrate 110 away from the plastic encapsulation transfer layer 120. The plurality of solder balls 150 are electrically connected to the plastic encapsulation circuit layer of the plastic encapsulation substrate 110 to lead out the signal of the entire chip packaging structure.
[0082] The chip packaging method of the disclosed embodiment forms a plastic packaging transfer layer on the surface of the plastic packaging substrate, and realizes the re-layout of the circuit through the plastic packaging transfer board. The plastic packaging substrate and the plastic packaging transfer layer use materials with the same characteristics and have similar expansion coefficients, which can effectively avoid the problem of stratification caused by inconsistent stress due to different expansion coefficients, and improve the connection reliability between the plastic packaging substrate and the plastic packaging transfer board. In particular, when assembling a highly trusted product group, its reliability packaging requirements can be met; the plastic packaging transfer layer is formed by a plastic packaging process, which simplifies the process flow and saves costs; the plastic packaging substrate and the plastic packaging transfer layer are used to replace the original substrate and silicon transfer board, and the cracking phenomenon caused by warping is weak and the reliability is high; the plastic packaging substrate and the plastic packaging transfer layer are both made of plastic packaging materials, which saves material costs.
[0083] like Fig.21 and Fig. 22 As shown, another aspect of the embodiment of the present disclosure provides a chip packaging structure 100 , including a plastic packaging substrate 110 , a plastic packaging transfer layer 120 , a chip module 130 and a plastic packaging body 140 .
[0084] The plastic transfer layer 120 is disposed on the surface of the plastic substrate 110 and is electrically connected to the plastic substrate 110 .
[0085] The chip module 130 is disposed on the plastic transfer layer 120 and is electrically connected to the plastic transfer layer 120 .
[0086] The plastic package body 140 is disposed on a surface of the plastic package transfer layer 120 away from the plastic package substrate 110 , and wraps the chip module 130 to protect the chip module 130 .
[0087] It should be noted that the chip module 130 may include one chip or multiple chips, and the chip may be a high-performance chip. The specific structural features of the chip module 130 are specifically defined in this embodiment and may be selected according to actual needs. Fig.21 As shown, in one embodiment, a plurality of chips may be stacked sequentially on the plastic transfer layer 120, and the chips may be electrically connected to the wiring layer 124 of the plastic transfer layer 120 via bonding wires. Fig. 22 As shown, in another embodiment, a plurality of chips can be arranged flat on the surface of the plastic transfer layer 120. A plurality of chips can be arranged flip-chip on the plastic transfer layer 120 and electrically connected to the connection bumps 125 of the plastic transfer layer 120.
[0088] In the chip packaging device of the disclosed embodiment, the plastic-encapsulated substrate and the plastic-encapsulated transfer layer are made of materials with the same characteristics and have similar expansion coefficients, which can effectively avoid the problem of delamination caused by inconsistent stress due to different expansion coefficients, and improve the connection reliability between the plastic-encapsulated substrate and the plastic-encapsulated transfer board. In particular, when assembling a highly trusted product group, the reliability packaging requirements can be met; the process of forming the plastic-encapsulated transfer layer is simple, the process flow is simplified, and costs are saved; the plastic-encapsulated substrate and the plastic-encapsulated transfer layer are used to replace the original substrate and silicon transfer board, the cracking phenomenon caused by warping is weak, and the reliability is high; the plastic-encapsulated substrate and the plastic-encapsulated transfer layer are both made of plastic materials, saving material costs.
[0089] For example, Fig.21 and Fig. 22 As shown, the plastic encapsulation substrate 110 includes a plastic encapsulation substrate circuit layer and a first plastic encapsulation layer 113 wrapping the plastic encapsulation substrate circuit layer.
[0090] Specifically, Fig.21 and Fig. 22 As shown, the circuit layer of the plastic encapsulation substrate includes a first circuit layer 111 arranged flatly and a second circuit layer 112 connected to the first circuit layer 111 and arranged vertically, wherein the plastic encapsulation transfer layer 120 is electrically connected to the second circuit layer 112 .
[0091] For example, Fig.21 As shown, the plastic transfer layer 120 includes a second plastic layer 121 , a plurality of conductive pillars 123 and a wiring layer 124 .
[0092] The second plastic packaging layer 121 is disposed on the surface of the plastic packaging substrate 110 .
[0093] A plurality of conductive pillars 123 are arranged at intervals along the thickness direction of the second plastic encapsulation layer 121, wherein the conductive pillars 123 are electrically connected to the plastic encapsulation substrate 110. The conductive pillars 123 can realize vertical interconnection of the plastic encapsulation transfer layer 120.
[0094] The wiring layer 124 is disposed on the surface of the second plastic packaging layer 121 away from the plastic packaging substrate 110 and the surface of the conductive pillar 123, wherein the wiring layer 124 is electrically connected to the chip module 130. The wiring layer 124 can realize high-density interconnection of the chip module 130.
[0095] like Fig. 22 As shown, the plastic encapsulation transfer layer 120 may further include connection bumps 125, and the connection bumps 125 are arranged on the wiring layer 124. The connection bumps 125 may be used to realize the mounting of the flip chip and the plastic encapsulation transfer layer 120.
[0096] For example, in this embodiment, the same plastic materials are used in the plastic encapsulation substrate 110, the plastic encapsulation transfer layer 120, and the plastic encapsulation body 140. In this way, there will be no delamination problem due to different expansion coefficients causing inconsistent stress between the plastic encapsulation substrate 110 and the plastic encapsulation transfer layer 120, and between the plastic encapsulation transfer layer 120 and the plastic encapsulation body 140, further improving the reliability of chip packaging.
[0097] It should be noted that, in this embodiment, the plastic encapsulation materials in the plastic encapsulation substrate 110, the plastic encapsulation transfer layer 120 and the plastic encapsulation body 140 are selected from plastic encapsulation materials with higher reliability. Among them, the plastic encapsulation materials used in this embodiment include epoxy resin, curing agent, release agent, catalyst, filler and other substances. Among them, the filler accounts for the majority, accounting for about 78%, and the epoxy resin accounts for about 10% to 15%. The appropriate plastic encapsulation materials used in this embodiment are matched to obtain better reliability.
[0098] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the embodiments of the present disclosure, but the embodiments of the present disclosure are not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the embodiments of the present disclosure, and these modifications and improvements are also considered to be within the protection scope of the embodiments of the present disclosure.
Claims
1. A chip packaging method, characterized in that: The method comprises: forming a plastic encapsulation substrate; Forming a plastic transfer layer electrically connected to the plastic substrate on the plastic substrate; Fixing the chip module to the plastic packaging transfer layer so that the chip module is electrically connected to the plastic packaging transfer layer; A plastic packaging body wrapping the chip is formed on a side of the plastic packaging transfer layer away from the plastic packaging substrate.
2. The chip packaging method according to claim 1, characterized in that: The forming of the plastic encapsulation substrate comprises: forming a circuit layer of a plastic-encapsulated substrate; Forming a first plastic packaging layer wrapping the circuit layer of the plastic packaging substrate; The first plastic packaging layer is thinned to expose the plastic packaging substrate circuit layer.
3. The chip packaging method according to claim 2, characterized in that: The forming of the circuit layer of the plastic-encapsulated substrate comprises: Providing a metal plate, and fixing the metal plate to a temporary carrier plate; Patterning the metal plate to form a first circuit layer; forming a second circuit layer on the first circuit layer; Removing the temporary carrier; wherein, The step of thinning the first plastic packaging layer to expose the plastic packaging substrate circuit layer comprises: The first plastic packaging layer is thinned to expose the second circuit layer.
4. The chip packaging method according to any one of claims 1 to 3, characterized in that: The plastic sealing transfer layer electrically connected to the plastic sealing substrate is formed on the plastic sealing substrate, comprising: forming a second plastic encapsulation layer on the surface of the plastic encapsulation substrate; Patterning the second plastic encapsulation layer to form a plurality of through holes penetrating the thickness of the second plastic encapsulation layer; forming a conductive column in the through hole electrically connected to the plastic package substrate; A wiring layer is formed on the surface of the second plastic packaging layer away from the plastic packaging substrate and the surface of the conductive column, and the wiring layer is electrically connected to the conductive column; wherein, The step of fixing the chip module to the plastic packaging transfer layer includes: The chip module is fixed to the wiring layer, and the electrical connection between the chip module and the plastic packaging transfer layer is achieved through the wiring layer.
5. The chip packaging method according to any one of claims 1 to 3, characterized in that: The plastic encapsulation material properties of the plastic encapsulation substrate, the plastic encapsulation transfer layer and the plastic encapsulation body are the same.
6. The chip packaging method according to any one of claims 1 to 3, characterized in that: After forming a plastic packaging body wrapping the chip module on a side of the plastic packaging transfer layer away from the plastic packaging substrate, the method further includes: A plurality of solder balls are formed on a side of the plastic encapsulation substrate away from the plastic encapsulation transfer layer.
7. A chip packaging structure, characterized in that: It includes a plastic package substrate, a plastic package transfer layer, a chip module and a plastic package body; The plastic encapsulation transfer layer is arranged on the surface of the plastic encapsulation substrate and is electrically connected to the plastic encapsulation substrate; The chip module is arranged on the plastic packaging transfer layer and is electrically connected to the plastic packaging transfer layer; The plastic packaging body is arranged on a surface of the plastic packaging transfer layer away from the plastic packaging substrate, and wraps the chip module.
8. The chip packaging structure according to claim 7, characterized in that: The plastic encapsulation substrate comprises a plastic encapsulation substrate circuit layer and a first plastic encapsulation layer wrapping the plastic encapsulation substrate circuit layer.
9. The chip packaging structure according to claim 7, characterized in that: The plastic encapsulation transfer layer includes a second plastic encapsulation layer, a plurality of conductive pillars and a wiring layer; The second plastic encapsulation layer is disposed on the surface of the plastic encapsulation substrate; A plurality of the conductive pillars are arranged at intervals along the thickness direction of the second plastic packaging layer, wherein the conductive pillars are electrically connected to the plastic packaging substrate; The wiring layer is arranged on a surface of the second plastic packaging layer away from the plastic packaging substrate and a surface of the conductive pillar, wherein the wiring layer is electrically connected to the chip module.
10. The chip packaging structure according to any one of claims 7 to 9, characterized in that: The plastic encapsulation materials in the plastic encapsulation substrate, the plastic encapsulation transfer layer and the plastic encapsulation body are the same.