Aging analysis method and related equipment

Through the aging analysis method based on the aging unit library, the degree of chip aging is accurately evaluated, and the aging analysis problem in integrated circuit design is solved, and the accurate evaluation and timing analysis of the impact of chip aging is achieved, ensuring the long-term reliability of the product.

CN119716467AActive Publication Date: 2025-03-28HAIGUANG INTEGRATED CIRCUIT DESIGN (BEIJING) CO LTD
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Patent Information

Application Number
CN202411623437.0
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-11-13
Publication Date
2025-03-28
Estimated Expiration
2044-11-13

AI Technical Summary

Technical Problem

How to accurately evaluate the degree of chip aging in integrated circuit design and ensure the long-term and reliable operation of the product, it faces the problem of aging analysis method that is difficult to effectively solve in the existing technology.

Method used

An aging analysis method is provided. By obtaining the design object to be checked in time, the delayed aging rate of the standard unit is determined based on the aging unit library. The aging unit library includes multiple sub-aging unit libraries, which characterize the delayed aging rate under different aging mechanisms, and perform timing analysis after aging.

Benefits of technology

The accurate evaluation of the chip aging degree is achieved, and the aging degree of standard units under different excitation waveform conditions can be more accurately characterized, ensuring that the design object still meets the timing requirements after aging, and improving the long-term reliability of the integrated circuit.

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Abstract

The embodiment of the invention provides an aging analysis method and related equipment, and the method comprises the steps: obtaining a design object to be subjected to time sequence checking, and enabling the design object to be composed of a plurality of standard units; based on an aging unit library, the delay aging rate of the standard unit is determined, and the delay aging rate is used for representing the increasing proportion of signal transmission delay time caused by aging of the standard unit; wherein the aging unit library comprises a plurality of sub-aging unit libraries, the sub-aging unit libraries are used for representing the delay aging rate of a standard unit under a preset aging mechanism, and different sub-aging unit libraries correspond to different aging mechanisms; and based on the delay aging rate, performing time sequence analysis on the design object after aging, and obtaining a report. According to the embodiment of the invention, the method can achieve the accurate evaluation of the aging degree of the chip.
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