Method, apparatus, device and storage medium for managing accelerator

Abstract

According to embodiments of the present disclosure, methods, apparatuses, devices and storage media for managing accelerators are provided. A method for managing accelerators includes obtaining interface information associated with a set of accelerators in a computing device, the interface information indicating at least respective identification information and respective mapping information of the set of accelerators, wherein the mapping information of an accelerator indicates hardware resources for the accelerator in the computing device; initializing the set of accelerators according to the interface information with a driver of the computing device; and performing a task with at least a portion of the initialized set of accelerators. In this way, configuration flexibility and usage of the accelerators can be improved.

Description

Technical Field

[0001] The exemplary embodiments disclosed herein relate generally to the field of computers, and more particularly to methods, apparatuses, devices and computer-readable storage media for managing accelerators. Background Technology

[0002] With the rapid development of big data and artificial intelligence applications, the demand for computing power has increased significantly. For example, processors need to be extremely efficient when handling complex data analysis, machine learning, and deep learning tasks, thus there is a desire to configure processors in a more efficient way. Summary of the Invention

[0003] In a first aspect of this disclosure, a method for managing accelerators is provided. The method includes: acquiring interface information associated with a set of accelerators in a computing device, the interface information indicating at least corresponding identification information and corresponding mapping information for the set of accelerators, wherein the mapping information for one accelerator indicates hardware resources in the computing device used for that accelerator; initializing the set of accelerators according to the interface information using a driver of the computing device; and performing a task using at least a portion of the initialized set of accelerators.

[0004] In a second aspect of this disclosure, an apparatus for managing accelerators is provided. The apparatus includes: an interface information acquisition module configured to acquire interface information associated with a set of accelerators in a computing device, the interface information indicating at least corresponding identification information and corresponding mapping information for the set of accelerators, wherein the mapping information for one accelerator indicates hardware resources in the computing device for that accelerator; an accelerator initialization module configured to initialize the set of accelerators according to the interface information using a driver of the computing device; and a task execution module configured to execute a task using at least a portion of the initialized set of accelerators.

[0005] In a third aspect of this disclosure, an electronic device is provided. The device includes at least one processing unit; and at least one memory coupled to the at least one processing unit and storing instructions for execution by the at least one processing unit. When executed by the at least one processing unit, the instructions cause the device to perform the method of the first aspect.

[0006] In a fourth aspect of this disclosure, a computer-readable storage medium is provided. The computer-readable storage medium stores a computer program that can be executed by a processor to implement the method of the first aspect.

[0007] It should be understood that the content described in this content section is not intended to limit the key or essential features of the embodiments of this disclosure, nor is it intended to restrict the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0008] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. In the drawings, the same or similar reference numerals denote the same or similar elements, wherein:

[0009] Figure 1 A schematic diagram of an example environment in which embodiments of the present disclosure can be implemented is shown;

[0010] Figure 2 A schematic diagram of an example architecture of a processing unit including an accelerator according to some embodiments of the present disclosure is shown;

[0011] Figure 3 A schematic diagram illustrating example mapping relationships between an accelerator and other hardware resources according to some embodiments of the present disclosure is shown;

[0012] Figure 4 A schematic diagram illustrating an example of interface information according to some embodiments of the present disclosure is shown;

[0013] Figure 5 A schematic diagram of an example of managing an accelerator according to some embodiments of the present disclosure is shown;

[0014] Figure 6 A flowchart of a method for managing an accelerator according to some embodiments of the present disclosure is shown;

[0015] Figure 7 A block diagram of an apparatus for managing an accelerator according to some embodiments of the present disclosure is shown; and

[0016] Figure 8 A block diagram of an apparatus capable of implementing several embodiments of the present disclosure is shown. Detailed Implementation

[0017] It is understood that before using the technical solutions disclosed in the various embodiments of this disclosure, users should be informed of the types, scope of use, and usage scenarios of the personal information involved in this disclosure in an appropriate manner in accordance with relevant laws and regulations, and user authorization should be obtained.

[0018] For example, upon receiving a user's active request, a prompt message is sent to the user to explicitly inform them that the requested operation will require the acquisition and use of the user's personal information. This allows the user to independently choose whether to provide personal information to the software or hardware, such as the electronic device, application, server, or storage medium performing the operations of this disclosed technical solution, based on the prompt message.

[0019] As an optional but non-limiting implementation, in response to a user's active request, sending a prompt message to the user can be done via a pop-up window, which can display the prompt message in text format. Furthermore, the pop-up window can also include a selection control allowing the user to choose "agree" or "disagree" to provide personal information to the electronic device.

[0020] It is understood that the above notification and user authorization process are merely illustrative and do not constitute a limitation on the implementation of this disclosure. Other methods that comply with relevant laws and regulations may also be applied to the implementation of this disclosure.

[0021] It is understood that the data involved in this technical solution (including but not limited to the data itself, the acquisition or use of the data) shall comply with the requirements of relevant laws, regulations and related provisions.

[0022] The term "in response to" as used herein refers to a state in which a corresponding event occurs or a condition is satisfied. It will be understood that the timing of subsequent actions performed in response to such event or condition is not necessarily strongly correlated with the time when the event occurs or the condition is met. For example, in some cases, subsequent actions may be performed immediately upon the occurrence of the event or the fulfillment of the condition; while in others, they may be performed some time after the occurrence of the event or the fulfillment of the condition.

[0023] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0024] It should be noted that the headings of any section / subsection provided herein are not limiting. Various embodiments are described throughout this document, and embodiments of any type may be included under any section / subsection. Furthermore, embodiments described in any section / subsection may be combined in any way with any other embodiments described in the same section / subsection and / or different sections / subsections.

[0025] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The term "some embodiments" should be understood as "at least some embodiments". Other explicit and implicit definitions may also be included below. The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0026] As briefly mentioned earlier, due to the ever-increasing demand for computing power, traditional general-purpose processors may not be efficient enough when handling complex data analysis, machine learning, and deep learning tasks. Considering that general-purpose processors can consume a lot of energy when processing specific tasks, introducing dedicated accelerators can provide higher energy efficiency and lower power consumption. This is crucial for extending battery life, reducing heat generation, and improving device performance. For example, graphics processing units (GPUs) can work more efficiently than central processing units (CPUs) in graphics rendering. Furthermore, tensor processing units (TPUs) designed for deep learning tasks can significantly improve the speed of machine learning model training and inference.

[0027] Furthermore, some application platforms support accelerators that are often programmable, allowing developers to customize and optimize them as needed. Therefore, accelerators have become an important solution for meeting application requirements.

[0028] Some accelerator devices, such as those designed for the Peripheral Component Interconnect High Speed ​​(PPCIe) bus standard, can be configured on x86 application platforms. However, there is no universal solution for configuring accelerator devices that do not conform to the PCIe bus standard on application platforms such as those based on the Reduced Instruction Set Computing (RISC) architecture.

[0029] To at least partially address the aforementioned problems, embodiments of this disclosure propose a scheme for managing accelerators. According to various embodiments of this disclosure, interface information associated with a set of accelerators in a computing device is obtained. The interface information at least indicates corresponding identification information and corresponding mapping information for these accelerators. The mapping information for each accelerator indicates the hardware resources in the computing device used for that accelerator, such as address translation units, interrupt service units, etc. The driver of the computing device then initializes this set of accelerators based on the interface information, for example, by enumerating these accelerators. Furthermore, in subsequent business processing, at least a portion of this initialized set of accelerators is used to perform tasks according to actual needs. According to embodiments of this disclosure, the accelerators are used as platform devices, eliminating the need for PCIe enumeration; instead, the driver performs the accelerator enumeration. This improves the configuration flexibility and utilization rate of the accelerators.

[0030] Example embodiments of this disclosure are described below with reference to the accompanying drawings.

[0031] Figure 1 A schematic diagram of an example environment 100 in which embodiments of the present disclosure can be implemented is shown. In environment 100, a computing device 110 includes hardware for performing computing-related tasks. Such a computing device 110 is, for example, a personal computer, a server, a mobile device, etc.

[0032] The computing device 110 includes one or more accelerators 130, such as accelerator 130-1, accelerator 130-2, ..., accelerator 130-N, etc. These accelerators may be used individually or collectively as accelerators 130. Such accelerators 130 can be used to improve the execution speed of specific types of tasks (such as graphics processing, machine learning, etc.) or specific types of data.

[0033] Operating system 120 may be software running on computing device 110, used to allocate resources to applications running on computing device 110. Furthermore, operating system 120 may utilize computing device 110 to perform tasks, and may also utilize accelerator 130 to accelerate specific types of tasks or specific types of data.

[0034] It should be understood that the structure and function of environment 100 are described for illustrative purposes only and do not imply any limitation on the scope of this disclosure. References will follow. Figure 2 and Figure 3 Describe the architecture used to manage the accelerator from a hardware perspective.

[0035] Figure 2A schematic diagram of an example architecture 200 of a processing unit including an accelerator according to some embodiments of the present disclosure is shown. Architecture 200 may include multiple processing units, such as processing unit 210-1, processing unit 210-2, ..., processing unit 210-X, etc. These processing units may be individually or collectively referred to as processing unit 210.

[0036] Each processing unit 210 may include multiple processing cores, such as processing core 220-1, processing core 220-2, ..., processing core 220-Y, etc. These processing cores may be referred to individually or collectively as processing core 220. As a basic component of the processing unit 210, the processing core 220 can execute various instructions cooperatively or independently and coordinate system resources. The processing core 220 can run multiple threads or processes simultaneously and share certain resources such as caches and registers.

[0037] Each processing unit 210 may also include a system memory management unit (SMMU) 230. The SMMU 230 can be used for address translation, memory attribute translation, permission checks, etc., between the interface device and the bus.

[0038] Each processing unit 210 may also include an accelerator 130. In some embodiments, such as Figure 2 As shown, accelerator 130 may include multiple acceleration units, such as acceleration unit 250-1, acceleration unit 250-2, ..., acceleration unit 250-Z, etc. These acceleration units may be referred to individually or collectively as acceleration unit 250. Accelerator 130 containing multiple acceleration units 250 is also referred to as the first accelerator.

[0039] In some embodiments, an accelerator 130 can be considered as an independent platform device, serving as a parent device for multiple acceleration units 250 attached to it. This allows for unified operational support for acceleration unit resource management, overall device error handling, and recovery.

[0040] In some embodiments, depending on the device configuration settings in the Basic Input / Output System (BIOS) and support for Dynamic Advanced Configuration and Power Interface (ACPI), an acceleration unit 250 can be considered as a standalone platform device, or a combination of multiple acceleration units 250 can be considered as a platform device. Thus, one or more acceleration units 250 can be a sub-device attached to an accelerator 130.

[0041] It should be understood that although each processing unit 210 is shown to include the same number of processing cores and acceleration units, these processing units 210 may each include any appropriate number of processing cores and acceleration units, or may include only an appropriate number of processing cores and an accelerator, and this disclosure does not limit this.

[0042] Figure 3 A schematic diagram of an example mapping relationship 300 between an accelerator and other hardware resources according to some embodiments of the present disclosure is shown. The mapping relationship 300 generally relates to the accelerator 130, the SMMU 230, and the interrupt controller 320. With respect to the accelerator 130, the SMMU 230 and the interrupt controller 320 can be considered as hardware resources in the computing device 110 available to the accelerator 130.

[0043] Accelerator 130 is attached to bus 310 via SMMU 230. Secure isolation between accelerators 130 or between multiple acceleration units 250 contained within each accelerator 130 is achieved using SMMU 310. For example, SMMU 310 can assign a stream ID (SID) to each attached or connected accelerator 130. Thus, different accelerators 130 can be identified using the SID, thereby achieving secure isolation between accelerators. As another example, SMMU 310 can also assign a substream ID (SSID) to each attached or connected acceleration unit 250. Thus, different acceleration units 250 can be identified using the SSID, thereby achieving isolation of process address spaces.

[0044] The SMMU 230 can convert the stream identifier into a device ID recognizable by the interrupt controller 320 and communicate with the interrupt controller 320 via the bus 310. The interrupt controller 320 manages and distributes interrupt signals generated by hardware devices. For example, an interrupt signal triggered by the accelerator 130 or accelerator unit 250 is sent to the interrupt controller 320 via the SMMU 230. The interrupt controller 320 provides an Interrupt Translation Service (ITS) so that the operating system 120 can determine which accelerator 130 or accelerator unit 250 triggered the interrupt signal and execute the corresponding interrupt handler.

[0045] The above provides a hardware-level overview of the example architecture used for managing the accelerator. Example architecture 200 and example mapping 300 can be implemented in environment 100. See also... Figure 1 The operating system 120 can obtain interface information associated with a set of accelerators 130 in the computing device 110. Such interface information may include corresponding identification information for the set of accelerators 130, and may also include corresponding mapping information. The mapping information for each accelerator 130 may indicate the hardware resources in the computing device 110 used for that accelerator, such as indicating the SMMU and ITS used for that accelerator.

[0046] In some embodiments, interface information may be reported by the firmware to the operating system 120. For example, during the power-on self-test (POST) phase, the firmware may report the interface information used by the accelerator 130 to the operating system 120.

[0047] In some embodiments, the interface information may include a description table and a mapping table to help the operating system 120 identify the accelerator and determine the hardware resources for the accelerator. Figure 4 A schematic diagram of an example 400 of interface information according to some embodiments of the present disclosure is shown. Example 400 may include at least one of a mapping table 410, a description table 420 (also referred to as a first description table), or a description table 430 (also referred to as a second description table).

[0048] In some embodiments, mapping table 410 indicates hardware resources in computing device 110 for each accelerator, such as SMMU, interrupt translation services provided by the interrupt controller, etc. Exemplarily, mapping table 410 includes ITS node 412, SMMU node 414, and component node 416. In mapping table 410, component node 416 indicates accelerator 130 (e.g., Figure 4 The mapping table 410 shows the relationship between accelerators 130 (such as accelerator 1, accelerator 2, accelerator 3, etc.) and the SMMU and ITS. This mapping table 410 ensures that accelerator 130 can correctly initiate interrupts, such as line interrupts and message signal interrupts (MSI), within the operating system 120. SMMU node 414 indicates the SMMU hardware information in computing device 110, and ITS node 416 indicates the ITS-related hardware information in computing device 110. The mapping table 410 can be, for example, an input / output remapping table (IORT).

[0049] In some embodiments, description table 420 includes a set of corresponding hardware identifiers (HIDs) and corresponding register addresses for accelerators 130 to ensure that the operating system can properly access the registers of accelerators 130. Such description table 420 may, for example, include a Distinctive System Description Table (DSDT). In the Advanced Configuration and Power Interface (ACPI) specification, the DSDT supports matching defined and described hardware identifiers to corresponding accelerators.

[0050] A hardware identifier is a unique identifier used to mark and distinguish hardware devices; also known as a hardware identifier, it typically consists of a set of numbers and letters. Generally, hardware identifiers are assigned to each device by the device manufacturer during the manufacturing process. However, the ACPI specification does not provide a description for the Accelerator 130, which is considered a platform device.

[0051] In some embodiments, the operating system 120 can recognize and run the accelerators by customizing a set of hardware identifiers for the accelerators. For example, the accelerator 130 includes three types of accelerators, such as CDA accelerators, DTE accelerators, and DLA accelerators. For CDA accelerators, their hardware identifiers are, for example, BCDA0000, BCDA0001, BCDA0002, etc. For DTE accelerators, their hardware identifiers are, for example, BDTE0000, BDTE0001, BDTE0002, etc. For DLA accelerators, their hardware identifiers are, for example, DBLA0000, DBLA0001, DBLA002, etc. Thus, the accelerators can be used as platform devices and their hardware identifiers can be assigned.

[0052] In some embodiments, one or more accelerators in accelerator 130 (also referred to as first accelerators) may include multiple acceleration units 250, or multiple acceleration units of the first accelerator need to be exposed to the operating system as platform devices. In this embodiment, description table 420 may include a hardware identifier of the first accelerator and a register address corresponding to the first accelerator, and may also include register addresses corresponding to each acceleration unit. This allows acceleration units to be treated as sub-devices and assigned register addresses. In this way, flexible configuration of the acceleration units can be achieved.

[0053] In some embodiments, description table 430 includes corresponding identifiers of hardware resources in computing device 110 for a group of accelerators 130 to ensure that the group of accelerators 130 can properly access the interrupt controller. Such description table 420 includes, for example, an Advanced Programmable Interrupt Controller Description Table (MADT). In the ACPI specification, the MADT contains information related to the interrupt controller, such as... Figure 4 The ITS indexes shown are ITS 0, ITS 1, ITS 2, etc.

[0054] The interface information associated with a set of accelerators 130 has been described above through various embodiments. After obtaining such interface information, the operating system 120 can initialize a set of accelerators 130 using the driver of the computing device 110 based on this interface information. In other words, the driver enumerates the reported accelerators and their acceleration units (if applicable). Exemplarily, the driver first detects the accelerators 130 in the computing device 110, then enumerates and initializes the available accelerators 130 one by one. Further, the operating system 120 can utilize the initialized accelerators 130 to perform tasks. Exemplarily, after initializing the accelerators 130, the operating system 120 can select an accelerator with a suitable computing architecture and programming interface from the initialized accelerators 130 to perform computation. The following references... Figure 5 Describe a specific example.

[0055] Figure 5 A schematic diagram of example 500 for managing an accelerator according to some embodiments of the present disclosure is shown. Specifically, at block 510, the firmware side reports interface information associated with the accelerator, such as... Figure 4 The ACPI shown includes IORT, MADT, DSDT, etc. In block 520, the driver matches accelerators based on the reported interface information and performs accelerator enumeration. That is, the driver searches for all available accelerators in computing device 110 and performs hardware enable on the found accelerators. In block 530, the user side uses at least a portion of the enumerated accelerators to perform a specific task, such as a parallel computing task. Depending on the specific implementation, the user side can use one or more accelerators or one or more acceleration units from the enumerated accelerators.

[0056] In some embodiments, the operating system 120 (e.g., a driver) can also use the driver to set the sharing mode of the acceleration unit. Such a sharing mode indicates whether the acceleration unit can be shared by multiple processes. In this way, the problem of the limitation on the number of acceleration units can be solved.

[0057] For example, the operating system 120 can configure multiple acceleration units in a group of accelerators to support shared mode as needed, so that these acceleration units can only be shared by multiple processes. These multiple acceleration units can be those attached to one accelerator or those attached to different accelerators; this disclosure does not impose any limitations on this. Alternatively, the firmware can report which acceleration units support shared mode in the interface information. Furthermore, the driver can set the shared mode based on the firmware's report.

[0058] In some embodiments, the accelerator or acceleration unit can be used as a standalone device. In some embodiments, one or more acceleration units can be assigned to a virtual machine for use. References Figure 2 For a processing unit 210, the operating system 120 can also allocate a first number of processing cores 220 and a second number of acceleration units 250 to a virtual machine, and execute tasks through the virtual machine. In this way, flexibility in using acceleration units can be achieved in different application scenarios.

[0059] For example, the operating system 120 can utilize the SMMU 230 to assign an SSID to each acceleration unit 250. During virtualization deployment, an appropriate number of processing cores 220 and an appropriate number of acceleration units 250 are bound together, for example, four processing cores 220 and four acceleration units 250 are assigned to a single virtual machine. The operating system 120 can also dynamically configure a first number and a second number for different application scenarios. Additionally or alternatively, the first number of processing cores 220 and the second number of acceleration units 250 can also be used as a standalone device in non-virtualization deployments.

[0060] In some embodiments, the computing device 110 is based on an Advanced Reduced Instruction Set Computing (RISC) architecture, and as... Figure 2 As shown, the computing device 110 may include multiple processing units 210, and further may include a set of accelerators 130. In this way, the computing power, energy efficiency and power consumption requirements of the Advanced Reduced Instruction Set Computing (ARPC) architecture, as well as the diverse application scenarios and programmability requirements, can be met.

[0061] In summary, this disclosure proposes using the accelerator as a platform device and defining its hardware identifier. Furthermore, based on the obtained interface information associated with the accelerator, the driver can be used to initialize the accelerator and execute tasks using the initialized accelerator. Thus, an accelerator management scheme for non-PCIe bus standards can be implemented without PCIe bus enumeration. This approach improves the configuration flexibility and utilization of the accelerator.

[0062] Example process

[0063] Figure 6 A flowchart of a method 600 for managing an accelerator according to some embodiments of the present disclosure is shown. Method 600 may be implemented at operating system 120. Reference is made below. Figure 1 Description method 600.

[0064] In box 610, operating system 120 obtains interface information associated with a set of accelerators in a computing device. The interface information indicates at least corresponding identification information and corresponding mapping information for a set of accelerators, wherein the mapping information for one accelerator indicates the hardware resources in the computing device used for that accelerator.

[0065] In box 620, operating system 120 uses the computing device's driver to initialize a set of accelerators based on interface information.

[0066] In box 630, operating system 120 uses at least a portion of an initialized set of accelerators to perform a task.

[0067] In some embodiments, the interface information is reported by the firmware to the operating system of the computing device.

[0068] In some embodiments, the interface information includes at least one of the following: a first description table including corresponding hardware identifiers and corresponding register addresses of a set of accelerators; a mapping table indicating at least one hardware resource in the computing device for each accelerator in the set of accelerators; or a second description table including corresponding identifiers of hardware resources in the computing device for the set of accelerators.

[0069] In some embodiments, at least a first accelerator in a group of accelerators includes a plurality of acceleration units, and a first description table includes at least one of the following: a hardware identifier of the first accelerator, corresponding to a register address of the first accelerator, or corresponding to register addresses of the plurality of acceleration units respectively.

[0070] In some embodiments, at least one hardware resource includes at least one of the following: a system memory management unit, or an interrupt translation service.

[0071] In some embodiments, initializing a set of accelerators includes: using a driver to set a corresponding sharing mode for a plurality of accelerator units, wherein the sharing mode of one of the accelerator units indicates whether the accelerator unit is shared by a plurality of processes.

[0072] In some embodiments, the computing device is based on a high-level reduced instruction set architecture, and the processing unit of the computing device includes a set of accelerators.

[0073] In some embodiments, the computing device includes a plurality of processing cores, a second accelerator in a set of accelerators includes a plurality of acceleration units, and performing a task includes: allocating a first number of processing cores and a second number of acceleration units to a virtual machine; and performing the task through the virtual machine.

[0074] Example devices and equipment

[0075] Figure 7 A schematic structural block diagram of an apparatus 700 for managing an accelerator according to certain embodiments of the present disclosure is shown. The apparatus 700 may be implemented as or included in an operating system 120. Various modules / components in the apparatus 700 may be implemented by hardware, software, firmware, or any combination thereof.

[0076] As shown in the figure, device 700 includes an interface information acquisition module 710, configured to acquire interface information associated with a set of accelerators in a computing device. The interface information at least indicates corresponding identification information and corresponding mapping information for the set of accelerators, wherein the mapping information for one accelerator indicates hardware resources in the computing device used for that accelerator. Device 700 also includes an accelerator initialization module 720, configured to initialize the set of accelerators based on the interface information using a driver of the computing device. Device 700 also includes a task execution module 730, configured to execute a task using at least a portion of the initialized set of accelerators.

[0077] In some embodiments, the interface information is reported by the firmware to the operating system of the computing device.

[0078] In some embodiments, the interface information includes at least one of the following: a first description table including corresponding hardware identifiers and corresponding register addresses of a set of accelerators; a mapping table indicating at least one hardware resource in the computing device for each accelerator in the set of accelerators; or a second description table including corresponding identifiers of hardware resources in the computing device for the set of accelerators.

[0079] In some embodiments, at least a first accelerator in a group of accelerators includes a plurality of acceleration units, and a first description table includes at least one of the following: a hardware identifier of the first accelerator, corresponding to a register address of the first accelerator, or corresponding to register addresses of the plurality of acceleration units respectively.

[0080] In some embodiments, at least one hardware resource includes at least one of the following: a system memory management unit, or an interrupt translation service.

[0081] In some embodiments, the accelerator initialization module 720 is further configured to use a driver to set a corresponding sharing mode for a plurality of accelerator units, wherein the sharing mode of one of the accelerator units indicates whether the accelerator unit is shared by multiple processes.

[0082] In some embodiments, the computing device is based on a high-level reduced instruction set architecture, and the processing unit of the computing device includes a set of accelerators.

[0083] In some embodiments, the computing device includes a plurality of processing cores, a second accelerator in a set of accelerators includes a plurality of acceleration units, and the task execution module is further configured to assign a first number of processing cores in the plurality of processing cores and a second number of acceleration units in the plurality of acceleration units to a virtual machine; and to execute a task through the virtual machine.

[0084] Figure 8 A block diagram is shown illustrating an electronic device 800 in which one or more embodiments of the present disclosure may be implemented. It should be understood that... Figure 8The electronic device 800 shown is merely exemplary and should not be construed as limiting the functionality and scope of the embodiments described herein. Figure 8 The electronic device 800 shown can be used to achieve Figure 1 Operating system 120.

[0085] like Figure 8 As shown, electronic device 800 is in the form of a general-purpose electronic device. Components of electronic device 800 may include, but are not limited to, one or more processors or processing units 810, memory 820, storage device 830, one or more communication units 840, one or more input devices 850, and one or more output devices 860. Processing unit 810 may be a physical or virtual processor and is capable of performing various processes according to programs stored in memory 820. In a multiprocessor system, multiple processing units execute computer-executable instructions in parallel to improve the parallel processing capability of electronic device 800.

[0086] Electronic device 800 typically includes multiple computer storage media. Such media can be any accessible media that is accessible to electronic device 800, including but not limited to volatile and non-volatile media, removable and non-removable media. Memory 820 can be volatile memory (e.g., registers, cache, random access memory (RAM)), non-volatile memory (e.g., read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory), or some combination thereof. Storage device 830 can be a removable or non-removable medium and can include machine-readable media, such as flash drives, disks, or any other media that can be used to store information and / or data (e.g., training data for training) and can be accessed within electronic device 800.

[0087] Electronic device 800 may further include additional removable / non-removable, volatile / non-volatile storage media. Although not explicitly stated... Figure 8 As shown, disk drives for reading from or writing to removable, non-volatile disks (e.g., "floppy disks") and optical disk drives for reading from or writing to removable, non-volatile optical disks can be provided. In these cases, each drive can be connected to a bus (not shown) via one or more data media interfaces. Memory 820 may include computer program product 825 having one or more program modules configured to perform various methods or actions of various embodiments of this disclosure.

[0088] The communication unit 840 enables communication with other electronic devices via a communication medium. Additionally, the functionality of the components of the electronic device 800 can be implemented using a single computing cluster or multiple computing machines capable of communicating via communication connections. Therefore, the electronic device 800 can operate in a networked environment using logical connections to one or more other servers, network personal computers (PCs), or another network node.

[0089] Input device 850 can be one or more input devices, such as a mouse, keyboard, trackball, etc. Output device 860 can be one or more output devices, such as a monitor, speaker, printer, etc. Electronic device 800 can also communicate with one or more external devices (not shown) via communication unit 840 as needed. These external devices include storage devices, display devices, etc., and can communicate with one or more devices that enable user interaction with electronic device 800, or with any device that enables electronic device 800 to communicate with one or more other electronic devices (e.g., network card, modem, etc.). Such communication can be performed via input / output (I / O) interface (not shown).

[0090] According to an exemplary implementation of this disclosure, a computer-readable storage medium is provided that stores computer-executable instructions thereon, wherein the computer-executable instructions are executed by a processor to implement the methods described above. According to an exemplary implementation of this disclosure, a computer program product is also provided, which is tangibly stored on a non-transitory computer-readable medium and includes computer-executable instructions, which are executed by a processor to implement the methods described above.

[0091] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatuses, devices, and computer program products implemented according to this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0092] These computer-readable program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processing unit of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner. Thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0093] Computer-readable program instructions can be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions that execute on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0094] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction, which contains one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0095] Various implementations of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed implementations. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described implementations. The terminology used herein is chosen to best explain the principles, practical applications, or improvements to technology in the market, or to enable others skilled in the art to understand the various implementations disclosed herein.

Claims

1. A method for managing an accelerator, comprising: The interface information associated with a set of accelerators in the processing unit of the computing device is obtained. The interface information indicates at least the corresponding identification information and corresponding mapping information of the set of accelerators. The mapping information of one of the accelerators indicates the hardware resources in the computing device used for that accelerator. The set of accelerators is mounted to a bus through a system memory management unit. The system memory management unit assigns a flow identifier to each of the set of accelerators. Using the driver of the computing device, initialize the set of accelerators according to the interface information; as well as The task is performed using at least a portion of the initialized set of accelerators.

2. The method according to claim 1, wherein the interface information is reported by the firmware to the operating system of the computing device.

3. The method according to claim 1, wherein the interface information includes at least one of the following: The first description table includes the corresponding hardware identifiers and corresponding register addresses of the group of accelerators. A mapping table, for each of the set of accelerators, indicates at least one hardware resource in the computing device used for that accelerator, or The second description table includes corresponding identifiers of the hardware resources in the computing device used for the set of accelerators.

4. The method of claim 3, wherein at least the first accelerator in the group of accelerators comprises a plurality of acceleration units, and the first description table comprises at least one of the following: The hardware identifier of the first accelerator, Corresponding to the register address of the first accelerator, or These correspond to the register addresses of the plurality of acceleration units, respectively.

5. The method of claim 3, wherein the at least one hardware resource comprises at least one of the following: System memory management unit, or Translation service interrupted.

6. The method of claim 4, wherein initializing the set of accelerators comprises: The driver is used to set the corresponding sharing mode of the plurality of acceleration units, wherein the sharing mode of one of the acceleration units indicates whether the acceleration unit is shared by multiple processes.

7. The method of claim 1, wherein the computing device is based on an Advanced Reduced Instruction Set Computing (RISC) architecture.

8. The method of claim 1, wherein the computing device comprises a plurality of processing cores, the second accelerator in the set of accelerators comprises a plurality of acceleration units, and performing the task comprises: Assign a first number of processing cores and a second number of acceleration units from the plurality of processing cores to the virtual machine; as well as The task is performed using the virtual machine.

9. An apparatus for managing an accelerator, comprising: An interface information acquisition module is configured to acquire interface information associated with a group of accelerators in a processing unit of a computing device. The interface information indicates at least the corresponding identification information and corresponding mapping information of the group of accelerators. The mapping information of one of the accelerators indicates the hardware resources in the computing device used for that accelerator. The group of accelerators is mounted to a bus through a system memory management unit. The system memory management unit assigns a flow identifier to each accelerator in the group of accelerators. An accelerator initialization module is configured to initialize the set of accelerators according to the interface information using the driver of the computing device. as well as The task execution module is configured to perform a task using at least a portion of the initialized set of accelerators.

10. An electronic device, comprising: At least one processing unit; as well as At least one memory, coupled to the at least one processing unit and storing instructions for execution by the at least one processing unit, which, when executed by the at least one processing unit, cause the electronic device to perform the method according to any one of claims 1 to 8.

11. A computer-readable storage medium having a computer program stored thereon, the computer program being executable by a processor to implement the method according to any one of claims 1 to 8.

Images