Time sequence generator based on FPGA, time sequence generation method, terminal equipment and readable storage medium

Abstract

The invention relates to the field of semiconductors, and discloses an FPGA-based time sequence generator, a time sequence generation method, terminal equipment and a readable storage medium, and the FPGA-based time sequence generator comprises a clock source which is used for providing a working frequency; the test period buffer is used for sequentially caching the data of each test period; the time sequence data cache is used for sequentially caching all time sequence data; the test period counter is used for starting counting every time one test period is entered; the time sequence edge generator is used for determining whether the time sequence clock is enabled or not according to the count of the test period data of the same test period and the integer part value of the time sequence data, and outputting the decimal part value of the time sequence clock which is not full of the integer multiple; the data generator is used for generating the received one-bit mode data into parallel data with a preset bit width when the time sequence clock is enabled; and the converter is used for converting the parallel data into serial data by using the preset frequency multiplication clock of the working frequency and then outputting the serial data. According to the scheme, the time resolution based on the time sequence generator can be improved.

Description

Technical Field

[0001] The present application relates to the semiconductor field, and in particular to a FPGA-based timing generator, a timing generation method, a terminal device, and a readable storage medium. Background Art

[0002] In semiconductor test systems, the timing generator is an indispensable module. Its function is to generate test cycles and output the required data at a fixed time in each cycle, while keeping the rest of the time unchanged. Among them, the common tools for implementing timing generators are FPGA (Field-Programmable Gate Array) and IC chips dedicated to timing generation. Compared with using FPGA, IC chips are more expensive, require specialized IC chips, and have a long development cycle.

[0003] Therefore, it is necessary to propose a timing generator based on FPGA. However, FPGA needs to work in a rhythmic manner under a fixed-frequency clock. For example, the operating frequency of common industrial-grade FPGA chips is generally not higher than 200MHz. The problem brought about by this is that the time resolution of the timing generator is limited by the FPGA clock. Assuming the clock frequency is 200MHz, the time resolution is the clock period T=5ns, which often cannot meet the requirements when higher time resolution is required. Summary of the invention

[0004] In view of this, the present application provides a timing generator based on FPGA, a timing generation method, a terminal device and a readable storage medium, which can effectively improve the problem of FPGA-based time resolution.

[0005] In a first aspect, an embodiment of the present application provides a timing generator based on FPGA, comprising: The clock source is used to provide the operating frequency required by other units in the FPGA; A test cycle buffer, used to sequentially buffer each test cycle data, and output a first integer part value and a first decimal part value of each test cycle data calculated based on the operating frequency; A timing data buffer, used for sequentially buffering each timing data, and outputting a second integer part value and a second decimal part value of each timing data calculated based on the operating frequency; A test cycle counter, used for starting counting each time a test cycle is entered, and outputting the difference between the first decimal part value of the current test cycle data and the first decimal part value of the previous test cycle data; A timing edge generator, configured to determine whether a timing clock is enabled according to the count of the test cycle data of the same test cycle and the second integer part value, and output a third fractional part value that is less than an integer multiple of the timing clock according to the difference and the second fractional part value; A data generator, configured to generate parallel data of a preset bit width from the received one-bit pattern data according to the value of the third decimal part when the timing clock is enabled; The converter is used to convert the parallel data into serial data by using a preset multiplied clock of the working frequency and then output the serial data.

[0006] In some embodiments, the test cycle counter is further used to clear to zero when the count reaches a value where the difference between the first integer part of the current test cycle data and the test cycle borrow is zero.

[0007] In some embodiments, the test cycle buffer is specifically used to divide the test cycle data by the clock period corresponding to the operating frequency, and obtain the quotient and remainder as the first integer part value and the first decimal part value respectively.

[0008] In some embodiments, the timing data buffer is specifically used to divide the timing data by the clock period corresponding to the operating frequency, and the obtained quotient and remainder are used as the second integer part value and the second decimal part value respectively.

[0009] In some embodiments, the timing edge generator is specifically used to determine that the timing clock is enabled when the difference between the second integer part value and the borrow of the timing data in the same test cycle is equal to the count of the test cycle data; and to use the difference between the difference and the second decimal part value as the third decimal part value that is less than an integer multiple of the timing clock.

[0010] In some embodiments, the data generator is specifically used to determine the maintenance length of the pattern data according to the value of the third decimal part when the timing clock is enabled; Furthermore, the bits from the highest bit to the bits corresponding to the maintenance length in the preset bit width are set as the mode data, and the values ​​of the remaining bit widths except the maintenance length are set to the highest bit value of the mode data input in the previous test cycle to generate parallel data of the preset bit width.

[0011] In some embodiments, the value of the test cycle data is not less than the clock cycle corresponding to the operating frequency; The value range of the timing data is: test rate ~ T / 8; where test rate is the test period and T is the clock period.

[0012] In a second aspect, an embodiment of the present application further provides a timing generation method based on FPGA, which is applied to the timing generator; the method comprises: Obtain a first integer value and a first decimal value of each preset test cycle data calculated based on the operating frequency of the FPGA; Obtain a second integer part value and a second decimal part value of each preset time series data calculated based on the operating frequency; Each time a test cycle is entered, counting is started according to the working frequency, and the difference between the first decimal part value of the current test cycle data and the previous test cycle data is output; Determine whether the timing clock is enabled according to the count of the test cycle data of the same test cycle and the second integer part value, and output a third fractional part value that is less than an integer multiple of the timing clock according to the difference and the second fractional part value; When the timing clock is enabled, generating parallel data of a preset bit width from the received one-bit pattern data according to the value of the third decimal part; The parallel data is converted into serial data using a preset multiplied clock of the operating frequency and then output.

[0013] In a third aspect, an embodiment of the present application further provides a terminal device, the terminal device comprising an FPGA, and the terminal device is used to implement the FPGA-based timing generation method.

[0014] In a fourth aspect, an embodiment of the present application further provides a readable storage medium storing a computer program, wherein when the computer program is executed, the FPGA-based timing generation method is implemented.

[0015] The embodiments of the present application have the following advantages: The present application proposes a timing generator based on FPGA, including a clock source for providing an operating frequency, a test cycle buffer for caching test cycle data, a timing data buffer for caching timing data, and a test cycle counter for starting counting each time a test cycle is entered, and outputting the difference between the first fractional value of the current test cycle data and the first fractional value of the previous test cycle data; a timing edge generator for determining whether the timing clock is enabled according to the count of the test cycle data of the same test cycle and the integer value of the timing data, and outputting the fractional value of the timing clock that is not an integer multiple; a data generator for generating parallel data of a preset bit width from the received one-bit mode data when the timing clock is enabled; and a converter for converting the parallel data into serial data and outputting it using the preset multiplier clock of the operating frequency. Compared with the existing timing generator based on the FPGA platform, this solution can improve the resolution of the timing generator to T / 8 at the same FPGA operating frequency, thereby achieving more precise timing control. BRIEF DESCRIPTION OF THE DRAWINGS In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0016] Figure 1 A schematic diagram of the structure of a timing generator according to an embodiment of the present application is shown; Figure 2 A verification waveform diagram of the timing generator of an embodiment of the present application is shown; Figure 3 A flow chart of a timing generation method according to an embodiment of the present application is shown.

[0017] Description of main component symbols: 10-timing generator; 110-clock source; 120-test cycle buffer; 130-timing data buffer; 140-test cycle counter; 150-timing edge generator; 160-data generator; 170-converter. DETAILED DESCRIPTION

[0018] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0019] The components of the embodiments of the present application generally described and shown in the drawings herein may be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0020] Hereinafter, the terms "including", "having" and their cognates, which may be used in various embodiments of the present application, are intended only to indicate specific features, numbers, steps, operations, elements, components, or combinations of the foregoing items, and should not be understood as first excluding the existence of one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing items or adding the possibility of one or more features, numbers, steps, operations, elements, components, or combinations of the foregoing items.

[0021] Furthermore, the terms “first”, “second”, “third”, etc. are merely used for distinguishing descriptions and are not to be understood as indicating or implying relative importance.

[0022] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meanings as those generally understood by those skilled in the art to which the various embodiments of the present application belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meanings as the contextual meanings in the relevant technical field and will not be interpreted as having idealized meanings or overly formal meanings unless clearly defined in the various embodiments of the present application.

[0023] Figure 1 A schematic diagram of the structure of an FPGA-based timing generator 10 according to an embodiment of the present application is shown. Exemplarily, the timing generator 10 uses a hardware FPGA as a platform and combines software logic to solve the problem that the time resolution of FPGA is limited by the clock of the FPGA in the prior art, and can especially realize fractional timing signals to achieve the effect of improving the time resolution.

[0024] In order to facilitate the input and output signals of these components in the text, the English symbols and Chinese meanings involved in this application are first uniformly explained here.

[0025] T: clock period; test rate: test cycle data; rate_n: the integer part of the test cycle data, abbreviated as the first integer part value; rate_m: the decimal value of the test cycle data, abbreviated as the first decimal value; timing: timing data; timing_n: the integer part value of the timing data, abbreviated as the second integer part value; timing_m: the fractional value of the timing data, abbreviated as the second fractional value; fifo_rd: fifo read enable signal; counter: the count value when entering a test cycle, with a bit width of 8 bits, i.e. counter [7:0]; sum_m: the difference between the decimal values ​​of the current test cycle data and the previous test cycle data, abbreviated as the difference between the first decimal values; rate_borrow: borrow signal of the test cycle; period_sop: the start signal of a testing period; clk: the reference signal output by the clock source; clk_en: timing clock enable signal; clk_m: the fractional value of the timing clock that is not an integer multiple, abbreviated as the third fractional value; timing_borrow: borrow signal of timing data; pattern_data: pattern data used for testing; parall_data: parallel data, whose bit width can be 8 bits, that is, parall_data [7:0]; data_out: serial data output by the converter.

[0026] Exemplarily, the timing generator 10 includes: a clock source (base_clk) 110, a test cycle buffer (rate_fifo) 120, a timing data buffer (timing_fifo) 130, a test cycle counter (rate_counter) 140, a timing edge generator (timing_edge_generator) 150, a data generator (data_generate) 160 and a converter (oserdes) 170. Among them, the clock source 110 is respectively connected to the test cycle buffer 120, the timing data buffer 130, the test cycle counter 140, the timing edge generator 150, the data generator 160 and the converter 170 to provide the operating frequency required by each unit. The test cycle buffer 120, the test cycle counter 140, the timing edge generator 150, the data generator 160 and the converter 170 are connected in sequence; the timing data buffer 130 is respectively connected to the test cycle counter 140 and the timing edge generator 150.

[0027] The clock source 110 is used to provide the operating frequency required by each unit in the FPGA, so that each unit can work in a rhythmic manner under the clock period (denoted as T) corresponding to the operating frequency. For example, for an industrial-grade FPGA chip, the operating frequency can range from 1MHz to 200MHz. Accordingly, the clock period corresponding to the operating frequency can range from 1us to 5ns.

[0028] The test cycle buffer 120 is used to cache each test cycle data (denoted as test rate). After each test cycle of the FPGA is completed, the next test cycle data will be stored in the test cycle buffer 120. In the present application, test cycles of the same or different sizes can be set each time. Since the maximum operating frequency of the FPGA does not exceed 2000MHz, its corresponding time resolution is 5ns. For example, only one bit of data can be output within a 5ns period of time. Therefore, the present application sets a test cycle and enables the output of multiple data to be completed within the test cycle. Generally, the test cycle data can be taken according to the time resolution of the FPGA. For example, when the maximum operating frequency of the FPGA is 200MHz, the value range of the test cycle data can be set to 1us~5ns.

[0029] It should be noted that the timing generator 10 in the present application can be a decimal integral type, but considering that it is difficult to represent decimals in FPGA, all calculations about test cycles and timing data are converted into integer calculations. In order to better understand this solution, here we mainly take the example of improving the resolution of timing data to T / 8 as an example. Accordingly, in the actual addition and subtraction process, it is calculated according to octal system, that is, the decimal part is calculated by 1 every time it reaches 8. It can be understood that, assuming that the maximum operating frequency of the FPGA is 200MHz, compared with the original resolution (T=5ns), the resolution can be increased to 625ps (ie T / 8) after adopting the solution of this application. It should be noted that this solution is not limited to improving the resolution to T / 8, and can be adaptively adjusted according to actual needs, and no specific limitation is made here.

[0030] As an optional solution, the test cycle can be set to a non-integer multiple of the clock cycle, that is, it does not need to be an integer multiple of T. In the present application, the test cycle buffer 120 is also used to calculate and output the first integer part value (denoted as rate_n) and the first decimal part value (denoted as rate_m) of each test cycle data based on the current operating frequency of the FPGA. Among them, the meanings represented by the above-mentioned first integer part value and the first decimal part value are respectively: the test cycle contains an integer number of T and the remaining part less than one T.

[0031] For example, in one implementation, the quotient and remainder obtained by dividing the test rate by T can be used as the first integer value and the first decimal value, respectively. For example, assuming T=5ns, test rate=8.125ns, then rate_n=1, rate_m=5. It can be understood that the "first" identifier is used here mainly to distinguish from the integer and decimal values ​​of other data such as timing data mentioned later and to facilitate reference.

[0032] The timing data buffer 130 is used to cache each timing data. After the test cycle is specified, the timing data is used to control the output timing of the data within the test cycle. In the present application, the timing data should not be less than the minimum time resolution of the test cycle. In one embodiment, the minimum time resolution of the timing generator 10 is 1 / 8 of the clock cycle corresponding to the operating frequency, so the value range of the timing data can be test rate~T / 8. For example, if the time resolution of the current FPGA is 5ns, in order to make the resolution of the timing generator 10 T / 8 (that is, the resolution is 625ps), the timing data can take values ​​between (test rate~625ps).

[0033] As an optional solution, the timing data can also be set to a non-integer multiple of the timing value. In the present application, the timing data buffer 130 is also used to calculate and output the second integer part value (recorded as timing_n) and the second decimal part value (recorded as timing_m) of each timing data based on the current operating frequency of the FPGA. Among them, the meanings represented by the second integer part value and the second decimal part value are respectively: the timing contains an integer number of T and the remaining part less than one T.

[0034] For example, in one implementation, the quotient and remainder obtained by dividing timing by T can be used as the second integer value and the second decimal value, respectively. For example, assuming T=5ns, timing=1.25ns, then timing_n=0, timing_m=2. It can be understood that the "second" identifier is used here mainly to distinguish from the integer and decimal values ​​of other data mentioned above and to facilitate reference.

[0035] In some embodiments, the test cycle buffer 120 and the timing data buffer 130 can be implemented by a fifo (First In First Out) unit. Furthermore, the fifo units can be operated in a FWFT (first_word_fall_through) mode. It can be understood that the first valid data can be read out in the first cycle when the read enable signal (fifo_rd) of the fifo is valid in the FWFT mode, which can reduce the read delay of one cycle compared to the fifo in the Standard mode. The test cycle counter 140 is used to start counting (the count value is recorded as counter) every time a test cycle is entered, and output the difference between the first decimal part of the current test cycle data and the previous test cycle data (recorded as sum_m). The purpose of the count value counter is to count the number of clock cycles included in the current test cycle. The difference sum_m is used to record the extra decimal time in the previous test cycle. It can be understood that when entering the first test cycle, since there is no previous test cycle data, the difference sum_m of the first test cycle is 0 at this time. In the next test cycle, the extra time of the previous test cycle needs to be subtracted.

[0036] Exemplarily, after the test cycle buffer 120 obtains a test cycle data, the test cycle counter 140 starts counting from 0 according to the beat of the FPGA clock cycle until the count reaches the difference between the first integer part value rate_n of the current test cycle data and the test cycle borrow rate_borrow is zero, and then it is cleared.

[0037] For example, if we use an expression to describe it, we have: when counter = rate_n-rate_borrow, counter is reset to 0. Among them, rate_borrow is the borrow of the test cycle, indicating whether the part of the current test cycle that is less than T is enough to deduct the extra time of the previous test cycle, that is, whether rate_m - sum_m will generate a borrow. If a borrow occurs, rate_borrow=1, so the integer part of the count counter of the current test cycle is reduced by 1.

[0038] As an optional solution, after the count is cleared, the test cycle counter 140 will restart counting when the next test cycle data arrives. At the same time, each time a new test cycle is entered, the test cycle counter 140 sets the signal fifo_rd of the test cycle buffer 120 and the timing data buffer 130 to 1 (i.e., sets the read enable signal of the fifo to be valid). In addition, the start signal period_sop for indicating the start of a test cycle is valid.

[0039] Furthermore, when the read enable of the fifo is valid, the test cycle counter 140 starts to perform a subtraction operation on the difference between the first decimal part of the current test cycle data and the previous test cycle data. For example, in one embodiment, the subtraction rule of the difference is as follows: If the first fractional value rate_m of the current test cycle is less than the difference value sum_m of the previous test cycle, then a new difference value of the current test cycle is updated by borrowing one bit from the first integer value of the current test cycle, and a valid count borrow rate_borrow is generated (that is, rate_borrow is 1). Otherwise, the difference between the first fractional value rate_m of the current test cycle and the difference value sum_m of the previous test cycle is directly used as the updated difference value.

[0040] The timing edge generator 150 is used to determine whether the timing clock (denoted as clk_en) is enabled according to the count and the second integer part value of the test cycle data of the same test cycle, and output the third decimal part value (denoted as clk_m) of the timing clock that is less than an integer multiple according to the difference and the second decimal part value.

[0041] Among them, the timing clock is enabled (i.e., clk_en=1), which means that in each test cycle, the time of an integer clock cycle T of the timing data (timing) has been reached. The third decimal part of the timing clock that is not an integer multiple is used to indicate how many non-integer Ts are left when the integer T of timing is reached in the current test cycle. Among them, the initial value of clk_m is 0.

[0042] As for the method of determining the timing clock, exemplarily, within the same test cycle, if the difference between the second integer part of the timing data and the borrow of the timing data is equal to the count of the test cycle data, if described by an expression, that is, counter=timing_n-timing_borrow, then the timing clock is determined to be enabled.

[0043] Specifically, there are two situations: no timing data borrow is generated (ie, timing_borrow=0) and no timing data borrow is generated (ie, timing_borrow=1).

[0044] In one case, when timing_borrow=0, if the value of the second integer part of the timing data is equal to the count of the current test cycle data (such as equal to 0), it is determined that the timing clock is enabled. Figure 2 As shown, in the first test cycle, timing = 1.25ns, timing_n = 0, timing_m = 2, sum_m = 0, timing_m - sum_m does not generate a carry (that is, timing_borrow = 0), counter = timing_n - timing_borrow = 0-0 = 0, clk_en = 1.

[0045] In another case, when timing_borrow=1, if the difference between the value of the second integer part of the timing data and the borrow of the timing data is equal to the count of the current test cycle data, the timing clock can also be determined to be enabled. Figure 2 As shown, in the second test cycle, timing = 5.625ns, timing_n = 1, timing_m = 1, sum_m = 3, timing_m - sum_m generates a carry (that is, timing_borrow = 1), counter = timing_n -timing_borrow = 1-1=0, and clk_en = 1.

[0046] The third fractional value is related to the difference between the first fractional value calculated in the current test cycle and the second fractional value of the timing data in the same test cycle. When entering each test cycle, the fractional value of the residual of the timing clock that is not a full integer begins to be subtracted. For example, in one embodiment, the subtraction operation rule of the third fractional value is as follows: In the same test cycle, when the second decimal part of the time series data is greater than or equal to the difference between the first decimal part, since there is no need to borrow to subtract, the third decimal part is equal to the difference between the second decimal part and the difference. On the contrary, it is necessary to borrow to subtract from the integer part of the time series data, so the third decimal part is equal to the second decimal part plus 8 and the difference.

[0047] For example, in the first test cycle, clk_m = timing_m - sum_m = 2-0=2; in the second test cycle, clk_m = timing_m - sum_m = 1-3, which is not enough for subtraction, so after borrowing, clk_m = timing_m + 8 - sum_m=1+8-3=6, and so on.

[0048] It can be understood that when the timing clock in the customized test cycle is enabled, it means that data can be read or output.

[0049] The data generator 160 is used to generate parallel data with a preset bit width from the received one-bit pattern data according to the value of the third decimal part when the integer timing clock is enabled.

[0050] The parallel data (parall_data) can be described by using multiple bit widths, for example, 2 to 8 bits, which can be set according to actual needs. Taking 8 bits as an example, the parallel data can be described as [7:0], where 7 is used to represent the highest bit and 0 is used to represent the lowest bit.

[0051] In some embodiments, when the timing clock is enabled, the data generator 160 determines the maintenance length of the pattern data (pattern_data) according to the value of the third fractional part. Further, after the maintenance length is determined, the bits from the highest bit to the bits corresponding to the maintenance length in the preset bit width are set as the pattern data, and the values ​​of the remaining bit widths except the maintenance length are set as the highest bit value of the pattern data input in the previous test cycle, thereby generating parallel data of the preset bit width.

[0052] Taking the preset bit width of 8 bits as an example, when clk_en is 1, according to the value of clk_m, pattern_data is placed on the bits [7:clk_m] of the parallel (parall_data) data; the remaining bits maintain the 7th bit of the previous parall_data data. For example, when the value of clk_m is 2, pattern_data=1, and the previous parall_data data is 8'b0000_0000 in binary. Then the 3rd to 8th bits of the parallel data of the current test cycle are: parall_data[7:2]=6'b111111, and the 1st to 2nd bits of the parallel data are: parall_data[1:0]=2'b00. Therefore, the combination can obtain 8-bit parallel data, that is, 8'b1111_1100, and its corresponding hexadecimal is 8'hfc.

[0053] The converter 170 is used to convert the parallel data into serial data using the preset multiplier clock of the FPGA's operating frequency and then output it. It can be understood that by converting the generated parallel data into serial output by the converter 170, continuous output of multi-bit data can be achieved within one test cycle.

[0054] For example, in one implementation, the preset frequency-multiplied clock may be adaptively set according to the bit width of the parallel data, for example, when the bit width of the parallel data is 8 bits, the preset frequency-multiplied clock may be set to be a quadruple frequency clock of the reference signal (referred to as clk) (e.g. Figure 1 The clk quadruple frequency signal shown in the figure) is output at each rising edge and falling edge of clk (recorded as data_out), thereby completing the output of 8 bits of data under a quadruple frequency clock.

[0055] In order to verify the feasibility of the timing generator of this application, Figure 2 As shown, by selecting the operating frequency of 2000MHz, the clock cycle T is 5ns, as the clk signal, and setting 4 test cycles and timing data, respectively: the first test cycle data is 8.125ns, the first timing data is 1.25ns; the second test cycle is 10.625ns, the second timing data is 5.625ns, the third test cycle is 7.5ns, the third timing data is 5ns, the fourth test cycle is 12.5ns, and the fourth timing data is 8.125ns. In each test cycle, it can be seen from the waveform of the generated parallel data that 8-bit data output can be achieved in each 5ns. Therefore, it can be explained that the minimum time resolution of the timing generator 10 can be increased to 1 / 8 of the clock cycle T of the FPGA.

[0056] The FPGA-based timing generator 10 of the present application cooperates by utilizing the test cycle buffer 120 and the timing data buffer 130, the test cycle counter 140, the timing edge generator 150, the data generator 160 and the converter 170. Under the premise of using fewer lookup table (LUT) resources and storage resources, the time resolution of the timing generator 10 can be improved to 1 / 8 of the FPGA working cycle T at the same frequency, thereby achieving more precise timing control. Moreover, by adopting the fifo unit in FWFT mode, it only takes one clock cycle to delay from reading data from the fifo to generating the timing clock enable signal and accumulating the fractional part of the timing information, thus achieving a low latency effect.

[0057] Figure 3 A flow chart of a timing generation method based on FPGA according to an embodiment of the present application is shown. Exemplarily, the timing generation method based on FPGA includes: S100, obtaining the first integer value and the first decimal value of each preset test cycle data calculated based on the working frequency of the FPGA. This step is mainly performed by the test cycle buffer 120 to store and output the first integer value and the first decimal value.

[0058] S200, obtaining the second integer value and the second decimal value of each preset time series data calculated based on the operating frequency. In this step, the time series data buffer 130 is mainly used to store and output the second integer value and the second decimal value.

[0059] S300, each time a test cycle is entered, counting is started according to the working frequency, and the difference between the first decimal part of the current test cycle data and the previous test cycle data is output. This step is mainly implemented by the test cycle counter 140 mentioned above.

[0060] S400, determining whether the integer timing clock is enabled according to the count of the test cycle data of the same test cycle and the second integer part value, and outputting the third fractional part value of the less than integer timing clock according to the difference and the second fractional part value. This step is mainly implemented by the timing edge generator 150 mentioned above.

[0061] S500, when the timing clock is enabled, generating parallel data of a preset bit width from the received one-bit pattern data according to the value of the third fractional part. This step is mainly implemented by the above-mentioned data generator 160.

[0062] S600, using a preset multiplied clock of the working frequency to convert the parallel data into serial data and then output it. This step is mainly implemented by the converter 170 mentioned above.

[0063] It can be understood that the timing generation method of this embodiment is implemented by various modules in the timing generator 10 of the above embodiment, so the specific implementation details of each step can be referred to the corresponding records of the above embodiment, and will not be repeated here. In addition, the options in the above embodiment are also applicable to this embodiment, so they will not be repeated here.

[0064] The present application also provides a terminal device. Exemplarily, the terminal device includes an FPGA, wherein the terminal device is used to use the FPGA to implement the timing generation method of the embodiment of the present application.

[0065] The present application also provides a computer-readable storage medium for storing a computer program used in the above-mentioned terminal device. For example, the computer-readable storage medium may include, but is not limited to, various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0066] In several embodiments provided in the present application, it should be understood that the disclosed apparatus and method can also be implemented in other ways. The apparatus embodiments described above are merely schematic, for example, the flowcharts and structure diagrams in the accompanying drawings show the possible architecture, functions and operations of the apparatus, method and computer program product according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and a module, a program segment or a part of a code contains one or more executable instructions for implementing a specified logical function. It should also be noted that in an alternative implementation, the functions marked in the box can also occur in a different order from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the structure diagram and / or the flow diagram, and the combination of boxes in the structure diagram and / or the flow diagram, can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0067] In addition, the functional modules or units in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0068] If the function is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a smart phone, a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods of each embodiment of the present application.

[0069] The above are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be covered by the protection scope of the present application.

Claims

1. A timing generator based on FPGA, characterized in that: include: The clock source is used to provide the operating frequency required by other units in the FPGA; A test cycle buffer, used to sequentially buffer each test cycle data, and output a first integer part value and a first decimal part value of each test cycle data calculated based on the operating frequency; A timing data buffer, used for sequentially buffering each timing data, and outputting a second integer part value and a second decimal part value of each timing data calculated based on the operating frequency; A test cycle counter, used to start counting each time a test cycle is entered, and output the difference between the value of the first decimal part of the current test cycle data and the value of the first decimal part of the previous test cycle data; A timing edge generator, configured to determine whether a timing clock is enabled according to the count of the test cycle data of the same test cycle and the second integer part value, and output a third fractional part value that is less than an integer multiple of the timing clock according to the difference and the second fractional part value; A data generator, configured to generate parallel data of a preset bit width from the received one-bit pattern data according to the value of the third decimal part when the timing clock is enabled; The converter is used to convert the parallel data into serial data by using a preset multiplied clock of the working frequency and then output the serial data.

2. The timing generator according to claim 1, characterized in that: The test cycle counter is further used for clearing to zero when the count reaches a value where the difference between the first integer part value of the current test cycle data and the test cycle borrow is zero.

3. The timing generator according to claim 2, characterized in that: The test cycle counter is also used to restart counting when the next test cycle data arrives after the count is cleared; at the same time, when entering each new test cycle, the read enable signals of the test cycle buffer and the timing data buffer are valid, and the start signal indicating the start of a test cycle is valid.

4. The timing generator according to claim 3, characterized in that: The test cycle counter is also used to start subtracting the difference between the first decimal part of the current test cycle data and the first decimal part of the previous test cycle data when the read enable signal is valid, specifically including: If the first decimal part value of the current test cycle is smaller than the difference value of the previous test cycle, the new difference value of the current test cycle is updated by borrowing one bit from the first integer part value of the current test cycle; otherwise, the difference between the first decimal part value of the current test cycle and the difference value of the previous test cycle is directly taken as the updated difference value.

5. The timing generator according to claim 1, characterized in that: The test cycle buffer is specifically used to divide the test cycle data by the clock cycle corresponding to the operating frequency, and obtain the quotient and remainder as the first integer part value and the first decimal part value respectively.

6. The timing generator according to claim 1, characterized in that: The timing data buffer is specifically used to divide the timing data by the clock period corresponding to the operating frequency, and obtain the quotient and remainder as the second integer part value and the second decimal part value respectively.

7. The timing generator according to claim 1, characterized in that: The timing edge generator is specifically used to determine that the timing clock is enabled when the difference between the second integer part value and the borrow of the timing data in the same test cycle is equal to the count of the test cycle data; And, the difference between the difference and the second fractional part value is taken as the third fractional part value of the timing clock which is less than an integer multiple.

8. The timing generator according to claim 1, characterized in that: The data generator is specifically configured to determine the maintenance length of the pattern data according to the value of the third decimal part when the timing clock is enabled; Furthermore, the bits from the highest bit to the bits corresponding to the maintenance length in the preset bit width are set as the mode data, and the values ​​of the remaining bit widths except the maintenance length are set to the highest bit value of the mode data input in the previous test cycle to generate parallel data of the preset bit width.

9. The timing generator according to claim 1, characterized in that: The value of the test cycle data is not less than the clock cycle corresponding to the operating frequency; The value range of the timing data is: test rate ~ T / 8; where test rate is the test period and T is the clock period.

10. A timing generation method based on FPGA, characterized in that: Applicable to a timing generator as claimed in any one of claims 1 to 7; the method comprising: Obtain a first integer value and a first decimal value of each preset test cycle data calculated based on the operating frequency of the FPGA; Obtain a second integer part value and a second decimal part value of each preset time series data calculated based on the operating frequency; Each time a test cycle is entered, counting is started according to the working frequency, and the difference between the first decimal part value of the current test cycle data and the previous test cycle data is output; Determine whether the timing clock is enabled according to the count of the test cycle data of the same test cycle and the second integer part value, and output a third fractional part value that is less than an integer multiple of the timing clock according to the difference and the second fractional part value; When the timing clock is enabled, generating parallel data of a preset bit width from the received one-bit pattern data according to the value of the third decimal part; The parallel data is converted into serial data using a preset multiplied clock of the operating frequency and then output.

11. A terminal device, characterized in that: The terminal device includes an FPGA, and the terminal device is used to implement the FPGA-based timing generation method described in claim 10.

12. A computer-readable storage medium, characterized in that: A computer program is stored therein, and when the computer program is executed, the timing generation method based on FPGA according to claim 10 is implemented.

Images