Memory device, system, and method of operation thereof

Abstract

A memory device, system and method of operation are disclosed, wherein the memory device comprises: a memory array comprising a plurality of memory cells; a peripheral circuit coupled with the memory array, comprising: a plurality of page buffers; each page buffer comprising: at least two groups of latch circuits; each group of latch circuits comprising: a first sub-latch circuit and a second sub-latch circuit; the first sub-latch circuit coupled with a sense node, configured to latch a first information on the sense node; the second sub-latch circuit coupled with the sense node, configured to latch a second information on the sense node through the first sub-latch circuit; wherein the first information of the first sub-latch circuit and the second information of the second sub-latch circuit are exchanged through the sense node.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a memory device, system, and method of operating the device. Background Technology

[0002] As the storage density of 3D NAND flash memory devices increases, a large number of page buffers are used in these devices. These page buffers occupy a significant area in the peripheral circuitry of the memory device. Summary of the Invention

[0003] In view of the above, embodiments of this application provide a memory device, system, and operating method.

[0004] In a first aspect, embodiments of this application provide a memory device, including:

[0005] A memory array, comprising multiple memory cells;

[0006] The peripheral circuitry, coupled to the memory array, includes: multiple page buffers; each page buffer includes: at least two sets of latch circuits; each set of latch circuits includes: a first sub-latch circuit and a second sub-latch circuit, wherein;

[0007] The first sub-latch circuit is coupled to the sensing node and is configured to latch the first information on the sensing node;

[0008] The second sub-latch circuit is coupled to the sensing node and is configured to latch the second information on the sensing node through the first sub-latch circuit;

[0009] The first information of the first sub-latch circuit and the second information of the second sub-latch circuit are exchanged through the sensing node.

[0010] In the above scheme, each group of latching circuits further includes: a transmission control switch, which connects the first sub-latching circuit and the second sub-latching circuit, and is configured to: be in an on state in response to a transmission control signal, and transmit the first information stored in the first sub-latching circuit to the second sub-latching circuit.

[0011] In the above scheme, the second sub-latch circuit includes: a parasitic capacitor for storing the second information; the parasitic capacitor is connected to the end of the transmission control switch away from the first sub-latch circuit.

[0012] In the above scheme, the at least two sets of latch circuits are configured to store data to be written or to read data.

[0013] In the above scheme, one of the at least two sets of latching circuits is configured to store intermediate data during the programming process or verification data during the verification process.

[0014] The other latch circuits in the at least two latch circuits are configured to store data to be written or to read data.

[0015] In the above scheme, the first sub-latch circuit includes: a set switch and a storage element, wherein,

[0016] The set switch is coupled to the sensing node and connected to the storage element, and is configured to latch first information on the sensing node to the storage element in response to a set signal.

[0017] In the above scheme, the first sub-latch circuit further includes a reset switch, connected to the storage element, configured to reset the storage element in response to a reset signal.

[0018] In the above scheme, the first sub-latch circuit further includes: a sensing control switch, one end of which is connected to the set switch and the reset switch, and the other end is grounded; the sensing control switch is configured to: be turned on under the action of the level of the sensing node, and write the first information of the sensing node into the storage element through the set switch.

[0019] In the above scheme, the first sub-latch circuit further includes: a reset control switch, one end of which is connected to the set switch and the reset switch, and the other end is grounded; the reset control switch is further configured to: in response to a reset control signal, reset the first sub-latch circuit through the reset switch;

[0020] The reset control signal is generated by the control logic contained in the peripheral circuit.

[0021] In the above scheme, the storage element includes: a first inverter and a second inverter; wherein, the input terminal of the first inverter is connected to the output terminal of the second inverter to form a first node; the output terminal of the first inverter is connected to the input terminal of the second inverter to form a second node; the second node is connected to the second sub-latch circuit and is configured to store the first information.

[0022] In the above scheme, the set switch includes a first transistor with one end connected to the first node; the reset switch includes a second transistor with one end connected to the second node;

[0023] The other end of the first transistor is connected to the other end of the second transistor.

[0024] In the above scheme, each group of latching circuits further includes: a first control switch and a second control switch connected in series between the sensing node and ground, wherein the first control switch is controlled by the second information latched by the second sub-latch circuit; the second control switch is controlled by a read control signal, wherein...

[0025] When the second information controls the first control switch to turn on and the read control signal controls the second control switch to turn on, the second information is read into the sensing node.

[0026] In the above scheme, the transmission control switch includes: a transmission gate with a single MOS transistor structure or a transmission gate with a dual MOS transistor structure; the dual MOS transistor structure includes a CMOS transmission gate formed by a PMOS transistor and an NMOS transistor connected in parallel.

[0027] In the above scheme, the page buffer further includes: a main latch circuit coupled to the sensing node, configured to: store intermediate data during the programming process or verification data during the verification process;

[0028] The main latch circuit has the same structure as the first sub-latch circuit; or, the main latch circuit and the first sub-latch circuit share the sensing control switch and the reset control switch, and the rest of the structures are the same.

[0029] In the above scheme, the at least two sets of latching circuits include: two sets of latching circuits configured to store LP data, MP data, UP data and XP data to be written or read.

[0030] In the above scheme, the at least two sets of latch circuits include: three sets of latch circuits, wherein,

[0031] The two sets of latch circuits are configured to store LP data, MP data, UP data, and XP data to be written or read;

[0032] The remaining set of latch circuits is configured to store intermediate data during the programming process or verification data during the verification process.

[0033] Secondly, embodiments of this application also provide an operation method for a memory device, the memory device including a page buffer; the page buffer including at least two sets of latch circuits; each set of latch circuits including a first sub-latch circuit and a second sub-latch circuit that are mutually dependent and coupled to a sensing node; the operation method including:

[0034] When selecting the pending data state for programming or verification operations of the memory device, the second information latched in the second sub-latch circuit is read into the sensing node;

[0035] The second information of the sensing node is stored in the sensing latch circuit of the page buffer;

[0036] Exchange the second information of the second sub-latch circuit with the first information latched by the first sub-latch circuit;

[0037] The first information is read from the second sub-latch circuit to the sensing node, and the second information is read from the sensing latch circuit to the sensing node to obtain selection information for indicating the state of the data to be operated.

[0038] In the above scheme, the sensing latch circuit includes a first sensing latch circuit and a second sensing latch circuit; the data state to be operated includes a data state to be programmed or a data state to be verified; the step of storing the second information of the sensing node in the sensing latch circuit included in the page buffer includes:

[0039] When selecting the programmable data state corresponding to the programming operation of the memory device, the second information of the sensing node is stored in the second sensing latch circuit; wherein, the first verification information stored in the second sensing latch circuit is invalid;

[0040] When selecting the data state to be verified corresponding to the verification operation of the memory device, the second information of the sensing node is stored in the first sensing latch circuit, wherein the second verification information stored in the first sensing latch circuit is invalid;

[0041] The first verification information and the second verification information were generated during the previous verification operation performed on the memory device.

[0042] In the above scheme, exchanging the second information of the second sub-latch circuit and the first information latched by the first sub-latch circuit includes:

[0043] The sensing node is charged so that its voltage level reaches a preset threshold, so that the second information can be read onto the sensing node.

[0044] In response to the transmission control signal, the transmission path between the first sub-latch circuit and the second sub-latch is closed, and the first information is transmitted to the second sub-latch circuit;

[0045] Perform a clear operation on the first sub-latch circuit to restore it to its initial state;

[0046] The second information is written into the first sub-latch circuit.

[0047] In the above scheme, the operation method further includes:

[0048] When writing second information to the second sub-latch circuit during programming or verification operations of the memory device, the second information is written to the first sub-latch circuit; the first sub-latch circuit and the second sub-latch circuit are swapped so that the second information is stored in the second sub-latch circuit.

[0049] Thirdly, embodiments of this application also provide a memory system, including: one or more of the aforementioned memory devices and a memory controller coupled to the memory devices and used to control the memory.

[0050] This application provides a memory device, system, and operating method. The memory device includes: a memory array comprising multiple memory cells; peripheral circuitry coupled to the memory array, including: multiple page buffers; each page buffer including: at least two sets of latching circuits; each set of latching circuits including: a first sub-latch circuit and a second sub-latch circuit, wherein: the first sub-latch circuit is coupled to a sensing node and configured to: latch first information on the sensing node; the second sub-latch circuit is coupled to the sensing node and configured to: latch second information on the sensing node through the first sub-latch circuit; wherein the first information of the first sub-latch circuit and the second information of the second sub-latch circuit are exchanged through the sensing node. The page buffer included in the memory device provided in this application, by using at least two sets of interdependent sub-latch circuits, reduces the number of components constituting the page buffer to a certain extent, saving the area occupied by the page buffer on the memory chip (such as a NAND chip). Attached Figure Description

[0051] In accompanying drawings that are not necessarily drawn to scale, the same reference numerals can describe similar components in different views. The same numbers with different letter suffixes can represent different instances of similar components. The accompanying drawings generally illustrate the various embodiments discussed in this document by way of example, not limitation.

[0052] Figure 1 This is an exemplary system block diagram of an electronic device having a memory system according to embodiments of this application;

[0053] Figure 2 This is a schematic diagram of an exemplary memory card with a memory device provided according to an embodiment of this application;

[0054] Figure 3 This is a schematic diagram of an exemplary SSD with a memory device provided according to an embodiment of this application;

[0055] Figure 4This is a schematic diagram of an exemplary memory device including peripheral circuitry provided according to embodiments of this application;

[0056] Figure 5 This is a block diagram of an exemplary memory device including a memory array and peripheral circuitry according to embodiments of this application;

[0057] Figure 6 This is a schematic diagram illustrating the relationship between the page buffer group and the memory array included in the memory device provided according to an embodiment of this application;

[0058] Figure 7 This is a schematic diagram of the structure of a memory device according to an embodiment of this application;

[0059] Figure 8 This is a schematic diagram of the structure of a first sub-latch circuit according to an embodiment of this application;

[0060] Figure 9 This is a schematic diagram illustrating a connection relationship where the second sub-latch circuit is coupled to SO according to an embodiment of this application;

[0061] Figure 10 This is a schematic diagram of a page buffer comprising two sets of latching circuits according to an embodiment of this application;

[0062] Figure 11 This is a schematic diagram of a page buffer comprising three sets of latching circuits according to an embodiment of this application;

[0063] Figure 12 This is a flowchart illustrating an operation method of a memory device according to an embodiment of this application;

[0064] Figure 13 This is a flowchart illustrating the programming process provided according to an embodiment of this application;

[0065] Figure 14 This is a flowchart illustrating the verification process provided according to an embodiment of this application. Detailed Implementation

[0066] The various embodiments of this application are described in more detail below with reference to the accompanying drawings. Other embodiments, which can be variations of any disclosed embodiment, can be formed by different configurations or arrangements of the elements and features in the embodiments of this application. Therefore, the embodiments of this application are not limited to the embodiments set forth herein. Rather, the described embodiments are provided so that the embodiments of this application are thorough and complete, and fully convey the scope of the embodiments of this application to those skilled in the art to which the embodiments of this application pertain. It should be noted that references to "embodiment," "another embodiment," etc., do not necessarily indicate only one embodiment, and different references to any such phrases do not necessarily refer to the same embodiment. It should be understood that although the terms "first," "second," "third," etc., may be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element having the same or similar name. Therefore, without departing from the spirit and scope of the embodiments of this application, a first element in one embodiment may also be referred to as a second or third element in another embodiment.

[0067] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale may be enlarged to clearly show the features of the embodiments. When an element is referred to as a connection or coupling to another element, it should be understood that the former may be directly connected to or coupled to the latter, or may be electrically connected to or coupled to the latter via one or more intermediate elements between the two. Furthermore, it should be understood that when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or there may be one or more intermediate elements.

[0068] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application. Singular forms as used herein are intended to include plural forms unless the context clearly indicates otherwise. Unless otherwise stated or clearly understood from the context, the articles “a” and / or “an” used in the embodiments of this application and the appended claims should be interpreted as meaning “one or more”. It should be further understood that the terms “comprising,” “including,” “containing,” and “comprising” as used in the embodiments of this application specify the presence of the stated element and do not exclude the presence or addition of one or more other elements. The term “and / or” as used in the embodiments of this application includes any and all combinations of one or more of the associated listed items. Unless otherwise defined, all terms used in the embodiments of this application, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains in light of the embodiments of this application. It should be further understood that unless explicitly defined in the embodiments of this application, terms such as “belong to” as defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the embodiments of this application and related technologies, and should not be interpreted in an idealized or overly formal manner.

[0069] In the following description, numerous specific details are set forth to provide a thorough understanding of this application, which can be practiced without some or all of these specific details. In other instances, well-known processing structures and / or processes have not been described in detail to avoid unnecessarily obscuring this application. It should also be understood that, in some cases, unless otherwise specifically apparent to those skilled in the art, a feature or element described with respect to one embodiment may be used alone or in combination with other features or elements of another embodiment. Various embodiments of this application are described in detail below with reference to the accompanying drawings. The following description focuses on details to facilitate understanding of embodiments of this application. Well-known technical details may have been omitted to avoid obscuring the features and aspects of the embodiments of this application.

[0070] The embodiments of this application will be further described in detail below with reference to the accompanying drawings and specific examples.

[0071] Figure 1 A block diagram of an exemplary system with memory according to some aspects of this application is shown. Figure 1 In this context, system 100 can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. For example... Figure 1As shown, system 100 may include a host 108 and a memory system 102, wherein the memory system 102 has one or more memory devices 104 and a memory controller 106; the host 108 may be a processor of an electronic device, such as a central processing unit (CPU) or a system-on-a-chip (SoC), wherein the SoC may be, for example, an application processor (AP). The host 108 may be configured to send data to or receive data from the memory device 104. Specifically, the memory device 104 may be any memory disclosed in this application, such as phase-change random access memory (PCRAM), three-dimensional NAND flash memory, etc.

[0072] According to some embodiments, a memory controller 106 is coupled to a memory device 104 and a host 108. It is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as on a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices with low duty cycle environments such as personal calculators, digital cameras, and mobile phones. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment, such as on a Solid State Drive (SSD) or an embedded Multimedia Card (eMMC), where the SSD or eMMC is used as data storage for mobile devices with high duty cycle environments such as smartphones, tablets, and laptops, as well as enterprise storage arrays. The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECCs) relating to data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with external devices (e.g., host 108) according to specific communication protocols.For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0073] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2 In one example shown, the memory controller 106 and a single memory device 104 can be integrated into the memory card 202. The memory card can include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card can also include a connector for the memory card to a host computer (e.g., Figure 1 The memory card connector 204 is coupled to the host 108. In such a way... Figure 3 In another example shown, the memory controller 106 and multiple memory devices 104 can be integrated into the SSD 302. The SSD may also include a connection between the SSD and a host (e.g., Figure 1 The SSD connector 304 is coupled to the host device 108. In some embodiments, the storage capacity and / or operating speed of the SSD is greater than that of the memory card. Furthermore, the memory controller 106 may also be configured to control erase, read, and write operations of the memory device 104.

[0074] Figure 4 A schematic diagram of an exemplary memory including peripheral circuitry is shown. Figure 4As shown, the memory device 104 may include a memory array 401 and peripheral circuitry 402 coupled to the memory array 401. The memory array 401 may be a NAND flash memory array, wherein memory cells 406 are provided in the form of an array of NAND memory strings 408, each NAND memory string 408 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 408 includes a plurality of memory cells 406 coupled in series and stacked vertically. Each memory cell 406 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the storage region of the memory cell 406. Each memory cell 406 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0075] In some embodiments, each memory cell 406 is a single-level cell (SLC) with two possible data states and thus capable of storing one bit of data. For example, a first data state "0" may correspond to a first voltage range, and a second data state "1" may correspond to a second voltage range. In some embodiments, the first and second voltage ranges may be referred to as the threshold voltage distribution of the memory cell. In some embodiments, each memory cell 406 may be a multi-level cell (MLC). For example, an MLC may store two bits per cell, three bits per cell (also known as a trinary level cell (TLC), or four bits per cell (also known as a quadruple level cell (QLC)). Regardless of the type of memory cell, the data states include an erase state and one or more programming states. When a programming operation is performed on a memory cell, the memory cell in the erase state is programmed to a programming state. Generally, the voltage value in the voltage range corresponding to the programming state of the memory cell is relatively large.

[0076] like Figure 4As shown, each NAND memory string 408 may include a source select gate (SSG) 410 at its source end and a drain select gate (DSG) 412 at its drain end. SSG 410 and DSG 412 can be configured to activate the selected NAND memory string 408 (column of the array) during read and program (or write) operations. In some embodiments, the sources of NAND memory strings 408 in the same memory block 404 are coupled via the same source line (SL) 414 (e.g., common SL). In other words, according to some embodiments, all NAND memory strings 408 in the same memory block 404 have an array common source (ACS). According to some embodiments, the DSG 412 of each NAND memory string 408 is coupled to a corresponding bit line 416, from which data can be read and written via an output bus (not shown). In some embodiments, each NAND memory string 408 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having DSG412) or a deselection voltage (e.g., 0 volts (V)) to the corresponding DSG412 via one or more DSG lines 413 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having SSG410) or a deselection voltage (e.g., 0V) to the corresponding SSG410 via one or more SSG lines 415.

[0077] like Figure 4 As shown, NAND memory strings 408 can be organized into multiple memory blocks 404, each of which can have a common source line 414 (e.g., coupled to ground). In some embodiments, each memory block 404 is a basic data unit with an erase operation, i.e., all memory cells 406 on the same memory block 404 are erased simultaneously. To erase memory cells 406 in a selected memory block 404, a bias voltage (Vers) (e.g., a high positive voltage of 20V or higher) can be used to couple the source line 414 of the selected memory block 404 and the unselected memory blocks 404 on the same plane as the selected memory block 404. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at any suitable number of blocks or any suitable fraction of blocks. Memory cells 406 of adjacent NAND memory strings 408 can be coupled via word lines 418, which select which row of memory cells 406 receives read and program operations.

[0078] Return to reference Figure 4The peripheral circuitry 402 can be coupled to the memory array 401 via bit line 416, word line 418, source line 414, SSG line 415, and DSG line 413. The peripheral circuitry 402 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory array 401 by applying voltage and / or current signals to each target memory cell 406 via bit line 416, word line 418, source line 414, SSG line 415, and DSG line 413, and by sensing voltage and / or current signals from each target memory cell 406. The peripheral circuitry 402 can include various types of circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuitry is shown. Peripheral circuitry 402 includes a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic unit 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 5 Additional circuitry not shown.

[0079] Page buffer / sensor amplifier 504 can be configured to read data from memory array 401 and program (write) data to memory array 401 according to control signals from control logic unit 512. In one example, page buffer / sensor amplifier 504 can store a page of programming data (write data) to be programmed into a page 420 of memory array 401. In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 406 coupled to selected word line 418. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 416 representing a data bit stored in memory cell 406 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 506 can be configured to be controlled by control logic unit 512 and select one or more NAND memory strings 408 by applying a bit line voltage generated from voltage generator 510.

[0080] The row decoder / word line driver 508 can be configured to be controlled by the control logic unit 512 and to select / deselect memory blocks 404 of the memory array 401 and to select / deselect word lines 418 of memory blocks 404. The row decoder / word line driver 508 can also be configured to drive word lines 418 using word line voltages generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive SSG lines 415 and DSG lines 413. As described in detail below, the row decoder / word line driver 508 is configured to perform an erase operation on memory cells 406 coupled to one or more selected word lines 418. The voltage generator 510 can be configured to be controlled by the control logic unit 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 401.

[0081] Control logic unit 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic unit 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic unit 512 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic unit 512, as well as to buffer status information received from control logic unit 512 and relay it to the host. Interface 516 can also be coupled to column decoder / bitline driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 401.

[0082] For the memory device or memory system described above, its included page buffer, such as Figure 6 The diagram shows a schematic representation of the structure of a page buffer group included in a memory device. Figure 6The page buffer group also includes the page buffer / sensor amplifier 504 as described above. In the memory device, each bit line 416 is coupled to a page buffer; that is, in some embodiments, the memory device may include a page buffer group 600, which may include page buffer 1 (PB1) to page buffer k (PBK). Each page buffer 601 is coupled to the memory array 401 via a bit line; for example, page buffers PB1 to PBK may be coupled to the memory array 401 via corresponding bit lines BL1 to BLk, respectively. The page buffers mentioned in this application refer to any one of the aforementioned page buffer groups 60. As the storage density of memory devices increases, the number of page buffers used also increases significantly, thus occupying a large area and resulting in higher manufacturing costs for the memory device.

[0083] To address one or more of the aforementioned technical problems, embodiments of this application provide a memory device, such as... Figure 7 As shown, the memory device 70 includes:

[0084] Memory array 71 includes multiple memory cells;

[0085] Peripheral circuitry 72, coupled to the memory array, includes: a plurality of page buffers 721; each page buffer includes: at least two sets of latch circuits 7211; each set of latch circuits includes: a first sub-latch circuit 72111 and a second sub-latch circuit 72112, wherein;

[0086] The first sub-latch circuit is coupled to the sensing node and is configured to latch the first information on the sensing node 7212;

[0087] The second sub-latch circuit is coupled to the sensing node and is configured to latch the second information on the sensing node through the first sub-latch circuit;

[0088] The first information of the first sub-latch circuit and the second information of the second sub-latch circuit are exchanged through the sensing node.

[0089] The structure of the memory array 71 described here can be found in references such as those mentioned above. Figure 4 The structure is shown in the diagram. Most of the structure of the described peripheral circuit 72 can be found in previous examples. Figure 5The structure is shown in the diagram. In this application, each page buffer in the peripheral circuitry includes at least two sets of latch circuits 7211. Each set of latch circuits includes a first sub-latch circuit 72111 and a second sub-latch circuit 72112. The first sub-latch circuit 72111 is coupled to a sensing node and configured to latch the first information of the sensing node (SO). The second sub-latch circuit is also coupled to the sensing node and configured to latch the second information on the sensing node through the first sub-latch circuit. The first information in the first sub-latch circuit and the second information in the second sub-latch circuit are exchanged through the sensing node. The foregoing description indicates a certain dependency between the first and second sub-latch circuits. This means that when the first and / or second sub-latch circuits are needed in the programming or verification operations of the memory device, they must cooperate to complete the corresponding operations. The dependency between them will be explained in detail later.

[0090] Here, SO refers to a node in the page buffer coupled to a corresponding bit line (the bit line connected to the page buffer). This SO is a crucial node in the programming or verification process of the memory device, assisting in various operations. For example, in some embodiments, the SO can be pre-charged to a higher potential, and then undergo at least one discharge operation. This allows the sensing circuit in the page buffer to sense the voltage at the SO corresponding to different discharge stages of the memory cell, and to determine whether the verification of the memory cell is complete based on this sensing result. In other embodiments, the SO can also read second information from a second sub-latch circuit to exchange the first information in the first sub-latch circuit with the second information in the second sub-latch circuit. These two scenarios will be illustrated in detail later.

[0091] Here, each set of latching circuits may further include: a transmission control switch 72113, which connects the first sub-latching circuit and the second sub-latching circuit, and is configured to: be in an on state in response to a transmission control signal, and transmit the first information stored in the first sub-latching circuit to the second sub-latching circuit.

[0092] In other words, the first sub-latch circuit and the second sub-latch circuit are connected by a transmission control switch, and the transmission control switch is in the conducting state under the control of the transmission control signal. At this time, the first information in the first sub-latch circuit can be stored in the second sub-latch circuit.

[0093] For the transmission control switch, the transmission control switch may include: a transmission gate with a single MOS transistor structure or a transmission gate with a dual MOS transistor structure; the dual MOS transistor structure includes a CMOS transmission gate formed by a PMOS transistor and an NMOS transistor connected in parallel.

[0094] It should be noted that the transmission control switch can be implemented by various controllable switching elements, such as the transmission gate with a single MOS transistor structure or a transmission gate with a dual MOS transistor structure provided in the embodiments of this application.

[0095] Here, the second sub-latch circuit may include: a parasitic capacitor for storing the second information; the parasitic capacitor is connected to the end of the transmission control switch away from the first sub-latch circuit.

[0096] In other words, the second sub-latch circuit stores the second information through its parasitic capacitance.

[0097] The memory device provided in this application embodiment includes a page buffer comprising at least two sets of latch circuits, and each set of latch circuits includes a first sub-latch circuit and a second sub-latch circuit that are interdependent. The interdependence between the two is manifested in the following ways: On the one hand, when the second sub-latch circuit latches second information, it requires the assistance of the first sub-latch circuit. For example, when the second sub-latch circuit latches second information, the second information can first be latched onto the first sub-latch circuit, and then a transmission control switch can be opened to transmit the second information to the parasitic capacitance of the second sub-latch circuit, thereby achieving the latching of the second information onto the second sub-latch circuit. On the other hand, the first information latched by the first sub-latch circuit and the second information latched by the second sub-latch circuit can be exchanged with the assistance of the transmission control switch and a sensing node. For example, when it is necessary to exchange the first and second information, the second information can be read onto SO first. Then, the transmission control switch is turned on (i.e., the transmission control signal is connected, putting it in the conducting state), and the first information is transmitted to the second sub-latch circuit and latched to its parasitic capacitance. Then, the first information in the first sub-latch circuit is cleared (the first sub-latch circuit is reset). Then, the transmission control switch is turned off (the transmission control signal is removed, putting it in the off state), and the second information on SO is latched to the first sub-latch circuit, thus completing the exchange of the first and second information. With this design, the number of components used in the second sub-latch circuit is reduced, thereby reducing the area of ​​the chip on which the memory device is located, and thus saving the cost of manufacturing the memory device.

[0098] In practical applications, page buffers contain two types of latching circuits. One type is used to temporarily store data to be programmed into the memory array or data read from the memory array; this type of latching circuit can be called a data latching circuit. The other type is used to temporarily store intermediate data during the programming operation (or programming process) of the memory cell or verification data during the verification operation (or verification process) after the programming operation; this type of latching circuit can be called a sensing circuit, where the sensing circuit includes at least the main latching circuit. A detailed explanation of intermediate data and verification data will be provided when describing the programming and verification processes.

[0099] Based on this, in some embodiments, the at least two sets of latch circuits are configured to store data to be written or to read data.

[0100] In other words, the at least two sets of latching circuits provided in this application embodiment are all used to temporarily store part or all of the data to be written and the data to be read.

[0101] In some embodiments, one of the at least two sets of latching circuits is configured to: store intermediate data during the programming process or verification data during the verification process;

[0102] The other latch circuits in the at least two latch circuits are configured to store data to be written or to read data.

[0103] In other words, the at least two sets of latching circuits provided in this application embodiment are used to temporarily store intermediate data in the programming process or verification data in the verification process; the other remaining sets of latching circuits are used to store part or all of the data to be written or read.

[0104] In some embodiments, the at least two sets of latching circuits include: two sets of latching circuits; wherein...

[0105] The two sets of latch circuits are configured to store LP data, MP data, UP data, and XP data to be written or read.

[0106] It should be noted that when the storage unit is configured as QLC type, the storage unit can store 4 bits of data, namely: low page (LP) data, middle page (MP) data, up page (UP) data, and extra page (XP) data. In this configuration, the storage unit corresponds to 16 data states (i.e., 16 threshold voltage distributions, with each storage unit's threshold voltage belonging to one of these 16 distributions); it requires four latch circuits to store the LP, MP, UP, and XP data. These four latch circuits can utilize the two sets of latch circuits provided in this application (including two first sub-latch circuits and two second sub-latch circuits, for a total of four latch circuits) to store the LP, MP, UP, and XP data respectively.

[0107] In other words, if the at least two sets of latch circuits include two sets of latch circuits, then both sets of latch circuits are used as data latch circuits. When the memory cell is configured as an OLC type, it contains 16 data states, corresponding to 4 pages of data (LP data, MP data, UP data, and XP data). Then, each of the two sets of latch circuits is used to store the corresponding LP data, MP data, UP data, and XP data.

[0108] In some embodiments, the at least two sets of latch circuits include: three sets of latch circuits; wherein,

[0109] The two sets of latch circuits are configured to store the LP data, MP data, UP data, and XP data corresponding to the data to be written or read;

[0110] The remaining set of latch circuits is configured to store intermediate data during the programming process or verification data during the verification process.

[0111] It should be noted that the page buffer provided in this application may include three sets of latch circuits, and the structure of each set of latch circuits is as described above. Figure 7 The described structure. When the storage unit is also configured as QLC type, two of the three latch circuits can be used to store the LP data, MP data, UP data, and XP data corresponding to the data to be written or read; the remaining latch circuit can be used to store intermediate data during the programming process or verification data during the verification process.

[0112] Here, the intermediate data in the programming process may include, but is not limited to, data temporarily stored on a latch circuit not used in the operation before the operation is performed, because certain operations may damage the data (or information) on the sensing node. The verification data in the verification process may include, but is not limited to, verification results such as 4BL sensing information, 3BL sensing information, and pass sensing information in programming verification operations using a 4BL (bit line) scheme.

[0113] It should be noted that when the at least two sets of latch circuits include two sets of latch circuits, the following design is also feasible: for example, one set is used to store the data to be written or a portion of the data to be read; the other set of latch circuits is used for intermediate data during the programming process or verification data during the verification process. In this design, the page buffer also includes other independent latch circuits used to store another portion of the data to be written or read. The specific situation can be determined according to the specific circuit. Here, the memory cell can also be configured as a double-level cell (DLC), TLC, or SLC, etc. Different types of memory cells require different numbers of data latch circuits, but the working principle of each set of latch circuits provided in the embodiments of this application is the same. Therefore, in the following description, unless otherwise specified, the page buffer provided in the embodiments of this application is described as working in the memory device with the memory cell configured as a QLC type.

[0114] In some embodiments, such as Figure 8 As shown, the first sub-latch circuit may include: a set switch 801 and a storage element 802, wherein,

[0115] The set switch is coupled to the sensing node and connected to the storage element, and is configured to latch first information on the sensing node to the storage element in response to a set signal.

[0116] In some embodiments, the first sub-latch circuit may further include: a reset switch 803, connected to the storage element, configured to: reset the storage element in response to a reset signal.

[0117] It should be noted that this first sub-latch circuit can also be called a static latch, which may include a set switch and a storage element. The set switch may be a control switch for writing data to the storage element, configured to latch the first information on the sensing node to the storage element in response to a set signal, that is, to write (or store) the first information on the sensing node to the storage element. The first sub-latch circuit may also include a reset switch coupled to the storage element, which may be a control switch for resetting the storage element included in the first sub-latch circuit, configured to reset the storage element in response to a reset signal.

[0118] Among them, such as Figure 8 As shown, the storage element 802 may include: a first inverter 8021 and a second inverter 8022; wherein, the input terminal of the first inverter is connected to the output terminal of the second inverter to form a first node 8023; the output terminal of the first inverter is connected to the input terminal of the second inverter to form a second node 8024; the second node is connected to the second sub-latch circuit and is configured to store the first information.

[0119] The set switch 801 includes a first transistor with one end connected to the first node; the reset switch 803 includes a second transistor with one end connected to the second node.

[0120] The other end of the first transistor is connected to the other end of the second transistor.

[0121] Here, both the first transistor and the second transistor can be NMOS transistors. When the set signal (set) is applied to the control terminal of the first transistor, it transmits the first information on SO to the second node 8024. When the reset signal (rst) is applied to the control terminal of the second transistor, it resets the second node 8024 contained in the storage element.

[0122] In some embodiments, such as Figure 8 As shown, the first sub-latch circuit may further include: a sensing control switch 804, one end of which is connected to the set switch and the reset switch, and the other end is grounded; the sensing control switch is configured to: be turned on under the action of the level of the sensing node, and write the first information of the sensing node into the storage element through the set switch.

[0123] The type of the reset control switch can be the same as the type of the set switch and the reset switch. That is, the reset control switch can also include an NMOS transistor, which can be called a sensing transistor.

[0124] In some embodiments, the first sub-latch circuit may further include: a reset control switch 805, one end of which is connected to the set switch and the reset switch, and the other end is grounded; the reset control switch is further configured to: in response to a reset control signal, reset the first sub-latch circuit through the reset switch;

[0125] The reset control signal is generated by the control logic contained in the peripheral circuit.

[0126] The type of the reset control switch can be the same as the type of the set switch and the reset switch. That is, the reset control switch can also include an NMOS transistor, which can be called a reset transistor.

[0127] In other words, based on the aforementioned reset switch, set switch, and storage element, the first sub-latch circuit may further include a sensing control switch. This sensing control switch is turned on or off according to the level of SO, and when it is on, the first information on the sensing node is written into the storage element through the set switch. The first sub-latch circuit may also include a reset control switch, which is connected to a reset control signal to reset the first sub-latch circuit. The reset control signal can be generated by the peripheral circuit containing control logic according to actual conditions.

[0128] It should be noted that, according to, Figure 8 The first sub-latch circuit shown has a sensing transistor whose on / off state is affected by the level of the sensing node. In some embodiments, the sensing transistor can be an NMOS transistor with its gate connected to the sensing node, its drain connected to the source terminal of a first transistor and a second transistor connected together, and its source terminal grounded. In this case, when the level of the sensing node is high (e.g., the high voltage is greater than the on-state voltage of the third transistor), the sensing transistor applies ground voltage to the first transistor or the second transistor. Subsequently, the control terminal of the first transistor stores the ground voltage at the first node when a set signal is received; or the control terminal of the second transistor stores the ground voltage at the second node when a reset signal is received. In some embodiments, storing ground voltage at the first node can represent storing data "0".

[0129] Specifically, the first node can store the ground voltage in the following way: when the sensing transistor is turned on, the ground voltage is allowed to be transmitted to the first transistor through the sensing transistor. The first transistor is turned on under the action of the set control signal, transmitting the ground voltage to the first node. The second transistor is turned on under the action of the reset control signal, transmitting the ground voltage to the second node.

[0130] In some embodiments, a high voltage at the first node (e.g., a voltage higher than ground) can represent the stored data "1"; correspondingly, a low voltage at the second node (e.g., ground) can represent the stored data "0". In other embodiments, a high voltage at the second node can represent the stored data "1", while a low voltage at the first node can represent the stored data "0". In practical applications, a low voltage at the first node can represent the stored data "1", and vice versa. The specific representation method depends on the specific encoding method.

[0131] One alternative implementation is that transmitting ground voltage to the first node signifies storing data from the SO to the second node; transmitting ground voltage to the second node signifies resetting the storage element. Specifically, whether to use data "0" or data "1" to represent the data on the SO depends on the specific encoding method.

[0132] The control logic and implementation method of the sensing control switch described above are as follows: Figure 8 As shown, the first sub-latch circuit 702111 may also include a reset control switch. The reset transistor within this switch can reset the first sub-latch circuit during the exchange of first information in the first sub-latch circuit and second information in the second sub-latch circuit, thereby clearing the first information in the first sub-latch circuit. The exchange process between the first information in the first sub-latch circuit and the second information in the second sub-latch circuit can be as follows: First, the second information in the second sub-latch circuit is read onto SO; then, the control switch is turned on, and the first information is transmitted to the second sub-latch circuit; subsequently, the first sub-latch circuit is reset to clear its first information, restoring it to its initial state (e.g., the first or second node of the first sub-latch circuit stores data "1" or data "0" to restore the initial state). Here, the reset transistor serves to reset the first sub-latch circuit, and the reset control signal rst_latch connected to its control terminal can be directly generated by the control logic unit 512 in the aforementioned peripheral circuit; that is, the reset operation can be directly controlled by the control logic unit 512.

[0133] It should be noted that, for example Figure 8In the first sub-latch circuit shown, if the first information is stored in the second node, according to the working principle described above, the reset of the first sub-latch circuit can also be achieved through the reset transistor and the first transistor. That is, when both the reset transistor and the first transistor are in the on state, the ground voltage is latched at the first node. If a high level represents the reset logic, then at this time, the second node is at a high level, which means the reset operation is achieved. In other words, whether the set switch and reset switch in the first sub-latch circuit are used for setting or resetting depends on the specific control logic. As long as it can be implemented and is logically reasonable, it can be used. That is to say, there is no restriction on the specific operation steps of reset and set.

[0134] In some embodiments, such as Figure 9 As shown, each group of latching circuits further includes: a first control switch 901 and a second control switch 902 connected in series between the sensing node and ground, wherein the first control switch 901 is controlled by the second information latched by the second sub-latch circuit; the second control switch 902 is controlled by a read control signal, wherein...

[0135] When the second information controls the first control switch to turn on and the read control signal controls the second control switch to turn on, the second information is read into the sensing node.

[0136] It should be noted that the first and second control switches here can also include NMOS transistors, and the first and second control switches are connected in series between the sensing node and ground, controlled by the second information and the read control signal respectively, and can be used to realize the circuit connection for exchanging the first and second information as described above. Specifically, the process of exchanging the first and second information described above can be as follows: Under the action of the read control signal, the second control switch is in the on state, reading the second information from the second sub-latch circuit to SO; then, under the action of the transmission control signal, the transmission control switch is turned on, transmitting the first information to the second sub-latch circuit; then, the first sub-latch circuit is reset; finally, under the action of the set signal, the first transistor is in the on state, latching the second information into the first sub-latch circuit, thereby realizing the exchange of the first and second information.

[0137] In some embodiments, the page buffer 721 may further include: a main latch circuit coupled to the sensing node, configured to: store intermediate data during the programming process or verification data during the verification process;

[0138] The main latch circuit has the same structure as the first sub-latch circuit; or, the main latch circuit and the first sub-latch circuit share the sensing control switch and the reset control switch, and the rest of the structures are the same.

[0139] In other words, the structure of the main latch circuit is the same as that of the first sub-latch circuit. Specifically, the main latch circuit includes the first inverter, second inverter, first transistor, second transistor, sensing transistor, and reset transistor found in the first sub-latch circuit, and the connection structure between these components is also the same as that of the first sub-latch circuit. In some other implementations, the first inverter, second inverter, first transistor, and second transistor included in the main latch circuit have the same structure as those in the first sub-latch circuit, and the main latch circuit can share the sensing transistor and reset transistor with the first sub-latch circuit.

[0140] It should be noted that the data used in the programming process mentioned here has the same meaning as described above, and will not be repeated here. Similarly, the verification data used in the verification process has the same meaning as described above, and will not be repeated here. The main latch circuit mentioned here and the first sensing latch circuit described later can refer to the same latch circuit, such as DS. Describing it as the main latch circuit in the memory device, while describing the operation method later as the first sensing latch circuit, is to establish a correspondence with the second sensing latch circuit (such as DL) and the third sensing latch circuit (such as DM). It is merely a different naming convention used in different descriptions for ease of description and has no restrictive effect.

[0141] In some embodiments, the page buffer may further include: a data transmission circuit coupled to one of the two sets of latching circuits, configured to: receive data to be written and transmit the data to be written to each of the two sets of latching circuits; or, output read data.

[0142] It should be noted that this data transmission circuit can be used to temporarily store data to be written to the memory device via the data path and the latch circuit of the page buffer for later programming. This data transmission circuit can be coupled to one of the two sets of latch circuits used for data latching. That is, this data transmission circuit can sequentially connect to the LP, MP, UP, and XP pins of the data to be written, and sequentially store the corresponding data into the corresponding latch circuits in the two sets of latch circuits. This data transmission circuit can also output read data to the data path so that the memory device can feed the read data back to the memory controller or host.

[0143] In some embodiments, the page buffer may further include: a pre-charge circuit and a discharge circuit, wherein;

[0144] The pre-charging circuit is configured to pre-charge the sensing node corresponding to the selected storage cell in response to a pre-charging signal.

[0145] The discharge circuit is configured to discharge the sensing node corresponding to the selected storage unit in response to a discharge signal.

[0146] It should be noted that both the pre-charge circuit and the discharge circuit are coupled to their respective bit lines and work together to pre-charge or discharge the sensing node, thereby achieving a data latching operation. For example, during the verification process, the pre-charge circuit first pre-charges the sensing node SO to a preset initial voltage, and then the discharge circuit discharges the sensing node SO at least once to complete at least one verification operation. In this at least one verification operation, the verification result can be latched into the aforementioned main latch circuit or other related latch circuits. The structure of the pre-charge circuit and the discharge circuit can be implemented in various ways. The following description illustrates its working principle using one method.

[0147] To clarify the structure of the page buffer included in the memory device provided in this application embodiment, as follows: Figure 10 and Figure 11 As shown, where, Figure 10 A schematic diagram of a page buffer comprising two sets of latch circuits is provided for embodiments of this application; Figure 11 The page buffer provided in this embodiment includes a schematic diagram of a structure comprising three sets of latching circuits.

[0148] Figure 10The provided page buffer includes two sets of latch circuits for storing data to be written or read: one set of latch circuits includes d2 (first sub-latch circuit) and d1 (second sub-latch circuit); the other set of latch circuits includes dc (first sub-latch circuit) and d3 (second sub-latch circuit). D1 and D2 are connected via a transmission control switch, configured to connect D2 and D1 in response to the transmission control signal pass_2 (transmission control signal), and to complete the exchange of information between D2 and D1 with the assistance of SO. The second information in D1 is stored in its parasitic capacitance. Similarly, dc and D3 are described without further explanation. The page buffer also includes a main latch circuit (or first sensing latch circuit) ds, a latch circuit dl (second sensing latch circuit) for storing 3BL sensing information, and a latch circuit dm (third sensing latch circuit) for storing 4BL sensing information. The page buffer also includes a pre-charge circuit and a discharge circuit. The pre-charge circuit comprises three P-type transistors connected in parallel as follows: two P-type transistors form a transmission gate, which is then connected to another P-type transistor. One end of the pre-charge circuit is connected to a power supply voltage (e.g., VDD), and the other end is connected to SO. It charges the sensing node in response to pre-charge signals (Prech_all and Prech_sel signals). The discharge circuit includes two N-type transistors connected in series between the sensing node and ground (GND), configured to discharge SO in response to the discharge signal sodisch. Figure 10 As shown, the page buffer also includes data transmission circuitry configured to receive data to be written or output read data.

[0149] Figure 11 and Figure 10 The page buffers shown have essentially the same structure, with the difference being that the latch circuit dl for storing 3BL sensing information and the latch circuit dm for storing 4BL sensing information also employ the structure of a first sub-latch circuit and a second sub-latch circuit. In this design, the page buffer also includes a control circuit comprising two N-type transistors (a first control switch and a second control switch) connected in series between the power supply voltage and the sensing node. This control circuit is configured to read information from dm onto the sensing node in response to the control signal en_4bl_b, so that the information latched in dl (such as 3BL sensing information) can be subsequently transferred to dm, and then related information (such as 4BL sensing information) can be latched in dl.

[0150] It should be noted that, Figure 10 and Figure 11These are merely two exemplary structures based on the inventive concept provided in the embodiments of this application. Without departing from the inventive concept of this application, the page buffer may also have other structures, which will not be elaborated upon here.

[0151] based on Figure 10 and Figure 11 The basic working principle of each latch circuit in the page buffer is as follows:

[0152] (1) Switch the information of the first sub-latch circuit and the second latch circuit. Taking d1 and d2 as an example, here, D1 represents the second information stored in d1; D2 represents the first information stored in d2, that is, switch D1 / D2.

[0153] The specific steps may include: applying the prech_all+prech_sel signal to precharge the sensing node, which can be represented as "prech_all+prech_sel(SO=1)"; then, applying the rd_2 signal (read control signal) to read the second information in d1 onto SO, represented as rd_2(SO=~D1); then, applying the pass_2 (transmission control signal) to transmit the first information in d2 to d1, represented as pass_2(D1=D2); then, applying the rst_2_latch (reset control signal)+set_2 (set signal) to reset d2, represented as rst_2_latch+set_2(D2=1); finally, applying the rst_2 (reset signal) to latch the second information into d2, represented as rst_2(D2=~SO=D1).

[0154] (2) Read the data from the latch circuit onto SO (first sub-latch circuit or second sub-latch circuit).

[0155] For the second sub-latch circuit, let's take reading d1 as an example.

[0156] The process is as follows: prech_all + prech_sel (SO = 1); rd_2 (SO = ~D1).

[0157] For the first sub-latch circuit, taking reading d2 as an example, the process can be as follows: First, exchange the information between the first and second sub-latch circuits, and then read the information from the second sub-latch circuit to complete the reading of the information from the first sub-latch circuit onto SO.

[0158] (3) Write the data on SO into the latch circuit (first sub-latch circuit or second sub-latch circuit).

[0159] For writing to the first sub-latch circuit, take d2 as an example.

[0160] The process is as follows: apply set_2 (set signal) to write the data on SO into the first sub-latch circuit, using set_2 (D2 = ~SO).

[0161] For writing to the second sub-latch circuit, taking d1 as an example, the process can be as follows: First, write the data on SO to the first sub-latch circuit, and then exchange the information between the first and second sub-latch circuits to complete writing the data on SO to the second sub-latch circuit.

[0162] (4) Transmit the second information in the second sub-latch circuit to the first sub-latch circuit. Take the transmission of d3 to d2 as an example. The process can be as follows: rst_2_latch+set_2(D2=1); prech_all+prech_sel(SO=1); rd_c(SO=~D3); rst_2(D2=~so=D3).

[0163] It should be noted that the symbol "~" represents the negation logical operation; the symbol "=" represents the assignment operation.

[0164] In practical applications, when page buffers with different structures are used in memory devices, the implementation of each step in the programming and verification processes will differ. Therefore, the memory device described above includes a page buffer; the page buffer includes at least two sets of latching circuits; each set of latching circuits includes a first sub-latch circuit and a second sub-latch circuit that are interdependent and coupled to a sensing node; see also... Figure 12 As shown in the illustration, this application also provides an operation method for a memory device, the process of which may include:

[0165] Step 1201: When selecting the data state to be operated for programming or verification operations of the memory device, read the second information latched in the second sub-latch circuit into the sensing node;

[0166] Step 1202: Store the second information of the sensing node in the sensing latch circuit of the page buffer;

[0167] Step 1203: Exchange the second information of the second sub-latch circuit with the first information latched by the first sub-latch circuit;

[0168] Step 1204: Read the first information from the second sub-latch circuit to the sensing node, and read the second information from the sensing latch circuit to the sensing node to obtain selection information for indicating the state of the data to be operated.

[0169] It should be noted that this operation method may include a method for programming the memory device, which may be a method for programming the aforementioned memory device. Figures 7 to 11A method for programming and verifying a memory device with the structure shown. In this programming and verification method, due to the existence of... Figures 7 to 11 The page buffer shown contains interdependent first and second sub-latches. Therefore, when reading or writing information stored in the first and second sub-latches, some operational steps change. For example, during the selection of a data state in programming or verification, data needs to be read from the first and second sub-latches storing the data to be written onto SO. Since reading from the first sub-latch requires the assistance of the second sub-latch, information exchange between the second and first sub-latches is involved. During this information exchange, the data on SO is corrupted; therefore, the data read from SO needs to be temporarily stored in an unused latch circuit.

[0170] Therefore, in the embodiments of this application, based on such Figure 10 and Figure 11 Under the page buffer shown, the specific operation for selecting the data state can be as follows: First, the second information in the second sub-latch circuit is read from the sensing node. Then, the second information on the sensing node is stored in the sensing latch circuit included in the page buffer. Next, the second information of the second sub-latch circuit and the first information latched by the first sub-latch circuit are exchanged. Finally, the first information is read from the second sub-latch circuit to the sensing node, and the second information is read from the sensing latch circuit to the sensing node to obtain selection information indicating the data state to be operated. Afterwards, the control logic determines the data state to be operated (the data state to be programmed or the data state to be verified) based on the selection information on SO. Here, the sensing latch circuit may include the aforementioned... Figure 10 or Figure 11 The ds or dl in the text.

[0171] Specifically, in some embodiments, the sensing latch circuit includes a first sensing latch circuit and a second sensing latch circuit; the data state to be operated includes a data state to be programmed or a data state to be verified; the step of storing the second information of the sensing node in the sensing latch circuit included in the page buffer includes:

[0172] When selecting the programmable data state corresponding to the programming operation of the memory device, the second information of the sensing node is stored in the second sensing latch circuit; wherein, the first verification information stored in the second sensing latch circuit is invalid;

[0173] When selecting the data state to be verified corresponding to the verification operation of the memory device, the second information of the sensing node is stored in the first sensing latch circuit, wherein the second verification information stored in the first sensing latch circuit is invalid;

[0174] The first verification information and the second verification information were generated during the previous verification operation performed on the memory device.

[0175] Here, the second sensing latch circuit may include the aforementioned dl. The first sensing latch circuit may include the aforementioned ds, or the main latch circuit. The second verification information may refer to 3BL sensing information. The first verification information may refer to pass sensing information.

[0176] In some embodiments, exchanging the second information of the second sub-latch circuit and the first information latched by the first sub-latch circuit includes:

[0177] The sensing node is charged so that its voltage level reaches a preset threshold, so that the second information can be read onto the sensing node.

[0178] In response to the transmission control signal, the transmission path between the first sub-latch circuit and the second sub-latch is closed, and the first information is transmitted to the second sub-latch circuit;

[0179] Perform a clear operation on the first sub-latch circuit to restore it to its initial state;

[0180] The second information is written into the first sub-latch circuit.

[0181] It should be noted that the specific operating steps are described in the first point (1) of the basic working principle of the first sub-latch circuit and the second sub-latch circuit mentioned above.

[0182] In some embodiments, the operating method may further include:

[0183] When writing second information to the second sub-latch circuit during programming or verification operations of the memory device, the second information is written to the first sub-latch circuit; the first sub-latch circuit and the second sub-latch circuit are swapped so that the second information is stored in the second sub-latch circuit.

[0184] It should be noted that the description here refers to the steps of writing the second information into the second sub-latch circuit during programming or verification operations. For specific implementation, please refer to the third point (3) above regarding the basic working principles of the first and second sub-latch circuits.

[0185] To specifically understand the impact of the page buffer provided in the embodiments of this application on programming and verification, the following will use the aforementioned... Figure 11 The programming and verification of the memory device with the page buffer shown are illustrated using this example.

[0186] Specifically, such as Figure 13 The diagram illustrates the programming flow for a memory device. The flow specifically includes:

[0187] Step 1: Cache the data to be written. See the previous step of temporarily storing the data to be written for details.

[0188] Step 2: Preprocess the data to be written. See the preprocessing steps described above for details.

[0189] Step 3: Disable programming settings. That is, apply a bit line voltage to the memory cell in the first selected memory cell that is disabled for programming.

[0190] Step 4: First Forced Programming Settings. This involves using first forced information to adjust the bit line voltages of certain memory cells within the selected first memory cell to prevent over-programming.

[0191] Step 5: Second Forced Programming Settings. This involves using second forced information to adjust the bit line voltages of certain memory cells within the selected second memory cell to prevent over-programming.

[0192] Step 6: Selecting the data state to be programmed. That is, selecting the data state to which the first memory cell to be programmed.

[0193] In step 6, a programming pulse corresponding to the data state to be programmed should be applied to the selected first memory cell to program the memory cell that needs to be programmed.

[0194] Step 7: Fail Bit Count (FBC). This is the count of the number of programming failures after programming the selected first memory cell.

[0195] Step 8: Restore 4BL information.

[0196] Step 9: Programming is disabled by disabling programming operations. That is, the latch circuits in the page buffer corresponding to the selected first memory cell that has been programmed are all restored to their initial state, for example, storing all the numbers "1".

[0197] In step 1, the data to be written can be configured to include multiple pages of data, the type of which depends on the desired storage unit configuration. For example, if the storage unit is configured as QLC, the multiple pages of data can include LP data, MP data, UP data, and XP data. Similarly, if the storage unit is configured as TLC, the multiple pages of data can include LP data, MP data, and UP data. Regardless of the desired storage unit configuration type, the programming method is similar.

[0198] Specifically, for step 1, the multiple latch circuits include a first latch circuit and a second latch circuit; the data to be written is input from a data transmission circuit coupled to a first sub-latch circuit in the second latch circuit; the buffer of the data to be written (step 1) may include:

[0199] Receive the LP data to be written, and store the LP data in the first sub-latch circuit of the second group of latch circuits;

[0200] Disconnect the path between the first sub-latch circuit and the second sub-latch circuit in the second group of latch circuits;

[0201] Receive MP data to be written, and store the MP data in the second sub-latch circuit of the second group of latch circuits;

[0202] Receive UP data to be written, and store the UP data in the second sub-latch circuit of the first group of latch circuits;

[0203] Receive XP data to be written and store the XP data in the first sub-latch circuit of the first group of latch circuits.

[0204] It should be noted that, as Figure 11 and Figure 10 The page buffers d1 and d2 can be an example of a second set of latching circuits; dc and d3 can be an example of a first set of latching circuits. Figure 10 and Figure 11In the page buffer structure shown, temporarily storing data to be written can include: opening pass_2+pass_c, connecting the path between the first sub-latch circuit and the second sub-latch circuit in the first group of latch circuits; connecting the path between the first sub-latch circuit and the second sub-latch circuit in the second group of latch circuits, that is, connecting d1 and d2; and connecting dc and d3; dc receives LP data from the data transmission circuit and stores the LP data in the first sub-latch circuit (d1) in the second group of latch circuits; then, closing pass_2, dc receives MP data from the data transmission circuit and stores the MP data in the second sub-latch circuit (d2) in the second group of latch circuits; then, dc receives UP data from the data transmission circuit and stores the UP data in the second sub-latch circuit (d3) in the first group of latch circuits; and dc receives XP data from the data transmission circuit and stores the XP data in the first sub-latch circuit (dc) in the first group of latch circuits.

[0205] The above process can be simplified as follows: The data to be written includes the input of the four page data as described above. The user-input data to be written is sequentially input into the DC latch through the datapath. The data to be written needs to achieve D1=DC (DC receives data and transmits it to D1), D2=DC, and D3=DC in sequence. The operation of D1=DC can be as follows: pass_2+pass_c is turned on; D1 / D2 and D3 / DC are connected; DC data is transmitted to D2 and D1; pass_2 is turned off. The operation of D2=DC is as follows: pass_c is turned on, D3 / DC is connected; DC data is transmitted to D2. The operation of D3=DC is as follows: pass_c is turned on; pass_c is turned off.

[0206] Here, the reading and writing of the first sub-latch circuit (d2) and the second sub-latch circuit (d1), as well as the information exchange between the two, can be performed according to the steps described above, and will not be repeated here.

[0207] For step 2, preprocessing the data to be written may include: preprocessing the multi-page data so that the data to be written is stored in the corresponding latch circuit according to a preset encoding.

[0208] It should be noted that the purpose of this step is to re-encode the data to be written, which is already stored in the corresponding latch circuit, according to a preset encoding, and store it in the corresponding internal data that is convenient for operation by the memory device, so as to facilitate the operation of the page buffer. The logic to be implemented by the read latch circuit (latch) involved in the preprocessing process is: SO = ~DS&P*, where P* represents the selected data state, which is the same as the selection logic described above, and can be referred to the previous description; DS stores the unprocessed flags in the selected data state. The logic to be implemented by the write latch involved in the preprocessing process is to perform a set / rst operation on the latch circuit of the page buffer corresponding to the selected memory unit, so as to change the corresponding number in the original code to the corresponding number in the internal encoding, for example, changing the "0" corresponding to the original code to the "1" corresponding to the internal encoding.

[0209] For example, a memory device includes, Figure 11 The page buffer is shown. For cases requiring writing to the first sub-latch circuit, the selected information on SO can be directly used to write to the latch. For example, writing 1 to D2: SO = ~DS&P*, set_2 (D2 = 1). For cases requiring writing to the second sub-latch circuit, a switch operation with the first sub-latch circuit is required. Since DS contains preprocessed flag information, but DL is not used at this time, DL is used as a temporary storage for SO before the switch operation. For example, writing 0 to D1: SO is transferred to DL for temporary storage (DL = ~DS&P*); switch D1 / D2; prech_all + prech_sel (SO = 1); rd_l; rst_2 (D1 = 0).

[0210] For step 3, the programmability restriction setting may include sequentially storing the multi-page data into the first sensing latch circuit (i.e., ds) of the page buffer to generate programming suppression information. Specifically, this can be achieved through the following steps: First, the LP data stored in the second sub-latch circuit of the second group of latch circuits is transferred to the main latch circuit; then, the MP data stored in the first sub-latch circuit of the second group of latch circuits is transferred to the second sub-latch circuit of the second group of latch circuits; then, the MP data is read onto the sensing node and stored in the main latch circuit; finally, the UP data and the XP data are sequentially stored in the main latch circuit to generate programming suppression information.

[0211] It should be noted that the above steps achieve the logic DS = D1&D2&D3&DC, thus generating programming inhibition information. This programming inhibition information can be used to select memory cells that are inhibited from programming, and a programming-inhibited bit line voltage is applied to the bit line corresponding to the inhibited memory cell according to the programming inhibition information. That is, the operation as in step 3 is performed. Here, for step 3, the first selected memory cell can be selected by the control logic unit according to a preset programming method. Among the selected first memory cells, those memory cells that have been successfully programmed in the previous programming operation do not need to be programmed this time. Therefore, according to the programming inhibition information, a corresponding bit line voltage is provided to the selected memory cell. This bit line voltage can include the programming-inhibited bit line voltage (e.g., VDD) corresponding to the successfully programmed memory cell among the selected memory cells and the programming-enabled bit line voltage (e.g., ground voltage) corresponding to the unprogrammed memory cell among the selected memory cells.

[0212] Regarding the above process, it is still based on including Figure 11 The page buffer shown is used as an example for illustration. The process specifically includes the following steps:

[0213] 1. Transfer D1 to DS (DS = D1);

[0214] 2. Switch D1 / D2;

[0215] 3.prech_all+prech_sel(so=1);

[0216] 4.rd_2(so=~D2);

[0217] 5.rst_s(DS=D1&D2);

[0218] 6. Repeat steps 3-5 for D3 (DS = D1 & D2 & D3);

[0219] 7. Switch D3 / DC;

[0220] 8. Repeat step 6 (DS = D1 & D2 & D3 & D4).

[0221] After obtaining programming suppression information, a bit line voltage is provided to the selected first memory cell in the memory device according to the programming suppression information.

[0222] For steps 4 and 5, the first forced programming setting and the second forced programming setting may include: adjusting the bit line voltage according to the first bit line forced information stored in the second sensing latch circuit included in the page buffer and the second bit line forced information stored in the third sensing latch circuit.

[0223] It should be noted that the second sensing latch circuit mentioned can be as follows: Figure 10 or Figure 11 The third sensing latch circuit mentioned in the diagram (dl) can be as follows: Figure 10 or Figure 11 The first bit-line forcing information mentioned above can be the 3BL sensing information described earlier, and the second bit-line forcing information can be the 4BL sensing information described earlier. This programming method prevents the selected memory cell from being overprogrammed, thereby reducing the width of the threshold voltage distribution across multiple memory cells and improving the accuracy of the programming operation.

[0224] In practical applications, the selected first memory cell may include multiple memory cells; these memory cells may be coupled to the same word line or several word lines. In other words, the word lines coupled to the selected first memory cell will be simultaneously programmed with programming pulses for this programming operation. Furthermore, if the selected first memory cell is configured to store multiple data states, multiple programming pulses need to be applied to complete the programming of the selected first memory cell, progressively completing the programming of each data state. Therefore, before applying programming pulses to the word lines coupled to the selected first memory cell, the corresponding state to be programmed, i.e., the data state to be programmed, needs to be selected first to apply the corresponding programming pulses.

[0225] For step 6, the selection of the data state to be programmed may include: reading one or more pages of data selected from the multi-page data into the sensing node to generate selection operation information according to preset logic. The specific steps may include: selecting the first page of data to be used from the multi-page data according to the preset logic.

[0226] If the first page data is stored in the first sub-latch circuit, the data on the sensing node is temporarily stored in the first sensing latch circuit or the second sensing latch circuit of the page buffer; the first page data is transferred to the second sub-latch circuit associated with the first sub-latch circuit; the first page data is read into the sensing node; the data in the first sensing latch circuit or the second sensing latch circuit is invalid data;

[0227] If the first page of data is stored in the second sub-latch circuit, the first page of data is directly read into the sensing node;

[0228] The data on the first page includes one of the following: LP data, MP data, UP data, and XP data.

[0229] Here, the pre-defined logic refers to the logical algorithm designed before programming to obtain the data state to be programmed. For example, the selected memory cell type is QLC, which contains 16 data states (P0, P1, P2, ..., P15 in order), and selecting a data state can be achieved by selecting all the "0"s in the encoded data corresponding to the data to be written. Then, for example, the logic for selecting state P1 is SO = ~D1 & ~D2 & ~D3 & ~DC; the logic for selecting P3 is SO = ~D1 & ~D3 & ~DC; the logic for selecting P7 is SO = ~D1 & ~D2; and the logic for selecting P15 is SO = ~D3.

[0230] The second sensing latch circuit mentioned here can be as follows: Figure 11 The page buffer shown includes dl. The first sensing latch circuit mentioned can be as follows: Figure 11 The page buffer shown contains ds. Based on the description of reading SO from the information stored in the first sub-latch circuit described above, it needs to be converted to read information from the second sub-latch circuit. Since this process will corrupt the data already read from SO, before exchanging information in the first and second sub-latch circuits, the data on SO is temporarily stored in a latch circuit to prevent data loss. For example, during the selection operation of the data state to be programmed in the programming process, the first sensing latch circuit stores 4BL sensing information, while the data in dl is useless (i.e., invalid data), and the data on SO can be temporarily stored in dl. As another example, during the programming process, when the selection operation of the data state in the programming operation is disabled, the data in the first sensing latch circuit is useless (invalid data), and SO data can be temporarily stored in DS. Furthermore, during the verification process, the selection of the data state to be verified and the selection of the memory cell that has passed programming can also be achieved by temporarily storing SO data in DS. That is: in response to the latch circuit storing the first page of data being a first sub-latch circuit, the data on the sensing node is temporarily stored in the first sensing latch circuit or the second sensing latch circuit of the page buffer; the first page of data is transferred to the second sub-latch circuit associated with the first sub-latch circuit; and the first page of data is read into the sensing node. When the first page of data is stored in the second sub-latch circuit, the stored information can be directly read into SO.

[0231] It should be noted that the first page of data here may include one or more pages from the multiple pages of data. When the first page of data includes one page, the above procedure can be executed once. However, when the first page of data includes several pages, the above procedure should be executed multiple times to ensure that all pages of data involved are read onto the SO, and calculations are performed on the SO according to certain logic to generate selection operation information or other selection operation information, thereby realizing the selection of the data state to be programmed.

[0232] The implementation process in the specific circuit is as described above. Figure 11 The page buffer shown is used as an example. Taking the selected data state P1 to be programmed during the programming process as an example, the specific operation process can be as follows: rst_sa_latch+set_l(DL=1); prech_all+prech_sel(so=1); rd_2+rd_c(so=~D1&~D3); rst_l(DL=~(~D1&~D3)); switchD1 / D2; switch D3 / DC(D1=D2, D3=DC); rd_l, rd_2, rd_c(so=~D1&~D2&~D3&~DC).

[0233] For example, in the programming process, the selection operation of data state P1 in the programming operation is prohibited. The specific operation process can be as follows: rst_sa_latch+set_s(DS=1); prech_all+prech_sel(so=1); rd_2+rd_c(so=~D1&~D3); rst_s(DS=~(~D1&~D3)); switch D1 / D2, switch D3 / DC(D1=D2, D3=DC); rd_s, rd_2, rd_c(so=~D1&~D2&~D3&~DC).

[0234] For example, the specific operation of selecting the memory unit (in P1 state) during the verification process can be as follows: prech_all+prech_sel(SO=1); rd_s+rd_2+rd_c(so=~DS&~D1&~D3); rst_sa_latch+set_s(DS=1); rst_s(DS=~(~DS&~D1&~D3)); switch D1 / D2, switch D3 / DC(D1=D2, D3=DC); rd_s, rd_2, rd_c(SO=~DS&~D1&~D2&~D3&~DC).

[0235] The operations in steps 7 and 8 that do not involve the latch circuit in the page buffer of this application embodiment will not be described in detail here.

[0236] See Figure 14 It shows a schematic diagram of the specific verification process.

[0237] exist Figure 14 In this context, the verification process may include:

[0238] Step 1: Begin verification by selecting the Pn programming state. Assume that after Pn-1 verification completes, the system enters the verify Pn state, selecting the programming state operation DS = P*, where P* performs the selected Pn programming state operation based on the data in D1 / D2 / D3 / DC.

[0239] Step 2, 3BL Sensing; Here, before 3BL sensing, the SO corresponding to the first and second storage units is precharged and precharged to a preset initial voltage. During 3BL sensing, the first verification information is latched into the first sensing latch circuit dl. The SO is precharged using the data from DS (DS = P*), and then the SO is continuously developed and discharged. After the develop time of t_sodev_3bl, soblk and sodisch are turned off to stop developing, and then rst_l is turned on to store the 3BL sensing information into DL (DL = DL & ~ SO). Here, the symbol & represents logical AND; the symbol ~ represents logical NOT.

[0240] Step 3, Exchange DL / DM. Transmit the 3BL sensing information to the DL / DM.

[0241] Step 4, 4BL sensing; that is: DL = ~SO. Here, based on 3BL sensing, SO is discharged for a period of time (e.g., a second preset duration), and then the second verification information (i.e., 4BL sensing information) is latched into the first sensing latch circuit DL.

[0242] Step 5, Pass Sensing; Here, based on 4BL sensing, SO is discharged for a period of time (e.g., the third preset duration), and then the third verification information (i.e., pass sensing information) is latched into the main latch circuit DS. The specific circuit operation is described as follows: Soblk and Sodisch are turned on, and after the t_sodev_Pass develop time, Soblk and Sodisch are turned off to stop develop; the DS data is cleared to prepare for Pass sensing (DS=1); rst_s is turned on to sense the Pass data into DS (DS=~SO); during the develop process, because Sodisch is turned on, the 4BL' data on SO will be cleared by DS.

[0243] Step 6: Disable programming of the Pass memory cell; here, based on the first verification information, the second verification information, and the third verification information, the bit line voltages of the bit lines coupled to the first memory cell are adjusted accordingly. The memory cells that have passed verification are disabled from programming (the disable programming bit line voltage is applied to the third bit line connected to the third group of memory cells). The Pass data in DS is used to inhibit the data of D1 / D2 / D3 / DC in the Pn state, i.e., written as 1. That is: D* = ～ DS&P*.

[0244] Step 7: Determine if this is the final programming state;

[0245] Step 8: If not, swap DL / DM. This step involves swapping the data in DL / DM. After the swap, DL contains 3BL sensing information, and DM contains 4BL sensing information. Then, proceed to the Pn+1 state for the verify operation, similar to the above.

[0246] Step 9: If yes, end verification. Pn+1 is the last verify programming state, so after it ends, it directly enters verify recovery, ending the verify sequence.

[0247] It should be noted that the verification process also involves the selection of data states, similar to the programming process. Specifically, the process may include: reading one or more pages of data from the multi-page data into a sensing node according to the preset logic, generating selection operation information to indicate the data state to be verified; the second selection operation information is used to select a second storage unit in the data state to be verified; then, based on the three different potentials of the sensing node corresponding to the second storage unit, the first verification information, the second verification information, and the third verification information are stored respectively in the first sensing latch circuit, the second sensing latch circuit, and the third sensing latch circuit included in the memory device; wherein, the first verification information, the second verification information, and the third verification information are used to verify the programming result of the second storage unit.

[0248] It should be noted that the preset logic here has the same meaning as the preset logic in the previous programming, and will not be repeated here. This can be a verification operation after programming the memory cell. The first sensing latch circuit described here can be as follows: Figure 10 or Figure 11 The second sensing latch circuit mentioned in the diagram (ds) can be as follows: Figure 10 or Figure 11 The third sensing latch circuit mentioned in the diagram (dl) can be as follows: Figure 10 or Figure 11The dm shown. The first verification information can be pass sensing information as described above. The second verification information can be 3BL sensing information as described above. The third verification information can refer to the verification result obtained by 4BL sensing in the verification operation of the 4BL BIAS programming method.

[0249] It should be noted that when using Figure 11 When the page buffer shown performs programming or verification, the latch circuit used to store the data to be written consists of two sets of interdependent first and second sub-latch circuits, making... Figure 13 and Figure 14 In the programming and verification processes shown, some operations involving reading from and writing to the latch circuit have been changed. For example, Figure 13 The programming process shown and Figure 14 The operations for reading the latch circuit during the verification process include: buffering the data to be written (step 1 in the programming process), selecting the data state (steps 6 and 9 in the programming process, and step 1 in the verification process), and disabling programming settings (step 3 in the programming process). The operations for writing to the latch circuit include: buffering the data to be written (step 1 in the programming process), data preprocessing (step 2 in the programming process), disabling programming (step 9 in the programming process, and step 6 in the verification process), etc. The operations involved in each step have been explained in detail above and will not be repeated here.

[0250] This application provides embodiments such as Figure 10 and Figure 11 The page buffer shown can reduce its area by setting the latch circuit as several interdependent sets of latch circuits (first sub-latch circuit and second sub-latch circuit), which greatly saves the cost of manufacturing memory devices.

[0251] This application also provides a memory system, including: one or more of the aforementioned memory devices and a memory controller coupled to the memory devices and used to control the memory.

[0252] This application also provides an electronic system, including: the aforementioned memory system and a host coupled to the memory system.

[0253] It should be noted that the memory system and electronic system provided in the embodiments of this application include the aforementioned memory, and the two have the same technical features. The structure of the memory and the terms appearing in the technical solutions related to this application have been described in detail above. Therefore, the terms appearing here can be understood according to the meanings described above, and will not be repeated here.

[0254] The above description is intended to be illustrative and not restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used, such as those applicable to a person skilled in the art upon reading the above description. It should be understood that it is not intended to interpret or limit the scope or meaning of the claims. Furthermore, in the above detailed description, various features may be combined to simplify the application. This should not be construed as meaning that any unclaimed disclosed feature is essential to any claim. Rather, the subject matter of the disclosure may lie in fewer than all features of a particular disclosed embodiment. Therefore, the appended claims are thus incorporated into the detailed description, wherein each claim is an independent, separate embodiment, and these embodiments are contemplated to be combined with each other in various combinations or substitutions. The scope of this application should be determined by reference to the appended claims and the full scope of their equivalents.

Claims

1. A memory device, characterized in that, include: A memory array, comprising multiple memory cells; The peripheral circuitry, coupled to the memory array, includes: multiple page buffers; each page buffer includes: at least two sets of latch circuits; each set of latch circuits includes: a first sub-latch circuit and a second sub-latch circuit, wherein; The first sub-latch circuit is coupled to the sensing node and is configured to latch the first information on the sensing node; The second sub-latch circuit is coupled to the sensing node and is configured to latch the second information on the sensing node through the first sub-latch circuit; Each set of latching circuits also includes: a transmission control switch, which connects the first sub-latching circuit and the second sub-latching circuit. The first information of the first sub-latch circuit and the second information of the second sub-latch circuit are exchanged through the sensing node, including: The sensing node is charged so that its voltage level reaches a preset threshold, so that the second information can be read onto the sensing node. In response to the transmission control signal, the transmission control switch is closed, and the first information stored in the first sub-latch circuit is transmitted to the second sub-latch circuit. Perform a clear operation on the first sub-latch circuit to restore it to its initial state; The second information is written into the first sub-latch circuit.

2. The memory device according to claim 1, characterized in that, The second sub-latch circuit includes: a parasitic capacitor for storing the second information; the parasitic capacitor is connected to the end of the transmission control switch away from the first sub-latch circuit.

3. The memory device according to claim 1, characterized in that, The at least two sets of latch circuits are configured to store data to be written or to read data.

4. The memory device according to claim 1, characterized in that, One of the at least two sets of latching circuits is configured to store intermediate data during the programming process or verification data during the verification process. The other latch circuits in the at least two latch circuits are configured to store data to be written or to read data.

5. The memory device according to any one of claims 1 to 4, characterized in that, The first sub-latch circuit includes: a set switch and a storage element, wherein, The set switch is coupled to the sensing node and connected to the storage element, and is configured to latch first information on the sensing node to the storage element in response to a set signal.

6. The memory device according to claim 5, characterized in that, The first sub-latch circuit further includes a reset switch, connected to the storage element, configured to reset the storage element in response to a reset signal.

7. The memory device according to claim 6, characterized in that, The first sub-latch circuit further includes: a sensing control switch, one end of which is connected to the set switch and the reset switch, and the other end is grounded; the sensing control switch is configured to: be turned on under the action of the level of the sensing node, and write the first information of the sensing node into the storage element through the set switch.

8. The memory device according to claim 7, characterized in that, The first sub-latch circuit further includes: a reset control switch, one end of which is connected to the set switch and the reset switch, and the other end is grounded; the reset control switch is further configured to: in response to a reset control signal, reset the first sub-latch circuit through the reset switch; The reset control signal is generated by the control logic contained in the peripheral circuit.

9. The memory device according to claim 6, characterized in that, The storage element includes: a first inverter and a second inverter; wherein, the input terminal of the first inverter is connected to the output terminal of the second inverter to form a first node; the output terminal of the first inverter is connected to the input terminal of the second inverter to form a second node; the second node is connected to the second sub-latch circuit and is configured to store the first information.

10. The memory device according to claim 9, characterized in that, The set switch includes a first transistor with one end connected to the first node; the reset switch includes a second transistor with one end connected to the second node. The other end of the first transistor is connected to the other end of the second transistor.

11. The memory device according to any one of claims 1 to 4, characterized in that, Each latching circuit further includes: a first control switch and a second control switch connected in series between the sensing node and ground, wherein the first control switch is controlled by the second information latched by the second sub-latch circuit; and the second control switch is controlled by a read control signal, wherein... When the second information controls the first control switch to turn on and the read control signal controls the second control switch to turn on, the second information is read into the sensing node.

12. The memory device according to claim 1, characterized in that, The transmission control switch includes: a transmission gate with a single MOS transistor structure or a transmission gate with a dual MOS transistor structure; the dual MOS transistor structure includes a CMOS transmission gate formed by a PMOS transistor and an NMOS transistor connected in parallel.

13. The memory device according to claim 8, characterized in that, The page buffer further includes a main latch circuit coupled to the sensing node, configured to store intermediate data during the programming process or verification data during the verification process. The main latch circuit has the same structure as the first sub-latch circuit; or, the main latch circuit and the first sub-latch circuit share the sensing control switch and the reset control switch, and the rest of the structures are the same.

14. The memory device according to claim 3, characterized in that, The at least two sets of latching circuits include: two sets of latching circuits configured to store LP data, MP data, UP data and XP data to be written or read.

15. The memory device according to claim 4, characterized in that, The at least two sets of latch circuits include: three sets of latch circuits, wherein... The two sets of latch circuits are configured to store LP data, MP data, UP data, and XP data to be written or read; The remaining set of latch circuits is configured to store intermediate data during the programming process or verification data during the verification process.

16. A method of operating a memory device, characterized in that, The memory device includes a page buffer; the page buffer includes at least two sets of latch circuits; each set of latch circuits includes a first sub-latch circuit and a second sub-latch circuit that are interdependent and coupled to a sensing node; the operation method includes: When selecting the pending data state for programming or verification operations of the memory device, the second information latched in the second sub-latch circuit is read into the sensing node; The second information of the sensing node is stored in the sensing latch circuit of the page buffer; Exchange the second information of the second sub-latch circuit with the first information latched by the first sub-latch circuit; The first information is read from the second sub-latch circuit to the sensing node, and the second information is read from the sensing latch circuit to the sensing node to obtain selection information for indicating the state of the data to be operated.

17. The operating method according to claim 16, characterized in that, The sensing latch circuit includes a first sensing latch circuit and a second sensing latch circuit; the data state to be operated includes a data state to be programmed or a data state to be verified; the step of storing the second information of the sensing node in the sensing latch circuit included in the page buffer includes: When selecting the programmable data state corresponding to the programming operation of the memory device, the second information of the sensing node is stored in the second sensing latch circuit; wherein, the first verification information stored in the second sensing latch circuit is invalid; When selecting the data state to be verified corresponding to the verification operation of the memory device, the second information of the sensing node is stored in the first sensing latch circuit, wherein the second verification information stored in the first sensing latch circuit is invalid; The first verification information and the second verification information were generated during the previous verification operation performed on the memory device.

18. The operating method according to claim 16, characterized in that, The exchange of the second information of the second sub-latch circuit and the first information latched by the first sub-latch circuit includes: The sensing node is charged so that its voltage level reaches a preset threshold, so that the second information can be read onto the sensing node. In response to the transmission control signal, the transmission path between the first sub-latch circuit and the second sub-latch is closed, and the first information is transmitted to the second sub-latch circuit; Perform a clear operation on the first sub-latch circuit to restore it to its initial state; The second information is written into the first sub-latch circuit.

19. The operating method according to claim 16, characterized in that, The operation method further includes: When writing second information to the second sub-latch circuit during programming or verification operations of the memory device, the second information is written to the first sub-latch circuit; the first sub-latch circuit and the second sub-latch circuit are swapped so that the second information is stored in the second sub-latch circuit.

20. A memory system, characterized in that, include: One or more memory devices according to any one of claims 1 to 16 and a memory controller coupled to the memory device and used for controlling the memory.

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