Memory device

Abstract

The application discloses a memory device, which comprises a first chip and a second chip, the second chip is stacked above the first chip along a third direction, the first chip comprises a storage array, the storage array comprises at least one storage block, the second chip comprises a first local bit line decoder, a second local bit line decoder, a first word line decoder and a second word line decoder electrically connected with the storage block, by constructing the first local bit line decoder block, the second local bit line decoder block, the first word line decoder block and the second word line decoder block in the storage block in the overhead projection area of the second chip, the occupied area of the first chip and the second chip after stacking can be reduced, thereby the planar occupied space of the memory device is reduced, which is helpful to realize the minimum size of the memory device.

Description

[0001] This application is a divisional application of the invention patent with application number "2021111607925", application date "2021.09.30", and title "Storage device and preparation method thereof". Technical Field

[0002] This application relates to the field of storage technology, specifically to a storage device and its fabrication method. Background Technology

[0003] like Figure 1 As shown, the memory device in the conventional technical solution includes multiple memory arrays 510, multiple local bit-line decoders 520, multiple word-line decoders 540, multiple global bit-line decoders 530, and peripheral circuits 550. The construction regions of the memory arrays 510, local bit-line decoders 520, word-line decoders 540, global bit-line decoders 530, and peripheral circuits 550 do not overlap. For example, the construction region of the local bit-line decoder 520 is located on one side of the construction region of the corresponding memory array 510, the word-line decoder 540 is located on the other side of the construction region of the corresponding local bit-line decoder 520 and / or the construction region of the memory array 510, and the construction region of the global bit-line decoder 530 is located between the construction region of the corresponding local bit-line decoder 520 and the construction region of the peripheral circuit region 550.

[0004] Specifically, such as Figure 2 As shown, a memory block 511 in the memory array 510 is electrically connected to a local bit-line decoder 520 via multiple first connection traces 531, and the memory block 511 is electrically connected to a word-line decoder 540 via multiple second connection traces 532. The local bit-line decoder 520 is located on one side of the memory block 511, and the word-line decoder 540 is located on the other side of the memory block 511. Similarly, Figure 2 The construction regions of the central storage block 511, the local bit line decoder 520, and the word line decoder 540 do not overlap.

[0005] Thus, the storage devices in the aforementioned traditional technical solutions require a large space to integrate the various structural components, which is not conducive to minimizing the size of the storage devices.

[0006] It should be noted that the above description of the background technology is merely for the purpose of facilitating a clear and complete understanding of the technical solutions of this application. Therefore, it should not be assumed that the technical solutions mentioned above are known to those skilled in the art simply because they appear in the background technology of this application. Summary of the Invention

[0007] This application provides a storage device and a method for manufacturing the same, in order to alleviate the technical problem that storage devices require a large amount of space.

[0008] In a first aspect, this application provides a memory device comprising a first chip and a second chip, the second chip being stacked above the first chip along a third direction. The first chip includes a memory array, the memory array including at least one memory block, the memory block including a plurality of word lines extending along a first direction and a plurality of bit lines extending along a second direction. The second chip includes a first local bit line decoder, a second local bit line decoder, a first word line decoder, and a second word line decoder electrically connected to the memory block. The second chip has a top-view projection area of ​​the memory block, and the first local bit line decoder, the second local bit line decoder, the first word line decoder, and the second word line decoder respectively form a non-overlapping first local bit line decoder block, a second local bit line decoder block, a first word line decoder block, and a second word line decoder block in the top-view projection area.

[0009] In some embodiments, in the first direction, the sum of the first length of the first local bit line decoder block and the second length of the second local bit line decoder block is less than or equal to the length of the top-view projection area, and the projections of the first local bit line decoder block and the second local bit line decoder block in the second direction do not overlap; in the second direction, the sum of the third length of the first word line decoder block and the fourth length of the second word line decoder block is less than or equal to the width of the top-view projection area, and the projections of the first word line decoder block and the second word line decoder block in the first direction do not overlap.

[0010] In some implementations, the first length is different from the second length; and the third length is different from the fourth length.

[0011] In some embodiments, a portion of the multiple bit lines is electrically connected to a first local bit line decoder, and another portion of the multiple bit lines is electrically connected to a second local bit line decoder; a portion of the multiple word lines is electrically connected to a first word line decoder, and another portion of the multiple word lines is electrically connected to a second word line decoder.

[0012] In some embodiments, in a first direction, a first word line decoder block is located between a first edge of the top-view projection region extending along a second direction and a first local bit line decoder block, and the width of the first local bit line decoder block in the second direction is less than the length of the first word line decoder block in the second direction; in a second direction, the first word line decoder block is located between a second edge of the top-view projection region extending along a first direction and a second local bit line decoder block, and the length of the second local bit line decoder block in the first direction is greater than the width of the first word line decoder block in the first direction.

[0013] In some embodiments, in the first direction, the second word line decoder block is located between the third edge of the top-view projection area extending along the second direction and the second local bit line decoder block, and the width of the second local bit line decoder block in the second direction is less than the length of the second word line decoder block in the second direction; in the second direction, the second word line decoder block is located between the fourth edge of the top-view projection area extending along the first direction and the first local bit line decoder block, and the length of the first local bit line decoder block in the first direction is greater than the width of the second word line decoder block in the first direction.

[0014] In some embodiments, the first local bit line decoder and the second local bit line decoder each have multiple first transmission terminals, and each first transmission terminal is electrically connected to a bit line through a first through-silicon via or a pair of first bonding pads.

[0015] In some embodiments, the first word line decoder and the second word line decoder each have multiple second transmission terminals, and each second transmission terminal is electrically connected to a word line through a second through-silicon via or a pair of second bonding pads.

[0016] In some embodiments, the first chip includes a first bonding layer, the first bonding layer including at least one first bonding pad and / or a second bonding pad; the second chip includes a second bonding layer, the second bonding layer including at least one first bonding pad and / or a second bonding pad; the first bonding pad located on the first bonding layer is bonded to the first bonding pad located on the second bonding layer, and / or, the second bonding pad located on the first bonding layer is bonded to the second bonding pad located on the second bonding layer.

[0017] In some embodiments, the top-view projection area is rectangular, with the first local bit-line decoder block located at one of the first or third right angles of the top-view projection area, and the second local bit-line decoder block located at the other of the first or third right angles of the top-view projection area; the first word-line decoder block located at one of the second or fourth right angles of the top-view projection area, and the second word-line decoder block located at the other of the second or fourth right angles of the top-view projection area; or, the first local bit-line decoder block located at one of the second or fourth right angles of the top-view projection area, and the second local bit-line decoder block located at the other of the second or fourth right angles of the top-view projection area; the first word-line decoder block located at one of the first or third right angles of the top-view projection area, and the second word-line decoder block located at the other of the first or third right angles of the top-view projection area; wherein the first and third right angles are located at the two ends of one diagonal of the top-view projection area, and the second and fourth right angles are located at the two ends of the other diagonal of the top-view projection area.

[0018] In some embodiments, in a first direction, the first word line decoder block is located between the left end of the second local bit line decoder block and the left end of the first local bit line decoder block; in the first direction, the second word line decoder block is located between the right end of the first local bit line decoder block and the right end of the second local bit line decoder block.

[0019] In some embodiments, in the second direction, the first local bit-line decoder block is located between the upper end of the first word-line decoder block and the upper end of the second word-line decoder block; in the second direction, the second local bit-line decoder block is located between the lower end of the second word-line decoder block and the lower end of the first word-line decoder block.

[0020] In some embodiments, in a first direction, the length of the first local bit line decoder block and the length of the second local bit line decoder block are both less than or equal to the length of the top-view projection area; in a second direction, the first word line decoder block is located between the first local bit line decoder block and the second local bit line decoder block, and the second word line decoder block is located between the first local bit line decoder block and the second local bit line decoder block.

[0021] In some embodiments, in the second direction, the length of the first word line decoder block and the length of the second word line decoder block are both less than or equal to the width of the top-view projection area; in the first direction, the first local bit line decoder block is located between the first word line decoder block and the second word line decoder block, and the second local bit line decoder block is located between the first word line decoder block and the second word line decoder block.

[0022] Secondly, this application provides a method for fabricating a memory device, comprising: constructing a memory array on a first chip, the memory array including at least one memory block, the memory block including a plurality of word lines extending along a first direction and a plurality of bit lines extending along a second direction; constructing a first local bit line decoder, a second local bit line decoder, a first word line decoder and a second word line decoder on a second chip, the second chip having a top-view projection area of ​​the memory block, the first local bit line decoder, the second local bit line decoder, the first word line decoder and the second word line decoder being electrically connected to the memory block, and forming non-overlapping first local bit line decoder blocks, second local bit line decoder blocks, first word line decoder blocks and second word line decoder blocks in the top-view projection area; and stacking the second chip on top of the first chip along a third direction.

[0023] In some embodiments, the preparation method further includes: in a first direction, configuring the sum of a first length of a first local bit line decoder block and a second length of a second local bit line decoder block to be less than or equal to the length of the top-view projection area, and the projections of the first local bit line decoder block and the second local bit line decoder block in the second direction do not overlap; in a second direction, configuring the sum of a third length of a first word line decoder block and a fourth length of a second word line decoder block to be less than or equal to the width of the top-view projection area, and the projections of the first word line decoder block and the second word line decoder block in the second direction do not overlap.

[0024] In some embodiments, the fabrication method further includes: electrically connecting a portion of a plurality of bit lines to a first local bit line decoder; electrically connecting another portion of the plurality of bit lines to a second local bit line decoder; electrically connecting a portion of a plurality of word lines to the first word line decoder; and electrically connecting another portion of the plurality of word lines to the second word line decoder.

[0025] In some embodiments, the fabrication method further includes: constructing a first bonding layer on a first chip; constructing a second bonding layer on a second chip; and stacking the second chip on top of the first chip, and forming a bonding structure through the first bonding layer and the second bonding layer to electrically connect the first chip and the second chip.

[0026] The memory device and its fabrication method provided in this application, by constructing a first local bit line decoder block, a second local bit line decoder block, a first word line decoder block, and a second word line decoder block located within the top-view projection area of ​​the memory block on the second chip, can reduce the area occupied by the first chip and the second chip after stacking, thereby reducing the planar space occupied by the memory device and helping to achieve the minimum size of the memory device.

[0027] Furthermore, in the first direction, the first length of the first local bit line decoder block and the second length of the second local bit line decoder block are less than or equal to the length of the top-view projection area, and the projections of the first local bit line decoder block and the second local bit line decoder block in the second direction do not overlap. In the second direction, the third length of the first word line decoder block and the fourth length of the second word line decoder block are less than or equal to the width of the top-view projection area, and the first word line decoder block and the second word line decoder block do not overlap in the first direction, which facilitates the realization of the corresponding electrical connections between word lines, bit lines and the first local bit line decoder, the second local bit line decoder, the first word line decoder and the second word line decoder in the memory block.

[0028] Meanwhile, by constructing a non-overlapping first local bit-line decoder block, second local bit-line decoder block, first word-line decoder block, and second word-line decoder block, the local bit-line decoder block and word-line decoder block can all be set within the projection range of the memory array / memory block, reducing the cross-relationship of electrical connections in the second chip, further reducing the chip size, and facilitating the second chip to achieve electrical connection with the first chip with a thinner thickness.

[0029] By splitting the word line decoder and / or bit line decoder into two sub-modules, both the word line decoder and the bit line decoder can be placed entirely within the projection range of the memory array / memory block. Based on the fact that the decoder is completely within the projection range and the stacked structure of the two chips, the decoder can be vertically connected to the memory array without the need for additional lateral traces. Therefore, no trace space is required between the two sub-modules, which can further reduce the area of ​​the first chip and the second chip. Attached Figure Description

[0030] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0031] Figure 1 A schematic diagram showing the distribution of various parts of a storage device provided by a conventional technical solution.

[0032] Figure 2 A schematic diagram showing another distribution of the various parts of the storage device provided by a conventional technical solution.

[0033] Figure 3 This is a schematic diagram of the first structural distribution of the storage device provided in the embodiments of this application.

[0034] Figure 4 This is a schematic diagram of a second structural distribution of the storage device provided in an embodiment of this application.

[0035] Figure 5 This is a schematic diagram of a third structural distribution of the storage device provided in an embodiment of this application.

[0036] Figure 6 This is a schematic diagram of a fourth structural distribution of the storage device provided in an embodiment of this application.

[0037] Figure 7 This is a schematic diagram of the fifth structural distribution of the storage device provided in the embodiments of this application.

[0038] Figure 8 This is a schematic flowchart illustrating the fabrication method of the storage device provided in the embodiments of this application. Detailed Implementation

[0039] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0040] In the description of this disclosure, word line decoders are also described as X-DECs, and bit line decoders can be described as bit line selectors, bit line multiplexers, or Y-MUXs for locating a majority of memory cells in a memory array for further read and write operations on the memory cells.

[0041] In the description of this disclosure, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the purpose of simplifying the description of this disclosure. They do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as limiting this disclosure. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.

[0042] In the description of this disclosure, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0043] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through a third feature other than themselves. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0044] Please see Figures 3 to 8 This embodiment provides a storage device including a first chip 100 and a second chip 200. The second chip 200 is stacked above the first chip 100 along a third direction DR3. The first chip 100 includes a storage array 10, which includes at least one storage block 11. The storage block 11 includes multiple word lines extending along a first direction DR1 and multiple bit lines extending along a second direction DR2. The second chip 200 includes a first local bit line decoder, a second local bit line decoder, a first word line decoder, and a second word line decoder electrically connected to the storage block 11. The second chip 200 has a top-view projection area of ​​the storage block 11, and the first local bit line decoder, the second local bit line decoder, the first word line decoder, and the second word line decoder respectively form a non-overlapping first local bit line decoder block, a second local bit line decoder block, a first word line decoder block, and a second word line decoder block in the top-view projection area.

[0045] It is understood that the memory device provided in this embodiment, by constructing a first local bit line decoder block, a second local bit line decoder block, a first word line decoder block, and a second word line decoder block located in the top-view projection area of ​​the memory block 11 in the second chip 200, can reduce the area occupied by the first chip 100 and the second chip 200 after stacking, thereby reducing the planar space occupied by the memory device and helping to achieve the minimum size of the memory device.

[0046] In the first direction DR1, the sum of the first length of the first local bit line decoder block and the second length of the second local bit line decoder block is less than or equal to the length of the top-view projection area, and the projections of the first local bit line decoder block and the second local bit line decoder block in the second direction DR2 do not overlap. In the second direction DR2, the sum of the third length of the first word line decoder block and the fourth length of the second word line decoder block is less than or equal to the width of the top-view projection area, and the projections of the first word line decoder block and the second word line decoder block in the second direction DR1 do not overlap. This facilitates the corresponding electrical connections between the word lines and bit lines in the memory block 11 and the first local bit line decoder 21, the second local bit line decoder 22, the first word line decoder 31, and the second word line decoder 32.

[0047] Meanwhile, by constructing the first local bit line decoder block, the second local bit line decoder block, the first word line decoder block, and the second word line decoder block to be non-overlapping, the cross-relationship of electrical connections in the second chip 200 is reduced, which is beneficial for the second chip 200 to achieve electrical connection with the first chip 100 with a thinner thickness and reduce delay.

[0048] In one embodiment, a continuous portion of the multiple bit lines is electrically connected to a first local bit line decoder 21, and another continuous portion of the multiple bit lines is electrically connected to a second local bit line decoder 22; a continuous portion of the multiple word lines is electrically connected to a first word line decoder 31, and another continuous portion of the multiple word lines is electrically connected to a second word line decoder 32.

[0049] In one embodiment, in the first direction DR1, the first word line decoder block is located between the first edge of the top-view projection area extending along the second direction DR2 and the first local bit line decoder block, and the width of the first local bit line decoder block in the second direction DR2 is less than the length of the first word line decoder block in the second direction DR2; in the second direction DR2, the first word line decoder block is located between the second edge of the top-view projection area extending along the first direction DR1 and the second local bit line decoder block, and the length of the second local bit line decoder block in the first direction DR1 is greater than the width of the first word line decoder block in the first direction DR1.

[0050] In one embodiment, in the first direction DR1, the second word line decoder block is located between the third edge of the top-view projection area extending along the second direction DR2 and the second local bit line decoder block, and the width of the second local bit line decoder block in the second direction DR2 is less than the length of the second word line decoder block in the second direction DR2; in the second direction DR2, the second word line decoder block is located between the fourth edge of the top-view projection area extending along the first direction DR1 and the first local bit line decoder block, and the length of the first local bit line decoder block in the first direction DR1 is greater than the width of the second word line decoder block in the first direction DR1.

[0051] In one embodiment, the first local bit line decoder 21 and the second local bit line decoder 22 each have a plurality of first transmission terminals, and a first transmission terminal is electrically connected to a bit line through a first silicon via or a pair of first bonding pads.

[0052] In one embodiment, both the first word line decoder 31 and the second word line decoder 32 have multiple second transmission terminals, and each second transmission terminal is electrically connected to a word line through a second through-silicon via or a pair of second bonding pads.

[0053] Any of the transmission ends may be, but is not limited to, a metal pad, such as a copper pad or a metal block.

[0054] It should be noted that the first edge can be either the left or right edge of the top-view projection area, and the third edge can be either the left or right edge of the top-view projection area. The second edge can be either the lower or upper edge of the top-view projection area, and the fourth edge can be either the lower or upper edge of the top-view projection area.

[0055] In one embodiment, the first chip 100 and the second chip 200 are electrically connected by a bonding structure, which includes a first bonding layer on the first chip 100 and a second bonding layer on the second chip 200.

[0056] Specifically, the first chip includes a first bonding layer, the first bonding layer including at least one first bonding pad and / or a second bonding pad; the second chip includes a second bonding layer, the second bonding layer including at least one first bonding pad and / or a second bonding pad; the first bonding pad located in the first bonding layer is bonded to the first bonding pad located in the second bonding layer, and / or, the second bonding pad located in the first bonding layer is bonded to the second bonding pad located in the second bonding layer.

[0057] It should be noted that in this embodiment, the first chip 100 and the second chip 200 can be electrically connected by a bonding structure. Specifically, conventional techniques can be used to implement the bonding process, which will not be elaborated here.

[0058] like Figure 3 As shown, this embodiment provides a storage device including a first chip 100 and a second chip 200. The first chip 100 includes a storage array 10, which includes at least one storage block 11, wherein the area where one of the storage blocks 11 is located is a top-view projection area. The second chip 200 includes a logic control circuit, which includes a first local bit-line decoder 21 and a second local bit-line decoder 22. One of the storage blocks 11 is electrically connected to the first local bit-line decoder 21 and the second local bit-line decoder 22. The first local bit-line decoder block formed by the first local bit-line decoder 21 at least partially overlaps with the top-view projection area, and the second local bit-line decoder block formed by the second local bit-line decoder 22 at least partially overlaps with the top-view projection area. The relative positions of the first local bit-line decoder block and the second local bit-line decoder block are set at a first diagonal.

[0059] It is understood that the memory device provided in this embodiment can reduce the area occupied by the stacked first chip 100 and second chip 200 by at least partially overlapping the top-view projection area formed by one of the memory blocks 11 with the first local bit line decoder block and the second local bit line decoder block, thereby reducing the space occupied by the memory device and helping to achieve the minimum size of the memory device; and the relative positions of the first local bit line decoder block and the second local bit line decoder block are set at the first diagonal, which facilitates the electrical connection between one of the memory blocks 11 and the first local bit line decoder 21 and the second local bit line decoder 22.

[0060] The storage device can be, but is not limited to, NOR Flash, or other types of storage chips.

[0061] It should be noted that each structural region and / or each sub-structural region may be, but is not limited to, a rectangle, a regular polygon, or a circle or other shapes.

[0062] The logic control circuit includes a local bit-line decoder 20, which includes a first local bit-line sub-decoder 20A, a first local bit-line sub-decoder 20A, and a second local bit-line decoder 22. Each memory block 11 can be configured with a corresponding local bit-line sub-decoder.

[0063] In one embodiment, one of the memory blocks 11 includes a plurality of bit lines, a portion of which is electrically connected to a first local bit line decoder 21, and another portion of which is electrically connected to a second local bit line decoder 22.

[0064] It should be noted that multiple bit lines can be arranged in the first direction DR1.

[0065] In one embodiment, one of the memory blocks 11 further includes a plurality of word lines, a portion of which is electrically connected to a first local bit line decoder 21, and another portion of which is electrically connected to a second local bit line decoder 22.

[0066] It should be noted that multiple letter lines can be arranged in the second direction DR2.

[0067] In one embodiment, the thickness direction of the stacked first chip 100 and second chip 200 can be defined as third direction DR3.

[0068] like Figure 3 and Figure 4 As shown, in one embodiment, the first local bit line decoder block at least partially overlaps with the first upper right structural region or the first lower right structural region of the top-view projection region; if the first local bit line decoder block at least partially overlaps with the first upper right structural region of the top-view projection region, then the second local bit line decoder block at least partially overlaps with the first lower left structural region of the top-view projection region; if the first local bit line decoder block at least partially overlaps with the first lower right structural region of the top-view projection region, then the second local bit line decoder block at least partially overlaps with the first upper left structural region of the top-view projection region.

[0069] In one embodiment, the first local bit line decoder block at least partially overlaps with the first upper left structural region or the first lower left structural region of the top-view projection region; if the first local bit line decoder block at least partially overlaps with the first upper left structural region of the top-view projection region, then the second local bit line decoder block at least partially overlaps with the first lower right structural region of the top-view projection region; if the first local bit line decoder block at least partially overlaps with the first lower left structural region of the top-view projection region, then the second local bit line decoder block at least partially overlaps with the first upper right structural region of the top-view projection region.

[0070] In one embodiment, the logic control circuit further includes a first word line decoder 31 and a second word line decoder 32, wherein a memory block 11 is electrically connected to the first word line decoder 31 and the second word line decoder 32, the first word line decoder block formed by the first word line decoder 31 overlaps at least partially with the top-view projection area, the second word line decoder block formed by the second word line decoder 32 overlaps at least partially with the top-view projection area, and the relative positions of the first word line decoder block and the second word line decoder block are set at a second diagonal, wherein the second diagonal is different from the first diagonal.

[0071] It should be noted that the logic control circuit includes a word line decoder 30, which includes a first word line sub-decoder 30A, and the first word line sub-decoder 30A includes a first word line decoder 31 and a second word line decoder 32. Each memory block 11 can be configured with one corresponding word line sub-decoder.

[0072] like Figure 3 and Figure 4 As shown, in one embodiment, the first word line decoder block at least partially overlaps with the second upper left structural region or the second lower left structural region of the top-view projection area; if the first word line decoder block at least partially overlaps with the second upper left structural region of the top-view projection area, then the second word line decoder block at least partially overlaps with the second lower right structural region of the top-view projection area; if the first word line decoder block at least partially overlaps with the second lower left structural region of the top-view projection area, then the second word line decoder block at least partially overlaps with the second upper right structural region of the top-view projection area.

[0073] In one embodiment, the first word line decoder block at least partially overlaps with the second upper right structural region or the second lower right structural region of the top-view projection area; if the first word line decoder block at least partially overlaps with the second upper right structural region of the top-view projection area, then the second word line decoder block at least partially overlaps with the second lower left structural region of the top-view projection area; if the first word line decoder block at least partially overlaps with the second lower right structural region of the top-view projection area, then the second word line decoder block at least partially overlaps with the second upper left structural region of the top-view projection area.

[0074] like Figure 3 and Figure 4As shown, in one embodiment, this embodiment provides a storage device including a first chip 100 and a second chip 200. The first chip 100 includes a storage array 10, which includes at least one storage block 11, wherein the area where one of the storage blocks 11 is located is a top-view projection area. The second chip 200 includes a logic control circuit, which includes a first word line decoder 31 and a second word line decoder 32. One of the storage blocks 11 is electrically connected to the first word line decoder 31 and the second word line decoder 32. The first word line decoder block formed by the first word line decoder 31 at least partially overlaps with the top-view projection area, and the second word line decoder block formed by the second word line decoder 32 at least partially overlaps with the top-view projection area. The relative positions of the first word line decoder block and the second word line decoder block are arranged at a second diagonal.

[0075] It is understood that the storage device provided in this embodiment can reduce the area occupied by the stacked first chip 100 and second chip 200 by at least partially overlapping the top-view projection area formed by one of the storage blocks 11 with the first word line decoder block and the second word line decoder block, thereby reducing the space occupied by the storage device and helping to achieve the minimum size of the storage device; and the relative positions of the first word line decoder block and the second word line decoder block are set at the second diagonal, which facilitates the electrical connection between one of the storage blocks 11 and the first word line decoder 31 and the second word line decoder 32.

[0076] In one embodiment, the logic control circuit further includes a first local bit-line decoder 21 and a second local bit-line decoder 22, wherein a memory block 11 is electrically connected to the first local bit-line decoder 21 and the second local bit-line decoder 22, the first local bit-line decoder block formed by the first local bit-line decoder 21 at least partially overlaps with the top-view projection area, the second local bit-line decoder block formed by the second local bit-line decoder 22 at least partially overlaps with the top-view projection area, and the relative positions of the first local bit-line decoder block and the second local bit-line decoder block are set at a first diagonal, wherein the first diagonal is different from the second diagonal.

[0077] Specifically, the top-view projection area can be rectangular. The first local bit-line decoder block is located at one of the first or third right angles of the top-view projection area, and the second local bit-line decoder block is located at the other of the first or third right angles of the top-view projection area. The first word-line decoder block is located at one of the second or fourth right angles of the top-view projection area, and the second word-line decoder block is located at the other of the second or fourth right angles of the top-view projection area. Alternatively, the first local bit-line decoder block is located at one of the second or fourth right angles of the top-view projection area, and the second local bit-line decoder block is located at the other of the second or fourth right angles of the top-view projection area; the first word-line decoder block is located at one of the first or third right angles of the top-view projection area, and the second word-line decoder block is located at the other of the first or third right angles of the top-view projection area. The first and third right angles are located at the two ends of one diagonal of the top-view projection area, and the second and fourth right angles are located at the two ends of the other diagonal of the top-view projection area.

[0078] In one embodiment, the first word line decoder 31 and the second word line decoder 32 may interchange their respective sub-construction regions.

[0079] In one embodiment, the first local bit-line decoder 21 may also interchange its respective sub-construction regions with the second local bit-line decoder 22.

[0080] like Figure 5 As shown, in one embodiment, the positions of the first word line decoder block and the second word line decoder block can be flexibly set on the first direction DR1. For example, the first word line decoder block can be located on the first direction DR1 between the left end of the second local bit line decoder block and the left end of the first local bit line decoder block, for example, it can be externally connected to the first local bit line decoder block; similarly, the second word line decoder block can be located on the first direction DR1 between the right end of the first local bit line decoder block and the right end of the second local bit line decoder block, for example, it can be externally connected to the second local bit line decoder block.

[0081] The positions of the first local bit line decoder block and the second local bit line decoder block can be flexibly set on the second direction DR2. For example, the first local bit line decoder block can be located on the second direction DR2 between the upper end of the first word line decoder block and the upper end of the second word line decoder block, for example, it can be externally connected to the second word line decoder block; similarly, the second local bit line decoder block can be located on the second direction DR2 between the lower end of the second word line decoder block and the lower end of the first word line decoder block, for example, it can be externally connected to the first word line decoder block.

[0082] like Figure 6As shown, in one embodiment, in the first direction DR1, the length of the first local bit line decoder block and the length of the second local bit line decoder block are both less than or equal to the length of the top-view projection area; in the second direction DR2, the first word line decoder block is located between the first local bit line decoder block and the second local bit line decoder block, and the second word line decoder block is located between the first local bit line decoder block and the second local bit line decoder block.

[0083] like Figure 7 As shown, in one embodiment, in the second direction DR2, the length of the first word line decoder block and the length of the second word line decoder block are both less than or equal to the width of the top-view projection area; in the first direction DR1, the first local bit line decoder block is located between the first word line decoder block and the second word line decoder block, and the second local bit line decoder block is located between the first word line decoder block and the second word line decoder block.

[0084] like Figure 8 As shown, in one embodiment, this embodiment provides a method for manufacturing a storage device, which includes the following steps:

[0085] Step S10: Construct a memory array on the first chip. The memory array includes at least one memory block. The memory block includes multiple word lines extending along a first direction and multiple bit lines extending along a second direction.

[0086] Step S20: Construct a first local bit line decoder, a second local bit line decoder, a first word line decoder, and a second word line decoder on a second chip. The second chip has a top-view projection area of ​​a memory block. The first local bit line decoder, the second local bit line decoder, the first word line decoder, and the second word line decoder are electrically connected to the memory block, and non-overlapping first local bit line decoder blocks, second local bit line decoder blocks, first word line decoder blocks, and second word line decoder blocks are respectively formed in the top-view projection area.

[0087] And step S30: stack the second chip on top of the first chip along the third direction.

[0088] It is understood that the fabrication method provided in this embodiment, by constructing a first local bit line decoder block, a second local bit line decoder block, a first word line decoder block, and a second word line decoder block located in the top-view projection area of ​​the storage block 11 in the second chip 200, can reduce the area occupied by the first chip 100 and the second chip 200 after stacking, thereby reducing the planar space occupied by the storage device and helping to achieve the minimum size of the storage device.

[0089] Furthermore, in the first direction DR1, the sum of the first length of the first local bit line decoder block and the second length of the second local bit line decoder block is less than or equal to the length of the top-view projection area, and the projections of the first local bit line decoder block and the second local bit line decoder block in the second direction DR2 do not overlap; in the second direction DR2, the sum of the third length of the first word line decoder block and the fourth length of the second word line decoder block is less than or equal to the width of the top-view projection area, and the projections of the first word line decoder block and the second word line decoder block in the second direction DR1 do not overlap, which facilitates the corresponding electrical connection between the word lines and bit lines in the storage block 11 and the first local bit line decoder 21, the second local bit line decoder 22, the first word line decoder 31, and the second word line decoder 32.

[0090] Meanwhile, by constructing the first local bit line decoder block, the second local bit line decoder block, the first word line decoder block, and the second word line decoder block to be non-overlapping, the cross-relationship of electrical connections in the second chip 200 is reduced, which is beneficial for the second chip 200 to achieve electrical connection with the first chip 100 with a thinner thickness and reduce delay.

[0091] In one embodiment, the fabrication method further includes: electrically connecting a continuous portion of a plurality of bit lines to a first local bit line decoder 21; electrically connecting another continuous portion of a plurality of bit lines to a second local bit line decoder 22; electrically connecting a continuous portion of a plurality of word lines to a first word line decoder 31; and electrically connecting another continuous portion of a plurality of word lines to a second word line decoder 32.

[0092] In one embodiment, the fabrication method further includes: constructing a first bonding layer on a first chip 100; constructing a second bonding layer on a second chip 200; and stacking the second chip 200 on top of the first chip 100, and forming a bonding structure through the first bonding layer and the second bonding layer to electrically connect the first chip 100 and the second chip 200.

[0093] In one embodiment, this embodiment provides a method for manufacturing a storage device, which includes the following steps:

[0094] A storage array 10 is constructed on the first chip 100. The storage array 10 includes at least one storage block 11, wherein the area where one of the storage blocks 11 is located is the top-view projection area.

[0095] A logic control circuit is constructed on the second chip 200. The logic control circuit includes a first local bit line decoder 21 and a second local bit line decoder 22. The area where the first local bit line decoder 21 is located is the first local bit line decoder block, and the area where the second local bit line decoder 22 is located is the second local bit line decoder block.

[0096] At least a portion of the first local bit line decoder block is stacked on one side of the upper right region of the top-view projection area, and / or at least a portion of the second local bit line decoder block is stacked on one side of the lower left region of the top-view projection area, and the relative positions of the first local bit line decoder block and the second local bit line decoder block are set at a first diagonal.

[0097] It is understood that the fabrication method provided in this embodiment can reduce the area occupied by the stacked first chip 100 and second chip 200 by at least partially overlapping the top-view projection area formed by one of the memory blocks 11 with the first local bit line decoder block and the second local bit line decoder block, thereby reducing the space occupied by the memory device and helping to achieve the minimum size of the memory device; and the relative positions of the first local bit line decoder block and the second local bit line decoder block are set at the first diagonal, which facilitates the electrical connection between one of the memory blocks 11 and the first local bit line decoder 21 and the second local bit line decoder 22.

[0098] In one embodiment, the fabrication method further includes: constructing a plurality of bit lines in one of the memory blocks 11; configuring a portion of the plurality of bit lines to be electrically connected to a first local bit line decoder 21; and configuring another portion of the plurality of bit lines to be electrically connected to a second local bit line decoder 22.

[0099] In one embodiment, the fabrication method further includes: constructing a first word line decoder 31 and a second word line decoder 32 in a logic control circuit, wherein the area where the first word line decoder 31 is located is a first word line decoder block, and the area where the second word line decoder 32 is located is a second word line decoder block; configuring a memory block 11 electrically connected to the first word line decoder 31 and the second word line decoder 32; and stacking at least a portion of the first word line decoder block on one side of the upper left region of the top-view projection area, and / or, at least a portion of the second word line decoder block on one side of the lower right region of the top-view projection area, and setting the relative positions of the first word line decoder block and the second word line decoder block at a second diagonal, wherein the second diagonal is different from the first diagonal.

[0100] It should be noted that the projections of the first word line decoder block and the second word line decoder block on the first direction DR1 do not overlap. This means that along the first direction DR1, the first word line decoder block can have its own projection, and the second word line decoder block can have its own projection; furthermore, on the first direction DR1, the projections of the first word line decoder block and the second word line decoder block do not overlap on any plane perpendicular to the first direction DR1.

[0101] The projections of the first local bit line decoder block and the second local bit line decoder block onto the second direction DR2 do not overlap. This means that along the second direction DR2, the first local bit line decoder block can have its own projection, and the second local bit line decoder block can have its own projection; furthermore, on the second direction DR2, the projections of the first and second local bit line decoder blocks do not overlap on any plane perpendicular to the second direction DR2.

[0102] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0103] The storage devices and their manufacturing methods provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A storage device, characterized in that, include: A first chip, the first chip including a memory array, the memory array including at least one memory block, the memory block including a plurality of word lines extending along a first direction and a plurality of bit lines extending along a second direction; The second chip is stacked on top of the first chip along a third direction. The second chip includes a first local bit line decoder, a second local bit line decoder, a first word line decoder, and a second word line decoder electrically connected to the memory block. The second chip has a top-view projection area of ​​the memory block, and the first local bit line decoder, the second local bit line decoder, the first word line decoder, and the second word line decoder respectively form a non-overlapping first local bit line decoder block, a second local bit line decoder block, a first word line decoder block, and a second word line decoder block in the top-view projection area. In the first direction, the sum of the first length of the first local bit line decoder block and the second length of the second local bit line decoder block is equal to the length of the top-view projection region, and the projections of the first local bit line decoder block and the second local bit line decoder block in the second direction do not overlap; and / or, in the second direction, the sum of the third length of the first word line decoder block and the fourth length of the second word line decoder block is equal to the width of the top-view projection region, and the projections of the first word line decoder block and the second word line decoder block in the first direction do not overlap.

2. The storage device according to claim 1, characterized in that, The first length is different from the second length; and the third length is different from the fourth length.

3. The storage device according to claim 1, characterized in that, A portion of the plurality of bit lines is electrically connected to the first local bit line decoder, and another portion of the plurality of bit lines is electrically connected to the second local bit line decoder; A portion of the multiple word lines is electrically connected to the first word line decoder, and another portion of the multiple word lines is electrically connected to the second word line decoder.

4. The storage device according to claim 1, characterized in that, In the first direction, the second word line decoder block is located between the third edge of the top-view projection area extending along the second direction and the second local bit line decoder block, and the width of the second local bit line decoder block in the second direction is less than the length of the second word line decoder block in the second direction; in the second direction, the second word line decoder block is located between the fourth edge of the top-view projection area extending along the first direction and the first local bit line decoder block, and the length of the first local bit line decoder block in the first direction is greater than the width of the second word line decoder block in the first direction.

5. The storage device according to claim 3, characterized in that, Both the first local bit line decoder and the second local bit line decoder have multiple first transmission terminals, and each first transmission terminal is electrically connected to a bit line through a first through-silicon via or a pair of first bonding pads.

6. The storage device according to claim 5, characterized in that, Both the first word line decoder and the second word line decoder have multiple second transmission terminals, and each second transmission terminal is electrically connected to a word line through a second through-silicon via or a pair of second bonding pads.

7. The storage device according to claim 5 or 6, characterized in that, The first chip includes a first bonding layer, the first bonding layer including at least one first bonding pad and / or a second bonding pad; the second chip includes a second bonding layer, the second bonding layer including at least one first bonding pad and / or a second bonding pad; the first bonding pad located on the first bonding layer is bonded to the first bonding pad located on the second bonding layer, and / or the second bonding pad located on the first bonding layer is bonded to the second bonding pad located on the second bonding layer.

8. The storage device according to claim 1, characterized in that, The top-view projection area is rectangular. The first local bit-line decoder block is located at one of the first right angles or the third right angle of the top-view projection area, and the second local bit-line decoder block is located at the other of the first right angles or the third right angle of the top-view projection area. The first word-line decoder block is located at one of the second right angles or the fourth right angle of the top-view projection area, and the second word-line decoder block is located at the other of the second right angles or the fourth right angle of the top-view projection area. Alternatively, the first local bit line decoder block is located at one of the second or fourth right angles of the top-view projection area, and the second local bit line decoder block is located at the other of the second or fourth right angles of the top-view projection area; the first word line decoder block is located at one of the first or third right angles of the top-view projection area, and the second word line decoder block is located at the other of the first or third right angles of the top-view projection area; The first right angle and the third right angle are located at the two ends of a pair of diagonals in the top-view projection area, and the second right angle and the fourth right angle are located at the two ends of the other pair of diagonals in the top-view projection area.

9. The storage device according to claim 1, characterized in that, In the first direction, the first word line decoder block is located between the left end of the second local bit line decoder block and the left end of the first local bit line decoder block. In the first direction, the second word line decoder block is located between the right end of the first local bit line decoder block and the right end of the second local bit line decoder block.

10. The storage device according to claim 1, characterized in that, In the second direction, the first local bit line decoder block is located between the upper end of the first word line decoder block and the upper end of the second word line decoder block; In the second direction, the second local bit-line decoder block is located between the lower end of the second word-line decoder block and the lower end of the first word-line decoder block.

11. The storage device according to claim 1, characterized in that, In the first direction, the length of the first local bit line decoder block and the length of the second local bit line decoder block are both less than or equal to the length of the top-view projection area; in the second direction, the first word line decoder block is located between the first local bit line decoder block and the second local bit line decoder block, and the second word line decoder block is located between the first local bit line decoder block and the second local bit line decoder block.

12. The storage device according to claim 1, characterized in that, In the second direction, the length of the first word line decoder block and the length of the second word line decoder block are both less than or equal to the width of the top-view projection area; in the first direction, the first local bit line decoder block is located between the first word line decoder block and the second word line decoder block, and the second local bit line decoder block is located between the first word line decoder block and the second word line decoder block.

13. A storage device, characterized in that, include: A first chip, the first chip including a memory array, the memory array including at least one memory block, the memory block including a plurality of word lines extending along a first direction and a plurality of bit lines extending along a second direction; The second chip is stacked on top of the first chip along a third direction. The second chip includes a first local bit line decoder, a second local bit line decoder, a first word line decoder, and a second word line decoder electrically connected to the memory block. The second chip has a top-view projection area of ​​the memory block, and the first local bit line decoder, the second local bit line decoder, the first word line decoder, and the second word line decoder respectively form a non-overlapping first local bit line decoder block, a second local bit line decoder block, a first word line decoder block, and a second word line decoder block in the top-view projection area. The first local bit line decoder block, the second local bit line decoder block, the first word line decoder block, and the second word line decoder block are all located within the top-view projection area.

14. The storage device according to claim 13, characterized in that, In the first direction, the sum of the first length of the first local bit line decoder block and the second length of the second local bit line decoder block is less than or equal to the length of the top-view projection area, and the projections of the first local bit line decoder block and the second local bit line decoder block in the second direction do not overlap; in the second direction, the sum of the third length of the first word line decoder block and the fourth length of the second word line decoder block is less than or equal to the width of the top-view projection area, and the projections of the first word line decoder block and the second word line decoder block in the first direction do not overlap.

15. The storage device according to claim 14, characterized in that, The first length is different from the second length; and the third length is different from the fourth length.

16. The storage device according to claim 14, characterized in that, A portion of the plurality of bit lines is electrically connected to the first local bit line decoder, and another portion of the plurality of bit lines is electrically connected to the second local bit line decoder; A portion of the multiple word lines is electrically connected to the first word line decoder, and another portion of the multiple word lines is electrically connected to the second word line decoder.

17. The storage device according to claim 14, characterized in that, In the first direction, the second word line decoder block is located between the third edge of the top-view projection area extending along the second direction and the second local bit line decoder block, and the width of the second local bit line decoder block in the second direction is less than the length of the second word line decoder block in the second direction; in the second direction, the second word line decoder block is located between the fourth edge of the top-view projection area extending along the first direction and the first local bit line decoder block, and the length of the first local bit line decoder block in the first direction is greater than the width of the second word line decoder block in the first direction.

18. The storage device according to claim 16, characterized in that, Both the first local bit line decoder and the second local bit line decoder have multiple first transmission terminals, and each first transmission terminal is electrically connected to a bit line through a first through-silicon via or a pair of first bonding pads.

19. The storage device according to claim 18, characterized in that, Both the first word line decoder and the second word line decoder have multiple second transmission terminals, and each second transmission terminal is electrically connected to a word line through a second through-silicon via or a pair of second bonding pads.

20. The storage device according to claim 18 or 19, characterized in that, The first chip includes a first bonding layer, the first bonding layer including at least one first bonding pad and / or a second bonding pad; the second chip includes a second bonding layer, the second bonding layer including at least one first bonding pad and / or a second bonding pad; the first bonding pad located on the first bonding layer is bonded to the first bonding pad located on the second bonding layer, and / or the second bonding pad located on the first bonding layer is bonded to the second bonding pad located on the second bonding layer.

21. The storage device according to claim 13, characterized in that, The top-view projection area is rectangular. The first local bit-line decoder block is located at one of the first right angles or the third right angle of the top-view projection area, and the second local bit-line decoder block is located at the other of the first right angles or the third right angle of the top-view projection area. The first word-line decoder block is located at one of the second right angles or the fourth right angle of the top-view projection area, and the second word-line decoder block is located at the other of the second right angles or the fourth right angle of the top-view projection area. Alternatively, the first local bit line decoder block is located at one of the second or fourth right angles of the top-view projection area, and the second local bit line decoder block is located at the other of the second or fourth right angles of the top-view projection area; the first word line decoder block is located at one of the first or third right angles of the top-view projection area, and the second word line decoder block is located at the other of the first or third right angles of the top-view projection area; The first right angle and the third right angle are located at the two ends of a pair of diagonals in the top-view projection area, and the second right angle and the fourth right angle are located at the two ends of the other pair of diagonals in the top-view projection area.

22. The storage device according to claim 13, characterized in that, In the first direction, the first word line decoder block is located between the left end of the second local bit line decoder block and the left end of the first local bit line decoder block. In the first direction, the second word line decoder block is located between the right end of the first local bit line decoder block and the right end of the second local bit line decoder block.

23. The storage device according to claim 13, characterized in that, In the second direction, the first local bit line decoder block is located between the upper end of the first word line decoder block and the upper end of the second word line decoder block; In the second direction, the second local bit-line decoder block is located between the lower end of the second word-line decoder block and the lower end of the first word-line decoder block.

24. The storage device according to claim 13, characterized in that, In the first direction, the length of the first local bit line decoder block and the length of the second local bit line decoder block are both less than or equal to the length of the top-view projection area; in the second direction, the first word line decoder block is located between the first local bit line decoder block and the second local bit line decoder block, and the second word line decoder block is located between the first local bit line decoder block and the second local bit line decoder block.

25. The storage device according to claim 13, characterized in that, In the second direction, the length of the first word line decoder block and the length of the second word line decoder block are both less than or equal to the width of the top-view projection area; in the first direction, the first local bit line decoder block is located between the first word line decoder block and the second word line decoder block, and the second local bit line decoder block is located between the first word line decoder block and the second word line decoder block.

Images