Semiconductor packaging structure, electronic equipment and vehicle

By designing vertically drawn power terminals and top heat dissipation structures in the semiconductor package structure, the problem of insufficient flow capacity and thermal resistance of the package structure in the prior art is solved, and more efficient current flow and heat dissipation effects are achieved, which is suitable for applications with greater power.

CN119725250APending Publication Date: 2025-03-28JINAN BYD SEMICON TECH CO LTD
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Patent Information

Application Number
CN202311269440.2
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2023-09-27
Publication Date
2025-03-28

AI Technical Summary

Technical Problem

The package structure of existing power semiconductor devices has limited flow capacity and large thermal resistance, which limits the application in higher power occasions.

Method used

A semiconductor package structure is designed in which the power terminals are drawn perpendicularly along the thickness direction of the entire device to form a single tube package structure, reducing parasitic inductance and dissipating heat through the top.

Benefits of technology

The flowability and thermal resistance performance of the semiconductor packaging structure are improved, making it suitable for applications with higher power, and the overall heat dissipation effect is improved through top heat dissipation.

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Abstract

The embodiment of the invention discloses a semiconductor packaging structure, which comprises a substrate, at least one semiconductor power chip and a source electrode power terminal, and is characterized in that the semiconductor power chip is arranged on the substrate, and the semiconductor power chip is provided with a source electrode; the source electrode power terminal is arranged on the top surface of the semiconductor power chip and is electrically connected with the source electrode, and the source electrode power terminal extends along the thickness direction of the semiconductor packaging structure and is vertically led out.
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