Semiconductor device with isolation structure and method of manufacturing semiconductor device

By forming an isolated structure and patterned metallization on the silicon layer of a high-voltage semiconductor device, the problem of difficulty in effectively controlling the internal potential and field of the device in the prior art is solved, and more efficient circuit routing and device function improvement is achieved.

CN119725279APending Publication Date: 2025-03-28INFINEON TECH AUSTRIA AG
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Patent Information

Application Number
CN202411340611.0
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Priority Date
2023-09-27
Filing Date
2024-09-25
Publication Date
2025-03-28

AI Technical Summary

Technical Problem

When the prior art optimizes the robustness, low on-resistance and breakdown voltage of a high-voltage semiconductor device, it is difficult to effectively control the potential and field inside the device, resulting in limited efficiency improvement.

Method used

By forming an isolation structure between the front and back surfaces of the silicon layer, two device areas are separated horizontally, and patterned metallization parts are provided on both sides to provide a transverse circuit path and a back bias voltage, so as to realize the combination of vertical circuit path and back circuit path.

Benefits of technology

Power and signal routing along both the front and back of the device is achieved, enhancing the functionality of the device, such as reducing leakage, improving on-current and transient operating performance, and allowing high voltage devices to be stacked for higher voltages.

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Abstract

A semiconductor device includes: a silicon layer having a thickness in a range of 2 [mu] m to 200 [mu] m between a front surface and a back surface of the silicon layer; a first device region and a second device region laterally isolated from each other in the silicon layer by an isolation structure extending from the front side to the back side of the silicon layer; a first insulating layer on the front surface of the silicon layer; a first patterned metallization on the first insulating layer; a second insulating layer on the back surface of the silicon layer; and a second patterned metallization on the second insulating layer. The first patterned metallization provides lateral routing along the front face of the silicon layer. The second patterned metallization provides lateral routing along the backside of the silicon layer. Additional embodiments of a semiconductor device and a method of manufacturing a semiconductor device are also described.
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