Semiconductor device including side interconnects
By providing side interconnection and insulation patterns on the side surface of the stacked structure of the semiconductor device, the technical problem of multi-chip parallel connection is solved, and efficient semiconductor device operation speed and high integration are achieved.
CN119725309APending Publication Date: 2025-03-28SK HYNIX INC
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Patent Information
- Application Number
- CN202410228722.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-09-26
- Filing Date
- 2024-02-29
- Publication Date
- 2025-03-28
AI Technical Summary
Technical Problem
The prior art is difficult to achieve efficient parallel connection between multiple semiconductor chips, which limits the operation speed and high integration of semiconductor devices.
Method used
By providing side interconnections on the side surface of the stack structure and providing an insulating pattern between the side interconnections and the stack structure, efficient connection between the multiple semiconductor chips is achieved.
Benefits of technology
A semiconductor device with fast operating speed and high integration is achieved, and the technical challenges of multi-chip parallel connection are solved through the design of side interconnection and insulation patterns.
✦ Generated by Eureka AI based on patent content.
Abstract
The invention relates to a semiconductor device including side interconnects. The semiconductor device may include a stacked structure having a plurality of semiconductor chips. Each of the plurality of semiconductor chips may have an interlayer insulating layer disposed on or on the substrate, a chip top interconnect disposed on or on the interlayer insulating layer, and a chip top insulating layer disposed on or on the chip top interconnect. Side interconnects disposed on or on the side surfaces of the stack structure and connected to the chip top interconnects may be provided. A plurality of insulating patterns may be disposed between the stacked structure and the side interconnects. Each of the plurality of insulating patterns may contact a side surface of the substrate of an adjacent semiconductor chip among the plurality of semiconductor chips and the interlayer insulating layer.
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