High performance microelectronic assembly including through silicon via bridging using top die last method
By interconnecting microelectronic components with multi-layer structures and conductive paths in the redistribution layer, the problem of difficult to achieve high interconnect density and signal integrity in the prior art is solved, and efficient signal transmission is achieved and manufacturing costs are reduced.
CN119725338APending Publication Date: 2025-03-28INTEL CORP
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Patent Information
- Application Number
- CN202411176255.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-09-27
- Filing Date
- 2024-08-26
- Publication Date
- 2025-03-28
AI Technical Summary
Technical Problem
Existing multi-chip IC packaging technologies are difficult to achieve high interconnect density, short wiring distances, and improved signal and power integrity, while manufacturing processes are complex and costly.
Method used
Microelectronic components adopting a multi-layer structure, including the dies of the first and second layers, each layer of die has different thicknesses and surface areas, and are interconnected through conductive paths in the redistribution layer (RDL), to achieve electrical coupling between the dies.
Benefits of technology
Improves interconnect density, reduces wiring distance, improves signal and power integrity, and reduces manufacturing complexity and cost.
✦ Generated by Eureka AI based on patent content.
Abstract
High performance microelectronic components including through silicon via bridging employing a top die last method, related devices and methods are disclosed herein. In some embodiments, a microelectronic component may include: a first layer including a first die in a first insulating material; a second layer on the first layer, the second layer comprising a second die and a third die in a second insulating material, the second die having a first thickness, the third die having a second thickness different from the first thickness, and the second die and the third die having a surface, the surfaces of the second die and the third die have a total surface area between 3000 square millimeters (mm2) and 9000 mm2; and a redistribution layer (RDL) between the first layer and the second layer, the RDL including a conductive path through the RDL, where the first die is electrically coupled to the second die and the third die through the conductive path through the RDL and through an interconnect.
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