Multilayer wiring board and method for manufacturing the same

Abstract

This invention discloses a multilayer circuit board and its manufacturing method, relating to the field of additive manufacturing technology for electronic circuits. The manufacturing method combines printing and etching processes to construct circuit patterns at different levels in the multilayer circuit board using different processes, which can effectively improve the production efficiency of the circuit board and reduce waste and pollution treatment costs.

Description

Technical Field

[0001] This invention belongs to the field of additive manufacturing technology for electronic circuits, and particularly relates to a multilayer circuit board and its manufacturing method. Background Technology

[0002] Most double-sided or multi-layer circuit boards on the market are manufactured using chemical etching technology. Although this technology is mature and can meet the requirements for producing high-precision circuit patterns, it results in low production efficiency, significant environmental pollution, and high costs for waste materials and pollution treatment. Summary of the Invention

[0003] In view of this, one objective of the present invention is to provide a method for manufacturing multilayer circuit boards, as well as double-sided circuit boards and multilayer circuit boards, thereby solving the problems of low production efficiency, high environmental pollution, and high waste material and pollution treatment costs of traditional circuit board processes.

[0004] In some illustrative embodiments, the method for manufacturing the multilayer circuit board includes: preparing a first insulating layer having a first side and a second side vertically opposite each other; forming a first printed circuit pattern on the first side of the first insulating layer using a conductive paste, and electroplating a first plated circuit pattern on the first printed circuit pattern; preparing a laminate; the laminate includes: a second insulating layer having a first side and a second side vertically opposite each other, and a metal foil layer formed on the first side of the second insulating layer; bonding the second side of the second insulating layer of the laminate with the side of the first insulating layer containing the plated circuit pattern; and forming a through-hole between the first insulating layer and the first printed circuit. The circuit pattern extends directly to the first blind hole of the first plated circuit pattern, and the second blind hole penetrates the metal foil layer and the second insulating layer to extend directly to the first plated circuit pattern; a second printed circuit pattern is formed on the second surface of the first insulating layer using conductive paste, and the first blind hole is filled to form a conductive pillar that realizes the conductive interconnection between the second printed circuit pattern and the first plated circuit pattern; the second blind hole is subjected to hole metallization treatment to obtain a metallized hole that realizes the conductive interconnection between the metal foil layer and the first plated circuit pattern; the second plated circuit pattern is formed by electroplating the second printed circuit pattern, and the metal foil layer is etched to form an etched circuit pattern.

[0005] In some alternative embodiments, the minimum line width and / or minimum line spacing of the printed circuit pattern is greater than that of the etched circuit pattern.

[0006] In some optional embodiments, the metallization process for the second blind via includes: using a stacked structure with the second printed circuit pattern and conductive pillars as a semi-process circuit board; temporarily bonding two semi-process circuit boards with the second printed circuit surface facing each other; forming a conductive carbon layer electrically connected to the metal foil layer and the first plated circuit pattern on the wall of the second blind via; and then forming a plated metal layer on the conductive carbon layer by electroplating; and separating and restoring the semi-process circuit board after electroplating is completed.

[0007] In some alternative embodiments, the metal foil layer may or may not be plated during the electroplating process.

[0008] In some optional embodiments, the step of electroplating the second printed circuit pattern to form a second plated circuit pattern includes: using the stacked structure with the second printed circuit pattern and conductive pillars as a semi-process circuit board; temporarily bonding the two semi-process circuit boards together with the surfaces of the metal foil layers; electroplating the second printed circuit pattern to form a second plated circuit pattern; and separating and restoring the semi-process circuit board after electroplating is completed.

[0009] In some alternative embodiments, the two semi-process circuit boards are temporarily bonded together by an adhesive layer; wherein the adhesive layer comprises: a first adhesive layer, a carrier layer, and a second adhesive layer stacked together; wherein the stress intensity of the carrier layer is greater than that of the first adhesive layer and / or the second adhesive layer; and the adhesion of the first adhesive layer and / or the second adhesive layer to the carrier layer is greater than its adhesion to the semi-process circuit board.

[0010] In some alternative embodiments, prior to applying the conductive paste, the method further includes: forming a base coating on the substrate of the conductive paste, the conductive paste being applied onto the base coating; wherein the base coating is used to enhance the adhesion of the conductive paste to the substrate.

[0011] Another object of the present invention is to provide a multilayer circuit board to solve the problems in the prior art.

[0012] In some illustrative embodiments, the multilayer circuit board is obtained by any of the manufacturing methods described above.

[0013] In some illustrative embodiments, the multilayer circuit board includes: a second plated circuit pattern, a second printed circuit pattern, a first insulating layer, a first printed circuit pattern, a first plated circuit pattern, a second insulating layer, and an etched circuit pattern stacked sequentially; wherein the first plated circuit pattern is formed on the first printed circuit pattern, the second plated circuit pattern is formed on the second printed circuit pattern, the first printed circuit pattern and the second printed circuit pattern are interconnected by conductive pillars penetrating the first insulating layer, and the first plated circuit pattern and the etched circuit pattern are interconnected by metallized vias penetrating the second insulating layer.

[0014] In some illustrative embodiments, a cover layer is formed on the etched circuit pattern and / or the second plated circuit pattern; wherein the cover layer covers part or all of the etched circuit pattern and / or the second plated circuit pattern; and / or, a base layer is formed between the first insulating layer and the first printed circuit pattern and / or between the first insulating layer and the second printed circuit pattern, wherein the conductive pillar penetrates the base layer; wherein the base layer is used to enhance the adhesion of the conductive paste to the first insulating layer.

[0015] Compared with the prior art, this application has the following advantages:

[0016] This invention combines printing and etching processes, which can effectively improve the production efficiency of circuit boards and reduce waste and pollution treatment costs. Attached Figure Description

[0017] Figure 1 This is a flowchart example of the circuit board manufacturing method in an embodiment of the present invention;

[0018] Figure 2 This is a process example of the circuit board manufacturing method in the embodiments of the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] It should be noted that, where there is no conflict, the various technical features in the embodiments of the present invention can be combined with each other.

[0021] This invention discloses a method for fabricating a multilayer circuit board, specifically, as follows: Figure 1-2 As shown, Figure 1 This is a flowchart example of the method for manufacturing a multilayer circuit board in an embodiment of the present invention; Figure 2 This is a process example of a method for manufacturing a multilayer circuit board according to an embodiment of the present invention. The method for manufacturing this multilayer circuit board includes:

[0022] Step S11: Prepare the first insulating layer 110;

[0023] The first insulation layer can be made of rigid board or flexible board. Rigid board includes, but is not limited to: FR-4, CEM-1, 22F, CEM-3, wood, glass, plastic, PMMA (acrylic), etc.; flexible board includes, but is not limited to: PET, PVC, PU, ​​PC, PP, PA, PI, CPI (transparent PI), TPE, TPU, TPV, etc.

[0024] Step S12: A first printed circuit pattern 310 is formed on the first surface of the first insulating layer 110 using conductive paste.

[0025] The printing processes used in the embodiments of the present invention include, but are not limited to, screen printing, direct writing printing, inkjet printing, etc.

[0026] The conductive paste in this embodiment of the invention refers to a composite low-temperature conductive paste mainly composed of conductive fillers, resin binders and solvents. After the paste is fully cured, the solvent will evaporate, thereby transforming it into a conductive film in which the conductive fillers are bound by the resin film-forming material.

[0027] The conductive filler is not limited to one or more of the following: metal particles, graphene, conductive carbon black, carbon nanotubes, and conductive particles with core-shell structures; the metal particles are not limited to one or more of the following: gold, silver, copper, iron, nickel, zinc, and silver-coated copper powder; the resin binder may be any commercially available resin, including but not limited to one or more of the following: epoxy resin, acrylic resin, naphthalene-containing epoxy resin, polyaromatic epoxy resin, multifunctional epoxy resin, bismaleimide resin, and polyimide resin. This application does not restrict the selection of solvents.

[0028] The curing method of the conductive paste in the embodiments of the present invention is not limited to thermosetting, photocuring, electromagnetic irradiation or other curing methods.

[0029] Step S13: Electroplating is performed on the first printed circuit pattern 310 to form a first plated circuit pattern 410;

[0030] The primary function of the first plated circuit pattern is to improve one or more of the following properties of the printed circuit pattern: conductivity, stability, solderability, oxidation resistance, and surface properties.

[0031] In some embodiments, the plated metal includes, but is not limited to, gold, silver, copper, iron, aluminum, zinc, nickel, etc.

[0032] Step S14: Prepare a layer of stacked material;

[0033] The laminate includes: a second insulating layer 120 having a first surface and a second surface that are vertically opposite each other, and a metal foil layer 210 formed on the first surface of the second insulating layer;

[0034] The second insulating layer can be made of rigid board or flexible board. Rigid board includes, but is not limited to: FR-4, CEM-1, 22F, CEM-3, wood, glass, plastic, PMMA (acrylic), etc.; flexible board includes, but is not limited to: PET, PVC, PU, ​​PC, PP, PA, PI, CPI (transparent PI), TPE, TPU, TPV, etc.

[0035] The metal foil layer includes, but is not limited to, gold, silver, copper, iron, aluminum, zinc, and nickel. The metal foil layer may also include conductive alloy materials with the aforementioned materials as their main components.

[0036] The metal foil layer can be formed on the insulating layer by means of lamination or deposition (chemical deposition, vapor deposition or sputtering), and the present invention does not limit this.

[0037] Step S15: The second surface of the second insulating layer 120 of the laminate is bonded to the surface of the first plated circuit pattern 410 on the first insulating layer 110.

[0038] Alternatively, the two can be bonded together using adhesive layer 810.

[0039] Step S16: Open a first blind hole that penetrates the first insulating layer 110 and the first printed circuit pattern 310 and reaches the first plated circuit pattern 410, and open a second blind hole that penetrates the metal foil layer 210 and the second insulating layer 120 and reaches the first plated circuit pattern 410.

[0040] The first blind via and / or the second blind via are not limited to being achieved by mechanical drilling or laser drilling. Specifically, they can be etched from the second side of the first insulating layer / second insulating layer until the first plated circuit pattern is etched.

[0041] Optionally, after the first blind hole and / or the second blind hole are processed, the process may further include: using a plasma generator to clean the inside of the blind hole, thereby removing the residual first insulating layer and / or second insulating layer, exposing the complete metal surface at the bottom of the blind hole as much as possible, so as to improve the reliability of subsequent conductive interconnection and reduce contact resistance.

[0042] Preferably, the temperature of the first insulating layer and / or the second insulating layer can be controlled to reach the glass transition temperature of the material, and then surface treatment can be performed by plasma, which can effectively improve the removal effect of residual impurities.

[0043] Step S17: A second printed circuit pattern 320 is formed on the second surface of the first insulating layer 110 using conductive paste, and the first blind hole is filled to form a conductive post 510 that realizes the conductive interconnection between the second printed circuit pattern 320 and the first plated circuit pattern 410.

[0044] The second printed circuit pattern and the conductive pillar can be formed in one printing operation or separately through multiple printing operations; this application does not impose any limitation on this. Furthermore, in embodiments where they are formed separately, the forming order of the conductive pillar and the second printed circuit pattern can be reversed, depending on actual needs; this application does not impose any limitation on this.

[0045] The printing processes used in the embodiments of the present invention include, but are not limited to, screen printing, direct writing printing, inkjet printing, etc.

[0046] Preferably, in embodiments employing screen printing technology, the second printed circuit pattern and conductive pillars can be formed separately through two printing processes, with different control parameters for each printing process to meet the forming quality requirements of surface molding and hole plugging.

[0047] Step S18: Perform hole metallization treatment on the second blind hole to obtain a metallized hole that realizes the conductive interconnection between the metal foil layer 210 and the first plated circuit pattern 410.

[0048] Optionally, a conductive carbon layer 515 electrically connected to the metal foil layer 210 and the first plated circuit pattern 410 is formed on the wall of the second blind hole, and then a plated metal layer 520 (wherein the plated metal layer is not limited to the hole wall metal or the columnar structure that fills the blind hole) is formed by electroplating on the conductive carbon layer 515, thereby forming a metallized hole.

[0049] Specifically, this involves forming a conductive carbon layer electrically connected to the metal foil layer and the second metal foil layer on the wall of the second blind hole, and then forming a plated metal layer on the conductive carbon layer by electroplating. The conductive carbon layer is not limited to conductive carbon black or conductive graphite, and is not limited to being formed through black hole or shadow treatment. In other embodiments, the conductive carbon layer can also be formed by methods such as laser carbon implantation (laser ablation to form a surface carbon layer).

[0050] The metal foil layer may or may not undergo surface plating during the electroplating process. This depends on the thickness of the metal foil layer and the raw material, as well as the target thickness of the etched circuit pattern. If surface plating is not required, a metal foil layer can be used for masking.

[0051] Step S19: Electroplating the second printed circuit pattern 320 to form a second plated circuit pattern 420, and etching the metal foil layer 210 to form an etched circuit pattern 210E.

[0052] The order of forming the second plated circuit pattern and the etched circuit pattern in this step can be reversed, and this application does not impose any restrictions on this.

[0053] In some embodiments, the process of forming a metallized hole in step S18 may include:

[0054] The stacked structure with the second printed circuit pattern 320 and conductive pillar 510 formed thereon is used as a half-process circuit board. The two half-process circuit boards are temporarily bonded together with the surface where the second printed circuit pattern 320 is located. The temporary bonding can be achieved by the adhesive layer 820.

[0055] A conductive carbon layer 515 is formed on the wall of the second blind hole, which is electrically connected to the metal foil layer 210 and the first plated circuit pattern 410, and then a plated metal layer 520 is formed on the conductive carbon layer 515 by electroplating.

[0056] After electroplating is completed, the semi-process circuit board is separated and restored.

[0057] In some embodiments, the process of electroplating to form a second plated circuit pattern on the second printed circuit pattern in step S19 may include:

[0058] The stacked structure with the second printed circuit pattern 320 and conductive pillar 510 is used as a semi-process circuit board. The two semi-process circuit boards are temporarily bonded together with the surface of the metal foil layer 210. This temporary bonding can be achieved by the adhesive layer 830.

[0059] A second plated circuit pattern 420 is formed by electroplating the second printed circuit pattern 320;

[0060] After electroplating is completed, the semi-process circuit board is separated and restored.

[0061] In some embodiments, temporary bonding of two semi-process circuit boards can be achieved by an adhesive layer (820 and / or 830); wherein the adhesive layer comprises: a first adhesive layer, a carrier layer and a second adhesive layer stacked together; wherein the stress intensity of the carrier layer is greater than that of the first adhesive layer and / or the second adhesive layer; and the adhesion of the first adhesive layer and / or the second adhesive layer to the carrier layer is greater than its adhesion to the semi-process circuit board.

[0062] By designing the carrier layer and double-sided adhesive layer, as well as their mutual adhesion, the problem of the single adhesive layer being difficult to remove is solved, making the adhesive layer easy to peel off. On the other hand, the addition of a carrier layer with a certain structural strength helps to reduce air bubbles between the adhesive bonding surfaces, making the bonding surfaces tighter and preventing the plating solution from leaking and causing undesirable plating on the metal foil surface.

[0063] The carrier layer includes, but is not limited to, non-adhesive flexible boards or rigid boards.

[0064] In some embodiments, before applying the conductive paste, the method further includes: forming a base coating on the substrate of the conductive paste, the conductive paste being applied on the base coating; wherein the base coating is used to enhance the adhesion of the conductive paste to the substrate.

[0065] The base coating includes, but is not limited to, a first base coating 710 between the first insulating layer 110 and the first printed circuit pattern 310 and / or a second base coating 720 between the first insulating layer 110 and the second printed circuit pattern 320.

[0066] The applicant discovered that the higher density and precision of double-sided / multi-layer circuit boards currently on the market can be achieved using only one or a few layers of two or more circuit boards, instead of designing all of them as higher precision circuits. Therefore, the circuits with higher precision requirements (i.e., the circuits occupying more actual area within a specified range) can be achieved using traditional etching processes, while the circuits of other layers can be achieved using printing processes with relatively lower precision.

[0067] Furthermore, since the etching is performed on the side with a higher density of deposits, the actual amount of metal foil etched is greatly reduced. This effectively reduces waste costs and pollution treatment costs while ensuring quality.

[0068] In some embodiments of the present invention, the minimum line width and / or minimum line spacing of the first printed circuit pattern is greater than that of the etched circuit pattern.

[0069] In some embodiments, the density of the printed circuit pattern on the insulating layer is less than that of the etched circuit pattern.

[0070] Optionally, the minimum line spacing and / or minimum line width of the etched circuit pattern can range from 1 to 100 μm, while the minimum line spacing and / or minimum line width of the printed circuit pattern can range from 2 to 200 μm.

[0071] Those skilled in the art should understand that, although the two ranges overlap, the minimum line spacing and / or minimum line width of the etched circuit pattern can be selected as needed, and the actual parameters should be smaller than the minimum line spacing and / or minimum line width of the printed circuit pattern.

[0072] This invention discloses a multilayer circuit board, which can be obtained by any of the manufacturing methods described above.

[0073] This invention discloses a multilayer circuit board, comprising: a second plated circuit pattern 420, a second printed circuit pattern 320, a first insulating layer 110, a first printed circuit pattern 310, a first plated circuit pattern 410, a second insulating layer 120, and an etched circuit pattern 210E, which are stacked sequentially. The first plated circuit pattern 410 is formed on the first printed circuit pattern 310, the second plated circuit pattern 420 is formed on the second printed circuit pattern 320, the first printed circuit pattern 310 and the second printed circuit pattern 320 are interconnected by conductive posts 510 penetrating the first insulating layer 110, and the first plated circuit pattern 410 and the etched circuit pattern 210E are interconnected by metallized vias penetrating the second insulating layer 120.

[0074] In some embodiments, a cover layer is formed on the etched circuit pattern and / or the second plated circuit pattern; wherein the cover layer covers part or all of the etched circuit pattern and / or the second plated circuit pattern.

[0075] In some embodiments, a base coating is formed between the first insulating layer and the first printed circuit pattern and / or between the first insulating layer and the second printed circuit pattern, and the conductive pillar penetrates the base coating; wherein the base coating is used to enhance the adhesion of the conductive paste to the first insulating layer.

[0076] The base coating includes, but is not limited to, a first base coating 710 between the first insulating layer 110 and the first printed circuit pattern 310 and / or a second base coating 720 between the first insulating layer 110 and the second printed circuit pattern 320.

[0077] In some embodiments of the present invention, the minimum line width and / or minimum line spacing of the first printed circuit pattern is greater than that of the etched circuit pattern.

[0078] In some embodiments, the density of the printed circuit pattern on the insulating layer is less than that of the etched circuit pattern.

[0079] Optionally, the minimum line spacing and / or minimum line width of the etched circuit pattern can range from 1 to 100 μm, while the minimum line spacing and / or minimum line width of the printed circuit pattern can range from 2 to 200 μm.

[0080] Those skilled in the art should understand that, although the two ranges overlap, the minimum line spacing and / or minimum line width of the etched circuit pattern can be selected as needed, and the actual parameters should be smaller than the minimum line spacing and / or minimum line width of the printed circuit pattern.

[0081] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a multilayer circuit board, characterized in that, include: Prepare a first insulating layer, having a first and a second surface that are vertically opposite each other; A first printed circuit pattern is formed on a first surface of the first insulating layer using a conductive paste, and a first plated circuit pattern is formed by electroplating on the first printed circuit pattern. Prepare a layer of stacked material; The laminate includes: a second insulating layer having a first surface and a second surface that are vertically opposite each other, and a metal foil layer formed on the first surface of the second insulating layer; The second surface of the second insulating layer of the laminate is bonded to the surface of the first insulating layer where the first plated circuit pattern is located. A first blind hole is formed that penetrates the first insulating layer and the first printed circuit pattern and reaches the first plated circuit pattern, and a second blind hole is formed that penetrates the metal foil layer and the second insulating layer and reaches the first plated circuit pattern. A second printed circuit pattern is formed on the second surface of the first insulating layer using conductive paste, and the first blind hole is filled to form a conductive pillar that realizes the conductive interconnection between the second printed circuit pattern and the first plated circuit pattern. The second blind via is subjected to a via metallization process to obtain a metallized via that enables conductive interconnection between the metal foil layer and the first plated circuit pattern. The second printed circuit pattern is electroplated to form a second plated circuit pattern, and the metal foil layer is etched to form an etched circuit pattern.

2. The production method according to claim 1, wherein The minimum line width and / or minimum line spacing of the printed circuit pattern is greater than that of the etched circuit pattern.

3. The method of making of claim 1, wherein, The process of metallizing the second blind hole includes: The stacked structure with the second printed circuit pattern and conductive pillars is used as a half-process circuit board, and the two half-process circuit boards are temporarily bonded together with the surface where the second printed circuit pattern is located. A conductive carbon layer electrically connected to the metal foil layer and the first plated circuit pattern is formed on the hole wall of the second blind hole, and then a plated metal layer is formed on the conductive carbon layer by electroplating. After electroplating is completed, the semi-process circuit board is separated and restored.

4. The production method according to claim 1 or 3, characterized by, The metal foil layer may or may not be plated during the electroplating process.

5. The method of making of claim 1, wherein, The process of electroplating the second printed circuit pattern to form the second plated circuit pattern includes: The stacked structure with the second printed circuit pattern and conductive pillars is used as a half-process circuit board, and the two half-process circuit boards are temporarily bonded together with the metal foil layer on the side. A second plated circuit pattern is formed by electroplating the second printed circuit pattern; After electroplating is completed, the semi-process circuit board is separated and restored.

6. The production method according to claim 3 or 5, characterized by, The two semi-process circuit boards are temporarily bonded together by an adhesive layer; wherein the adhesive layer comprises: a first adhesive layer, a carrier layer and a second adhesive layer stacked together; wherein the stress strength of the carrier layer is greater than that of the first adhesive layer and / or the second adhesive layer; and the adhesion of the first adhesive layer and / or the second adhesive layer to the carrier layer is greater than its adhesion to the semi-process circuit board.

7. The method of making of claim 1, wherein, Before applying the conductive paste, the method further includes: forming a base coating on the substrate of the conductive paste, and applying the conductive paste onto the base coating; wherein the base coating is used to improve the adhesion of the conductive paste to the substrate.

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