FPC prevents large impedance via structure

Abstract

The utility model discloses a kind of via hole structures of FPC preventing big impedance, belong to FPC board via hole field, a kind of via hole structure of FPC preventing big impedance, including FPC board, A line upper end, A line lower end, K line upper end, K line lower end are equipped on the FPC board, the A line upper end, K line upper end terminal are equipped with double via hole, the A line upper end is electrically connected with A line lower end by double via hole, the K line upper end is electrically connected with K line lower end by double via hole, wherein double via hole is specifically two via hole compositions, via hole outer diameter is specifically 0.5mm, via hole inner diameter is specifically 0.25mm, the hole spacing between two via holes is specifically 0.3mm;The utility model has the advantages of prior art in that: the number of via hole in the structure of FPC is increased to 2, avoid the risk of abnormal function caused by big impedance, reduce the burnout generated in the use process of product due to the via hole process problem of supplier, eliminate the negative influence caused by after-sales function bad, greatly reduce after-sales cost.

Description

Technical Field

[0001] This utility model belongs to the field of FPC board via technology, specifically relating to an FPC via structure to prevent high impedance. Background Technology

[0002] In the display module industry, display malfunctions are frequently encountered after sales due to via cracks in the vias of multilayer FPC boards, leading to increased impedance and eventual burnout. Currently, LCD screen FPCs on the market consist of two layers of circuitry, with some having four layers. The line width is typically 0.2mm, and the circuitry between the upper and lower layers is connected vias. Because some power lines in the FPC draw large currents (e.g., A-line, K-line), even with a wide line width, via cracks or thin walls due to supplier manufacturing processes can increase impedance, reduce current capacity, and cause malfunctions. This defect poses a significant risk to sold LCD screens, resulting in substantial after-sales costs and brand damage. This patent introduces a via design to prevent current overload, greatly avoiding after-sales malfunctions caused by FPC via damage. Utility Model Content

[0003] The purpose of this invention is to provide an FPC via structure that prevents high impedance, so as to solve the problems mentioned in the background art.

[0004] To achieve the above objectives, this utility model provides the following technical solution: a via structure for preventing high impedance in an FPC, comprising an FPC board, wherein the FPC board is provided with an upper end of line A, a lower end of line A, an upper end of line K, and a lower end of line K. Both the upper end of line A and the upper end of line K are provided with double vias. The upper end of line A is electrically connected to the lower end of line A through the double vias, and the upper end of line K is electrically connected to the lower end of line K through the double vias. Specifically, the double vias consist of two vias, with an outer diameter of 0.5 mm, an inner diameter of 0.25 mm, and a spacing of 0.3 mm between the two vias.

[0005] The technical effects and advantages of this utility model are as follows: This structure increases the number of vias in the FPC to two, which avoids the risk of functional abnormalities caused by high impedance, reduces the risk of product burnout during use due to supplier via process problems, eliminates the negative impact of poor after-sales function, and greatly reduces after-sales costs. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of the traditional via structure;

[0007] Figure 2 This is a schematic diagram of the through-hole structure of this utility model.

[0008] In the diagram: 101, FPC board; 102, upper end of line A; 103, lower end of line A; 104, upper end of line K; 105, lower end of line K; 106, single via; 107, double via. Detailed Implementation

[0009] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0010] This utility model provides, for example Figure 1-2 The FPC shown is a via structure to prevent high impedance, including an FPC board 101;

[0011] Specifically, the FPC board 101 is provided with an upper A-line 102, a lower A-line 103, an upper K-line 104, and a lower K-line 105. The upper A-line 102 and the upper K-line 104 are each provided with a double via 107. The upper A-line 102 is electrically connected to the lower A-line 103 through the double via 107, and the upper K-line 104 is electrically connected to the lower K-line 105 through the double via 107. The double via 107 is composed of two vias with an outer diameter of 0.5 mm, an inner diameter of 0.25 mm, and a spacing of 0.3 mm between the two vias. Example

[0012] Traditional FPC boards typically use single vias, suitable for most circuits. However, some circuits on a single FPC may experience high current draw during operation, leading to increased impedance and burnout during conduction due to the single via 106. This patent addresses this by increasing the number of vias on the high-current A and K lines to two, i.e., double vias 107. This avoids the risk of functional abnormalities caused by high impedance, reduces product burnout caused by supplier via manufacturing defects, eliminates the negative impact of after-sales malfunctions, and significantly reduces after-sales costs.

[0013] Finally, it should be noted that the above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Although the present utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. An FPC structure for preventing vias with high impedance, comprising an FPC board (101), characterized in that: The FPC board (101) is provided with an upper end (102) of line A, an lower end (103) of line A, an upper end (104) of line K, and an lower end (105) of line K. The upper end (102) of line A and the upper end (104) of line K are both provided with double vias (107). The upper end (102) of line A is electrically connected to the lower end (103) of line A through the double vias (107), and the upper end (104) of line K is electrically connected to the lower end (105) of line K through the double vias (107). The double vias (107) are specifically composed of two vias with an outer diameter of 0.5 mm, an inner diameter of 0.25 mm, and a spacing of 0.3 mm between the two vias.

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