Computational acceleration system, method, medium and product suitable for decryption

Abstract

The present application provides a computing acceleration system, method, medium and product suitable for decryption, which divides the cracking task through the main controller, and configures the instruction storage space, data storage space and interconnection mode between each Tile unit in the reconfigurable computing array of the on-chip acceleration device according to the task requirements, realizes the precise allocation of computing resources, avoids the idleness of high-performance hardware resources, reduces power consumption, and enables the system to support multiple encryption algorithms through the configuration of the on-chip acceleration device, thereby providing computing acceleration for multiple encryption algorithms, improving its versatility and application scope, and solving the problem of single support for existing decryption structure algorithms. The main controller efficiently controls the reconfigurable computing array, realizes parallel control and data scheduling of large-scale computing cores, and improves computing efficiency and flexibility.

Description

Technical Field

[0001] The present application relates to the technical field of password cracking, and in particular to a computing acceleration system, method, medium and product suitable for decryption. Background Art

[0002] With the rapid development of information technology, data security and privacy protection have become an indispensable part of modern society. As the most basic means of identity authentication, text passwords play a vital role in various information systems and daily applications. However, due to human habits and tendencies in using passwords, text passwords often have certain regularities and predictability, which makes them vulnerable to various attacks, especially brute force attacks.

[0003] Brute force attack is a method of trying all possible password combinations to find the correct password. One common attack method is to use high-performance hardware to implement brute force cracking using methods such as masks, rules, and dictionaries. For example, a GPU (graphics processing unit) or a high-performance cluster composed of multiple GPUs (graphics processing units) is used to implement brute force cracking of the target password. With its powerful parallel computing capabilities, GPU can try a large number of password combinations in a short period of time, making it a common tool in brute force cracking attacks. However, GPU is not designed specifically for encryption applications. Its rich internal floating-point computing units and large storage space are often not fully utilized in encryption algorithms, resulting in idle resources, increased power consumption, and reduced energy efficiency, making GPU not the most ideal acceleration platform. Therefore, how to more efficiently accelerate the decryption process, especially the computational acceleration of encryption algorithms, has become a hot topic in current research.

[0004] In order to meet this challenge, researchers began to explore more efficient decryption acceleration technologies. Some researchers proposed a document-oriented password decryption acceleration structure based on FPGA chips. By designing a dedicated accelerator with configurable calculation rounds for SHA1 and executing the symmetric algorithm part on the embedded CPU, it supports a variety of document encryption algorithms. However, the versatility of this structure is limited and it can only support specific types of encryption algorithms, such as document algorithms with SHA1 as a key derivation function, which limits its wide applicability in practical applications.

[0005] In order to further improve the acceleration effect of the algorithm, the researchers also designed a dedicated FPGA decryption structure for specific encryption algorithms. For example, for the RAR3 compression algorithm, the researchers proposed a dual-data granularity data path adaptive structure to solve the problem of uncertain input sources of the hash function in the key derivation function of the RAR3 encryption algorithm under different rounds and different input password lengths. However, the limitation of this structure is that it only supports the RAR3 algorithm and cannot provide computational acceleration for other encryption algorithms.

[0006] In order to support a variety of encryption algorithms, researchers began to explore acceleration structures based on reconfigurable computing arrays (CGRA). As a typical CGRA design, the Anole structure supports common hash algorithms and symmetric encryption algorithms by adopting distributed control networks, instruction configuration and computing parallel execution technology, and instruction compression methods. However, the Anole structure is not designed specifically for the field of decryption, but for normal encryption applications. Therefore, the Anole structure still has certain limitations in terms of parallel control and data scheduling for large-scale computing cores.

[0007] In order to combine the advantages of GPU and ASIC, researchers have also proposed a GPU+ASIC heterogeneous acceleration solution. This solution uses the flexibility of GPU and the high performance of ASIC to achieve support for a wider range of encryption algorithms. However, when faced with complex encryption algorithms that are beyond the support range of ASIC, the system performance of this solution often performs poorly. Summary of the invention

[0008] In view of the shortcomings of the prior art described above, the purpose of the present application is to provide a computing acceleration system, method, medium and product suitable for decryption, which is used to solve the technical problems existing in the existing decryption acceleration technology, such as insufficient resource utilization, limited versatility, and single algorithm support.

[0009] To achieve the above-mentioned purpose and other related purposes, the first aspect of the present application provides a computing acceleration system suitable for decryption, including: an off-chip control device and an on-chip acceleration device communicatively connected to the off-chip control device; the off-chip control device includes a main controller, and the main controller is communicatively connected to the on-chip acceleration device; the on-chip acceleration device includes a reconfigurable computing array composed of multiple Tile units; the main controller is used to perform the following: divide the cracking tasks according to the encryption algorithm adopted by the secret string file to be cracked; configure the on-chip acceleration device according to the requirements of each sub-cracking task after the task division, and the configuration content includes instruction storage space, data storage space and the interconnection method between each Tile unit in the reconfigurable computing array; control the reconfigurable computing array to attack the secret string file to be cracked, and collect the corresponding cracking results; accept the collected cracking results and output them.

[0010] In some embodiments of the first aspect of the present application, the off-chip control device also includes an off-chip memory communicatively connected to the main controller; the off-chip memory includes an instruction storage area and a data storage area; wherein, the method of dividing the cracking task according to the encryption algorithm adopted by the secret string file to be cracked includes: compiling the encryption algorithm adopted by the secret string file to be cracked to obtain the instruction file required to attack the secret string file to be cracked, and storing the instruction file in the instruction storage area of ​​the off-chip memory; setting a total attack mask according to the secret string file to be cracked and the instruction file; dividing the cracking task into several sub-cracking tasks according to the total attack mask and based on the scale of the reconfigurable computing array; performing data conversion on each of the sub-cracking tasks, and storing each of the sub-cracking tasks and the secret string file to be cracked after data conversion in the data storage area of ​​the off-chip memory.

[0011] In some embodiments of the first aspect of the present application, the on-chip acceleration device also includes an instruction distribution unit, a data distribution unit and a control unit; the main controller performs initialization operations on the instruction distribution unit and the data distribution unit through the control unit to configure the instruction storage space and data storage space of the on-chip acceleration device, and the method includes: configuring the address of each instruction block in the instruction file in the instruction storage area in the instruction distribution unit, and configuring the address of each sub-cracking task after data conversion and the encrypted string file to be cracked in the data storage area in the data distribution unit; wherein, the instruction file includes multiple instruction blocks.

[0012] In some embodiments of the first aspect of the present application, each Tile unit includes a shared memory and an instruction processing array composed of a plurality of PE units; and the method of controlling the reconfigurable computing array to attack the secret string file to be cracked includes:

[0013] In response to a configuration completion signal, causing the control unit to start the reconfigurable computing array;

[0014] The control unit sends an execution instruction signal to make the instruction distribution unit read the instruction block in the instruction file from the off-chip memory; and make the data distribution unit read the sub-cracking task and the data in the secret string file to be cracked after the data conversion associated with the instruction block from the off-chip memory, and store them in the shared memory;

[0015] The instruction distribution unit broadcasts each instruction in the instruction block read to each Tile unit in a one-by-one distribution manner; wherein each instruction block includes multiple instructions;

[0016] Each Tile unit decodes the received instruction, and reads the sub-cracking task after data conversion and the data in the secret string file to be cracked required to execute the corresponding instruction operation from the shared memory according to the decoding result of the instruction, so that the instruction processing array in each Tile unit can execute the corresponding instruction operation;

[0017] Repeat the above-mentioned processes of reading instruction blocks, broadcasting instructions, decoding, reading data, and executing instruction operations until all instruction blocks in the instruction file are executed, and collect the cracking results corresponding to the secret string file to be cracked.

[0018] In some embodiments of the first aspect of the present application, each Tile unit also includes an instruction cache unit, an instruction decoding unit, and an address generation unit; the instruction cache unit is used to store the instructions received by the Tile unit, and send the stored instructions to the instruction decoding unit; the instruction decoding unit is used to decode the sent instructions to obtain the instruction operation type and instruction operands; the address generation unit is used to generate the address of the data required for the instruction processing array to execute the corresponding instruction operation according to the instruction operation type and instruction operands.

[0019] In some embodiments of the first aspect of the present application, each PE unit includes a function unit for calculating different encryption algorithms; the function unit includes an arithmetic logic module and a number of bit operation modules, and the bit operation module includes a Galois field GFx2 operation module, a DES initial permutation module, a DES key transformation module, a DES extended transformation module, a DES permutation module, and a DES function module. One or more combinations of these modules.

[0020] In some embodiments of the first aspect of the present application, the off-chip control device also includes a configuration buffer that is communicatively connected to the main controller, and the main controller configures the interconnection method between each Tile unit in the reconfigurable computing array through the configuration buffer.

[0021] To achieve the above-mentioned purpose and other related purposes, the second aspect of the present application provides a computing acceleration method suitable for decryption, which is applied to the computing acceleration system suitable for decryption as described above, wherein the computing acceleration system suitable for decryption includes an off-chip control device and an on-chip acceleration device communicatively connected to the off-chip control device; the computing acceleration method suitable for decryption includes: dividing the cracking tasks according to the encryption algorithm adopted by the secret string file to be cracked; configuring the on-chip acceleration device according to the requirements of each sub-cracking task after the task division, and the configuration content includes instruction storage space, data storage space and the interconnection method between each Title unit in the reconfigurable computing array; controlling the reconfigurable computing array to attack the secret string file to be cracked, and collecting the corresponding cracking results; accepting the collected cracking results and outputting them.

[0022] To achieve the above-mentioned purpose and other related purposes, the third aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the computing acceleration method suitable for decryption as described above.

[0023] To achieve the above-mentioned purpose and other related purposes, the fourth aspect of the present application provides a computer program product, which includes a computer program code. When the computer program code runs on a computer, the computer implements the computing acceleration method suitable for decryption as described above.

[0024] As described above, the computing acceleration system, method, medium and product suitable for decryption in the present application have the following beneficial effects: the cracking task is divided by the main controller, and the instruction storage space, data storage space and interconnection mode between each Tile unit in the reconfigurable computing array of the on-chip acceleration device are configured according to the task requirements, so as to realize the accurate allocation of computing resources, avoid the idleness of high-performance hardware resources, reduce power consumption, and enable the system to support multiple encryption algorithms through the configuration of the on-chip acceleration device, thereby providing computing acceleration for multiple encryption algorithms, improving its versatility and application scope, and solving the problem of single support for existing decryption structure algorithm. The reconfigurable computing array is efficiently controlled by the main controller, and the parallel control and data scheduling of large-scale computing cores are realized, which improves the computing efficiency and flexibility. Furthermore, the present invention combines the off-chip control device and the on-chip acceleration device to form an efficient heterogeneous acceleration scheme, so that the system can show better performance when facing complex encryption algorithms. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 Shown is a schematic diagram of the structure of a computing acceleration system suitable for decryption in one embodiment of the present application.

[0026] Figure 2 Shown is a schematic diagram of the structure of a Tile unit in one embodiment of the present application.

[0027] Figure 3 Shown is a schematic diagram of the process of attacking a secret string file to be cracked in one embodiment of the present application.

[0028] Figure 4 Shown is a schematic diagram of the structure of a function unit in a PE unit in an embodiment of the present application.

[0029] Figure 5 Shown is a flowchart of a computing acceleration method suitable for decryption in one embodiment of the present application. DETAILED DESCRIPTION

[0030] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0031] Before further describing the present invention in detail, the nouns and terms involved in the embodiments of the present invention are explained. The nouns and terms involved in the embodiments of the present invention are applicable to the following interpretations:

[0032] <1> GPU (Graphics Processing Unit): A graphics processor is a microprocessor that is specifically designed to perform graphics rendering tasks on personal computers, workstations, game consoles, and some mobile devices (such as tablets, smartphones, etc.).

[0033] <2> FPGA (Field-Programmable Gate Array): Field-Programmable Gate Array is an integrated circuit chip (IC) with a programmable logic gate array and programmable internal connections.

[0034] <3> SHA1 hash algorithm (Secure Hash Algorithm 1): that is, Secure Hash Algorithm 1, whose working principle is based on a series of complex mathematical operations, mainly including modulus operations, bit shift operations, XOR operations, etc.

[0035] <4> CPU (Central Processing Unit): The central processing unit is the core component of the computer system, responsible for executing instructions in the program and processing data.

[0036] <5> RAR: is a lossless data compression file format and associated compression algorithm, which is popular among users for its high compression rate and password protection. RAR3 refers to the third version of the RAR compression algorithm, which is a type of RAR file format.

[0037] <6> CGRA (Coarse-Grained Reconfigurable Array): Coarse-grained reconfigurable array is an important form of reconfigurable computing architecture. Its technical principle is mainly based on its unique hardware structure and configuration mechanism.

[0038] <7> Anole structure: is a typical reconfigurable computing array (CGRA) design, which aims to accelerate various computing tasks through a highly flexible and configurable hardware architecture, combining coarse-grained reconfigurability and highly flexible configuration capabilities to provide efficient computing acceleration.

[0039] <8> ASIC (Application-Specific Integrated Circuit): An application-specific integrated circuit is an integrated circuit customized for a specific application.

[0040] <9> DES (Data Encryption Standard): It is a block encryption algorithm, which encrypts the plaintext in groups, taking a part of the plaintext in sequence each time.

[0041] <10> AES (Advanced Encryption Standard): is a symmetric encryption algorithm widely used in data encryption.

[0042] <11> Hashcat: is an open source tool for password cracking, known for its powerful password cracking capabilities and multiple attack modes. It uses the parallel computing power of GPU to significantly increase the speed of password cracking.

[0043] <12> MD5 (Message-Digest Algorithm 5): is a widely used cryptographic hash function used to generate message digests of data to ensure the integrity and authenticity of the data.

[0044] <13> SHA2-256 (Secure Hash Algorithm 2256-bit): An algorithm subdivided from Secure Hash Algorithm 2. It is a method of creating a small digital "fingerprint" from any kind of data. It compresses the message or data into a summary, making the data size smaller and fixing the format of the data.

[0045] <14> GPU Tesla V100: is a Volta architecture GPU.

[0046] <15> Volta architecture: is the sixth generation architecture of NVIDIA GPU.

[0047] The existing text password encryption and decryption acceleration technology has the following technical problems:

[0048] (1) Insufficient resource utilization: Although high-performance hardware such as GPU has powerful computing capabilities, it was not originally designed for encryption applications. Therefore, when executing encryption algorithms, its rich floating-point computing resources and storage resources are often not fully utilized, resulting in idle resources and increased power consumption.

[0049] (2) Limited versatility: Although the FPGA-based dedicated encryption algorithm acceleration structure can significantly improve the computational efficiency of specific algorithms, its versatility is relatively poor. For example, the document-oriented password decryption acceleration structure only supports specific types of encryption algorithms such as SHA1, which limits its application in other types of encryption algorithms.

[0050] (3) Single algorithm support: FPGA decryption structure designed for specific encryption algorithms, such as the dedicated structure for RAR3 compression algorithm, can solve specific problems but cannot provide computing acceleration for other encryption algorithms, limiting its scope of application.

[0051] (4) Limitations of parallel control and data scheduling: Although acceleration structures based on reconfigurable computing arrays (CGRAs), such as the Anole structure, can support a variety of encryption algorithms, they still have limitations in parallel control and data scheduling for large-scale computing cores, which affects their computing efficiency and flexibility.

[0052] (5) Performance bottleneck of heterogeneous acceleration solutions: Although the GPU+ASIC heterogeneous acceleration solution combines the flexibility of GPU and the high performance of ASIC, when faced with complex encryption algorithms that exceed the support range of ASIC, the system performance is often poor, which limits its widespread application.

[0053] In summary, the current text password encryption and decryption acceleration technology faces many technical problems such as insufficient resource utilization, limited versatility, single algorithm support, limitations of parallel control and data scheduling, and performance bottlenecks of heterogeneous acceleration solutions.

[0054] In order to solve the problems in the above-mentioned background technology, the present application provides a computing acceleration system, method, medium and product suitable for decryption, which is used to solve the technical problems existing in the existing decryption acceleration technology, such as insufficient resource utilization, limited versatility, and single algorithm support.

[0055] To facilitate understanding of the embodiments of the present application, first Figure 1 Detailed description. Figure 1 The schematic diagram of the structure of the computing acceleration system suitable for decryption in the embodiment of the present invention is shown. The computing acceleration system suitable for decryption in the embodiment mainly includes: an off-chip control device 1 and an on-chip acceleration device 2 which is connected to the off-chip control device in communication; the off-chip control device 1 includes a main controller 11, which is connected to the on-chip acceleration device 2 in communication; the on-chip acceleration device 2 includes a reconfigurable computing array composed of multiple tile units; the main controller is used to perform the following:

[0056] Divide the cracking tasks according to the encryption algorithm used by the secret string file to be cracked;

[0057] The on-chip acceleration device is configured according to the requirements of each sub-cracking task after task division, and the configuration content includes instruction storage space, data storage space and the interconnection method between each tile unit in the reconfigurable computing array;

[0058] Controlling the reconfigurable computing array to attack the secret string file to be cracked, and collecting corresponding cracking results;

[0059] Accept the collected cracking results and output them.

[0060] In this embodiment, the off-chip control device 1 further includes an off-chip memory 12 to which the main controller 11 is communicatively connected; the off-chip memory 12 includes an instruction storage area and a data storage area; wherein the manner of dividing the cracking task according to the encryption algorithm used by the secret string file to be cracked includes:

[0061] (1) Compiling the encryption algorithm used by the secret string file to be cracked to obtain an instruction file required to attack the secret string file to be cracked, and storing the instruction file in the instruction storage area of ​​the off-chip memory.

[0062] (2) According to the secret string file to be cracked and the instruction file, a general attack mask is set.

[0063] (3) According to the total attack mask and based on the scale of the reconfigurable computing array, the cracking task is divided into a plurality of sub-cracking tasks.

[0064] (4) Performing data conversion on each of the sub-cracking tasks, and storing each of the sub-cracking tasks after data conversion and the secret string file to be cracked in the data storage area of ​​the off-chip memory.

[0065] In this embodiment, the encryption algorithm used by the secret string file to be cracked is compiled to generate an instruction file that can guide the reconfigurable computing array to perform password cracking operations. The generated instruction file is stored in the instruction storage area of ​​the off-chip memory for subsequent reading and execution.

[0066] In this embodiment, the total attack mask is a strategy for screening and locating possible key values. The total attack mask is set according to the characteristics of the secret string file to be cracked and the known encryption algorithm. These total attack masks will help narrow the possible key space and improve the cracking efficiency. The scale of the reconfigurable computing array refers to the scale of each Tile unit, which determines the parallel processing capability of the reconfigurable computing array, that is, the number of tasks or data scale that can be processed simultaneously. The Tile unit is the basic computing unit in the reconfigurable computing array. Based on the total attack mask and the parallel processing capability of the reconfigurable computing array, the cracking task is divided into multiple smaller, independently executable sub-cracking tasks. Each sub-cracking task will process a different key space or algorithm part.

[0067] In this embodiment, the data required for each sub-cracking task is converted to ensure that they are compatible with the interface of the reconfigurable computing array. The processed sub-cracking task data and the original secret string file to be cracked are stored together in the data storage area of ​​the off-chip memory to ensure that the data can be quickly accessed when needed to support parallel processing.

[0068] In this embodiment, the on-chip acceleration device 2 also includes an instruction distribution unit, a data distribution unit and a control unit; the main controller performs initialization operations on the instruction distribution unit and the data distribution unit through the control unit to configure the instruction storage space and data storage space of the on-chip acceleration device, and the method includes: configuring the address of each instruction block in the instruction file in the instruction storage area in the instruction distribution unit, and configuring the address of each sub-cracking task after data conversion and the encrypted string file to be cracked in the data storage area in the data distribution unit; wherein, the instruction file includes multiple instruction blocks.

[0069] In this embodiment, the instruction distribution unit is responsible for reading the instruction block from the instruction storage area of ​​the off-chip memory, and distributing each instruction in the instruction block to each Tile unit in the reconfigurable computing array for execution. In the instruction distribution unit, the address of each instruction block in the instruction storage area in the instruction file is configured. By configuring these addresses, the instruction distribution unit can accurately read the instruction block in the instruction file according to the instruction PC pointer, and distribute each instruction in the read instruction block to each Tile unit for execution.

[0070] In this embodiment, the instruction PC pointer is a register or counter that stores the address of the current instruction block in the instruction storage area. As the instruction block is executed, the PC pointer will increment to point to the next instruction block to be executed. The address of each instruction block in the instruction file in the instruction storage area is configured in the instruction distribution unit. When the instruction distribution unit receives a signal to execute the instruction, it reads the corresponding instruction block from the instruction storage area according to the current value of the PC pointer. The read instruction block contains multiple instructions, which will be distributed by the instruction distribution unit to each Tile unit in the reconfigurable computing array for execution.

[0071] In this embodiment, the data distribution unit is responsible for reading data from the data storage area of ​​the off-chip memory and storing the read data in the shared memory of the Tile unit. In the data distribution unit, it is necessary to configure the addresses of the sub-cracking tasks after data conversion and the secret string files to be cracked in the data storage area. By configuring these addresses, the data distribution unit can accurately read the sub-cracking tasks after data conversion and the secret string files to be cracked, and store them in the shared memory for processing by the Tile unit.

[0072] In this embodiment, the off-chip control device 1 also includes a configuration buffer 13 that is communicatively connected to the main controller 11, and the main controller 11 configures the interconnection mode between each Tile unit in the reconfigurable computing array through the configuration buffer 13. Preferably, the interconnection mode between each Tile unit is configured as a single instruction multiple data mode (SIMD), so that each Tile unit is completely independent. In the single instruction multiple data mode, each Tile unit is completely independent and can execute the same instruction at the same time, but process different data. This mode is very suitable for application scenarios that require a large amount of parallel processing, such as password cracking, image processing, scientific computing, etc.

[0073] In this embodiment, the main controller 11, the off-chip memory 12, and the configuration buffer 13 provide the on-chip acceleration device 2 with necessary control, synchronization, and configuration reconstruction functions, and provide necessary instructions and data storage space for the normal operation of the reconfigurable computing array.

[0074] In this embodiment, if Figure 2As shown, a schematic diagram of the structure of the Tile unit in an embodiment of the present invention is shown. The reconfigurable computing array is an array structure composed of N rows and M columns of Tile units. Each Tile unit also includes an instruction cache unit, an instruction decoding unit, and an address generation unit; the instruction cache unit is used to store the instructions received by the Tile unit, and send the stored instructions to the instruction decoding unit; the instruction decoding unit is used to decode the sent instructions to obtain the instruction operation type and instruction operands; the address generation unit is used to generate the address of the data required for the instruction processing array to execute the corresponding instruction operation according to the instruction operation type and instruction operands. Among them, Figure 2 The east interconnection channel, west interconnection channel, south interconnection channel, and north interconnection channel represent the interconnection mode between the tile unit and the adjacent tile units.

[0075] In this embodiment, if Figure 3 As shown, a schematic diagram of the process of attacking the secret string file to be cracked in an embodiment of the present invention is shown. Each Tile unit also includes a shared memory and an instruction processing array composed of multiple PE units; the method of controlling the reconfigurable computing array to attack the secret string file to be cracked includes:

[0076] S301: In response to a configuration completion signal, instruct the control unit to start the reconfigurable computing array.

[0077] S302: Sending an execution instruction signal through the control unit to enable the instruction distribution unit to read the instruction block in the instruction file from the off-chip memory; and enable the data distribution unit to read the sub-cracking task and the data in the secret string file to be cracked after data conversion associated with the instruction block from the off-chip memory, and store them in the shared memory.

[0078] In this embodiment, the instruction distribution unit reads an instruction block from the instruction storage area of ​​the off-chip memory in direct memory access mode (DMA mode), and at the same time, the data distribution unit also reads the data associated with the instruction block from the data storage area of ​​the off-chip memory. These data include the sub-cracking tasks after data conversion and the data in the secret string file to be cracked, and the read data is stored in the shared memory so that each Tile unit can access and process these data.

[0079] In this embodiment, data is transmitted between the instruction distribution unit and the off-chip memory in a direct memory access manner without intervention by the CPU, thereby increasing the speed of data transmission.

[0080] In this embodiment, the shared memory provides a total of two write ports and two read ports, wherein the input data from the adjacent Tile unit and the input data of the data distribution unit share one write port, and the output of the shared memory and the instruction processing array share another write port. In order to facilitate data synchronization during the calculation process, the storage space of the shared memory is divided into two parts, namely the non-broadcast data storage area (UBD) and the broadcast data storage area (BD). Among them, the non-broadcast data storage area is used to store the sub-cracking tasks after data conversion, and the broadcast data storage area is used to store the encrypted string files to be cracked and static data, and the static data includes: constant variables in the encryption algorithm or the hash string of the encryption algorithm to be attacked, etc.

[0081] S303: The instruction distribution unit broadcasts each instruction in the read instruction block to each Tile unit in a one-by-one distribution manner; wherein each instruction block includes multiple instructions.

[0082] S304: Each Tile unit decodes the received instruction, and reads the sub-cracking task after data conversion and the data in the secret string file to be cracked required to execute the corresponding instruction operation from the shared memory according to the decoding result of the instruction, so that the instruction processing array in each Tile unit can execute the corresponding instruction operation.

[0083] In this embodiment, the instruction distribution unit reads the corresponding instruction block from the instruction storage area of ​​the off-chip memory in a direct memory access manner according to the current value of the PC pointer, and broadcasts each instruction in the instruction block to each Tile unit in a one-by-one distribution manner, and stores it in the instruction cache unit of each Tile unit. Once an instruction is stored in the instruction cache unit, the instruction decoding unit decodes the instruction to obtain the instruction operation type and instruction operand. Among them, the instruction operation type includes but is not limited to: read and write instructions, addition instructions, subtraction instructions, data transfer instructions, etc., and the instruction operand includes: data required to execute the instruction operation or the offset address of the data required to execute the instruction operation, etc.

[0084] In this embodiment, the address generation unit generates the address of the data required for the instruction processing array to execute the corresponding instruction operation according to the instruction operation type and the instruction operand, so as to ensure that the instruction processing array can accurately access the shared memory to obtain the data required to execute the instruction operation. The instruction processing array implements the calculation of the instruction according to the instruction operation type, the instruction operand and the address of the data required to execute the instruction operation. Exemplarily, for data read and write instructions, the address generation unit will generate the corresponding read and write addresses for the instruction processing array to write the data into the generated addresses.

[0085] S305: Repeat the above-mentioned processes of reading instruction blocks, broadcasting instructions, decoding, reading data, and executing instruction operations until all instruction blocks in the instruction file are executed, and collect the cracking results corresponding to the secret string file to be cracked.

[0086] In this embodiment, the instruction distribution unit reads the instruction blocks in the instruction file in sequence according to the instruction PC pointer, and broadcasts each instruction in the instruction block to each Tile unit. After decoding by the instruction decoding unit and address generation by the address generation unit, the instruction processing array obtains the data required to execute the instruction operation and performs instruction calculation until all instruction blocks in the instruction file are executed and the cracking results corresponding to the secret string file to be cracked are collected.

[0087] In this embodiment, if Figure 4 As shown, a schematic diagram of the structure of the function unit in the PE unit in an embodiment of the present invention is shown. The PE unit is a computing unit specifically used to process instructions. Each PE unit includes a function unit (FU) for calculating different encryption algorithms, which includes various computing modules required to execute the encryption algorithm. The function unit includes an arithmetic logic module (ALU) and several bit operation modules, and the bit operation module includes a Galois field GFx2 operation module, a DES initial permutation module, a DES key transformation module, a DES extension transformation module, a DES permutation module, and a DES function module. One or more combinations thereof.

[0088] In this embodiment, the arithmetic logic unit (ALU) is a unit that performs basic arithmetic and logical operations, such as addition, subtraction, multiplication, division, bit operations, etc. In encryption algorithms, ALU is often used to perform some basic mathematical operations. The bit operation module is used to perform bit-level operations. The Galois field GFx2 operation module (GFx2) is used to perform operations on the Galois field, which is the basis of some encryption algorithms (such as partial operations of AES). The DES initial permutation module (DES_IP) is used to perform the initial permutation step in the DES encryption algorithm. The DES key transformation module (DES_K) converts the key into a format suitable for the DES encryption algorithm. The DES extended transformation module (DES_E) is to expand a part of the key into a longer form during the DES encryption process so as to operate with the data block. The DES permutation module (DES_P) performs permutation operations on data blocks or keys to disrupt their original order. The DES function module (DES_F) is a core function in the DES encryption algorithm, which is used to perform complex operations in combination with keys and data blocks.

[0089] It should be noted that by combining different bit operation modules, the PE unit can flexibly support multiple encryption algorithms. With the emergence of new encryption algorithms, the function of the PE unit can be expanded by adding new bit operation modules, and the scalability is strong.

[0090] In this embodiment, if Figure 2 As shown, the PE unit also includes a state module and a register stack module (RF). After the execution of each instruction in the instruction block is completed, the state module will compare and verify the calculation result of the function unit with the attack string corresponding to the secret string file to be cracked. If the results are consistent, the PE unit will write a hit flag in the state module and record the current password cracking result in the state module. The hit flag and the corresponding password cracking result are output through the state module, summarized on the reconfigurable computing array, and output to the control unit.

[0091] In this embodiment, the register file module can store temporary data generated by the instruction processing array during the execution of instructions, and these data will be reused in subsequent calculations. This storage method helps to reduce access requirements, thereby greatly improving the efficiency of the computer processor.

[0092] In this embodiment, the main controller obtains the calculation results of the entire reconfigurable computing array by querying. If a hit occurs, the hit password and cracking result will be read back. Otherwise, the total attack mask will be reset and the next cracking task will be executed.

[0093] It is worth noting that the computing acceleration system suitable for decryption in the present invention divides the cracking tasks through the main controller, and configures the instruction storage space, data storage space and interconnection mode between each Tile unit in the reconfigurable computing array of the on-chip acceleration device according to the task requirements, thereby realizing the precise allocation of computing resources, avoiding the idleness of high-performance hardware resources, reducing power consumption, and enabling the system to support multiple encryption algorithms through the configuration of the on-chip acceleration device, thereby providing computing acceleration for multiple encryption algorithms, improving its versatility and application scope, and solving the problem of single support for existing decryption structure algorithms. The main controller efficiently controls the reconfigurable computing array, realizes the parallel control and data scheduling of large-scale computing cores, and improves computing efficiency and flexibility.

[0094] Furthermore, the computing acceleration system suitable for decryption in the present invention combines an off-chip control device and an on-chip acceleration device to form an efficient heterogeneous acceleration solution, so that the system can show better performance when facing complex encryption algorithms.

[0095] Furthermore, the computing acceleration system for decryption in the present invention can realize the computing acceleration of hash algorithms and symmetric algorithms, covering most of the algorithms in the current Hashcat open source framework. After the encryption algorithm is compiled, it is executed in each PE unit in a single instruction multiple data mode (SIMD). The entire acceleration structure was simulated under a 55nm process. Among them, under the experimental scale of 32 tile units and 256 PE units, the chip area of ​​the structure is 16.5mm 2 , running at 250MHz, when running typical algorithms such as MD5, SHA2-256, DES and AES, the computing efficiency per unit area is between 4.26-24.98 times that of GPU Tesla V100, and the energy efficiency is 4.09-20.86 times that of GPU Tesla V100.

[0096] To facilitate those skilled in the art to understand the computing acceleration system for decryption provided by the embodiment of the present application, the following takes the MD5 secret string decryption process as an example to further explain the attack process for cracking the secret string file, including the following steps:

[0097] (1) Compile the MD5 encryption algorithm used by the secret string file to be cracked to obtain an instruction file required to attack the secret string file to be cracked, name the instruction file MD5.bin, and store the instruction file in the instruction storage area of ​​the off-chip memory.

[0098] (2) The secret string file to be cracked, such as 0x25d55ad2, 0x83aa400a, 0xf464c76d, and 0x713c07ad, is input into the main controller, and based on the instruction file, a total attack mask is set, such as ?d?d?d?d?d?d?d?d?d.

[0099] In this embodiment, ?d represents an unknown numeric character, which means trying all possible numbers (0-9) at this position to find the correct key or password.

[0100] (3) The main controller divides the cracking task into several sub-cracking tasks according to the total attack mask and based on the size of each tile unit.

[0101] In this embodiment, the cracking task is divided into several sub-cracking tasks, so that each PE unit in the Tile unit can run an independent sub-cracking task.

[0102] (4) Performing data conversion on each of the decomposed sub-cracking tasks, and storing each of the sub-cracking tasks after data conversion and the secret string file to be cracked in the data storage area of ​​the off-chip memory.

[0103] (5) The main controller configures the interconnection mode between each tile unit in the reconfigurable computing array by configuring the cache.

[0104] In this embodiment, the interconnection mode between each Tile unit is configured as a single instruction multiple data mode (SIMD), so that each Tile unit is completely independent.

[0105] (6) The main controller initializes the instruction distribution unit and the data distribution unit through the control unit, configures the address of each instruction block in the instruction file in the instruction distribution unit, and configures the address of each sub-cracking task after data conversion and the encrypted string file to be cracked in the data storage area in the data distribution unit, and then starts the reconfigurable computing array through the control unit.

[0106] (7) The instruction distribution unit reads an instruction block from the instruction storage area of ​​the off-chip memory in a direct memory access manner, and broadcasts each instruction in the instruction block to each Tile unit in a one-by-one distribution manner, and stores them in the instruction cache unit of each Tile unit. Once an instruction is stored in the instruction cache unit, the instruction decoding unit decodes the instruction to obtain the instruction operation type and instruction operand. The address generation unit generates the address of the data required for the instruction processing array to execute the corresponding instruction operation based on the instruction operation type and instruction operand. At the same time, the data distribution unit also reads the data associated with the instruction block from the data storage area of ​​the off-chip memory and stores it in the shared memory. The instruction processing array reads the data required to execute the corresponding instruction operation based on the instruction operation type, instruction operand and the address of the data required to execute the instruction operation, and implements the calculation of the instruction.

[0107] (8) After all instruction blocks in the instruction file are executed, the state module will compare and verify the calculation result of the function unit with the attack string corresponding to the password string file to be cracked. If the results are consistent, the PE unit will write a hit flag in the state module and record the current password cracking result in the state module. The hit flag and the corresponding password cracking result will be output through the state module, summarized on the reconfigurable computing array, and output to the control unit.

[0108] (9) The main controller obtains the calculation results of the entire reconfigurable computing array by querying. If a hit occurs, the main controller reads back the hit password and the cracking result. Otherwise, it returns to step (3) and continues to execute the next cracking task.

[0109] It should be noted that in the embodiments of the present application, words such as "exemplary" or "for example" represent examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0110] In the embodiments of the present application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can represent: a, b, c, ab, ac, bc or abc, where a, b, c can be single or multiple.

[0111] Figure 5 1 is a flow chart of a computational acceleration method for decryption provided in an embodiment of the present application. Figure 5 As shown, the computing acceleration method applicable to decryption is applied to the computing acceleration system applicable to decryption as described above, the computing acceleration system applicable to decryption includes an off-chip control device and an on-chip acceleration device communicatively connected to the off-chip control device; the computing acceleration method applicable to decryption includes:

[0112] S501: Divide the cracking tasks according to the encryption algorithm used by the secret string file to be cracked.

[0113] S502: configuring the on-chip acceleration device according to the requirements of each sub-cracking task after task division, wherein the configuration content includes instruction storage space, data storage space and the interconnection method between each Title unit in the reconfigurable computing array.

[0114] S503: Control the reconfigurable computing array to attack the encrypted string file to be cracked, and collect corresponding cracking results.

[0115] S504: Accept the collected cracking results and output them.

[0116] It should be understood that the specific process of each module executing the above corresponding steps has been described in detail in the above system embodiment, and for the sake of brevity, it will not be repeated here.

[0117] It should also be understood that the division of modules in the embodiments of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation. In addition, each functional module in each embodiment of the present application may be integrated into a processor, or may exist physically separately, or two or more modules may be integrated into one module. The above-mentioned integrated modules may be implemented in the form of hardware or in the form of software functional modules.

[0118] According to the method provided in the embodiment of the present application, the present application also provides a computer program product, which includes: a computer program code, when the computer program code is run on a computer, the computer executes Figure 5 The method in the illustrated embodiment.

[0119] According to the method provided in the embodiment of the present application, the present application also provides a computer-readable storage medium, which stores a program code, and when the program code is run on a computer, the computer executes Figure 5 The method in the illustrated embodiment.

[0120] The terms "component", "module", "system", etc. used in this specification are used to represent computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program and / or a computer. By way of illustration, both applications running on a computing device and a computing device can be components. One or more components may reside in a process and / or an execution thread, and a component may be located on a computer and / or distributed between two or more computers. In addition, these components may be executed from various computer-readable media having various data structures stored thereon. Components may, for example, communicate through local and / or remote processes according to signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system and / or a network, such as the Internet interacting with other systems through signals).

[0121] Those of ordinary skill in the art will appreciate that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or in a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0122] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0123] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0124] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0125] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0126] In the above embodiments, the functions of each functional unit can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions (programs). When loading and executing computer program instructions (programs) on a computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. Computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that contains one or more available media integrations. Available media may be magnetic media (e.g., floppy disks, hard disks, tapes), optical media (e.g., high-density digital video discs (DVDs), or semiconductor media (e.g., solid state disks (SSDs), etc.).

[0127] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.

[0128] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0129] In summary, the present application provides a computing acceleration system, method, medium and product suitable for decryption. The main controller is used to divide the cracking task, and the instruction storage space, data storage space and interconnection method between each Tile unit in the reconfigurable computing array of the on-chip acceleration device are configured according to the task requirements, so as to achieve accurate allocation of computing resources, avoid idleness of high-performance hardware resources, reduce power consumption, and enable the system to support multiple encryption algorithms through the configuration of the on-chip acceleration device, thereby providing computing acceleration for multiple encryption algorithms, improving its versatility and application scope, and solving the problem of single support for existing decryption structure algorithms. The main controller is used to efficiently control the reconfigurable computing array, realize parallel control and data scheduling of large-scale computing cores, and improve computing efficiency and flexibility. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0130] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. A computing acceleration system suitable for decryption, characterized in that: include: An off-chip control device and an on-chip acceleration device communicatively connected to the off-chip control device; The off-chip control device comprises a main controller, and the main controller is communicatively connected with the on-chip acceleration device; The on-chip acceleration device includes a reconfigurable computing array composed of a plurality of Tile units; The main controller is used to perform the following: Divide the cracking tasks according to the encryption algorithm used by the secret string file to be cracked; The on-chip acceleration device is configured according to the requirements of each sub-cracking task after task division, and the configuration content includes instruction storage space, data storage space and the interconnection method between each tile unit in the reconfigurable computing array; Controlling the reconfigurable computing array to attack the secret string file to be cracked, and collecting corresponding cracking results; Accept the collected cracking results and output them.

2. The computing acceleration system suitable for decryption according to claim 1, characterized in that: The off-chip control device also includes an off-chip memory that is communicatively connected to the main controller; the off-chip memory includes an instruction storage area and a data storage area; wherein the method of dividing the cracking task according to the encryption algorithm used by the secret string file to be cracked includes: Compiling the encryption algorithm used by the secret string file to be cracked to obtain an instruction file required to attack the secret string file to be cracked, and storing the instruction file in the instruction storage area of ​​the off-chip memory; According to the secret string file to be cracked and the instruction file, a general attack mask is set; According to the total attack mask and based on the scale of the reconfigurable computing array, the cracking task is divided into a plurality of sub-cracking tasks; Data conversion is performed on each of the sub-cracking tasks, and each of the sub-cracking tasks after data conversion and the secret string file to be cracked are stored in the data storage area of ​​the off-chip memory.

3. The computing acceleration system suitable for decryption according to claim 2, characterized in that: The on-chip acceleration device further includes an instruction distribution unit, a data distribution unit, and a control unit; the main controller performs initialization operations on the instruction distribution unit and the data distribution unit through the control unit to configure the instruction storage space and the data storage space of the on-chip acceleration device, and the method includes: The address of each instruction block in the instruction file in the instruction storage area is configured in the instruction distribution unit, and the address of each sub-cracking task after data conversion and the encrypted string file to be cracked in the data storage area is configured in the data distribution unit; wherein the instruction file includes multiple instruction blocks.

4. The computing acceleration system suitable for decryption according to claim 3, characterized in that: Each Tile unit includes a shared memory and an instruction processing array consisting of multiple PE units; The method of controlling the reconfigurable computing array to attack the secret string file to be cracked includes: In response to a configuration completion signal, causing the control unit to start the reconfigurable computing array; The control unit sends an execution instruction signal to make the instruction distribution unit read the instruction block in the instruction file from the off-chip memory; and make the data distribution unit read the sub-cracking task and the data in the secret string file to be cracked after the data conversion associated with the instruction block from the off-chip memory, and store them in the shared memory; The instruction distribution unit broadcasts each instruction in the instruction block read to each Tile unit in a one-by-one distribution manner; wherein each instruction block includes multiple instructions; Each Tile unit decodes the received instruction, and reads the sub-cracking task after data conversion and the data in the secret string file to be cracked required to execute the corresponding instruction operation from the shared memory according to the decoding result of the instruction, so that the instruction processing array in each Tile unit can execute the corresponding instruction operation; Repeat the above-mentioned processes of reading instruction blocks, broadcasting instructions, decoding, reading data, and executing instruction operations until all instruction blocks in the instruction file are executed, and collect the cracking results corresponding to the secret string file to be cracked.

5. The computing acceleration system suitable for decryption according to claim 4, characterized in that: Each Tile unit also includes an instruction cache unit, an instruction decoding unit, and an address generation unit; the instruction cache unit is used to store the instructions received by the Tile unit and send the stored instructions to the instruction decoding unit; the instruction decoding unit is used to decode the sent instructions to obtain the instruction operation type and instruction operand; The address generating unit is used to generate the address of the data required for the instruction processing array to execute the corresponding instruction operation according to the instruction operation type and instruction operand.

6. The computing acceleration system suitable for decryption according to claim 4, characterized in that: Each PE unit includes a function unit for calculating different encryption algorithms; the function unit includes an arithmetic logic module and a plurality of bit operation modules, and the bit operation module includes a Galois field GFx2 operation module, a DES initial permutation module, a DES key transformation module, a DES extended transformation module, a DES permutation module, and a DES function module, one or more of which are combined.

7. The computing acceleration system suitable for decryption according to claim 1, characterized in that: The off-chip control device further comprises a configuration buffer which is communicatively connected to the main controller, and the main controller configures the interconnection mode between each Tile unit in the reconfigurable computing array through the configuration buffer.

8. A computing acceleration method suitable for decryption, characterized in that: The computing acceleration system for decryption and decoding as claimed in any one of claims 1 to 7, wherein the computing acceleration system for decryption and decoding comprises an off-chip control device and an on-chip acceleration device communicatively connected to the off-chip control device; The computing acceleration method applicable to decryption includes: Divide the cracking tasks according to the encryption algorithm used by the secret string file to be cracked; The on-chip acceleration device is configured according to the requirements of each sub-cracking task after task division, and the configuration content includes instruction storage space, data storage space and the interconnection method between each Title unit in the reconfigurable computing array; Controlling the reconfigurable computing array to attack the secret string file to be cracked, and collecting corresponding cracking results; Accept the collected cracking results and output them.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the computing acceleration method suitable for decryption and decoding as claimed in claim 8 is implemented.

10. A computer program product, characterized in that The computer program product includes computer program codes, and when the computer program codes are executed on a computer, the computer is enabled to implement the computing acceleration method for decryption as claimed in claim 8.

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