Wireless networking and communication method of capacitive voltage transformer

Abstract

The present application discloses a wireless networking and communication method for a capacitive voltage transformer, which involves wireless communication between at least one host and multiple slaves. The host is responsible for constructing a synchronization message in Ethernet format, and converting it into a wireless network format message and sending it to the slave to realize information interaction of the wireless synchronization message. The host also sends a time setting command to the slave at regular intervals through a broadcast command to ensure network synchronization. The received wireless network message is converted into Ethernet format by the host, and key information is extracted according to the message type for logical processing. In order to save energy, the slave is in a sleep state when it is not awakened, and the host activates the slave by broadcasting a wake-up command. If the slave is disconnected or lost, the host will periodically re-awaken and try to reconnect it to the wireless network to ensure the stability and reliability of the network.

Description

Technical Field

[0001] The present application relates to the technical field of power systems, and in particular to a wireless networking and communication method for capacitive voltage transformers. Background Art

[0002] In the power system, capacitive voltage transformer (CVT) is an important power equipment and is widely used in voltage measurement, power system protection and communication. With the development of smart grid, higher requirements are put forward for the monitoring, control and data transmission of CVT. Traditional wired communication methods have problems such as complex wiring, high maintenance cost and poor flexibility. Therefore, wireless networking and communication methods have become an effective way to solve these problems.

[0003] However, there are still some challenges and limitations in existing wireless networking and communication methods, such as how to achieve stable and reliable wireless communication between the host and multiple slaves, how to ensure the real-time and accuracy of communication, and how to effectively reconnect to the wireless network after the slave is disconnected or lost. Summary of the invention

[0004] In order to address the deficiencies in the prior art, the purpose of the present application is to provide a wireless networking and communication method for a capacitive voltage transformer, which can realize stable and reliable wireless communication between a host and multiple slaves, ensure the real-time and accuracy of communication, and effectively reconnect to the wireless network after the slave is disconnected or lost.

[0005] To achieve the above objectives, this application adopts the following technical solutions: The present application provides a wireless networking and communication method for a capacitive voltage transformer, the wireless networking and communication method for a capacitive voltage transformer comprising: At least one host and a plurality of slaves are provided, and wireless communication between the host and the plurality of slaves is performed; The host and each slave exchange information of wireless synchronization messages: the host converts the constructed Ethernet format synchronization message into a wireless network format message and transmits it to the slave; The host sends a time setting command to the slave regularly by broadcasting a wireless network format message to the slave; The host converts the received wireless network message into Ethernet format, determines the message type and extracts its key information for further logical processing; The host broadcasts a wake-up command to the slave to wake up the slave. At other times, the slave is in sleep mode. After the slave is disconnected or lost, the host periodically wakes up the slave and connects the slave to the wireless network.

[0006] As a preferred technical solution, in a wireless network scenario, the transmission of messages between the host and each slave relies on the 802.11 protocol. At the data link layer, the 802.1AS messages required for path delay measurement and time synchronization measurement are encapsulated into 802.11 data frames for protocol transmission.

[0007] As a preferred technical solution, an FPGA+SDR structure is used to realize wireless message transmission in a specific frequency band. In the wireless message receiving part, the reception and processing of the RF signal is completed through the analog-to-digital conversion part directly connected to the SDR. Secondly, the data is demodulated and the bit stream is converted through OFDM, and the message reception time is recorded. Finally, the data and the message reception time are sent to the host server for subsequent processing.

[0008] As a preferred technical solution, in the initial stage, the host server sends the gating time slot and other configuration information to complete the configuration of the sending queue gating list, and then schedules the transmission of the synchronization message data output by the host server according to the configured gating. Secondly, the data output rate is matched for the RF signal and the digital-to-analog conversion is completed. Finally, the wireless message is sent by transmitting it across the clock domain to the host wireless module.

[0009] As a preferred technical solution, the host sends a time setting command to the slave regularly by broadcasting a wireless network format message to the slave, including: The master node receives and parses the status information messages reported by each slave node, extracts the three decision attributes of the link congestion coefficient, link topology and clock source parameter set for the master clock selection, and establishes a master clock selection model based on the received information; The master node calculates the optimal weight values ​​corresponding to the three decision attributes according to the multi-attribute decision algorithm, substitutes them into the calculated clock attribute values ​​of each node, compares them to obtain the best master clock node and generates a redundant clock sequence; The host server periodically queries the best master clock node, sets a timeout threshold, and restarts the timeout count when receiving a new status report message. If the synchronization centralized control node does not receive new report information within the threshold range, it is assumed that the master clock node has unexpectedly failed, and the master clock node information and redundant clock sequence are updated and sent to each slave node; Monitor whether there are new time-sensitive nodes joining the network. If there are new nodes joining, receive and calculate the clock attribute value of the node, compare it with the original main clock node and redundant clock sequence, and update the above information.

[0010] As a preferred technical solution, the host server determines whether the input data message is a synchronization message. If it is not a synchronization message, it is directly output to the subsequent switch function module. If it is a synchronization message, the corresponding synchronization information is recorded or extracted according to the specific synchronization message type.

[0011] As a preferred technical solution, the host server receives the redundant clock sequence table sent by the master node, confirms the best master clock identification number, and updates the local redundant clock sequence table. The synchronization message sent by the slave node contains its own clock source parameter information and status information messages of network information such as link topology and link congestion, which are reported to the master node.

[0012] As a preferred technical solution, a master node request-slave node response mode is adopted to send or respond to delay request messages, and the link delay value of the adjacent node is calculated by considering the adjacent frequency ratio and link asymmetry; the Kalman filter algorithm is used to filter the measured value to reduce the synchronization error; at the same time, the link congestion situation is estimated by sending link detection packets, and the difference between the departure interval time and the arrival interval time of the data packet is compared to see whether it exceeds the time threshold to determine the link congestion coefficient of the adjacent link of the measurement node.

[0013] As a preferred technical solution, the host constructs or forwards synchronization information messages according to the local port role; if all ports are master ports, a two-step method is used to construct synchronization messages and follow-up messages and send them to other nodes; if a port is a slave clock port and there are master ports in other ports, the synchronization message is received and the local synchronization clock deviation is calculated and corrected, and the local residence time is added to the synchronization message correction field and forwarded to the other slave clock ports. In other cases, only the synchronization message is received and no forwarding operation is performed.

[0014] The wireless networking and communication method of the capacitive voltage transformer provided in this application shows many significant advantages and beneficial effects compared with the traditional wired communication method and the existing wireless communication technology: 1. Convenience and flexibility of wireless communication: By setting up wireless communication between the host and multiple slaves, the wiring work is greatly simplified, the installation and maintenance costs are reduced, and the flexibility and scalability of the system are improved.

[0015] 2. Efficient synchronous message transmission and processing: The host can efficiently convert Ethernet format synchronization messages into wireless network format messages and quickly transmit them to the slaves, ensuring time synchronization and data consistency of the entire network.

[0016] The host quickly converts and judges the received wireless network messages, extracts key information, and provides strong support for further logical processing.

[0017] 3. Energy-saving slave management mechanism: The introduction of the slave sleep mechanism puts the slave in a low-power sleep state during non-essential communication periods, significantly reducing the energy consumption of the entire system.

[0018] By broadcasting a wake-up command, the host can accurately wake up the slave for communication, further improving energy efficiency.

[0019] 4. Stable network reconstruction and recovery capabilities: When a slave device is disconnected or loses connection, the host can periodically reawaken the slave device and try to reconnect it to the wireless network, ensuring the stability and reliability of the network.

[0020] This network reconstruction mechanism helps to maintain the continuity and integrity of the communication network in a complex and changing power environment.

[0021] 5. Improve the intelligence level of power system: The application of this method provides a more efficient and convenient communication means for the monitoring, control and data transmission of capacitor voltage transformers, which helps to improve the intelligence level and overall operation efficiency of the power system.

[0022] In summary, the wireless networking and communication method of the capacitive voltage transformer provided in the present application not only simplifies the system structure and reduces costs, but also improves communication efficiency and stability, providing strong support for the intelligent development of the power system. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a schematic structural diagram of an online monitoring device for a capacitive voltage transformer of the present application; Figure 2 The circuit diagram of the AD acquisition module for this application; Figure 3 This is a schematic diagram of the connection structure of each unit of the AD acquisition module of this application; Figure 4 This is the circuit diagram of the AD acquisition chip U7 of this application; Figure 5 A circuit diagram of the linear regulator U6 of the present application; Figure 6 This is a circuit diagram of the crystal oscillator Y1 of the present application; Figure 7 The circuit diagram of the CVT transformer for this application; Figure 8 The circuit diagram of the MCU control module of this application; Fig. 9 This is a schematic diagram of the connection structure of each unit of the MCU control module of this application; Fig.10 The circuit diagram of the clock chip module of this application; Fig.11 Circuit diagram of the host MCU chip / slave MCU chip for this application; Fig.12A circuit diagram of a slave power supply control circuit of the present application; Fig.13 This is a schematic diagram of the connection structure of each unit of the slave power supply control circuit of the present application; Fig.14 A circuit diagram of the AD battery control circuit of this application; Fig.15 The circuit diagram of the MCU power control circuit of this application; Fig.16 A circuit diagram of the wireless power control circuit of this application; Fig.17 A circuit diagram of a first AD voltage conversion circuit of the present application; Fig.18 A circuit diagram of a second AD voltage conversion circuit of the present application; Fig.19 A circuit diagram of the wired synchronization module of this application; Fig. 20 This is a monitoring data diagram obtained by the online monitoring method of the capacitive voltage transformer of this application. DETAILED DESCRIPTION

[0024] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the specific implementation manner of the present application will be clearly and completely described below in conjunction with the drawings in the implementation manner of the present application.

[0025] like Figure 1 As shown, the present application provides an online monitoring device for a capacitor voltage transformer. The online monitoring device for a capacitor voltage transformer comprises: a host and a plurality of slaves.

[0026] It should be noted that multiple groups of hosts can be set up, and the multiple groups of hosts communicate with each other by wire or wirelessly, and each group of hosts communicates wirelessly with a number of slaves. Among them, each host represents a master node, and each slave represents a slave node.

[0027] In the present application, the online monitoring device includes: 1 group of host machines and 3 groups of slave machines.

[0028] The host includes: PC server, host MCU and host wireless module.

[0029] The PC server is connected to the host MCU via the UART1 line, which is used for serial communication between the PC server and the host MCU. The PC server is connected to the host wireless module via the UART2 line, which is used for serial communication between the PC server and the host wireless module.

[0030] The host MCU is connected to the 220V synchronization signal line 220VSYNC, which is used to provide voltage for the host and to synchronize the clock signals of the host and the slave. The host MCU is connected to the host wireless module via the SYNC1 / WAKEUP line. The SYNC1 / WAKEUP line is used to wake up the host wireless module synchronously after the host MCU receives the wake-up signal. In this application, the number of wake-up times is 5. The host MCU is connected to the host wireless module via the SYNC2 / SYNC line. The SYNC2 / SYNC line is used to synchronously transmit the signal of the host MCU to the host wireless module.

[0031] In this application, the host wireless module adopts a ZIGB module or the like.

[0032] Each slave includes: a slave MCU, a slave wireless module, an AD acquisition module, a wireless power module and an AD power module.

[0033] In this application, the slave wireless module adopts a ZIGB module or the like.

[0034] The slave wireless module is wirelessly connected to the host wireless module for data transmission between the slave wireless module and the host wireless module. The slave wireless module is connected to the slave MCU via the SYNC1 / WAKEUP line. The SYNC1 / WAKEUP line is used for waking up the slave MCU synchronously after the slave wireless module receives the wake-up signal. In this application, the number of wake-up times is 5 times. The slave wireless module is connected to the slave MCU via the SYNC2 / SYNC line. The SYNC2 / SYNC line is used to synchronously transmit the signal of the slave wireless module to the slave MCU. The slave wireless module and the slave MCU are connected via the UART1 line, and the UART1 line is used for serial communication between the slave wireless module and the slave MCU.

[0035] The slave MCU is connected to the spare 220V synchronization signal line 220VSYNC, which is used to provide voltage for the slave and to synchronize the clock signals of the host and the slave. The slave MCU is connected to the wireless power module via the ZIGBPOWER line, which is connected to the slave wireless module. The wireless power module is used to provide an appropriate voltage to the slave wireless module through voltage conversion. The slave MCU is connected to the AD power module via the ADPOWER line, which is connected to the AD acquisition module. The AD power module is used to provide an appropriate voltage to the AD acquisition module through voltage conversion. The slave MCU is connected to the AD acquisition module via the SPI line, which is used for serial communication between the slave MCU and the AD acquisition module.

[0036] The AD acquisition module is connected to a number of CVT transformers, and the AD acquisition module is used to collect fault signals of each CVT transformer.

[0037] The online monitoring device of the capacitive voltage transformer of the present application has the following working principle: the AD acquisition module triggers the analog-to-digital conversion, and the AD acquisition module acquires the fault signals of each CVT transformer; the AD acquisition module performs data conversion on the fault signal, and outputs the converted data to the slave MCU through the SPI serial port; each slave MCU sends the data to the host MCU, and the host MCU performs data processing and judgment, and the slave MCU and the host MCU send and receive data through the host wireless module and the slave wireless module.

[0038] Through the above configuration, the online monitoring device for capacitive voltage transformer of the present application can realize the fault signal collection of multiple groups of CVT transformers.

[0039] The online monitoring device of the capacitive voltage transformer of the present application is configured with two signal synchronization modes.

[0040] The first signal synchronization method: signal synchronization is performed through the 220V synchronization signal line 220VSYNC and the backup 220V synchronization signal line 220VSYNC.

[0041] The second signal synchronization method: The host broadcasts the wake-up command and the acquisition command to the slave through the broadcast command. The host wireless module is awakened, and the host wireless module drives the slave wireless module to wake up the slave MCU, so that all slaves wake up at the same time. The slave MCU drives the AD acquisition module to collect each CVT transformer fault signal, and each AD acquisition module starts to collect CVT transformer fault signal data at the same time to ensure the consistency and synchronization of the CVT transformer fault signal data collection time.

[0042] like Figure 2-Figure 6 As shown, the present application also provides an AD acquisition module suitable for a capacitive voltage transformer.

[0043] Furthermore, the AD acquisition module includes: an AD acquisition chip U7, a linear regulator U6 and a crystal oscillator Y1.

[0044] In the present application, the model of the AD acquisition chip U7 is AD7616H or ADS131, etc. In this implementation, ADS131 is taken as an example.

[0045] The AD acquisition chip U7 includes several groups of acquisition pins, each group of acquisition pins includes a positive input pin and a negative input pin, the positive input pin is connected to the live wire of the CVT transformer, and the negative input pin is connected to the neutral wire of the CVT transformer. Exemplarily, in this embodiment, the AD acquisition chip U7 with model ADS131M04IPWR includes 4 groups of acquisition pins, of which 1 group of acquisition pins is AIP0P and AIP0N, AIP0P is connected to the live wire of the CVT transformer, and AIP0N is connected to the neutral wire of the CVT transformer. The other 3 groups of acquisition pins are similar and will not be described in detail.

[0046] Capacitor C37 is connected in parallel between the acquisition pins AIP0P and AIP0N. The live wire terminal CVTA of the CVT transformer (CVT numbered A) is connected in series with resistors R41 and R42 in sequence and then connected to the acquisition pin AIP0P. The neutral wire terminal CVTAGND of the CVT transformer is connected in series with resistors R45 and R44 in sequence and then connected to the acquisition pin AIP0N. The two ends of resistor R43 are connected between resistors R41 and R42 and between resistors R45 and R44 respectively. The connection method of the remaining groups of CVT transformers is similar and will not be repeated.

[0047] The AD acquisition chip U7 includes an analog ground pin AGND, and the analog ground pin AGND is connected to an analog ground.

[0048] The AD acquisition chip U7 includes an analog voltage output pin AVDD, which is connected to the 3.3V analog working voltage line VDD3.3V_AVDD. Capacitors C33 and C35 are connected in parallel between the analog voltage output pin AVDD and the analog ground to play a filtering role. This configuration helps to smooth the power supply voltage, reduce voltage fluctuations and noise, and thus improve the stability and reliability of the circuit. Specifically, capacitor C35 is a high-frequency bypass capacitor with a capacitance value of 1μF, which is used to bypass the high-frequency interference signal introduced by the power supply; while capacitor C33 is used for filtering, and the capacitance value of C35 is 0.1μF to further purify the power supply voltage.

[0049] The AD acquisition chip U7 includes a ground pin GND, which is connected to a ground terminal. A resistor R40 is connected in series between the ground terminal and the analog ground.

[0050] The AD acquisition chip U7 includes a digital voltage input pin DVDD, which is connected to the 3.3VAD working voltage line VDD3.3V_AD. The 3.3VAD working voltage line VDD3.3V_AD is connected to the AD power module, and the AD power module provides the 3.3VAD working voltage. Capacitors C34 and C35 are connected in parallel between the digital voltage input pin DVDD and the ground terminal to play a filtering role. This configuration helps to smooth the power supply voltage, reduce voltage fluctuations and noise, and thus improve the stability and reliability of the circuit. Specifically, capacitor C36 is a high-frequency bypass capacitor with a capacitance value of 1μF, which is used to bypass the high-frequency interference signal introduced by the power supply; while capacitor C34 is used for filtering, with a capacitance value of 0.1μF, to further purify the power supply voltage.

[0051] The AD acquisition chip U7 includes a clock signal input pin CLKIN, and the clock signal input pin CLKIN is used to input a clock signal, so that the AD acquisition chip U7 of each slave machine simultaneously acquires the CVT transformer fault signal.

[0052] The AD acquisition chip U7 includes a capacitor pin CAP, the capacitor pin CAP is connected to the ground terminal, and a capacitor C38 is connected in series between the capacitor pin CAP and the ground terminal.

[0053] In this application, the model of the linear regulator U6 is HE2210M533R or the like.

[0054] ‌Linear regulator U6 is used to maintain voltage stability and protect the AD acquisition module from voltage fluctuations and noise, thereby extending the life of the AD acquisition module and improving the performance of the AD acquisition module. ‌Linear regulator U6 provides a stable output voltage and current by reducing the input voltage to the required level, ensuring that the load can operate normally without being affected by voltage changes.

[0055] ‌The linear regulator U6 includes a voltage input pin VIN, and the voltage input pin VIN is connected to the analog power supply voltage AVCC. The linear regulator U6 includes a ground pin GND, and the ground pin GND is connected to the analog ground. The linear regulator U6 includes an enable pin CE, and the enable pin CE is connected to the analog power supply voltage AVCC. The linear regulator includes a voltage output pin VOUT, and the voltage output pin VOUT outputs the analog working voltage VDD3.3V_AVDD. Capacitors C31 and C32 are connected in parallel between the voltage output pin VOUT and the analog ground to play a filtering role. This configuration helps to smooth the power supply voltage, reduce voltage fluctuations and noise, and thus improve the stability and reliability of the circuit. Specifically, capacitor C31 is a high-frequency bypass capacitor, and the capacitance value of C31 is 22μF. C31 uses a B-type tantalum capacitor. C31 is used to bypass the high-frequency interference signal introduced by the power supply; while capacitor C32 is used for filtering, and the capacitance value of C32 is 0.1μF to further purify the power supply voltage.

[0056] The linear regulator U6HE2210M533R includes a high-performance voltage error amplifier that provides high regulation accuracy under transient conditions, an undervoltage lockout circuit to prevent startup before the input voltage reaches 3.3V, an internal slow-start circuit to limit inrush current, and a voltage feed-forward circuit to improve transient response.

[0057] It should be noted that the above-mentioned “analog” refers to an analog circuit, and the above-mentioned “digital” refers to a digital circuit.

[0058] In this application, the model of the crystal oscillator Y1 is 4.096M, etc.

[0059] ‌The crystal oscillator Y1 is used to generate a highly stable oscillation frequency signal to provide an accurate time reference for the AD acquisition chip. ‌The crystal oscillator Y1 includes a voltage input pin VDD, which is connected to the 3.3VAD working voltage line VDD3.3V_AD, and a capacitor C42 is connected in series between the voltage input pin VDD and the ground terminal. The crystal oscillator Y1 includes a standby wake-up pin ST. The crystal oscillator Y1 includes a clock signal output pin CLK, and the clock signal output pin CLK of the crystal oscillator Y1 is connected to the clock signal input pin CLKIN of the AD acquisition chip. The crystal oscillator Y1 includes a ground pin GND, which is connected to the ground terminal.

[0060] The principle of the AD acquisition module collecting the fault signals of each CVT transformer is as follows: The structure of CVT transformer (capacitor voltage transformer) is as follows Figure 7As shown, C1 is composed of n1 capacitors with a capacitance of C in series, and C2 is composed of n2 capacitors with a capacitance of C in series. The AD acquisition module detects the secondary voltage value and calculates the U2 value (the near-end voltage difference between C1 and C2) through a certain ratio to determine the primary voltage value U1 (the far-end voltage difference between C1 and C2). By detecting the size of U2, it is possible to determine whether the capacitors C1 and C2 in the composition of the CVT transformer are damaged, whether the damage is at C1 or C2, and the number of damaged capacitors.

[0061] Under normal conditions: U2=U1*n2 / (n1+n2); (Formula 1) In the case that C1 damages X capacitors: U2=U1*n2 / (n1+n2-X); (Formula 2) In the case that C2 damages X capacitors: U2 = U1* (n2-x) / (n1 + n2-X); (Formula 3) When C1 damages X capacitors: voltage change rate K = (n1 + n2) / (n1 + n2 - X) - 1; When C2 damages X capacitors: voltage change rate K=[(n1+n2)*(n2-X)] / [(n1+n2-X)*n2]-1; In summary, the following CVT transformer fault types are summarized, as shown in Table 1: Table 1 Fault types of CVT transformers Fault type Voltage performance The primary and secondary windings of the intermediate transformer are open or short-circuited. No voltage output C2 capacitor has breakdown Secondary voltage reduction C1 capacitor has breakdown Secondary voltage rise Heavy pollution, high line harmonic content, frequent reclosing, and increased neutral point voltage Secondary waveform distortion Therefore, by determining the magnitude relationship between the secondary voltage U2 and the rated value of the secondary voltage U2 in a normal state, as well as the voltage change rate K, a specific CVT transformer fault can be determined.

[0062] The AD acquisition chip synchronously acquires analog signals, converts the analog signals into data, and outputs the converted data to the slave MCU through the SPI serial port. The AD acquisition chip triggers the analog-to-digital conversion.

[0063] The AD acquisition module of the present application can improve the sampling accuracy of the AD acquisition module because it adopts the linear regulator HE2210M533R; and can improve the synchronization of sampling data of each AD acquisition module because it adopts the crystal oscillator Y1.

[0064] This application uses a 24-bit 4-channel AD acquisition chip U7, which can accurately measure the voltage value on the secondary side of the CVT and ensure high precision of equipment sampling.

[0065] like Figure 8-Figure 11 As shown, the present application also provides an MCU control module suitable for a capacitive voltage transformer, the MCU control module includes a host MCU and a slave MCU, and the host MCU and the slave MCU communicate wirelessly or wired.

[0066] Furthermore, the host MCU includes a host MCU chip and a host clock circuit; the slave MCU includes a slave MCU chip and a slave clock circuit.

[0067] The present application also provides a clock chip module adapted to a capacitive voltage transformer, the clock chip module comprising a host clock circuit and a slave clock circuit. The host clock circuit and the slave clock circuit both comprise a clock chip U14. In the present application, the clock chip U14 adopts an RTC real-time clock chip of model RX80258.

[0068] The clock chip U14 includes a serial clock pin SCL, which is connected to the 3.3V MCU working voltage line VDD3.3V_MCU. A resistor R79 is connected in series between the serial clock pin SCL and the 3.3V MCU working voltage line VDD3.3V_MCU. In the present application, the resistance value of the resistor R79 is 10KΩ. The serial clock pin SCL is used by the host MCU to control the data transmission of the slave MCU. When the SCL signal is at a high level, the data on the data line is stable and can be sampled by the slave MCU; or, the serial clock pin SCL is used by the slave MCU to control the data transmission of the AD acquisition module. When the SCL signal is at a high level, the data on the data line is stable and can be sampled by the AD acquisition module. During the period when SCL is at a low level, the data on the data line can change to adapt to the next rising edge of SCL.

[0069] The clock chip U14 includes a serial data pin SDA, which is connected to the 3.3V MCU working voltage line VDD3.3V_MCU. A resistor R80 is connected in series between the serial data pin SDA and the 3.3V MCU working voltage line VDD3.3V_MCU. In this application, the resistance value of the resistor R80 is 10KΩ. The serial data pin SDA is responsible for serial data transmission between the host MCU and the slave MCU; or, the serial data pin SDA is responsible for serial data transmission between the slave MCU and the AD acquisition chip.

[0070] The clock chip U14 includes a clock signal output pin FOUT, which is connected to the RTC_SCK line. The clock signal output pin FOUT generates a clock pulse, which the host MCU sends to the slave MCU at a fixed rate during data transmission; or, the slave MCU sends to the AD acquisition module at a fixed rate. This clock pulse ensures that the sender and receiver perform data reading or writing operations at the correct time.

[0071] The clock chip U14 includes a voltage input pin VDD, which is connected to the working voltage terminal VDD3.3V_MCU of the host MCU chip. A capacitor C71 is connected in series between the working voltage terminal VDD3.3V_MCU of the host MCU chip and the ground terminal. In this application, the working parameter of capacitor C71 is 0.1μF / 50V.

[0072] The clock chip U14 includes a ground pin GND, and the ground pin GND is connected to the ground terminal.

[0073] The clock chip U14 includes an enable pin FOE, which is connected to a 3.3V MCU operating voltage line VDD3.3V_MCU. A resistor R81 is connected in series between the enable pin FOE and the 3.3V MCU operating voltage line VDD3.3V_MCU. In the present application, the resistance value of the resistor R81 is 10KΩ.

[0074] The clock chip U14 includes an interrupt pin INT, which is connected to a 3.3V MCU operating voltage line VDD3.3V_MCU. A resistor R82 is connected in series between the interrupt pin INT and the 3.3V MCU operating voltage line VDD3.3V_MCU. In the present application, the resistance value of the resistor R82 is 10KΩ.

[0075] Furthermore, the host MCU and the slave MCU also include a temperature compensation circuit, and the temperature compensation circuit includes a temperature compensation crystal oscillator Y3. The temperature compensation circuit uses the change of crystal load reactance with temperature to compensate the frequency-temperature characteristics of the crystal element to reduce its frequency-temperature offset.

[0076] In this application, the model of the temperature compensated crystal oscillator Y3 is TCXO-50M or the like.

[0077] The temperature compensated crystal oscillator Y3 includes a power supply voltage pin VCC, which is connected to a 3.3V MCU working voltage line VDD3.3V_MCU, and a capacitor C80 is connected in series between the 3.3V MCU working voltage line VDD3.3V_MCU and the ground terminal. The temperature compensated crystal oscillator Y3 includes a ground pin GND, which is grounded. The temperature compensated crystal oscillator Y3 includes a clock signal output pin OUT, which is connected to the SYS_CLK line, so that the clock signal offset of the online monitoring device is reduced.

[0078] In this application, the models of the host MCU chip and the slave MCU chip are both STM32L431RCT6, etc.

[0079] Both the host MCU chip and the slave MCU chip include the following pins: Working voltage pin VBAT: The working voltage pin VBAT is connected to the 3.3V working voltage VDD3.3V_MCU.

[0080] Clock signal input pin PC14-OSC32_IN: The clock signal input pin PC14-OSC32_IN is connected to the RTC_SCK line, and the clock signal input pin PC14-OSC32_IN receives the clock pulse generated by the clock signal output pin FOUT through the RTC_SCK line.

[0081] Crystal oscillator connection pins PHO_OSC_IN and PHO_OSC_OUT: A crystal oscillator Y2 is connected in parallel between the crystal oscillator connection pins PHO_OSC_IN and PHO_OSC_OUT, and the two ends of the crystal oscillator Y2 are connected to capacitors C66 and C68 respectively and then grounded. The crystal oscillator Y2 generates a highly stable oscillation frequency signal, providing an accurate time reference for the host MCU chip / slave MCU chip.

[0082] MCU reset pin NRST: MCU reset pin NRST is connected to NRESET line. MCU reset pin NRST is used to reset the host MCU / slave MCU.

[0083] Wireless module reset pin PC1: The wireless module reset pin PC1 is connected to the ZIGB_RESET line. The wireless module reset pin PC1 is used to reset the host wireless module / slave wireless module.

[0084] AD power pin BAT_AD: Battery pin BAT_AD is used to connect the AD power module. It should be noted that the AD power pin BAT_AD of the host MCU chip is left unconnected.

[0085] Slave output data pins PC2 and PC3: Slave output data pins PC2 and PC3 are connected to 7616_MISOB line. Slave output data pins PC2 and PC3 are used to output data from the slave to the AD acquisition chip U7. When the model of AD acquisition chip U7 is AD7616H, slave output data pins PC2 and PC3 are used.

[0086] Analog ground pin VSSA / VREF-: The analog ground pin VSSA / VREF- is connected to the ground terminal.

[0087] Analog voltage input pin VDDA / VREF+: The analog voltage input pin VDDA / VREF+ is connected to the operating voltage terminal VDD3.3V_MCU.

[0088] Wake-up pin PA0: The wake-up pin PA0 is connected to the WAKE_up line. The wake-up pin PA0 of the host MCU chip is used for the host pulse output wake-up signal, and the wake-up pin PA0 of the slave MCU chip is used to output the slave interrupt signal.

[0089] Synchronous sampling pin PA1: The synchronous sampling pin PA1 is connected to the Sync line. The synchronous sampling pin PA1 of the host MCU chip is used for host pulse output data, and the synchronous sampling pin PA1 of the slave MCU chip is used for slave interrupt output data.

[0090] Serial data transmission pin PA2: The serial data transmission pin PA2 is connected to the MCU_USART2_TX line. The serial data transmission pin PA2 is used to send host / slave serial data, specifically, the host sends serial data to the second group of slaves, and the second group of slaves sends serial data to the host.

[0091] Serial data receiving pin PA3: The serial data receiving pin PA3 is connected to the MCU_USART2_RX line. The serial data receiving pin PA3 is used to receive host / slave serial data, specifically, the host receives serial data sent by the second group of slaves and the second group of slaves receives serial data sent by the host.

[0092] Ground pin VSS: The ground pin VSS is connected to the ground terminal.

[0093] Voltage input pin VDD: Voltage input pin VDD is connected to the working voltage terminal VDD3.3V_MCU.

[0094] It should be noted that four groups of ground pins VSS and voltage input pins VDD are provided, corresponding to one group of host MCU chips and three groups of slave MCU chips respectively.

[0095] Serial current sampling pin PA4: The serial current sampling pin PA4 is connected to the SPI1_CS line and is used to detect the current of the serial data line.

[0096] Serial clock pin PA5: The serial clock pin PA5 is connected to the SPI1_SCLK line and is used for the slave to receive the serial clock signal from the master, or for the master to receive the serial clock signal from the slave.

[0097] Slave serial data input pin PA6: Slave serial data input pin PA6 is connected to SPI1_MISO line and is used for the slave MCU chip to input serial data from AD acquisition chip U7. It should be noted that when the model of AD acquisition chip U7 is ADS131, slave serial data input pin PA6 is used.

[0098] Slave serial data output pin PA7: Slave serial data output pin PA6 is connected to SPI1_MOSI line and is used to output serial data from slave MCU chip to AD acquisition chip U7. It should be noted that when the model of AD acquisition chip U7 is ADS131, slave serial data output pin PA7 is used.

[0099] Serial data sending pin PC4: Serial data sending pin PC4 is connected to MCU_USART3_TX line. Serial data sending pin PC4 is used to send host / slave serial data, specifically, the host sends serial data to the third group of slaves and the third group of slaves sends serial data to the host.

[0100] Serial data receiving pin PC5: Serial data receiving pin PC5 is connected to MCU_USART3_RX line. Serial data receiving pin PC5 is used to receive host / slave serial data, specifically for the host to receive serial data sent by the third group of slaves and for the third group of slaves to receive serial data sent by the host.

[0101] AD acquisition chip reset pin PB0: AD acquisition chip reset pin PB0 is connected to ADS131_RESET line. When the model of AD acquisition chip U7 is ADS131, AD acquisition chip reset pin PB0 is used to reset the AD acquisition chip.

[0102] Data read status pin PB2: Data read status pin PB2 is connected to ADS131_DRDY. When the model of AD acquisition chip U7 is ADS131, data read status pin PB2 is used for: When the slave completes data acquisition, data read status pin PB2 will become a low level to notify the host MCU that the data is ready and can start reading.

[0103] Serial clock pin PB10: The serial clock pin PB10 is connected to the 7616_SCLK line. When the model of the AD acquisition chip U7 is AD7616H, the serial clock pin PB10 is used to receive the serial clock signal from the AD acquisition chip U7.

[0104] Serial Data Pin PB11: Serial data pin PB11 is connected to ROM_SDA line and is used for serial data transmission between the master and slave.

[0105] Wireless power module pin PB9: The wireless power module pin PB9 is connected to the ZIGB_POWER line, which is used to input power to the wireless power module through the ZIGB_POWER line. It should be noted that the wireless power module pin PB9 of the host MCU chip is left unconnected. When the voltage of the AD power module is greater than 7V, the wireless power module is turned on. When the voltage of the AD power module is less than 6V, the wireless power module is turned off.

[0106] AD power module pin PB8: AD power module pin PB8 is connected to the AD_POWER line, which is used to input power to the AD power module through the AD_POWER line. It should be noted that the AD power module pin PB8 of the host MCU chip is left unconnected. After the slave wakes up, turn on the AD power module, and after the CVT fault information is collected, turn off the AD power module.

[0107] Boot pin BOOT0 / PH3: By setting the state of the boot pin BOOT0 / PH3, the boot mode of the host MCU chip / slave MCU chip after reset is selected.

[0108] Serial data pin PB7: Serial data pin PB7 is connected to the RTC_SDA line. Serial data pin PB7 is connected to the serial data pin SDA of the clock chip through the RTC_SDA line.

[0109] Serial clock pin PB6: Serial clock pin PB6 is connected to the RTC_SCL line. Serial clock pin PB6 is connected to the serial clock pin SCL of the clock chip through the RTC_SCL line.

[0110] Clock interrupt pin PB5: The clock interrupt pin PB5 is connected to the RTC_INT line. The clock interrupt pin PB5 is connected to the interrupt pin INT of the clock chip through the RTC_INT line.

[0111] Clock enable pin PB4: The clock enable pin PB4 is connected to the RTC_FOE line. The clock enable pin PB4 is connected to the enable pin FOE of the clock chip through the RTC_FOE line.

[0112] AD acquisition chip reset pin PB3: AD acquisition chip reset pin PB0 is connected to 7616_RESET line. When the model of AD acquisition chip U7 is AD7616H, AD acquisition chip reset pin PB3 is used to reset the AD acquisition chip.

[0113] AD acquisition chip serial port data pin PD2: AD acquisition chip serial port data pin PD2 is connected to 7616_SER1 line. When the model of AD acquisition chip U7 is AD7616H, AD acquisition chip serial port data pin PD2 is used to transmit the CVT fault data collected by AD acquisition chip U7 to the slave MCU chip.

[0114] Slave serial data output pin PC12: Slave serial data output pin PC12 is connected to 7616_MOSI line and is used to output serial data from the slave MCU chip to the AD acquisition chip U7. It should be noted that when the model of the AD acquisition chip U7 is AD7616H, the slave serial data output pin PC12 is used.

[0115] Slave serial data input pin PC11: Slave serial data input pin PC11 is connected to 7616_MISOA line and is used for the slave MCU chip to input serial data from the AD acquisition chip U7. It should be noted that when the model of the AD acquisition chip U7 is AD7616H, the slave serial data input pin PC11 is used.

[0116] It should be noted that when the model of the AD acquisition chip U7 is AD7616H, the slave MCU chip adopts dual-channel serial data input.

[0117] Serial clock pin PC10: The serial clock pin PC10 is connected to the 7616_SCLK line. When the model of the AD acquisition chip U7 is AD7616H, the serial clock pin PC10 is used to receive the serial clock signal from the AD acquisition chip U7.

[0118] Serial current sampling pin PA15: The serial current sampling pin PA15 is connected to the 7616_CS line. When the model of the AD acquisition chip U7 is AD7616H, it is used to detect the current of the 7616 serial data line (one of them).

[0119] Synchronous clock pin PA14: The synchronous clock pin PA14 is connected to the SWCLK line. The synchronous clock pin PA14 is used to transmit a clock signal to synchronize the data transmission process.

[0120] Serial communication pin PA13: Serial communication pin PA13 is connected to the SWDIO line. Serial communication pin PA13 can send command data and receive information data returned by the chip.

[0121] LED light pins PA12, PA11, PC9: LED light pins PA12, PA11, PC9 are used for fault signal indication of CVT detected by three groups of slave machines respectively.

[0122] Serial data transmission pin PA10: The serial data transmission pin PA2 is connected to the MCU_USART1_TX line. The serial data transmission pin PA10 is used to send host / slave serial data, specifically, the host sends serial data to the first group of slaves and the first group of slaves sends serial data to the host.

[0123] Serial data receiving pin PA9: The serial data receiving pin PA9 is connected to the MCU_USART1_RX line. The serial data receiving pin PA9 is used to receive host / slave serial data, specifically for the host to receive serial data sent by the first group of slaves and for the first group of slaves to receive serial data sent by the host.

[0124] Digital-to-analog conversion pin PA8: The digital-to-analog conversion pin PA8 is connected to the 7616_CONVER line. When the model of the AD acquisition chip U7 is AD7616H, it is used for digital-to-analog conversion of the acquisition signal.

[0125] State feedback pin PC8: The state feedback pin PC8 is connected to the 7616_BUSY line. When the model of the AD acquisition chip U7 is AD7616H, it is used for processing state feedback of the AD acquisition chip U7.

[0126] Synchronous voltage input pin PB14: The synchronous voltage input pin PB14 is connected to the 220_SYNC line and is used to input a synchronous voltage signal.

[0127] Clock signal transmission pin PB13: The clock signal transmission pin PB13 is connected to the ROM_SCL line and is used for clock signal transmission between the host and the slave.

[0128] Serial current sampling pin PB12: The serial current sampling pin PB12 is connected to the 7616_CS line. When the model of the AD acquisition chip U7 is AD7616H, it is used to detect the current of the 7616 serial data line (the second).

[0129] like Fig.12 and Fig.13 As shown, further, the slave MCU also includes a slave power supply control circuit.

[0130] The slave power supply control circuit includes an AD battery control circuit, an MCU power supply control circuit, a wireless power supply control circuit, a first AD voltage conversion circuit, and a second AD voltage conversion circuit.

[0131] Among them, the AD battery control circuit is as follows Fig.14 As shown; MCU power control circuit as shown Fig.15 As shown; the wireless power control circuit is as follows Fig.16 As shown; the first AD voltage conversion circuit is as shown Fig.17 As shown; the second AD voltage conversion circuit is as shown Fig.18 shown.

[0132] The MCU power control circuit includes a linear regulator HE2210M533R; the wireless power control circuit includes a wireless power control circuit; the first AD voltage conversion circuit includes a linear regulator HE2210M550R; the second AD voltage conversion circuit includes a linear regulator HE2210M533R, so the slave power control circuit improves the voltage stability of the slave MCU, the slave wireless module, the AD acquisition module, and the wireless power module.

[0133] like Fig.19 As shown, the present application also provides a wired synchronization module suitable for a capacitive voltage transformer.

[0134] Furthermore, the online monitoring device includes a wired synchronization module, which is used to achieve clock synchronization between the host and each slave. Clock synchronization is achieved by connecting each device that can generate a clock (in this application, the device is: the host MCU chip and the slave MCU chip) to the SCL line. Each of the above devices may have its own independent clock, and the frequency, period, phase and duty cycle of each clock signal may be different. As a result of "wire and", the low level width of the actual clock generated on the SCL line is determined by the device with the longest low level duration, and the high level width is determined by the device with the shortest high level duration.

[0135] The wired synchronization module includes: a synchronization current detection circuit and a timing circuit.

[0136] The synchronous current detection circuit includes a current detection chip U1. In the present application, the model of the current detection chip U1 is REF3318AIDBZR or the like.

[0137] The current detection chip U1 includes a signal input pin VI, and the signal input pin VI is connected to the 3.3V working voltage synchronization signal line VDD3.3V_SYNC. The current detection chip U1 includes a signal output pin VO, and the signal output pin VO is connected to the current detection signal output terminal VREF. The current detection chip U1 includes a ground pin GND, and the ground pin GND is connected to the ground terminal. A capacitor C1 is connected in series between the ground pin GND and the signal input pin VI, and a capacitor C2 is connected in series between the ground pin GND and the signal output pin VO.

[0138] The timing circuit includes a connector J1, an array resistor, a reverse protection diode D1, an operational amplifier comparator U2, and an operational amplifier comparator U3.

[0139] In the present application, the connector J1 adopts a single-row 2-pin connector of model HDR1x2, etc. The two interfaces of the connector J1 are respectively connected to three array resistors and then connected to two input terminals of the operational amplifier comparator U2.

[0140] In the present application, the model of the reverse protection diode D1 is BAT54S, etc. A reverse protection diode D1 and a capacitor C5 are connected in parallel between the two input terminals 2 and 3 of the operational amplifier comparator U2.

[0141] In the present application, the model of the operational amplifier comparator U2 is INA333AIDGKR, etc., and the operational amplifier comparator U2 is a single operational amplifier integrated chip; the model of the operational amplifier comparator U3 is ADA4891-2, etc., and the operational amplifier comparator U3 is a dual operational amplifier integrated chip.

[0142] The two input terminals 2 and 3 of the operational amplifier comparator U2 are connected in series with a resistor and then grounded. The positive voltage terminal 7 of the operational amplifier comparator U2 is connected to the 3.3V working voltage synchronization signal line VDD3.3V_SYNC, and the positive voltage terminal 7 of the operational amplifier comparator U2 is connected in series with the capacitor C3 and then grounded; the negative voltage terminal 4 of the operational amplifier comparator U2 is grounded. A resistor R2 is connected in series between the battery terminal 1 and the normally closed contact terminal 8 of the operational amplifier comparator U2. The battery terminal 5 of the operational amplifier comparator U2 is connected in series with a resistor R6 and then connected to the current detection signal output terminal VREF. The output terminal 6 of the operational amplifier comparator U2 is connected in series with a resistor R11 and then connected to the negative input terminal A2 of the operational amplifier comparator U3.

[0143] The positive input terminal A3 of the operational amplifier comparator U3 is connected in series with a resistor R13 and then connected to the current detection signal output terminal VREF. The positive voltage terminal 8 of the operational amplifier comparator U3 is connected to the 3.3V working voltage synchronization signal line VDD3.3V_SYNC, and the positive voltage terminal 8 of the operational amplifier comparator U3 is connected in series with a capacitor C4 and then grounded; the negative voltage terminal 4 of the operational amplifier comparator U3 is grounded. The output terminal A1 of the operational amplifier comparator U3 is connected in series with a resistor R10 and then connected to the positive input terminal A3 of the operational amplifier comparator U3. The output terminal A1 of the operational amplifier comparator U3 is connected in series with resistors R1 and R4 in sequence and then grounded. The 220_SYNC line is connected in series with resistor R3 and then connected between resistors R1 and R4.

[0144] The wired synchronization module performs timing state conversion through the logic operation of the timing circuit, so that the clock (VDD3.3V_SYNC) of each slave is synchronized with the clock (220_SYNC) of the host. Specifically, the wired synchronization module receives the host time reference signal (220VSYNC) and outputs the time synchronization signal and time information (VDD3.3V_SYNC) to the slave according to the required time accuracy, so that the slave clock signal is aligned and synchronized with the host clock signal, and then the AD acquisition module of each slave can synchronously collect the fault signals of each group of CVT transformers.

[0145] Based on the above-mentioned online monitoring device for capacitor voltage transformer, the present application also provides a wireless networking and communication method for capacitor voltage transformer, including: At least one host and a plurality of slaves are provided, and wireless communication between the host and the plurality of slaves is performed; The host and each slave exchange information of wireless synchronization messages: the host converts the constructed Ethernet format synchronization message into a wireless network format message and transmits it to the slave; The host sends a time setting command to the slave regularly by broadcasting a wireless network format message to the slave; The host converts the received wireless network message into Ethernet format, determines the message type and extracts its key information for further logical processing; The host broadcasts a wake-up command to the slave to wake up the slave. At other times, the slave is in sleep mode. After the slave is disconnected or lost, the host periodically wakes up the slave and connects the slave to the wireless network.

[0146] In this application, the host sends a time setting command to the slave regularly for 1 day.

[0147] Furthermore, in a wireless network scenario, the transmission of messages between the host and each slave relies on the 802.11 protocol. At the data link layer, the 802.1AS messages required in the path delay measurement and time synchronization measurement process are encapsulated into 802.11 data frames for protocol transmission.

[0148] The 802.1AS message includes: (1) majorSdoId: occupies 4 bits.

[0149] (2) messageType: occupies 4 bits and indicates the type of message. It is used to distinguish event messages from ordinary messages.

[0150] Its most significant bit is 0 for event message and 1 for normal message.

[0151] (3) minorVersionPTP: occupies 4 bits. For transmitted messages, this value is 1. For received messages, this value is Value is ignored.

[0152] (4) versionPTP: occupies 4 bits and indicates the version number of the protocol. The version number of the gPTP message is 2.

[0153] (5) messageLength: occupies 16 bits and indicates the total length of the message. The next one.

[0154] (6) domainNumber: occupies 8 bits and indicates the gPTP domain number of the device sending the message.

[0155] (7) minorSdoId: occupies 8 bits, the value is specified. If the received message is not a certain value specified, is ignored.

[0156] (8) Flags: Occupies 16 bits, and each bit of each node represents a characteristic of the network node.

[0157] (9) correctionField: occupies 64 bits and represents the correction field.

[0158] (10) messageTypeSpecific: occupies 32 bits and indicates the specific type of message.

[0159] (11) sourcePortIdentity: occupies 80 bits. This value is the PTPPort of the PTP port that transmits the PTP message. identity attribute.

[0160] (12) sequenceId, occupies 16 bits, indicating the sequence number. Each time a message of the same type appears, the sequence number increases by 1. When the sequence numbers of different messages are the same, it means that these messages are related. If the column numbers are the same, it means that the two frames are related. The time information carried in Follow_Up is the same for this same sequence. The Sync frame of the number.

[0161] (13)controlField: occupies 8 bits and its value is 0.

[0162] (14) logMessageInterval: occupies 8 bits and represents the message sending interval in logarithmic form.

[0163] Furthermore, in order to minimize the interference of other wireless signals in the same frequency band, this application adopts the structure of FPGA+SDR to realize the wireless message transmission in a specific frequency band. In the wireless message receiving part, firstly, the analog-to-digital conversion part directly connected to the SDR is designed to complete the reception and processing of the RF signal, then the data is demodulated and the bit stream is converted through OFDM and the reception time of the message is recorded, and finally the data and the message reception time are sent to the host server for subsequent processing.

[0164] Furthermore, in the initial stage, the host server sends the gating time slot and other configuration information to complete the configuration of the sending queue gating list, and then schedules the transmission of the synchronization message data output by the host server according to the configured gating. Secondly, the data output rate is matched for the RF signal and the digital-to-analog conversion is completed. Finally, the wireless message is sent by transmitting it across the clock domain to the host wireless module.

[0165] Furthermore, the host periodically sends a time setting command to the slave through a broadcast command of a wireless network format message of the slave, including: The master node receives and parses the status information messages reported by each slave node, extracts the three decision attributes of the link congestion coefficient, link topology and clock source parameter set for the master clock selection, and establishes a master clock selection model based on the received information.

[0166] The master node calculates the optimal weight values ​​corresponding to the three decision attributes according to the multi-attribute decision algorithm, substitutes them into the calculated clock attribute values ​​of each node, compares them to obtain the best master clock node and generates a redundant clock sequence.

[0167] The host server periodically queries the best master clock node, sets the timeout threshold, and restarts the timeout count when receiving a new status report message. If the synchronization centralized control node timeout count does not receive new report information within the threshold range, it is assumed that the master clock node has unexpectedly failed, and the master clock node information and redundant clock sequence are updated and sent to each slave node.

[0168] Monitor whether there are new time-sensitive nodes joining the network. If there are new nodes joining, receive and calculate the clock attribute value of the node, compare it with the original main clock node and redundant clock sequence, and update the above information.

[0169] Furthermore, the host server determines whether the input data message is a synchronization message. If it is not a synchronization message, it is directly output to the subsequent switch function module. If it is a synchronization message, the corresponding synchronization information is recorded or extracted according to the specific synchronization message type.

[0170] Furthermore, the host server receives the redundant clock sequence table sent by the master node, confirms the best master clock identification number, and updates the local redundant clock sequence table. The synchronization message sent by the slave node contains its own clock source parameter information and status information messages of network information such as link topology and link congestion, which are reported to the master node.

[0171] Furthermore, the present application adopts the mode of master node request-slave node response, sends or responds to delay request messages, and calculates the link delay value of adjacent nodes considering the adjacent frequency ratio and link asymmetry. The Kalman filter algorithm is used to filter the measured value to reduce the synchronization error. At the same time, the link congestion is estimated by sending a link detection packet, and the difference between the departure interval time and the arrival interval time of the data packet is compared to determine whether it exceeds the time threshold to determine the link congestion coefficient of the adjacent link of the measurement node.

[0172] Furthermore, the host constructs or forwards synchronization information messages according to the local port role. If all ports are master ports, a two-step method is used to construct synchronization messages and follow-up messages to be sent to other nodes. If a port is a slave clock port and there is a master port in the other ports, the synchronization message is received and the local synchronization clock deviation is calculated and corrected. At the same time, the local residence time is added to the correction field of the synchronization message and forwarded to the other slave clock ports. In other cases, only the synchronization message is received and no forwarding operation is performed.

[0173] The wireless networking and communication method of the capacitive voltage transformer proposed in this application, as well as the related technical implementation details, bring the following significant beneficial effects: 1. Improve monitoring efficiency and accuracy: By setting up wireless communication between the host and multiple slaves, real-time monitoring of capacitive voltage transformers (CVTs) is achieved, greatly improving the efficiency and accuracy of monitoring. The host can send time setting commands to the slaves at regular intervals to ensure time synchronization of all devices in the entire network, thereby ensuring the real-time and accuracy of monitoring data.

[0174] 2. Reduce communication interference and energy consumption: The FPGA+SDR structure is used to realize wireless message transmission in a specific frequency band, which can effectively reduce the interference of other wireless signals in the same frequency band and improve the stability and reliability of communication. At the same time, the host broadcasts a wake-up command to the slave to wake up the slave, and puts the slave in sleep mode at other times, which greatly reduces energy consumption.

[0175] 3. Optimize master clock selection and redundancy mechanism: The host receives and analyzes the status information messages reported by each slave node, establishes a master clock selection model, and calculates the optimal weight value based on the multi-attribute decision algorithm to select the best master clock node. At the same time, a redundant clock sequence is also established. When the master clock node fails, the master clock node information and redundant clock sequence can be quickly updated and sent to each slave node, ensuring the stability and reliability of the network.

[0176] 4. Improve synchronization accuracy and anti-interference ability: This application adopts the mode of master node request-slave node response, sends or responds to delay request messages, and calculates the link delay value of adjacent nodes considering the adjacent frequency ratio and link asymmetry. At the same time, the Kalman filter algorithm is used to filter the measured value to further reduce the synchronization error. In addition, the link congestion is estimated by sending link detection packets, and the communication strategy is adjusted according to the link congestion coefficient, which improves the anti-interference ability of the network.

[0177] 5. Flexibility and scalability: The wireless networking and communication method of the present application has high flexibility and scalability. The host can dynamically update the master clock node information and redundant clock sequence according to whether there are new time-sensitive nodes joining the network. At the same time, the slave node can also perform corresponding operations according to the command of the host, realizing dynamic adjustment and expansion of the network.

[0178] 6. Reduce maintenance costs: By implementing wireless networking and communication of CVT, the wiring and maintenance work required for wired connections are reduced, reducing maintenance costs. At the same time, since the operating status of CVT can be monitored in real time, potential problems can be discovered and handled in a timely manner, which also reduces downtime and maintenance costs caused by equipment failure.

[0179] To sum up, the wireless networking and communication method of the capacitive voltage transformer proposed in this application has many beneficial effects, which not only improves the monitoring efficiency and accuracy, but also reduces communication interference and energy consumption, optimizes the master clock selection and redundancy mechanism, improves synchronization accuracy and anti-interference ability, enhances flexibility and scalability, and reduces maintenance costs.

[0180] Based on the above-mentioned online monitoring device of a capacitor voltage transformer, the present application provides an online monitoring method of a capacitor voltage transformer, and the online monitoring method of a capacitor voltage transformer comprises: At least one host and a plurality of slaves are provided, and wireless and / or wired communication is performed between the host and the plurality of slaves; Each slave includes a slave MCU and an AD acquisition module. The slave MCU drives the AD acquisition module to collect each CVT transformer fault signal. Each AD acquisition module starts to collect CVT transformer fault signal data at the same time to ensure the consistency and synchronization of the CVT transformer fault signal data acquisition time. The AD acquisition module transmits the CVT transformer fault signal data to the slave MCU, and each slave MCU transmits the CVT transformer fault signal data to the host through wireless and / or wired signal transmission; The host machine reads and saves the CVT transformer fault signal data of all slave machines; The master compares the CVT transformer fault signal data of multiple slaves at the same time. The master compares the historical CVT transformer fault signal data of the same slave, analyzes the data performance, and obtains the fault point; The host sends out an alarm message based on the fault point.

[0181] Through the above settings, the online monitoring method of the capacitive voltage transformer of the present application can realize the fault signal collection of multiple groups of CVT transformers.

[0182] As an implementation method, each AD acquisition module simultaneously starts to collect CVT transformer fault signal data including: the AD acquisition module detects the secondary side voltage value, calculates the near-end voltage difference U2 value of the two capacitors C1 and C2 of the CVT transformer, and thus determines the far-end voltage difference voltage value U1 of C1 and C2 on the primary side; The host detects the size of U2 to determine whether capacitors C1 and C2 in the composition of the CVT transformer are damaged, whether the damage is at C1 or C2, and the number of damaged capacitors.

[0183] Furthermore, the host determines the specific CVT transformer fault by judging the magnitude relationship between the secondary voltage U2 and the rated value of the secondary voltage U2 in the normal state, as well as the voltage change rate K: When the secondary voltage U2 is not output, it is judged that the primary and secondary windings of the intermediate transformer are open or short-circuited; When the secondary voltage U2 decreases, it is judged that the capacitor C2 is broken down; When the secondary voltage U2 increases, it is judged that the capacitor C1 is broken down; When the waveform of the secondary voltage U2 is distorted, it is judged that the CVT transformer is heavily contaminated, the line harmonic content is high, the circuit breaker is frequently reclosed, and the neutral point voltage is increased.

[0184] The present application provides monitoring data obtained by the online monitoring method of the above-mentioned capacitor voltage transformer, such as Fig. 20 shown.

[0185] As another implementation method, the A phase, B phase and C phase of the CVT transformer are connected to a current transformer, and the value of the three-phase leakage current is sent out through the current transformer. The three current transformers are connected in parallel with a resistor, and the three current transformers are grounded through the resistor. A capacitor is connected in parallel next to the resistor to ensure the safety of the detection circuit.

[0186] Since one of the capacitor components of the C2 capacitor voltage divider of the CVT breaks down, the capacitance of C2 increases, which is 4.35% larger than the rated capacitance (the capacitor voltage divider C2 is composed of 23 identical components in series. According to calculations, the breakdown of one component will increase the capacitance by 4.3%), thus causing the capacitor voltage divider ratio to change, resulting in a drop in the secondary voltage of the CVT. Therefore, it is more sensitive to monitor the secondary voltage change of the CVT or the series resistance of the three-phase current transformer after interconnection, and monitor its resistance U0.

[0187] Furthermore, since three-phase voltage fluctuation or imbalance will affect the measurement, correction parameters can be added to the measurement system. The three-phase current and voltage can be measured synchronously to calculate the coefficients kA, kB, and kC of the three phases respectively. The current values ​​of the three phases are multiplied by 1 / kA, 1 / kB, and 1 / kC respectively, and the leakage current vectors are added to the rated voltage, thereby eliminating the impact caused by three-phase voltage fluctuation or imbalance.

[0188] Furthermore, if the three-phase voltage imbalance of the CVT is detected to be greater than 3%, and the voltages of other windings (CVT generally has three windings a1x1, a2x2, afxf) are compared, if the change trends are consistent, the defect should be reported and the change in capacitance should be observed simultaneously. If the change rate exceeds 4%, the power should be cut off to take it out of operation.

[0189] Furthermore, by collecting the capacitance and dielectric loss factors of the CVT online and comparing them with the same-phase equipment on the same busbar based on the changing trends of the indicators, if they continue to increase over a certain period of time, it indicates that there is a problem with the CVT insulation.

[0190] To summarize, the online monitoring method of the capacitive voltage transformer of the present application, when a short circuit fault occurs in the capacitive voltage divider of the CVT and the online monitoring capacitance and dielectric loss factor change significantly, the capacitance change rate can be combined with the secondary voltage curve of the CVT and combined with the comprehensive judgment of the three-phase changes to analyze the insulation defects of the CVT.

[0191] Furthermore, during actual operation, the heat generation of parts with insulation defects will usually increase. By using infrared temperature measurement of CVT to monitor the temperature changes of CVT, and coordinating with online monitoring fault diagnosis, we can strengthen the monitoring of CVT operation heating conditions and effectively prevent accidents.

[0192] The online monitoring method of the capacitive voltage transformer of the present application and its implementation method bring the following significant beneficial effects: 1. Real-time monitoring and fault warning: By setting up a host and multiple slaves, real-time monitoring of the capacitive voltage transformer (CVT) is achieved, which can promptly detect abnormal conditions of the CVT, provide early warning information to operation and maintenance personnel, and avoid power grid accidents caused by equipment failure.

[0193] 2. High-precision data acquisition: The AD acquisition module is used to simultaneously start collecting CVT transformer fault signal data, which ensures the time consistency and synchronization of data acquisition and improves the accuracy and reliability of the data.

[0194] 3. Intelligent fault analysis: The host can compare the CVT transformer fault signal data of multiple slaves at the same time, as well as the historical CVT transformer fault signal data of the same slave, determine the fault point through data analysis, and issue an alarm message, thus realizing intelligent fault analysis.

[0195] 4. Accurate fault location: By detecting the secondary side voltage value, calculating the proximal voltage difference U2 value of the two capacitors C1 and C2 of the CVT transformer, and judging the far-end voltage difference voltage value U1 of C1 and C2 on the primary side, the fault location of the CVT transformer can be accurately judged, including whether the capacitors C1 and C2 are damaged, the specific damage location and the number of damaged capacitors.

[0196] 5. Multiple fault judgment bases: In addition to judging faults by voltage values, a comprehensive judgment can also be made by combining multiple parameters such as the voltage change rate K, the voltage U0 of the series resistor after the three-phase current transformer is interconnected, thereby improving the accuracy of fault judgment.

[0197] 6. Eliminate the influence of three-phase voltage fluctuations: Correction parameters are added to the measurement system, and the three-phase current and voltage are measured synchronously to calculate the coefficients of each of the three phases, thereby eliminating the impact of three-phase voltage fluctuations or imbalances and improving measurement accuracy.

[0198] 7. Comprehensive judgment of insulation defects: By collecting the capacitance and dielectric loss factors of the CVT online, combined with the secondary voltage curve and three-phase changes of the CVT, the insulation defects of the CVT can be comprehensively judged, thereby improving the reliability and accuracy of fault judgment.

[0199] 8. Infrared temperature measurement auxiliary monitoring: By performing infrared temperature measurement on CVT, monitoring the temperature changes of CVT, and coordinating with online monitoring fault diagnosis, the monitoring of CVT operation heating conditions is strengthened, effectively preventing accidents.

[0200] 9. Reduce maintenance costs: Through real-time monitoring and intelligent fault analysis, potential problems can be discovered and dealt with in a timely manner, reducing downtime and maintenance costs caused by equipment failure.

[0201] 10. Improve grid stability: Real-time monitoring and fault warning of CVT are realized, the stability and reliability of the power grid are improved, and the safe operation of the power grid is ensured.

[0202] In summary, the online monitoring method of the capacitive voltage transformer of the present application and its implementation method have many beneficial effects, which not only improve the monitoring efficiency and accuracy, but also reduce the maintenance cost and improve the stability and reliability of the power grid.

[0203] It should be noted that the words "first", "second" and similar words used in the specification and claims of this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "a" do not indicate a quantitative limitation, but indicate the existence of at least one. "Multiple" or "several" means at least two. Unless otherwise specified, words such as "front", "back", "left", "right", "bottom" and / or "top" are only for the convenience of description and are not limited to one position or one spatial orientation. Words such as "include" or "comprise" mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, and may include electrical connections, whether direct or indirect.

[0204] The singular forms "a", "said" and "the" used in this specification and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0205] It should be understood that those skilled in the art can make improvements or changes based on the above description, and all these improvements and changes should fall within the scope of protection of the claims attached to this application.

Claims

1. A wireless networking and communication method for capacitive voltage transformer, characterized in that: The wireless networking and communication method of the capacitive voltage transformer comprises: At least one host and a plurality of slaves are provided, and wireless communication between the host and the plurality of slaves is performed; The host and each slave exchange information of wireless synchronization messages: the host converts the constructed Ethernet format synchronization message into a wireless network format message and transmits it to the slave; The host sends a time setting command to the slave regularly by broadcasting a wireless network format message to the slave; The host converts the received wireless network message into Ethernet format, determines the message type and extracts its key information for further logical processing; The host broadcasts a wake-up command to the slave to wake up the slave. At other times, the slave is in sleep mode. After the slave is disconnected or lost, the host periodically wakes up the slave and connects the slave to the wireless network.

2. The wireless networking and communication method of a capacitive voltage transformer according to claim 1, characterized in that: In the wireless network scenario, the transmission of messages between the host and each slave relies on the 802.11 protocol. At the data link layer, the 802.1AS messages required in the path delay measurement and time synchronization measurement process are encapsulated into 802.11 data frames for protocol transmission.

3. The wireless networking and communication method of a capacitive voltage transformer according to claim 1, characterized in that: The FPGA+SDR structure is used to realize wireless message transmission in a specific frequency band. In the wireless message receiving part, the reception and processing of the RF signal is completed through the analog-to-digital conversion part directly connected to the SDR. Secondly, the data is demodulated and the bit stream is converted through OFDM, and the message reception time is recorded. Finally, the data and the message reception time are sent to the host server for subsequent processing.

4. The wireless networking and communication method of capacitive voltage transformer according to claim 3, characterized in that: In the initial stage, the host server sends the gating time slot and other configuration information to complete the configuration of the sending queue gating list. Then, the transmission of the synchronous message data output by the host server is scheduled according to the configured gating. Secondly, the data output rate is matched for the RF signal and the digital-to-analog conversion is completed. Finally, the wireless message is sent to the host wireless module through cross-clock domain transmission.

5. The wireless networking and communication method of capacitive voltage transformer according to claim 1, characterized in that: The host sends a time setting command to the slave by broadcasting a wireless network format message to the slave, including: The master node receives and parses the status information messages reported by each slave node, extracts the three decision attributes of the link congestion coefficient, link topology and clock source parameter set for the master clock selection, and establishes a master clock selection model based on the received information; The master node calculates the optimal weight values ​​corresponding to the three decision attributes according to the multi-attribute decision algorithm, substitutes them into the calculated clock attribute values ​​of each node, compares them to obtain the best master clock node and generates a redundant clock sequence; The host server periodically queries the best master clock node, sets a timeout threshold, and restarts the timeout count when receiving a new status report message. If the synchronization centralized control node does not receive new report information within the threshold range, it is assumed that the master clock node has unexpectedly failed, and the master clock node information and redundant clock sequence are updated and sent to each slave node; Monitor whether there are new time-sensitive nodes joining the network. If there are new nodes joining, receive and calculate the clock attribute value of the node, compare it with the original main clock node and redundant clock sequence, and update the above information.

6. The wireless networking and communication method of capacitive voltage transformer according to claim 5, characterized in that: The host server determines whether the input data message is a synchronization message. If it is not a synchronization message, it is directly output to the subsequent switch function module. If it is a synchronization message, the corresponding synchronization information is recorded or extracted according to the specific synchronization message type.

7. The wireless networking and communication method of capacitive voltage transformer according to claim 5, characterized in that: The host server receives the redundant clock sequence table sent by the master node, confirms the best master clock identification number, and updates the local redundant clock sequence table; the synchronization message sent by the slave node contains its own clock source parameter information and status information messages of network information such as link topology and link congestion, and is reported to the master node.

8. The wireless networking and communication method of capacitive voltage transformer according to claim 7, characterized in that: The master node request-slave node response mode is adopted to send or respond to delay request messages, and the link delay value of the adjacent node is calculated considering the adjacent frequency ratio and link asymmetry; the Kalman filter algorithm is used to filter the measured value to reduce the synchronization error; at the same time, the link congestion situation is estimated by sending link detection packets, and the difference between the departure interval and the arrival interval of the data packet is compared to see if it exceeds the time threshold to determine the link congestion coefficient of the adjacent link of the measurement node.

9. The wireless networking and communication method of capacitive voltage transformer according to claim 6, characterized in that: The host constructs or forwards synchronization information messages according to the local port role; if all ports are master ports, a two-step method is used to construct synchronization messages and follow-up messages to other nodes; If a port is a slave clock port and the other ports have master ports, it receives the synchronization message and calculates and corrects the local synchronization clock deviation. At the same time, it adds the local residence time to the synchronization message correction field and forwards it to the other slave clock ports. In other cases, it only receives the synchronization message and does not forward it.

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