Array substrate, manufacturing method and electronic paper display

Abstract

The invention discloses an array substrate and a manufacturing method thereof, and an electronic paper display. The manufacturing method of the array substrate comprises the following steps: providing a substrate; a scanning line, a grid electrode, a grid electrode insulating layer, an active layer, a data line, a source electrode, a drain electrode, an insulating layer and a flat layer are manufactured on a substrate, then a third metal layer is formed on the flat layer, a second metal layer is etched, a patterned metal pixel electrode is formed, and the metal pixel electrode is electrically connected with the corresponding drain electrode; after the flat layer is etched and before the third metal layer is formed, the surface of the flat layer is subjected to roughening treatment and / or a contact dielectric layer is formed on the surface of the flat layer, and the contact dielectric layer is used for increasing the adhesive force between the flat layer and the third metal layer. The surface of the flat layer is roughened and / or the contact dielectric layer is formed on the surface of the flat layer, so that the adhesive force between the flat layer and the third metal layer can be increased, and the metal pixel electrode is prevented from falling off to cause product defects.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic paper displays, and in particular to an array substrate and a manufacturing method thereof, and an electronic paper display. Background Art

[0002] Display panels are thin, durable, and energy-saving and environmentally friendly with low power consumption, but they need to be used with a backlight, resulting in thick modules and high costs. Electronic paper displays (reflective displays) have become a type of display that meets the needs of the public. Electronic paper displays can use external light sources to display images, unlike LCD displays that require backlights. Therefore, in outdoor environments with strong sunlight, the information on the electronic paper can still be clearly seen without viewing angle issues. In addition, electronic paper displays are now widely used in electronic readers (such as e-books, e-newspapers) or other electronic components (such as price tags) due to their advantages such as power saving, high reflectivity and contrast ratio.

[0003] Existing electronic paper displays usually use E-Ink microcapsule technology (microcapsule electronic ink technology), SiPix microcup technology (microcup electrophoretic display technology), Bridgestone electronic liquid powder technology, cholesterol liquid crystal display (CLCD) technology, micro-electromechanical system (MEMS) technology or electrowetting technology. Among them, electronic paper displays are also driven by thin film transistor array substrates (Thin Film Transistor Array Substrate, TFT Array Substrate). Unlike liquid crystal display panels, electronic paper displays display by reflecting ambient light. Therefore, the thin film transistor array substrate needs to be set to a non-transparent state to prevent light from passing through the electronic paper display and affecting the display effect. The pixel electrodes of conventional liquid crystal display panels are usually made of transparent materials such as indium tin oxide (ITO) or indium zinc oxide (IZO), while the pixel electrodes of electronic paper displays need to be made of opaque metals, such as molybdenum (Mo), aluminum (Al), copper (Cu) and other metals, or opaque metals with transparent conductive materials to support the pixel opening area. However, the array substrate of existing electronic paper displays is directly covered with a metal layer after the OC (flat layer) is made. Due to the poor adhesion between the metal material and the OC, peeling is very likely to occur, resulting in product defects. Summary of the invention

[0004] In order to overcome the shortcomings and deficiencies in the prior art, the present invention aims to provide an array substrate and a manufacturing method thereof, and an electronic paper display, so as to solve the problem that the pixel electrodes of the array substrate in the prior art electronic paper display are easy to fall off.

[0005] The purpose of the present invention is achieved through the following technical solutions: The present invention provides a method for manufacturing an array substrate, comprising: providing a substrate; forming a first metal layer above the substrate, etching the first metal layer to form a patterned scan line and a gate, wherein the gate is conductively connected to the scan line; forming a gate insulating layer covering the first metal layer on the substrate; forming a semiconductor layer above the gate insulating layer, and etching the semiconductor layer to form an active layer corresponding to the gate; forming a second metal layer covering the semiconductor layer above the gate insulating layer, etching the second metal layer to form a patterned data line, a source electrode and a drain electrode, wherein the source electrode is conductively connected to the data line, and the source electrode and the drain electrode are connected via the active layer; forming an insulating layer covering the semiconductor layer and the second metal layer above the gate insulating layer, and etching the insulating layer to form a first opening corresponding to the drain electrode; forming a planar layer covering the insulating layer above the insulating layer, etching the planar layer to form a second opening corresponding to the drain electrode; forming a third metal layer above the planar layer, etching the second metal layer to form a patterned metal pixel electrode, wherein the metal pixel electrode is electrically connected to the corresponding drain electrode through the first opening and the second opening; After etching the planar layer and before forming the third metal layer, the surface of the planar layer is roughened and / or a contact dielectric layer is formed on the surface of the planar layer, wherein the contact dielectric layer is used to increase the adhesion between the planar layer and the third metal layer.

[0006] Further, including: After etching the planar layer and before forming the third metal layer, a plasma gas sputtering process is used to roughen the surface of the planar layer.

[0007] Furthermore, the contact dielectric layer is made of conductive material, and the manufacturing method includes: After etching the planar layer and before forming the third metal layer, the contact dielectric layer is formed on the surface of the planar layer, and the contact dielectric layer is etched to form a first sub-pixel electrode corresponding to the metal pixel electrode, and the surface of the first sub-pixel electrode is in direct contact with the surface of the metal pixel electrode.

[0008] Furthermore, the contact dielectric layer is made of insulating material, and the manufacturing method includes: After etching the planar layer and before forming the third metal layer, the contact dielectric layer is formed on the surface of the planar layer, the contact dielectric layer is etched to form a third opening corresponding to the drain, and the metal pixel electrode is electrically connected to the corresponding drain through the first opening, the second opening and the third opening.

[0009] Furthermore, the contact medium layer covers the inner side wall of the second opening.

[0010] Further, including: A transparent conductive layer is formed on the third metal layer, and the transparent conductive layer is etched to form a second sub-pixel electrode corresponding to the metal pixel electrode, wherein a surface of the second sub-pixel electrode is in direct contact with a surface of the metal pixel electrode.

[0011] Further, including: After etching the semiconductor layer and before forming the second metal layer, a channel protection layer is formed above the active layer, wherein the channel protection layer is located in a channel region between the source electrode and the drain electrode.

[0012] Further, including: The planar layer is firstly etched to form a second opening corresponding to the drain electrode, and then the insulating layer is etched to form a first opening corresponding to the drain electrode.

[0013] The present application also provides an array substrate, which is manufactured using the array substrate manufacturing method as described above.

[0014] The present application also provides an electronic paper display, comprising an opposing substrate, an array substrate arranged opposite to the opposing substrate, and a plurality of ink capsules arranged between the opposing substrate and the array substrate, wherein the array substrate is manufactured by the array substrate manufacturing method as described above; the ink capsules correspond one-to-one to the pixel units, ink particles are arranged in the ink capsules, a common electrode is arranged on the opposing substrate, and pixel electrodes corresponding one-to-one to the pixel units are arranged on the array substrate, and the pixel electrodes include the metal pixel electrodes.

[0015] The beneficial effect of the present invention is that by roughening the surface of the flat layer and / or forming a contact dielectric layer on the surface of the flat layer after etching the flat layer and before forming the third metal layer, the adhesion between the flat layer and the third metal layer can be increased to avoid the metal pixel electrode from falling off and causing product defects. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a structural schematic diagram of an array substrate in Embodiment 1 of the present invention.

[0017] Figures 2a to 9b It is a schematic flow chart of a method for manufacturing an array substrate in Embodiment 1 of the present invention.

[0018] Fig.10 It is a structural schematic diagram of an array substrate in Embodiment 2 of the present invention.

[0019] Figures 11 to 14 It is a schematic flow chart of a method for manufacturing an array substrate in the second embodiment of the present invention.

[0020] Fig.15 It is a structural schematic diagram of an array substrate in Embodiment 3 of the present invention.

[0021] Figures 16 to 19 It is a schematic flow chart of a method for manufacturing an array substrate in Embodiment 3 of the present invention.

[0022] Fig. 20 It is a schematic structural diagram of the electronic paper display in the present invention in an initial state.

[0023] Fig.21 It is a schematic diagram of the structure of the electronic paper display in the present invention when in a black state.

[0024] Fig. 22 It is a schematic structural diagram of the electronic paper display in the present invention in the white state.

[0025] Fig.23 It is a structural schematic diagram of the electronic paper display in the present invention when in display state. DETAILED DESCRIPTION

[0026] In order to further explain the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, the specific implementation, structure, features and effects of the array substrate and manufacturing method, and the electronic paper display proposed in the present invention are described in detail below in conjunction with the accompanying drawings and preferred embodiments: [Example 1] Figure 1 is a schematic structural diagram of an array substrate in Embodiment 1 of the present invention, Figures 2a to 9b FIG. 1 is a flow chart of a method for manufacturing an array substrate in Embodiment 1 of the present invention. Figures 1 to 9bAs shown, an array substrate provided by Embodiment 1 of the present invention includes: The substrate 10 may be made of glass, quartz, silicon, acrylic or polycarbonate. The substrate 10 may also be a flexible substrate. Suitable materials for the flexible substrate include, for example, polyethersulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinyl chloride (PVC), polyethylene terephthalate (PET) or a combination thereof.

[0027] A first metal layer 11 is provided on the substrate 10, and the first metal layer 11 includes a scan line 111 and a gate 112, and the gate 112 is conductively connected to the scan line 111. The first metal layer 11 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above metals such as Al / Mo, Cu / Mo, etc.

[0028] The gate insulating layer 101 is disposed above the first metal layer 11 and covers the scan line 111 and the gate 112. The gate insulating layer 101 is made of silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two.

[0029] The semiconductor layer 12 is disposed above the gate insulating layer 101, and includes an active layer 121 corresponding to the gate 112. The semiconductor layer 12 may be made of a metal oxide material, such as indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), zinc tin oxide (ZnSnO), gallium tin oxide (GaSnO), gallium zinc oxide (GaZnO), indium gallium zinc oxide (IGZO), or indium gallium zinc tin oxide (IGZTO).

[0030] A channel protection layer 131 is disposed on the upper surface of the active layer 121. The channel protection layer 131 is located in the channel region between the source 142 and the drain 143. The channel protection layer 131 can protect the active layer 121 and prevent external ambient light and subsequent processes (etching process of the second metal layer 14) from affecting the performance of the active layer 121.

[0031] The second metal layer 14 is disposed above the gate insulating layer 101 and the semiconductor layer 12. The second metal layer 14 includes a data line 141, a source electrode 142, and a drain electrode 143. The data line 141 is conductively connected to the source electrode 142. The source electrode 142 is conductively connected to the drain electrode 143 through the active layer 121. The plurality of scanning lines 111 and the plurality of data lines 141 are mutually insulated and cross-defined to form a plurality of pixel units. The second metal layer 14 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above metals such as Al / Mo, Cu / Mo, etc.

[0032] The insulating layer 102 is disposed above the gate insulating layer 101, and covers the data line 141, the source electrode 142, the drain electrode 143, and the active layer 121. The insulating layer 102 is provided with a first opening 102a corresponding to the drain electrode 143, and the drain electrode 143 is exposed from the first opening 102a. The material of the insulating layer 102 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of the two.

[0033] The flat layer 103 is disposed above the insulating layer 102, and the flat layer 103 is provided with a second opening 103a corresponding to the first opening 102a. The first opening 102a and the second opening 103a together form a contact hole H, and the drain 143 is exposed from the contact hole H. Optionally, the size of the second opening 103a is larger than the size of the first opening 102a, so that the first opening 102a is completely exposed from the second opening 103a.

[0034] The contact dielectric layer 16 and the third metal layer 15 are sequentially arranged above the planar layer 103, and the contact dielectric layer 16 is used to increase the adhesion between the planar layer 103 and the third metal layer 15. In this embodiment, the contact dielectric layer 16 is made of conductive material, the third metal layer 15 includes a metal pixel electrode 151, and the contact dielectric layer 16 includes a first sub-pixel electrode 161 corresponding to the metal pixel electrode 151. The surface of the first sub-pixel electrode 161 is in direct contact with the surface of the metal pixel electrode 151. The first sub-pixel electrode 161 and the metal pixel electrode 151 together form a pixel electrode PE to reduce the impedance of the pixel electrode PE. The pixel electrode PE is electrically connected to the corresponding drain 143 through the contact hole H, and the pixel electrode 151 is a block electrode corresponding to the pixel unit. The contact dielectric layer 16 may be made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO). The third metal layer 15 may be made of a metal such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above metals such as Al / Mo, Cu / Mo, etc. The thickness of the contact dielectric layer 16 is, for example, 300 Å, and the third metal layer 15 is composed of Al and Mo, the thickness of Mo is, for example, 700 Å, and the thickness of Al is, for example, 500 Å.

[0035] In this embodiment, a transparent conductive layer 17 is further provided above the third metal layer 15, and the transparent conductive layer 17 includes a second sub-pixel electrode 171 corresponding to the metal pixel electrode 151, and the surface of the second sub-pixel electrode 171 is in direct contact with the surface of the metal pixel electrode 151, and the first sub-pixel electrode 161, the metal pixel electrode 151 and the second sub-pixel electrode 171 together form a pixel electrode PE to further reduce the impedance of the pixel electrode PE. The transparent conductive layer 17 can be a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). Of course, in other embodiments, the transparent conductive layer 17 may not be provided, and can be provided according to actual needs.

[0036] The direction from the substrate 10 toward the first metal layer 11 is an upward direction, and the direction from the substrate 10 away from the first metal layer 11 is a downward direction.

[0037] Continue to refer Figures 2a to 9b The present application also provides a method for manufacturing an array substrate, which is used to manufacture the array substrate as described above. The manufacturing method comprises: like Figure 2a and Figure 2bAs shown, a substrate 10 is provided. The substrate 10 can be made of materials such as glass, quartz, silicon, acrylic or polycarbonate. The substrate 10 can also be a flexible substrate. Suitable materials for the flexible substrate include, for example, polyethersulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinyl chloride (PVC), polyethylene terephthalate (PET) or a combination thereof.

[0038] A first metal layer 11 is formed on the substrate 10, and the first metal layer 11 is etched to form a patterned scan line 111 and a gate 112 in the first metal layer 11, and the gate 112 is conductively connected to the scan line 111. The first metal layer 11 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above metals such as Al / Mo, Cu / Mo, etc.

[0039] A gate insulating layer 101 is formed on the first metal layer 11 to cover the scan line 111 and the gate 112. The gate insulating layer 101 is made of silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two. Of course, the gate insulating layer 101 can also be etched to form an opening in the non-display area at the edge of the gate insulating layer 101 to facilitate the wiring layout in the edge area.

[0040] like Figure 3a and Figure 3b As shown, a semiconductor layer 12 is formed on the gate insulating layer 101, and the semiconductor layer 12 is etched to form a patterned active layer 121 in the semiconductor layer 12, and the active layer 121 corresponds to the gate 112. The semiconductor layer 12 can be made of metal oxide materials, such as indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), zinc tin oxide (ZnSnO), gallium tin oxide (GaSnO), gallium zinc oxide (GaZnO), indium gallium zinc oxide (IGZO) or indium gallium zinc tin oxide (IGZTO) and other semiconductor materials.

[0041] like Figure 4a and Figure 4b As shown, a channel protection layer 131 is formed above the active layer 121. The channel protection layer 131 is located in the channel region between the source 142 and the drain 143. The channel protection layer 131 can protect the active layer 121 and prevent external ambient light and subsequent processes (etching process of the second metal layer 14) from affecting the performance of the active layer 121.

[0042] like Figure 5a and Figure 5bAs shown, a second metal layer 14 is formed on the gate insulating layer 101, the semiconductor layer 12 and the channel protection layer 131, and the second metal layer 14 is etched to form a patterned data line 141, a source electrode 142 and a drain electrode 143 in the second metal layer 14. The data line 141 is conductively connected to the source electrode 142, and the source electrode 142 is conductively connected to the drain electrode 143 through the active layer 121. A plurality of scanning lines 111 and a plurality of data lines 141 are insulated from each other and cross-defined to form a plurality of pixel units. The second metal layer 14 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above metals such as Al / Mo, Cu / Mo, etc.

[0043] like Figure 6 As shown, an insulating layer 102 covering the data line 141, the source electrode 142, the drain electrode 143 and the active layer 121 is formed above the second metal layer 14, and the insulating layer 102 is etched to form a first opening 102a corresponding to the drain electrode 143 in the insulating layer 102, and the drain electrode 143 is exposed from the first opening 102a. The material of the insulating layer 102 is silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two. Of course, the insulating layer 102 can also be formed with openings in the non-display area at the edge to facilitate the wiring layout in the edge area.

[0044] like Figure 7 As shown, a flat layer 103 is formed on the insulating layer 102, and the flat layer 103 is etched to form a second opening 103a corresponding to the first opening 102a in the flat layer 103, and the first opening 102a and the second opening 103a together form a contact hole H, and the drain 143 is exposed from the contact hole H. Optionally, the size of the second opening 103a is larger than the size of the first opening 102a, so that the first opening 102a is completely exposed from the second opening 103a. Of course, the insulating layer 102 can also be formed with openings in the non-display area at the edge to facilitate the wiring layout of the edge area.

[0045] In another embodiment, when forming the insulating layer 102 , the insulating layer 102 may not be etched temporarily. The planar layer 103 is first etched to form a second opening 103 a corresponding to the drain 143 , and then the insulating layer 102 is etched to form a first opening 102 a corresponding to the drain 143 .

[0046] like Figures 8 to 9bAs shown, a contact dielectric layer 16, a third metal layer 15 and a transparent conductive layer 17 are sequentially formed above the planar layer 103, and the contact dielectric layer 16, the third metal layer 15 and the transparent conductive layer 17 are etched to form a patterned first sub-pixel electrode 161, a metal pixel electrode 151 and a second sub-pixel electrode 171, respectively. The metal pixel electrode 151 is located between the first sub-pixel electrode 161 and the second sub-pixel electrode 171. The first sub-pixel electrode 161, the metal pixel electrode 151 and the second sub-pixel electrode 171 together form a pixel electrode PE to reduce the impedance of the pixel electrode PE. The pixel electrode PE is electrically connected to the corresponding drain 143 through the contact hole H. The pixel electrode PE is a block electrode corresponding to the pixel unit. The first sub-pixel electrode 161 is used to increase the adhesion between the planar layer 103 and the metal pixel electrode 151, and at the same time reduce the impedance of the pixel electrode PE. Among them, the contact dielectric layer 16 can be made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO) and other transparent conductive materials; the third metal layer 15 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above metals such as Al / Mo, Cu / Mo, etc. The thickness of the contact dielectric layer 16 is, for example, 300 Å, and the third metal layer 15 is composed of Al and Mo, the thickness of Mo is, for example, 700 Å, and the thickness of Al is, for example, 500 Å. The transparent conductive layer 17 can be a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). Of course, in other embodiments, the transparent conductive layer 17 may not be provided, and can be provided according to actual needs. Alternatively, the contact dielectric layer 16, the third metal layer 15 and the transparent conductive layer 17 can be etched separately using a single mask process. The contact dielectric layer 16 , the third metal layer 15 and the transparent conductive layer 17 may also form edge wiring and pads in the edge non-display area to facilitate the wiring layout of the edge area.

[0047] [Example 2] Fig.10 is a schematic diagram of the structure of an array substrate in Embodiment 2 of the present invention, Figures 11 to 14 FIG. 1 is a flow chart of a method for manufacturing an array substrate in Embodiment 2 of the present invention. Figures 10 to 14 As shown, the array substrate provided in the second embodiment of the present invention is different from that in the first embodiment ( Figure 1 ) are basically the same, except that: In this embodiment, the contact dielectric layer 16 is made of insulating material, and the contact dielectric layer 16 is provided with a third opening 162 corresponding to the drain electrode 143. The first opening 102a, the second opening 103a and the third opening 162 together form a contact hole H, and the pixel electrode PE is electrically connected to the corresponding drain electrode 143 through the contact hole H. That is, in this embodiment, the pixel electrode PE is formed by the metal pixel electrode 151 and the second sub-pixel electrode 171 together to form the pixel electrode PE, and the contact hole H is formed by the first opening 102a, the second opening 103a and the third opening 162. Among them, the material of the contact dielectric layer 16 can be silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two, and its thickness is, for example, 1000 Å.

[0048] Optionally, the contact dielectric layer 16 covers the inner sidewall of the second opening 103 a , thereby increasing the adhesion between the metal pixel electrode 151 in the contact hole H and the planar layer 103 .

[0049] Continue to refer Figures 11 to 14 This embodiment also provides a method for manufacturing an array substrate, which is similar to the method of the first embodiment ( Figures 2a to 9b ) are basically the same, except that: In this embodiment, the manufacturing method includes: like Fig.11 As shown, a flat layer 103 is formed on the insulating layer 102, and the flat layer 103 is etched to form a second opening 103a corresponding to the first opening 102a in the flat layer 103, and the first opening 102a and the second opening 103a together form a contact hole H, and the drain 143 is exposed from the contact hole H. Optionally, the size of the second opening 103a is larger than the size of the first opening 102a, so that the first opening 102a is completely exposed from the second opening 103a. Of course, the insulating layer 102 can also be formed with openings in the non-display area at the edge to facilitate the wiring layout of the edge area.

[0050] like Fig.12As shown, a contact dielectric layer 16 is formed on the surface of the flat layer 103, and the contact dielectric layer 16 is etched to form a third opening 162 corresponding to the drain electrode 143. The first opening 102a, the second opening 103a and the third opening 162 together form a contact hole H, and the pixel electrode PE is electrically connected to the corresponding drain electrode 143 through the contact hole H. That is, in this embodiment, the pixel electrode PE is formed by the metal pixel electrode 151 and the second sub-pixel electrode 171 together to form the pixel electrode PE, and the contact hole H is formed by the first opening 102a, the second opening 103a and the third opening 162. Among them, the material of the contact dielectric layer 16 can be silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two, and its thickness is, for example, 1000 Å. The contact dielectric layer 16 can be formed with openings in the non-display area at the edge to facilitate the wiring layout of the edge area. Optionally, the contact dielectric layer 16 covers the inner sidewall of the second opening 103 a , thereby increasing the adhesion between the metal pixel electrode 151 in the contact hole H and the planar layer 103 .

[0051] like Fig.13 and Fig.14 As shown, a third metal layer 15 and a transparent conductive layer 17 are sequentially formed above the contact dielectric layer 16, and the third metal layer 15 and the transparent conductive layer 17 are etched to form patterned metal pixel electrodes 151 and second sub-pixel electrodes 171, respectively. The metal pixel electrode 151 is located between the contact dielectric layer 16 and the second sub-pixel electrode 171, and the metal pixel electrode 151 and the second sub-pixel electrode 171 together form a pixel electrode PE to reduce the impedance of the pixel electrode PE. The pixel electrode PE is electrically connected to the corresponding drain electrode 143 through the contact hole H, and the pixel electrode PE is a block electrode corresponding to the pixel unit. Among them, the material of the contact dielectric layer 16 can be silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two; the third metal layer 15 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above metals such as Al / Mo, Cu / Mo, etc. The thickness of the contact dielectric layer 16 is, for example, 1000Å, and the third metal layer 15 is composed of Al and Mo, the thickness of Mo is, for example, 700Å, and the thickness of Al is, for example, 500Å. The transparent conductive layer 17 can be a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). Of course, in other embodiments, the transparent conductive layer 17 may not be provided, and can be provided according to actual needs. Alternatively, the third metal layer 15 and the transparent conductive layer 17 can be etched separately using a single mask process. The third metal layer 15 and the transparent conductive layer 17 can also form edge wiring and pads in the non-display area of ​​the edge to facilitate the wiring layout of the edge area.

[0052] The manufacturing process of the scan line 111, the gate 112, the gate insulating layer 101, the active layer 121, the channel protection layer 131, the data line 141, the source 142, the drain 143 and the insulating layer 102 can refer to the first embodiment and will not be repeated here.

[0053] It should be understood by those skilled in the art that the rest of the structure and working principle of this embodiment are the same as those of the first embodiment and will not be described in detail here.

[0054] [Example 3] Fig.15 Schematic diagram of the structure of the array substrate in the third embodiment of the present invention. Fig.15 As shown, the array substrate provided in the third embodiment of the present invention is different from that in the first embodiment ( Figure 1 )、Example 2 ( Fig.10 ) are basically the same, except that: In this embodiment, the surface of the flat layer 103 is provided with a rough structure, so as to increase the adhesion between the flat layer 103 and the third metal layer 15. Therefore, in this embodiment, it is not necessary to provide a contact dielectric layer 16 to increase the adhesion between the flat layer 103 and the third metal layer 15, thereby reducing the thickness of the array substrate and a mask process. Of course, in other embodiments, a rough structure may be provided on the surface of the flat layer 103, and a contact dielectric layer 16 may be provided between the third metal layer 15 and the flat layer 103, so as to further improve the adhesion between the flat layer 103 and the third metal layer 15 and prevent the metal pixel electrode 151 from falling off.

[0055] Figures 16 to 19 It is a schematic flow chart of a method for manufacturing an array substrate in Embodiment 3 of the present invention. Figures 16 to 19 As shown, this embodiment also provides a method for manufacturing an array substrate and the method of embodiment 1 ( Figures 2a to 9b )、Example 2 ( Figures 11 to 14 ) are basically the same, except that: In this embodiment, the manufacturing method includes: like Fig.16 As shown, a flat layer 103 is formed on the insulating layer 102, and the flat layer 103 is etched to form a second opening 103a corresponding to the first opening 102a in the flat layer 103, and the first opening 102a and the second opening 103a together form a contact hole H, and the drain 143 is exposed from the contact hole H. Optionally, the size of the second opening 103a is larger than the size of the first opening 102a, so that the first opening 102a is completely exposed from the second opening 103a. Of course, the insulating layer 102 can also be formed with openings in the non-display area at the edge to facilitate the wiring layout of the edge area.

[0056] like Fig.17 As shown, the surface of the planar layer 103 is roughened by a plasma gas sputtering process, for example, nitrogen (N2) plasma treatment can be used to form a rough structure on the surface of the planar layer 103 to increase the adhesion between the planar layer 103 and the third metal layer 15.

[0057] like Fig.18 and Fig.19 As shown, a third metal layer 15 and a transparent conductive layer 17 are sequentially formed on the flat layer 103, and the third metal layer 15 and the transparent conductive layer 17 are etched to form a patterned metal pixel electrode 151 and a second sub-pixel electrode 171 respectively. The metal pixel electrode 151 is located between the flat layer 103 and the second sub-pixel electrode 171. The metal pixel electrode 151 and the second sub-pixel electrode 171 together form a pixel electrode PE to reduce the impedance of the pixel electrode PE. The pixel electrode PE is electrically connected to the corresponding drain 143 through a contact hole H, and the pixel electrode PE is a block electrode corresponding to the pixel unit. Among them, the third metal layer 15 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above metals such as Al / Mo, Cu / Mo, etc. The third metal layer 15 is composed of Al and Mo, and the thickness of Mo is, for example, 700 Å, and the thickness of Al is, for example, 500 Å. The transparent conductive layer 17 can be a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). Of course, in other embodiments, the transparent conductive layer 17 may not be provided, and may be provided according to actual needs. Alternatively, the third metal layer 15 and the transparent conductive layer 17 may be etched separately using a single mask process. The third metal layer 15 and the transparent conductive layer 17 may also form edge wiring and pads in the non-display area of ​​the edge to facilitate the wiring layout of the edge area.

[0058] The manufacturing process of the scan line 111, the gate 112, the gate insulating layer 101, the active layer 121, the channel protection layer 131, the data line 141, the source 142, the drain 143 and the insulating layer 102 can refer to the first embodiment and will not be repeated here.

[0059] It should be understood by those skilled in the art that the rest of the structure and working principle of this embodiment are the same as those of the first embodiment and will not be described in detail here.

[0060] Fig. 20 Schematic diagram of the structure of the electronic paper display in the present invention in the initial state. Fig. 20The present application also provides an electronic paper display, comprising an opposing substrate 20, an array substrate arranged opposite to the opposing substrate 20, and a plurality of ink capsules 30 arranged between the opposing substrate 20 and the array substrate, wherein the array substrate is manufactured by the manufacturing method of the array substrate as described above. A retaining wall 40 is also provided between the opposing substrate 20 and the array substrate, and the retaining wall 40 is used to separate the gap between the opposing substrate 20 and the array substrate into a plurality of accommodating cavities distributed in an array, and each accommodating cavity forms a pixel unit. The ink capsule 30 is arranged in the accommodating cavity and corresponds to the pixel unit one by one. Ink particles are arranged in the ink capsule 30, and the ink particles 30 include a plurality of black particles 31 and a plurality of white particles 32, and the electrical properties of the black particles 31 are opposite to those of the white particles 32. By providing electric fields in different directions to the ink capsule 30, the black particles 31 and the white particles 32 can move in corresponding directions. For example, the black particles 31 are negatively charged and the white particles 32 are positively charged, so that the white particles 32 move in the direction of the electric field and the black particles 31 move in the opposite direction of the electric field. If an electric field is applied in an upward direction, the white particles 32 move upward and the black particles 31 move downward; if an electric field is applied in a downward direction, the white particles 32 move downward and the black particles 31 move upward. Of course, the black particles 31 may be positively charged and the white particles 32 may be negatively charged, so that the black particles 31 move in the direction of the electric field and the white particles 32 move in the opposite direction of the electric field.

[0061] The counter substrate 20 is provided with a common electrode 21, and the array substrate is provided with a pixel electrode PE corresponding to each pixel unit one by one. By controlling the voltage on the pixel electrode PE, the direction and strength of the electric field between the pixel electrode PE and the common electrode 21 are controlled, thereby controlling the movement direction of the black particles 31 and the white particles 32. The common electrode 21 and the pixel electrode PE can both be block electrodes corresponding to each pixel unit one by one. Of course, the common electrode 21 can also be a planar electrode covering the entire surface of the counter substrate 20.

[0062] Fig.21 Schematic diagram of the structure of the electronic paper display in the present invention in the black state. Fig.21 As shown, in the black state, a 0V common voltage is applied to the common electrode 21, and corresponding positive polarity voltages and negative polarity voltages are applied to all pixel electrodes PE. For example, the black particles 31 are negatively charged, and the white particles 32 are positively charged, so that the white particles 32 move in the direction of the electric field, and the black particles 31 move in the opposite direction of the electric field. When negative polarity voltages are applied to all pixel electrodes PE, the direction of the electric field between the pixel electrode PE and the common electrode 21 is from the common electrode 21 to the pixel electrode PE, then the white particles 32 move toward the pixel electrode PE, and the black particles 31 move toward the common electrode 21, so that all ink capsules 30 are in a black state.

[0063] Fig. 22 Schematic diagram of the structure of the electronic paper display in the present invention in the white state. Fig. 22 As shown, in the white state, a 0V common voltage is applied to the common electrode 21, and corresponding positive polarity voltages and negative polarity voltages are applied to all pixel electrodes PE. For example, the black particles 31 are negatively charged, and the white particles 32 are positively charged, so that the white particles 32 move in the direction of the electric field, and the black particles 31 move in the opposite direction of the electric field. When a positive polarity voltage is applied to all pixel electrodes PE, the direction of the electric field between the pixel electrode PE and the common electrode 21 is from the pixel electrode PE to the common electrode 21, then the white particles 32 move toward the common electrode 21, and the black particles 31 move toward the pixel electrode PE, so that all ink capsules 30 are in a white state.

[0064] Fig.23 Schematic diagram of the structure of the electronic paper display in the present invention when in display state. Fig.23 As shown, in the black and white display mode, a 0V common voltage is applied to the common electrode 21, and a corresponding positive polarity voltage and a negative polarity voltage are applied to the pixel electrode PE. For example, the black particles 31 are negatively charged and the white particles 32 are positively charged, so that the white particles 32 move in the direction of the electric field and the black particles 31 move in the opposite direction of the electric field. When a negative polarity voltage is applied to the pixel electrode PE, the direction of the electric field between the pixel electrode PE and the common electrode 21 is from the common electrode 21 to the pixel electrode PE, then the white particles 32 move toward the pixel electrode PE, and the black particles 31 move toward the common electrode 21, so that the corresponding ink capsule 30 is in a black state. When a positive polarity voltage is applied to the pixel electrode PE, the direction of the electric field between the pixel electrode PE and the common electrode 21 is from the pixel electrode PE to the common electrode 21, then the white particles 32 move toward the common electrode 21, and the black particles 31 move toward the pixel electrode PE, so that the corresponding ink capsule 30 is in a white state. By combining the black and white colors of different pixel units, the electronic paper display can display black and white images using ambient light.

[0065] In this document, the directional words such as up, down, left, right, front, and back are defined by the positions of the structures in the drawings and the positions of the structures relative to each other, just for the sake of clarity and convenience in expressing the technical solution. It should be understood that the use of the directional words should not limit the scope of protection claimed in this application. It should also be understood that the terms "first" and "second" used in this document are only used to distinguish names and are not used to limit quantity and order.

[0066] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modifications to the technical contents disclosed above without departing from the scope of the technical solution of the present invention, which are equivalent embodiments of equivalent changes. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for manufacturing an array substrate, characterized in that: include: Providing a substrate (10); Forming a first metal layer (11) above the substrate (10), etching the first metal layer (11) to form a patterned scan line (111) and a gate (112), wherein the gate (112) is conductively connected to the scan line (111); forming a gate insulating layer (101) covering the first metal layer (11) on the substrate (10); Forming a semiconductor layer (12) above the gate insulating layer (101), etching the semiconductor layer (12) to form an active layer (121) corresponding to the gate (112); A second metal layer (14) covering the semiconductor layer (12) is formed above the gate insulating layer (101), and the second metal layer (14) is etched to form a patterned data line (141), a source electrode (142) and a drain electrode (143), wherein the source electrode (142) is conductively connected to the data line (141), and the source electrode (142) and the drain electrode (143) are connected via the active layer (121); forming an insulating layer (102) covering the semiconductor layer (12) and the second metal layer (14) above the gate insulating layer (101), etching the insulating layer (102) to form a first opening (102a) corresponding to the drain electrode (143); Forming a flat layer (103) covering the insulating layer (102) above the insulating layer (102), etching the flat layer (103) to form a second opening (103a) corresponding to the drain electrode (143); forming a third metal layer (15) above the flat layer (103), etching the second metal layer (15) to form a patterned metal pixel electrode (151), wherein the metal pixel electrode (151) is electrically connected to the corresponding drain electrode (143) through the first opening (102a) and the second opening (103a); After etching the flat layer (103) and before forming the third metal layer (15), the surface of the flat layer (103) is roughened and / or a contact dielectric layer (16) is formed on the surface of the flat layer (103), wherein the contact dielectric layer (16) is used to increase the adhesion between the flat layer (103) and the third metal layer (15).

2. The method for manufacturing an array substrate according to claim 1, characterized in that: include: After etching the flat layer (103) and before forming the third metal layer (15), a plasma gas sputtering process is used to roughen the surface of the flat layer (103).

3. The method for manufacturing an array substrate according to claim 1, characterized in that: The contact dielectric layer (16) is made of conductive material, and the manufacturing method comprises: After etching the flat layer (103) and before forming the third metal layer (15), the contact dielectric layer (16) is formed on the surface of the flat layer (103), and the contact dielectric layer (16) is etched to form a first sub-pixel electrode (161) corresponding to the metal pixel electrode (151), wherein the surface of the first sub-pixel electrode (161) is in direct contact with the surface of the metal pixel electrode (151).

4. The method for manufacturing an array substrate according to claim 1, characterized in that: The contact medium layer (16) is made of insulating material, and the manufacturing method comprises: After etching the planar layer (103) and before forming the third metal layer (15), the contact dielectric layer (16) is formed on the surface of the planar layer (103), the contact dielectric layer (16) is etched to form a third opening (162) corresponding to the drain electrode (143), and the metal pixel electrode (151) is electrically connected to the corresponding drain electrode (143) through the first opening (102a), the second opening (103a) and the third opening (162).

5. The method for manufacturing an array substrate according to claim 4, characterized in that: The contact medium layer (16) covers the inner side wall of the second opening (103a).

6. The method for manufacturing an array substrate according to any one of claims 1 to 5, characterized in that: include: A transparent conductive layer (17) is formed above the third metal layer (15), and the transparent conductive layer (17) is etched to form a second sub-pixel electrode (171) corresponding to the metal pixel electrode (151), wherein the surface of the second sub-pixel electrode (171) is in direct contact with the surface of the metal pixel electrode (151).

7. The method for manufacturing an array substrate according to any one of claims 1 to 5, characterized in that: include: After etching the semiconductor layer (12) and before forming the second metal layer (14), a channel protection layer (131) is formed above the active layer (121), wherein the channel protection layer (131) is located in the channel region between the source electrode (142) and the drain electrode (143).

8. The method for manufacturing an array substrate according to any one of claims 1 to 5, characterized in that: include: The planar layer (103) is first etched to form a second opening (103a) corresponding to the drain electrode (143), and then the insulating layer (102) is etched to form a first opening (102a) corresponding to the drain electrode (143).

9. An array substrate, characterized in that: The array substrate is manufactured by the manufacturing method of any one of claims 1 to 8.

10. An electronic paper display, characterized in that: The invention comprises an opposing substrate (20), an array substrate arranged opposite to the opposing substrate (20), and a plurality of ink capsules (30) arranged between the opposing substrate (20) and the array substrate, wherein the array substrate is manufactured by the method for manufacturing an array substrate according to any one of claims 1 to 8; the ink capsules (30) correspond one-to-one to the pixel units, and ink particles are arranged in the ink capsules (30); a common electrode (21) is arranged on the opposing substrate (20), and pixel electrodes (PE) corresponding one-to-one to the pixel units are arranged on the array substrate, and the pixel electrodes (PE) include the metal pixel electrodes (151).

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