Ethernet and AUTBUS communication systems and chips

Abstract

The embodiment of the present application provides a communication system and chip for Ethernet and AUTBUS, wherein a write control module is used to receive and parse a data packet sent by a sender, and write the data packet into a write target cache queue determined by a queue control module, wherein the write target cache queue is a cache queue in a cache; a read control module is used to read a data packet from a read target cache queue determined by a queue control module and encapsulate and send the data packet to a receiver, wherein the read target cache queue is a cache queue in a cache; and a queue control module is used to determine a write target cache queue for a write control module and a read target cache queue for a read control module. Thus, the conversion communication between Ethernet and AUTBUS is completed by hardware, and interconnection between different types of networks is realized quickly and reliably inside the chip, which is not limited by CPU resources, thereby improving the communication efficiency between Ethernet and AUTBUS.

Description

Technical Field

[0001] The present application belongs to the field of industrial automation technology, and specifically relates to an Ethernet and AUTBUS communication system and chip. Background Art

[0002] In modern industrial automation, the combination of AUTBUS and Ethernet communication provides strong support for the interconnection between devices. It enables industrial equipment to not only communicate efficiently within the same network, but also expand to a wider area through Ethernet, realizing cross-regional equipment control and data exchange. For example, in a smart factory, robots, sensors, and consoles on the production line can be combined with Ethernet through the AUTBUS protocol to achieve real-time monitoring and control. Among them, the AUTBUS national standard: GB / T 42019-2022 was officially released in October 2022. The AUTBUS international standards: IEC61158-Type 28, IEC61784-CPF22 were officially released in March 2023.

[0003] Since AUTBUS and Ethernet use different data packet protocols and cannot communicate directly, in the existing technology, the communication between AUTBUS and Ethernet is implemented based on the central processing unit (CPU). The CPU can receive data from AUTBUS, convert it into data packets of Ethernet protocol, and send it out through Ethernet. Alternatively, the CPU can receive data from Ethernet, convert it into data packets of AUTBUS protocol, and send it out through AUTBUS.

[0004] However, using the existing technology, the communication efficiency of Ethernet and AUTBUS is not high. Summary of the invention

[0005] The embodiments of the present application provide an Ethernet and AUTBUS communication system and chip to solve the problem of low efficiency of Ethernet and AUTBUS communication in the prior art.

[0006] The first aspect of the present application provides an Ethernet and AUTBUS communication system, comprising: a write control module, a queue control module, a read control module and a buffer, wherein the buffer comprises: a plurality of buffer queues;

[0007] The write control module is used to receive and parse the data packet sent by the sender, and write the data packet into the write target cache queue determined by the queue control module, wherein the write target cache queue is a cache queue in the cache;

[0008] The read control module is used to read the data packet from the read target cache queue determined by the queue control module and send it to the receiving end after encapsulation, wherein the read target cache queue is a cache queue in the cache;

[0009] The queue control module is used to determine the write target cache queue for the write control module and determine the read target cache queue for the read control module.

[0010] Optionally, the queue control module is specifically used to maintain a queue state vector, a write state vector and a read state vector, and determine the write target cache queue and / or the read target cache queue based on the queue state vector, the write state vector and the read state vector;

[0011] Among them, each vector contains the multiple bits, each bit corresponds to a cache queue, the queue state vector is used to characterize the empty and full states of each cache queue, the write state vector is used to characterize the write state of each cache queue, and the read state vector is used to characterize the read state of each cache queue.

[0012] Optionally, the write control module is further used to maintain the packet assembly state information corresponding to the node, and the packet assembly state information is used to record the target cache queue corresponding to the node in the packet assembly state and the length of the written data;

[0013] When the write control module receives a data packet from AUTBUS, if the data packet is an independent packet or the first subpacket, it applies to the queue control module for allocation of a write target cache queue, and writes the data packet into the write target cache queue; and based on the node information of the first subpacket, records the packet assembly status information corresponding to the node; if the data packet is an intermediate subpacket or the last subpacket, based on the target cache queue corresponding to the node of the data packet and the length of the written data, writes the data packet to the end of the previous subpacket of the node in the write target cache queue, and updates the write status information corresponding to the node.

[0014] Optionally, the read-out control module is specifically used to determine that the length of the data packet in the read target cache queue is less than or equal to a first preset length, then read the data packet from the read target cache queue and encapsulate it according to the AUTBUS protocol and send it to the AUTBUS; if it is determined that the length of the data packet in the read target cache queue is greater than the first preset length, then sub-packetize the data packet in the read target cache queue in accordance with a second preset length and read it in sequence, and encapsulate each sub-packet according to the AUTBUS protocol and send it to the AUTBUS, wherein the second preset length is less than or equal to the first preset length.

[0015] Optionally, the queue control module is specifically used to obtain, in order of bits from high to low, the first cache queue that satisfies both the empty and full states in the queue status vector and the write status in the write status vector as the write target cache queue; and to obtain, in order of bits from low to high, the first cache queue that satisfies both the empty and full states in the queue status vector and the read status in the read status vector as the read target cache queue.

[0016] Optionally, the index number of the write target cache queue is the sum of the sequence number of the write target cache queue in the queue state vector plus the value of the queue shift counter; the index number of the read target cache queue is the sum of the sequence number of the read target cache queue in the queue state vector plus the value of the queue shift counter.

[0017] Optionally, the write control module is specifically used to complete writing a data packet to a write target cache queue, then set the empty and full states corresponding to the write target cache queue in the queue state vector to full, set the write state corresponding to the write target cache queue in the write state vector to unwritten, and circularly shift all bits of the queue state vector, the write state vector and the read state vector to the right once, and control the value of the queue shift counter to increase by 1;

[0018] The read control module is specifically used to complete reading a data packet from a read target cache queue, then set the empty and full states corresponding to the read target cache queue in the queue state vector to empty, and set the read state corresponding to the read target cache queue in the read state vector to unread.

[0019] Optionally, the packet assembly state information corresponding to the node includes: an index number or a base address of a write target cache queue storing data packets of the node, and a length of written data;

[0020] The write control module is specifically used to determine the base address of the write target cache queue based on the index number or base address of the write target cache queue, and determine the write start address of the data packet based on the base address and the length of the written data.

[0021] Optionally, the queue control module is further used to send the address information of the read target cache queue and the length information of the data packet to the read control module, and the address information of the data packet includes: an index number or a base address.

[0022] The second aspect of the present application provides an Ethernet and AUTBUS communication chip, comprising: a write control module, a queue control module, a read control module and a buffer, wherein the buffer comprises: a plurality of buffer queues;

[0023] The write control module is used to receive and parse the data packet sent by the sender, and write the data packet into the write target cache queue determined by the queue control module, wherein the write target cache queue is a cache queue in the cache;

[0024] The read control module is used to read the data packet from the read target cache queue determined by the queue control module and send it to the receiving end after encapsulation, wherein the read target cache queue is a cache queue in the cache;

[0025] The queue control module is used to determine the write target cache queue for the write control module and determine the read target cache queue for the read control module.

[0026] The communication system and chip of Ethernet and AUTBUS provided by the embodiment of the present application include: a write control module, a queue control module, a read control module and a buffer, wherein the buffer includes: multiple buffer queues; the write control module is used to receive and parse the data packet sent by the sender, and write the data packet into the write target buffer queue determined by the queue control module, wherein the write target buffer queue is a buffer queue in the buffer; the read control module is used to read the data packet from the read target buffer queue determined by the queue control module and encapsulate it and send it to the receiving end, wherein the read target buffer queue is a buffer queue in the buffer; the queue control module is used to determine the write target buffer queue for the write control module and determine the read target buffer queue for the read control module. Thus, the conversion communication between Ethernet and AUTBUS is completed by hardware, and the interconnection between different types of networks is realized quickly and reliably inside the chip, which is not limited by CPU resources, and the communication efficiency of Ethernet and AUTBUS is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A schematic diagram of the structure of an Ethernet and AUTBUS communication system provided in an embodiment of the present application;

[0028] Figure 2 A schematic diagram of the structure of another Ethernet and AUTBUS communication system provided in an embodiment of the present application;

[0029] Figure 3 A schematic diagram of the structure of a communication system for sending data from Ethernet to AUTBUS provided in an embodiment of the present application;

[0030] Figure 4 A schematic diagram of a process of sending data from Ethernet to AUTBUS provided in an embodiment of the present application;

[0031] Figure 5A schematic diagram of another process of sending data from Ethernet to AUTBUS provided in an embodiment of the present application;

[0032] Figure 6 A schematic diagram of a process of sending data from Ethernet to AUTBUS provided in another embodiment of the present application;

[0033] Figure 7 A schematic diagram of a process of sending data from Ethernet to AUTBUS provided in another embodiment of the present application;

[0034] Figure 8 A schematic diagram of the structure of a communication system for sending data from AUTBUS to Ethernet provided in an embodiment of the present application;

[0035] Fig. 9 A schematic diagram of a process of sending data from AUTBUS to Ethernet provided in an embodiment of the present application;

[0036] Fig.10 A schematic diagram of another process of sending data from AUTBUS to Ethernet provided in an embodiment of the present application;

[0037] Fig.11 A schematic diagram of a process of sending data from AUTBUS to Ethernet provided in another embodiment of the present application;

[0038] Fig.12 A schematic diagram of the structure of an Ethernet and AUTBUS communication chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of this application.

[0040] The terms "first", "second", etc. of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way are interchangeable where appropriate, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first" and "second" are generally of one type, and the number of objects is not limited, for example, the first object can be one or more. In addition, "or" in the present application represents at least one of the connected objects. For example, "A or B" covers three schemes, namely, Scheme 1: including A but not including B; Scheme 2: including B but not including A; Scheme 3: including both A and B. The character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0041] The term "indication" in this application can be a direct indication (or explicit indication) or an indirect indication (or implicit indication). A direct indication can be understood as the sender explicitly informing the receiver of specific information, operations to be performed, or request results in the sent indication; an indirect indication can be understood as the receiver determining the corresponding information based on the indication sent by the sender, or making a judgment and determining the operation to be performed or the request result based on the judgment result.

[0042] The prior art uses CPU as an intermediate medium to perform protocol parsing, packetization, packaging and encapsulation and decapsulation processing on Ethernet and AUTBUS data packets to complete the communication between Ethernet and AUTBUS. However, due to limited CPU resources and heavy CPU load, the communication efficiency between Ethernet and AUTBUS is not high. The present application implements the conversion communication between Ethernet and AUTBUS through hardware, and performs data processing and interaction through a read control module, a write control module, a buffer and a queue controller inside the chip, so as to quickly and reliably realize the interconnection between different types of networks, thereby improving the efficiency of communication between Ethernet and AUTBUS without the participation of the CPU, reducing the CPU load and improving the overall performance of the system.

[0043] In the communication system of Ethernet and AUTBUS, there are two directions of communication, one direction is Ethernet sending data to AUTBUS, and the other direction is AUTBUS sending data to Ethernet. In order to realize the communication between Ethernet and AUTBUS, the communication system of Ethernet and AUTBUS is provided with a read control module, a write control module, a buffer and a queue controller. Figure 1 As shown, the cache includes: multiple cache queues; wherein the write control module is used to receive and parse the data packets sent by the sender, and write the data packets into the write target cache queue determined by the queue control module, wherein the write target cache queue is a cache queue in the cache; the read control module is used to read the data packets from the read target cache queue determined by the queue control module and encapsulate and send them to the receiving end, wherein the read target cache queue is a cache queue in the cache; the queue control module is used to determine the write target cache queue for the write control module, and determine the read target cache queue for the read control module.

[0044] Optionally, in the process of AUTBUS sending data to Ethernet, the queue controller is specifically used to maintain three state vectors, namely a queue state vector, a write state vector and a read state vector, and determine the write target cache queue and / or the read target cache queue based on the queue state vector, the write state vector and the read state vector;

[0045] Among them, each vector contains the multiple bits, each bit corresponds to a cache queue, the queue state vector is used to characterize the empty and full states of each cache queue, the write state vector is used to characterize the write state of each cache queue, and the read state vector is used to characterize the read state of each cache queue.

[0046] The queue control module may determine the write target cache queue or the read target cache queue based on the three state vectors in the following manner:

[0047] Specifically, the queue control module is specifically used to obtain, in order of bits from high to low, the first cache queue that simultaneously satisfies the conditions that the empty and full states in the queue status vector are empty, and the write state in the write status vector is not written, as the write target cache queue; and in order of bits from low to high, obtain the first cache queue that simultaneously satisfies the conditions that the empty and full states in the queue status vector are full, and the read state in the read status vector is not read, as the read target cache queue.

[0048] Among them, the index number of the write target cache queue is the sum of the sequence number of the write target cache queue in the queue state vector plus the value of the queue shift counter; the index number of the read target cache queue is the sum of the sequence number of the read target cache queue in the queue state vector plus the value of the queue shift counter.

[0049] Optionally, the values ​​of the three state vectors may be maintained through the following possible implementations:

[0050] When the write control module completes writing a data packet to the write target cache queue, the empty and full states corresponding to the write target cache queue in the queue state vector are set to full, the write state corresponding to the write target cache queue in the write state vector is set to unwritten, and all bits of the queue state vector, the write state vector and the read state vector are circularly shifted right once, and the value of the control queue shift counter is increased by 1, wherein the completion of writing a data packet refers to the completion of writing an independent independent data packet, or the completion of writing the last sub-packet;

[0051] The read-out control module is specifically used to complete reading a data packet from a read target cache queue, and then set the empty and full states corresponding to the read target cache queue in the queue state vector to empty, and set the read state corresponding to the read target cache queue in the read state vector to unread, wherein the completion of reading a data packet refers to the completion of reading an independent data packet or the completion of reading the last data packet.

[0052] Optionally, in the process of sending data from AUTBUS to Ethernet, since the data packets supported by the AUTBUS protocol are relatively small, AUTBUS may write sub-packets of a certain node during the writing process. In this process, the writing control module is also used to maintain the packet assembly state information corresponding to the node, and the packet assembly state information is used to record the target cache queue corresponding to the node in the packet assembly state and the length of the written data;

[0053] When the write control module receives a data packet from AUTBUS, if the data packet is an independent packet or the first subpacket, it applies to the queue control module for allocation of a write target cache queue, and writes the data packet into the write target cache queue; and based on the node information of the first subpacket, records the packet assembly status information corresponding to the node; if the data packet is an intermediate subpacket or the last subpacket, based on the target cache queue corresponding to the node of the data packet and the length of the written data, writes the data packet to the end of the previous subpacket of the node in the write target cache queue, and updates the write status information corresponding to the node.

[0054] The packet assembly state information corresponding to the node includes: the index number or base address of the write target cache queue storing the data packet of the node, and the length of the written data;

[0055] The write control module is specifically used to determine the base address of the write target cache queue based on the index number or base address of the write target cache queue, and determine the write start address of the data packet based on the base address and the length of the written data.

[0056] Optionally, in the process of sending data from Ethernet to AUTBUS, since the data packets supported by the Ethernet protocol are larger, the size of the stored data packets may be larger, while the data packets supported by the AUTBUS protocol are smaller. Therefore, when AUTBUS reads the data packets sent by Ethernet, it may be necessary to perform packet reading. In this case, the queue control module is used to send the address information of the read target cache queue and the length information of the data packet to the read control module, and the address information of the data packet includes: an index number or a base address.

[0057] The read-out control module is specifically used to determine that the length of the data packet in the read target cache queue is less than or equal to the first preset length, then read the data packet from the read target cache queue and encapsulate it according to the AUTBUS protocol and send it to the AUTBUS; if it is determined that the length of the data packet in the read target cache queue is greater than the first preset length, then sub-packetize the data packet in the read target cache queue in accordance with the second preset length and read it in sequence, and encapsulate each sub-packet according to the AUTBUS protocol and send it to the AUTBUS, wherein the second preset length is less than or equal to the first preset length, and wherein the first preset length is the maximum length supported by the AUTBUS protocol.

[0058] The following embodiments of the present application describe the processing flows in the data writing process and the data reading process in two directions respectively. For the convenience of description, the direction in which Ethernet sends data to AUTBUS is described as the first direction, and the write control module for implementing the sending of data from Ethernet to AUTBUS is described as the first write control module, the queue control module is described as the first queue control module, the read control module is described as the first read control module, and the buffer is described as the first buffer, wherein the cache queue included in the first buffer is described as the first cache queue, and during the writing process, the first cache queue determined by the queue controller is described as the first write target cache queue, and during the reading process, the first cache queue determined by the queue controller is described as the first read target cache queue.

[0059] Similarly, the direction in which AUTBUS sends data to Ethernet is described as the second direction, the write control module that implements AUTBUS sending data to Ethernet is described as the second write control module, the queue control module is described as the second queue control module, the read control module is described as the second read control module, and the buffer is described as the second buffer, wherein the cache queue included in the second buffer is described as the second cache queue, and during the writing process, the second cache queue determined by the queue controller is described as the second write target cache queue, and during the reading process, the second cache queue determined by the queue controller is described as the first read target cache queue.

[0060] Figure 2 A schematic diagram of the structure of another Ethernet and AUTBUS communication system provided in an embodiment of the present application, wherein a corresponding write control module, a queue control module, a read control module and a buffer are set in each direction, such as Figure 2The system of the present embodiment shown includes: Ethernet, AUTBUS, a first write control module, a first queue control module, a first read control module, and a first buffer, wherein the first buffer includes: a first preset number of first cache queues; a second write control module, a second queue control module, a second read control module, and a second buffer, wherein the second buffer includes: a second preset number of second cache queues.

[0061] The following describes the communication method of the Ethernet and AUTBUS communication system of the present application by taking several embodiments as examples.

[0062] Figure 3 A structural schematic diagram of a communication system for sending data from Ethernet to AUTBUS provided in an embodiment of the present application, the system of this embodiment includes: a first write control module, a first queue control module, a first read control module, and a first buffer, wherein the first buffer includes: a first preset number of first cache queues; wherein the first write control module is used to receive and parse a first data packet from the Ethernet, and write the first data packet into a first write target cache queue determined by the first queue control module, wherein the first write target cache queue is a first cache queue in the first buffer; the first read control module is used to read the first data packet from the first read target cache queue determined by the first queue control module and send it to the AUTBUS after encapsulation, wherein the first read target cache queue is a first cache queue in the first buffer; the first queue control module is used to determine the first write target cache queue for the first write control module, and determine the first read target cache queue for the first read control module.

[0063] Optionally, the length of the data packet supported by Ethernet can be from a minimum of 64 bytes to a maximum of 1500 bytes, or, in some cases, larger. The AUTBUS protocol supports smaller data packet lengths, and the specific supported data packet length can be set according to the specific application scenario. In some scenarios, when the length of the data packet transmitted by Ethernet exceeds the length of the data packet that the AUTBUS protocol can handle, packetization processing is required to split the Ethernet data packet into multiple smaller data packets to meet the data transmission requirements of the AUTBUS protocol.

[0064] In these scenarios, the first read-out control module is specifically used to determine that the length of the first data packet in the first read target cache queue determined by the first queue control module is less than or equal to the first preset length, then read the first data packet from the first read target cache queue, encapsulate it according to the AUTBUS protocol and send it to the AUTBUS; if it is determined that the length of the first data packet in the first read target cache queue determined by the first queue control module is greater than the first preset length, then sub-packetize the first data packet in the first read target cache queue in sequence according to the second preset length, and encapsulate each sub-packet according to the AUTBUS protocol and send it to the AUTBUS, wherein the second preset length is less than or equal to the first preset length, and wherein the first preset length is the maximum length of the data unit supported by the AUTBUS protocol.

[0065] In the above embodiment, in the scenario where Ethernet sends data packets to AUTBUS, the first queue control module determines the first write target cache queue in a preset order based on the empty and full flags of each first cache queue. Specifically, the first queue control module is specifically used to determine the first read target cache queue and the first write target cache queue according to the empty and full flags of each first cache queue in the first cache and the preset order; control the first write control module to set the empty and full flags of the first write target cache queue to full after writing the first data packet to the first write target cache queue, and control the first read control module to set the empty and full flags of the first read target cache queue to empty after completing reading the first data packet from the first read target cache queue.

[0066] In the above embodiment, the first queue control module is specifically used to traverse the empty and full flags of the first cache queues in a preset order, determine that the first cache queue whose empty and full flag is empty is the first write target cache queue, determine the base address of the first write target cache queue based on the index number of the first write target cache queue and the size of each of the first cache queues, and send the base address of the first write target cache queue to the first write control module, so that the first write control module writes the first data packet to the first write target cache queue according to the base address of the first write target cache queue;

[0067] The first queue control module is specifically used to traverse the empty and full flags of the first cache queues in a preset order, determine that the first cache queue whose empty and full flag is full is the first read target cache queue, determine the base address of the first read target cache queue based on the index number of the first read target cache queue and the size of the first cache queues, and send the base address of the first read target cache queue and the length of the first data packet to the first read-out control module, so that the first read-out control module reads the first data packet from the first read target cache queue according to the base address of the first read target cache queue.

[0068] In the above embodiment, the first queue control module maintains a first queue state vector, which contains a first preset number of bits, and each bit corresponds to a first cache queue; when the first write control module completes writing the first data packet to the first write target cache queue, the empty and full states corresponding to the first write target cache queue in the first queue state vector are set to full, and all the bits of the first queue state vector are circularly shifted right once to control the value of the first queue shift counter to increase by 1; when the first read control module completes reading the first data packet from the first read target cache queue, the empty and full states corresponding to the first read target cache queue in the first queue state vector are set to empty.

[0069] In the above embodiment, the first queue control module determines that the first cache queue with the first empty or full state in the first queue state vector is the first write target cache queue in the order of bits from high to low, and the index number of the first write target cache queue is the sum of the sequence number of the first write target cache queue in the first queue state vector plus the value of the first queue shift counter; the first queue control module determines that the first cache queue with the first empty or full state in the first queue state vector is the first read target cache queue in the order of bits from low to high, and the index number of the first read target cache queue is the sum of the sequence number of the first read target cache queue in the first queue state vector plus the value of the first queue shift counter.

[0070] Figure 3 Each module in the system of the embodiment shown can be used to execute Figures 4 to 7 The technical solution of the embodiment of the communication method of Ethernet and AUTBUS shown in the figure, and its implementation principle and technical effect can be found in Figures 4 to 7 Detailed description of the illustrated embodiments.

[0071] Figures 4 to 7 The following is an example of sending data from Ethernet to AUTBUS, that is, a description of communication in the first direction. Figure 4A schematic diagram of a process of sending data from Ethernet to AUTBUS provided in an embodiment of the present application, combined with Figure 4 , Figure 4 The flow of the method shown is as follows:

[0072] S41: The first write control module receives and parses a first data packet from the Ethernet, and writes the first data packet into a first write target cache queue determined by the first queue control module.

[0073] After receiving the first data packet from the Ethernet, the first write control module parses the first data packet according to the Ethernet protocol to obtain the parsed first data packet. The first write control module sends a write request to the first queue control module, and the write request is used to request to write the first data packet. The first queue control module determines the first write target cache queue for the first write control module. Specifically, a cache queue is determined from each first cache queue of the first cache as the first write target cache queue. The first queue control module sends the write response to the first write control module, and the write response includes: address-related information of the first write target cache queue, wherein the address-related information can be the queue index number corresponding to the first write target cache queue, or the base address of the first write target cache queue. The first write control module writes the parsed first data packet into the first write target cache queue.

[0074] S42: The first read control module reads the first data packet from the first read target cache queue determined by the first queue control module, encapsulates the first data packet, and sends the first data packet to the AUTBUS.

[0075] When the first read-out control module wants to read data, the first read-out control module sends a read request to the first queue control module, the read request is used to request to read the first data packet, the first queue control module determines the first read target cache queue for the first read-out control module, specifically, determines a cache queue from each first cache queue of the first cache as the first read target cache queue, the first queue control module sends a read response to the first read-out control module, the read response includes: address-related information of the first read target cache queue, wherein the address-related information may be the queue index number corresponding to the first read target cache queue, or the base address of the first read target cache queue, the first read-out control module reads the first data packet from the first read target cache queue, encapsulates the first data packet according to the AUTBUS protocol, and sends it to the AUTBUS.

[0076] In this embodiment, a first write control module is used to receive and parse a first data packet from the Ethernet, and write the first data packet into a first write target cache queue determined by a first queue control module. A first read control module is used to read the first data packet from a first read target cache queue determined by the first queue control module, encapsulate the data packet and send it to the AUTBUS. Thus, data is sent from the Ethernet to the AUTBUS through hardware. In this process, the CPU does not need to be involved, which improves communication efficiency and reduces the burden on the CPU.

[0077] Figure 5 Another schematic diagram of a process of sending data from Ethernet to AUTBUS provided in an embodiment of the present application, Figure 5 is Figure 4 Based on the embodiment shown, a possible implementation of S41 and S42 is further described as follows: Figure 5 As shown, the method of this embodiment is as follows:

[0078] S411: The first write control module receives and parses a first data packet from the Ethernet.

[0079] S412: The first queue control module determines the first write target cache queue according to the empty and full flags of each first cache queue in the first buffer and a preset order.

[0080] Among them, the first cache includes multiple first cache queues, for example, there can be 256 first cache queues, and the first queue control module maintains the empty and full flags of each first cache queue. When the empty and full flags of the first cache queue are empty flags, it means that there is no valid data in the first cache queue, and new data can be written to the first cache queue, and it can be determined as the first write target cache queue; when the empty and full flags of the first cache queue are full flags, it means that there is valid data in the first cache queue, and new data cannot be written to the first cache queue. The empty and full flags corresponding to each first cache queue can be represented by 1 bit. When the value of the bit is 1, it indicates that the corresponding first cache queue is full, and when the value of the bit is 0, it indicates that the corresponding first cache queue is empty. The opposite is also true. For example, when the value of the bit is 1, it indicates that the corresponding first cache queue is empty, and when the value of the bit is 0, it indicates that the corresponding first cache queue is full.

[0081] The preset order may be to poll in descending order according to the index number of the first cache queue; or it may be determined in other orders, and this application does not impose any restrictions on this. As long as the first queue control module can determine a first cache queue in an empty state as the first write target cache queue according to the empty and full flags of each first cache queue in the first buffer.

[0082] S413: The first write control module writes the first data packet into the first write target cache queue determined by the first queue control module.

[0083] S414: the first queue control module controls the first write control module to set the empty and full flags of the first write target cache queue to full after writing the first data packet into the first write target cache queue.

[0084] After the first write control module writes the first data packet into the first write target cache queue, the first queue control module needs to set the empty and full flags of the first write target cache queue to full, so as to prevent the first queue control module from allocating the first write target cache queue to the first write control module again for data packet writing before the first data packet in the first write target cache queue is read. Thus, the reliability of data transmission is improved.

[0085] S421: The first queue control module determines the first read target cache queue according to the empty and full flags of each first cache queue in the first buffer and a preset order.

[0086] When the empty and full flags of the first cache queue are empty flags, it means that there is no valid data in the first cache queue, that is, there is no data that needs to be read. When the empty and full flags of the first cache queue are full flags, it means that there is valid data in the first cache queue, which can be allocated to the first read-out control module, and the first read-out control module reads the valid data therein.

[0087] When determining the first read target cache queue, a first-in-first-out read strategy may be adopted, that is, first read the first written data, then read the later written data, thereby ensuring the continuity and timeliness of the data, etc. The first queue control module determines a first cache queue in a full state from the first cache in a preset order as the first read target cache queue.

[0088] S422: The first read control module reads the first data packet from the first read target cache queue and sends it to the AUTBUS.

[0089] S423: The first queue control module controls the first read control module to set the empty and full flags of the first read target cache queue to empty after the first read target cache queue has finished reading the first data packet from the first read target cache queue.

[0090] After the first read control module completes reading the first data packet from the first read target cache queue, the first queue control module sets the empty and full flags of the first read target cache queue to empty, which means that the data in the first read target cache queue is invalid after being read, and the first queue control module can be allocated to the first write control module to write new data.

[0091] In this embodiment, the first queue control module determines the first write target cache queue for the first write control module through the empty and full flags of the first cache queue, and determines the first read target cache queue for the first read control module. The empty and full flags of the first cache queue can be maintained by hardware registers, which is simple to implement and low cost.

[0092] Figure 6 A schematic diagram of a process of sending data from Ethernet to AUTBUS provided in another embodiment of the present application, Figure 6 is Figure 5 Based on the illustrated embodiment, a possible implementation of S412, S413, S421, and S422 is further described as follows:

[0093] Among them, a possible implementation of S412 is as follows: Description of S4121-S4123:

[0094] S4121: The first queue control module traverses the empty and full flags of the first cache queues in a preset order, and determines that the first cache queue whose empty and full flag is empty is the first write target cache queue.

[0095] Optionally, the first queue control module can maintain a first queue state vector, which includes a first preset number of bits, each bit corresponding to a first cache queue; the first preset number can be set according to the number of first cache queues, for example, if the number of first cache queues is 256, then the first preset number is 256, that is, the width of the first queue state vector is 256 bits, each bit corresponds to a first cache queue, and the initial value of the first queue state vector is [00000000…0], wherein the highest bit, that is, the 255th bit, corresponds to the first cache queue with index number 255, and the lowest bit, that is, the 0th bit, corresponds to the first cache queue with index number 0.

[0096] Optionally, the first queue control module can determine, in order of bits from high to low, that the first cache queue with the first empty or full state in the first queue state vector is the first write target cache queue, and the index number of the first write target cache queue is the sum of the sequence number of the first write target cache queue in the first queue state vector plus the value of the first queue shift counter; for example: the current first queue state vector is [00000000…0], the value of the first queue shift counter is 0, and the sequence number of the first bit that is 0 is 255. Based on the bit sequence number and the value of the first queue shift counter, it can be determined that the index number of the first write target cache queue is 255.

[0097] S4122: The first queue control module determines a base address of the first write target cache queue based on the index number of the first write target cache queue and the size of each of the first cache queues.

[0098] The sizes of the first cache queues in the first cache are equal, so the base address of the first cache queue can be determined based on the index number of the first cache queue and the size of the first cache queue. The base address refers to the starting position of the first cache queue storing data in the memory. Based on the multiplication of the index number and the size of the first cache queue, the base address of the corresponding first cache queue can be obtained. For example: the size of the first cache queue is S bytes, the index number of the first cache queue is 0, then the base address of the first cache queue is 0, the index number of the first cache queue is 1, then the base address of the first cache queue is S, the index number of the first cache queue is 2, then the base address of the first cache queue is 2S, ..., and so on. The index number of the first cache queue is 255, then the base address of the first cache queue is 255S.

[0099] S4123: The first queue control module sends the base address of the first write target cache queue to the first write control module.

[0100] Optionally, the first queue control module can send the base address of the first write target cache queue to the first write control module; the first queue control module can also send the index number of the first target cache queue to the first write control module, and the first queue control module determines the base address of the first target cache queue based on the size of the first cache queue with the index number.

[0101] Accordingly, a possible implementation of S413 is shown in S413':

[0102] S413': The first write control module writes the first data packet into the first write target cache queue according to the base address of the first write target cache queue.

[0103] S414: the first queue control module controls the first write control module to set the empty and full flags of the first write target cache queue to full after writing the first data packet into the first write target cache queue.

[0104] When the first write control module completes writing the first data packet to the first write target cache queue, the empty and full states corresponding to the first write target cache queue in the first queue state vector are set to full. For example, the index number of the first target cache queue is 255. When the first write control module completes writing the first data packet to the first write target cache queue, the 255th bit position is set to 1, and the first queue state vector is changed to [10000000…0]. Then, all bits of the first queue state vector are circularly shifted right once, and the first queue state vector becomes [01000000…0]. The value of the first queue shift counter is controlled to increase by 1. The value of the shift counter can be stored in the shift count register. For example, the first right shift of 1 bit causes the value of the first queue shift counter to be 1.

[0105] A possible implementation of S421 is as follows: Description of S4211-S4213:

[0106] S4211: The first queue control module traverses the empty and full flags of the first cache queues in a preset order, and determines that the first cache queue whose empty and full flag is full is the first read target cache queue.

[0107] Optionally, the first queue control module can determine, in order of bits from low to high, that the first cache queue with a full empty or full state in the first queue state vector is the first read target cache queue, and the index number of the first read target cache queue is the sum of the sequence number of the first read target cache queue in the first queue state vector plus the value of the first queue shift counter.

[0108] Combined with the above example, the first queue state vector becomes [01000000…0], the first bit numbered 1 is 254, and the value of the first queue shift counter is 1. Based on the bit number and the value of the first queue shift counter, it can be determined that the index number of the first read target cache queue is 255.

[0109] S4212: The first queue control module determines a base address of the first read target cache queue based on the index number of the first read target cache queue and the size of each first cache queue.

[0110] This step can be described in detail in S4122 and will not be repeated here.

[0111] S4213: The first queue control module sends the base address of the first read target cache queue and the length of the first data packet to the first read control module.

[0112] Accordingly, a possible implementation of S422 is shown in S422':

[0113] S422': The first read control module reads the first data packet from the first read target cache queue according to the base address of the first read target cache queue.

[0114] S423: When the first read control module completes reading the first data packet from the first read target cache queue, the empty or full state corresponding to the first read target cache queue in the first queue state vector is set to empty.

[0115] In this embodiment, the empty and full states of the first cache queue are maintained based on the first queue state vector, and the first write target cache queue and the first read target cache queue are determined based on the first queue state vector and the first queue shift counter. The implementation is simple, and the first write target cache queue is determined in order from high bits to low bits, and the first read target cache queue is determined in order from low bits to high bits, which improves the search efficiency and reduces the communication delay.

[0116] When the size of the first data packet sent by Ethernet is larger than the data packet length that can be processed by the AUTBUS protocol, the first readout control module needs to perform packet processing on the first data packet to split the Ethernet data packet into multiple smaller data packets to meet the data transmission requirements of the AUTBUS protocol. Figure 7 As shown, Figure 7 A schematic diagram of a process of sending data from Ethernet to AUTBUS provided in another embodiment of the present application, Figure 7 Based on the above embodiment, a possible implementation of S42 is further described:

[0117] S42A: The first read control module determines whether the length of the first data packet in the first read target cache queue determined by the first queue control module is less than or equal to the first preset length. If so, execute S42B, if not, execute S42C.

[0118] Among them, the first preset length can be the length of the data packet that can be processed by the AUTBUS protocol. When the first readout control module determines that the length of the first data packet sent by the first queue control module is less than or equal to the first preset length, S42B can be executed, that is, the requirement of the length of the data packet that can be processed by the AUTBUS protocol is met, and there is no need to perform packet subdivision processing. When the first readout control module determines that the length of the first data packet sent by the first queue control module is greater than the first preset length, it means that it exceeds the requirement of the length of the data packet that can be processed by the AUTBUS protocol, and it is necessary to perform packet subdivision processing, and execute S42C.

[0119] S42B: The first read control module reads the first data packet from the first read target cache queue, encapsulates the data packet, and sends the data packet to the AUTBUS.

[0120] S42C: The first read control module reads the first data packet in the first read target cache queue in packets in sequence according to a second preset length, and encapsulates each packet and sends it to the AUTBUS.

[0121] Wherein, the second preset length is less than or equal to the first preset length.

[0122] For example, the length of the first data packet is 1000 bytes, and the maximum transmission capacity of the AUTBUS protocol is 100 bytes. Assuming that the second preset length is 100 bytes, the control module will divide the first data packet into 10 packets of 100 bytes. The first readout control module reads 100 bytes of data each time, and after reading, encapsulates the read packet data according to the AUTBUS protocol, which may include adding the header information, tail check, packet type identification, and packet sequence number required by the AUTBUS protocol to ensure that the data transmission on the AUTBUS network is reliable and compliant with the protocol. After encapsulation, these packets will be sent to the AUTBUS network in sequence.

[0123] In this embodiment, the first read-out control module determines whether the length of the first data packet in the first read target cache queue determined by the first queue control module is less than or equal to the first preset length, and the first data packet whose length is greater than the first preset length is packetized, thereby realizing the communication of large data packets between Ethernet and AUTBUS through hardware, reducing the limit on the data packet size and expanding the application scenarios.

[0124] Figure 8 A structural schematic diagram of a communication system for sending data from AUTBUS to Ethernet provided in an embodiment of the present application, the system of this embodiment includes: a second write control module, a second queue control module, a second read control module, and a second buffer, wherein the second buffer includes: a second preset number of second cache queues; wherein the second write control module is used to receive and parse a second data packet from AUTBUS, and write the second data packet into a second write target cache queue determined by the second queue control module, wherein the second write target cache queue is a second cache queue in the second buffer; the second read control module is used to read the second data packet from the second read target cache queue determined by the second queue control module and encapsulate it and send it to the Ethernet, wherein the second read target cache queue is a second cache queue in the second buffer; the second queue control module is used to determine the second write target cache queue for the second write control module, and determine the second read target cache queue for the second read control module.

[0125] Optionally, since the AUTBUS protocol supports transmission of smaller data packets, the data packets received by AUTBUS may be independent data packets or subpackets. In order to ensure the continuity and reliability of data transmission, the subpackets belonging to the same node need to be written into the same cache queue. In this scenario, the second write control module is specifically used to determine that the second data packet received from AUTBUS is an independent data packet, and then write the second data packet into the second write target cache queue determined by the second queue control module; when it is determined that the second data packet received from AUTBUS is a subpacket of the target node, the subpacket is stored in the second write target cache queue corresponding to the target node according to the sequence number of the subpacket. The second write target cache queue corresponding to the target node is the second write target cache queue determined by the second queue control module when the second write control module receives the first subpacket of the target node, and all subpackets of the same target node are written into the same second write target cache queue.

[0126] Optionally, the second write control module is specifically used to determine that the second data packet received from AUTBUS is a subpacket of the target node, then determine the starting address for writing the second data packet according to the base address of the second write target cache queue corresponding to the target node determined by the second queue control module and the length of the written subpacket of the target node, and start writing the second data packet from the starting address.

[0127] Optionally, the second queue control module is specifically used to determine the second write target cache queue and the second read target cache queue according to the empty and full status of each second cache queue in the second cache, the write status of the second cache queue and the read status of the second cache queue.

[0128] Optionally, the second queue control module is specifically used to determine that the second cache queue whose empty and full states are empty and whose write state is not written is the second write target cache queue; and determine that the second cache queue whose empty and full states are full and whose read state is not read is the second read target cache queue.

[0129] Optionally, the second queue control module is specifically used to maintain a second queue state vector, a write state vector and a read state vector, and determine the write target cache queue and / or the read target cache queue based on the second queue state vector, the write state vector and the read state vector;

[0130] Among them, each vector contains the multiple bits, each bit corresponds to a cache queue, the second queue state vector is used to characterize the empty and full status of each cache queue, the write state vector is used to characterize the write status of each cache queue, and the read status vector is used to characterize the read status of each cache queue.

[0131] Optionally, the second write control module is further used to maintain the packet assembly state information corresponding to the node, wherein the packet assembly state information is used to record the target cache queue corresponding to the node in the packet assembly state and the length of the written data;

[0132] When the second write control module receives a data packet from AUTBUS, if the data packet is an independent packet or the first subpacket, it applies to the second queue control module for allocation of a second write target cache queue, and writes the data packet into the second write target cache queue; and based on the node information of the first subpacket, records the packet assembly status information corresponding to the node; if the data packet is an intermediate subpacket or the last subpacket, based on the target cache queue corresponding to the node of the data packet and the length of the written data, writes the data packet to the end of the previous subpacket of the node in the second write target cache queue, and updates the write status information corresponding to the node.

[0133] Optionally, the second read-out control module is specifically used to determine that the length of the data packet in the second read target cache queue is less than or equal to a first preset length, then read the data packet from the second read target cache queue and encapsulate it according to the AUTBUS protocol and send it to the AUTBUS; if it is determined that the length of the data packet in the second read target cache queue is greater than the first preset length, then read the data packet in the second read target cache queue in packets according to the second preset length in sequence, and encapsulate each packet according to the AUTBUS protocol and send it to the AUTBUS, wherein the second preset length is less than or equal to the first preset length.

[0134] Optionally, the second queue control module is specifically used to obtain, in order of bits from high to low, the first cache queue that satisfies both the empty and full states in the second queue state vector and the write state in the write state vector as the second write target cache queue; and to obtain, in order of bits from low to high, the first cache queue that satisfies both the empty and full states in the second queue state vector and the read state in the read state vector as the second read target cache queue.

[0135] Optionally, the index number of the second write target cache queue is the sum of the sequence number of the second write target cache queue in the second queue state vector plus the value of the queue shift counter; the index number of the second read target cache queue is the sum of the sequence number of the second read target cache queue in the second queue state vector plus the value of the queue shift counter.

[0136] Optionally, the write control module is specifically used to complete writing a data packet to the second write target cache queue, then set the empty and full states corresponding to the second write target cache queue in the second queue state vector to full, set the write state corresponding to the second write target cache queue in the write state vector to not written, and circularly shift all bits of the second queue state vector, the write state vector and the read state vector to the right once, and control the value of the queue shift counter to increase by 1;

[0137] The second read-out control module is specifically used to complete reading the data packet from the second read target cache queue, then set the empty and full states corresponding to the second read target cache queue in the second queue state vector to empty, and set the read state corresponding to the second read target cache queue in the read state vector to unread.

[0138] Optionally, the packet assembly state information corresponding to the node includes: an index number or a base address of a second write target cache queue storing data packets of the node, and a length of written data;

[0139] The write control module is specifically used to determine the base address of the second write target cache queue based on the index number or base address of the second write target cache queue, and determine the write start address of the data packet based on the base address and the length of the written data.

[0140] Figure 8 Each module in the system of the embodiment shown can be used to execute Figures 9 to 11 The technical solution of the embodiment of the communication method of Ethernet and AUTBUS shown in the figure, and its implementation principle and technical effect can be found in Figures 9 to 11 Detailed description of the illustrated embodiments.

[0141] Figures 9 to 11 The following is an example of sending data from AUTBUS to Ethernet, that is, a description of communication in the second direction. Fig. 9 A schematic diagram of a process of sending data from AUTBUS to Ethernet provided in an embodiment of the present application, combined with Figure 8 , Fig. 9 The flow of the method shown is as follows:

[0142] S91: The second write control module receives and parses the second data packet from AUTBUS, and writes the second data packet into the second write target cache queue determined by the second queue control module.

[0143] Among them, after the second write control module receives the second data packet from AUTBUS, it parses the second data packet according to the AUTBUS protocol to obtain the parsed second data packet. The second write control module sends a write request to the second queue control module, and the write request is used to request to write the second data packet. The second queue control module determines the second write target cache queue for the second write control module. Specifically, a cache queue is determined from each second cache queue of the second cache as the second write target cache queue. The second queue control module sends a write response to the second write control module, and the write response includes: address-related information of the second write target cache queue, wherein the address-related information can be the queue index number corresponding to the second write target cache queue, or the base address of the second write target cache queue. The second write control module writes the parsed second data packet into the second write target cache queue.

[0144] S92: The second read control module reads the second data packet from the second read target cache queue determined by the second queue control module, encapsulates the data packet and sends it to the Ethernet.

[0145] When the second read-out control module wants to read data, the second read-out control module sends a read request to the second queue control module, the read request is used to request to read the second data packet, the second queue control module determines the second read target cache queue for the second read-out control module, specifically, determines a cache queue from each second cache queue of the second cache as the second read target cache queue, the second queue control module sends a read response to the second read-out control module, the read response includes: address-related information of the second read target cache queue, wherein the address-related information can be the queue index number corresponding to the second read target cache queue, or the base address of the second read target cache queue, the second read-out control module reads the second data packet from the second read target cache queue, and encapsulates the second data packet according to the Ethernet protocol and sends it to the Ethernet.

[0146] In this embodiment, a second write control module is used to receive and parse a second data packet from AUTBUS, and write the second data packet into a second write target cache queue determined by a second queue control module. A second read control module is used to read the second data packet from a second read target cache queue determined by the second queue control module, encapsulate the data packet and send it to the Ethernet. Thus, data is sent from AUTBUS to Ethernet through hardware, and the CPU does not need to be involved in the process, thereby improving communication efficiency and reducing the burden on the CPU.

[0147] Fig.10 Another schematic diagram of a process of sending data from AUTBUS to Ethernet provided in an embodiment of the present application, Fig.10 is Fig. 9 Based on the embodiment shown, a possible implementation of S91 and S92 is further described as follows: Fig.10 As shown, the method of this embodiment is as follows:

[0148] S911: The second writing control module receives and parses the second data packet from AUTBUS.

[0149] Since the data packets transmitted by the AUTBUS protocol are small, the data packets received by the AUTBUS may be independent data packets or sub-packets. In order to ensure the continuity and reliability of data transmission, the sub-packets belonging to the same node need to be written into the same cache queue.

[0150] After receiving the second data packet from AUTBUS, the second write control module parses the second data packet according to the AUTBUS protocol to obtain a parsed second data packet, and determines whether the second data packet is an independent data packet or a sub-packet according to the parsing result.

[0151] When the second data packet is an independent data packet or the first subpacket of a node, an application is made to the second queue control module for allocation of a second write target cache queue, and S912 is executed. When the second data packet is an intermediate subpacket or the last subpacket, the second write target cache queue is determined based on the packet assembly state information of the node maintained by the second write control module. Specifically, the second write target cache queue can be determined from the packet assembly state information of the node based on the node information to which the intermediate subpacket or the last subpacket belongs.

[0152] S912: The second queue control module determines the second write target cache queue according to the empty and full flags of each second cache queue in the second buffer and the write status of the second cache queue.

[0153] Among them, the second cache includes multiple second cache queues, for example, there can be 256 second cache queues, and the second queue control module maintains the empty and full flags and write status of each second cache queue. When the empty and full flags of the second cache queue are empty flags and the write status is not written, it means that there is no valid data in the second cache queue, and new data can be written to the second cache queue. Therefore, it can be determined that the second cache queue with an empty and full flag and a write status of not written is the second write target cache queue.

[0154] Among them, the empty and full flags corresponding to each second cache queue can be represented by 1 bit, for example, the value of the bit is 1, indicating that the empty and full flags of the second cache queue are full, and the value of the bit is 0, indicating that the empty and full flags of the second cache queue are empty. The write status corresponding to each second cache queue can also be represented by 1 bit, for example, the value of the bit is 1, indicating that the write status of the second cache queue is write completed or write in progress, and the value of the bit is 0, indicating that the write status of the second cache queue is not written. When the value of the bit corresponding to the empty and full flags of the second cache queue is 0 and the value of the bit corresponding to the write status is also 0, it can be determined as the second write target cache queue.

[0155] The reverse is also possible, for example: the empty and full flags corresponding to each second cache queue can be represented by 1 bit, for example, the value of the bit is 0, indicating that the empty and full flags of the second cache queue are full, and the value of the bit is 1, indicating that the empty and full flags of the second cache queue are empty. The write status corresponding to each second cache queue can also be represented by 1 bit, for example, the value of the bit is 0, indicating that the write status of the second cache queue is write completed or write in progress, and the value of the bit is 1, indicating that the write status of the second cache queue is not written. When the value of the bit corresponding to the empty and full flags of the second cache queue is 1 and the value of the bit corresponding to the write status is also 1, it can be determined as the second write target cache queue.

[0156] S913: The second write control module writes the second data packet into the second write target cache queue determined by the second queue control module.

[0157] When the second data packet received by AUTBUS is an independent data packet, the second data packet is written into the second write target cache queue determined by the second queue control module.

[0158] When the second data packet received by AUTBUS is the first subpacket, the second data packet is written into the second write target cache queue determined by the second queue control module, and the packet assembly status information corresponding to the node to which the first subpacket belongs is recorded, wherein the packet assembly status information includes but is not limited to: the second target cache queue corresponding to the node and the packet assembly status.

[0159] If the data packet is an intermediate subpacket or the last subpacket, based on the second target cache queue corresponding to the node of the data packet and the length of the written data, the data packet is written to the end of the previous subpacket of the node in the second write target cache queue, thereby writing all subpackets of the same node into the same second write target cache queue and updating the write status information corresponding to the node.

[0160] Specifically, the base address of the second write target cache queue may be determined according to the index number or base address of the second write target cache queue, and the write start address of the data packet may be determined based on the base address and the length of the written data.

[0161] Optionally, the packet assembly status information includes: packet assembly status (status), the index of the second write target cache queue (addr_index) and the length of the written data (the length of the written sub-packet) (len), wherein status is 1, indicating that the node is in the packet assembly state, and 0 indicates that the target node is not in the packet assembly state. Whether the packet assembly is completed can be determined based on the packet assembly status. Addr_index is used to calculate the base address of the second write target cache queue, and len is used for subsequent packet assembly to find the starting address of the second data packet to be written and calculate the total length of the second data packet; Optionally, it can also include: sequence number (sn), sn represents the sequence number of the sub-packet, and can detect whether an out-of-order packet error occurs. The packet assembly status information can be stored in a RAM, and the RAM is named by the node identifier, thereby establishing a correspondence between the node and the packet assembly status information.

[0162] S914: After the second queue control module controls the second write control module to write the second data packet into the second write target cache queue, the second write target cache queue is set to be full.

[0163] When the second data packet is an independent data packet, after the second write control module writes the second data packet into the second write target cache queue, the second queue control module needs to set the empty and full status of the second write target cache queue to full and the read status of the second write target cache queue to unread.

[0164] When the second data packet is a sub-packet, the second write control module sets the write state of the second write target cache queue to write in progress before starting to write the second data packet.

[0165] When the second data packet is the last subpacket, after the second write control module writes the second data packet into the second write target cache queue, the second queue control module needs to set the empty and full status of the second write target cache queue to full and the read status of the second write target cache queue to unread.

[0166] Thus, the second queue control module is prevented from allocating the second write target cache queue to the second write control module for data packet writing again before the second data packet in the second write target cache queue is read, thereby improving the reliability of data transmission.

[0167] S921: The second queue control module determines the second read target cache queue according to the empty and full flags of each second cache queue in the second cache and the read status of the second cache queue.

[0168] When the empty and full flags of the second cache queue are empty flags, and the write status is not written, it means that there is no valid data in the second cache queue, that is, there is no data that needs to be read. When the empty and full flags of the second cache queue are full flags, and the read status is not read, it means that there is valid data in the second cache queue, which can be allocated to the second read-out control module, that is, the target cache queue that cannot be read is determined, and the second read-out control module reads the valid data therein.

[0169] When determining the second read target cache queue, a first-in-first-out read strategy may be adopted, that is, first read the data written first, then read the data written later, thereby ensuring the continuity and timeliness of the data, etc. The second queue control module determines a second cache queue whose empty and full flag is in a full state and whose read state is unread from the second cache as the second read target cache queue.

[0170] S922: The second read control module reads the second data packet from the second read target cache queue and sends it to the Ethernet.

[0171] S923: After the second queue control module controls the second read control module to complete reading the second data packet from the second read target cache queue, the empty and full states of the second read target cache queue are set to empty, and the write state of the second read target cache queue is set to unwritten.

[0172] After the second read control module completes reading the second data packet from the second read target cache queue, the second queue control module sets the empty and full flags of the second read target cache queue to empty, which means that the data in the second read target cache queue is invalid after being read, and the second queue control module can be assigned to the second write control module to write new data.

[0173] In this embodiment, the second queue control module determines the second write target cache queue for the second write control module through the empty and full flags, write status and read status of the second cache queue, and determines the second read target cache queue for the second read control module. The empty and full flags, write status and read status of the second cache queue can be maintained through hardware registers, which is simple to implement and low cost.

[0174] Fig.11 A schematic diagram of a process of sending data from AUTBUS to Ethernet provided in another embodiment of the present application, Fig.11 is Fig.10 Based on the illustrated embodiment, a possible implementation of S912, S913, S921, and S922 is further described as follows:

[0175] A possible implementation of S912 is as follows: Description of S9121-S9123:

[0176] S9121: The second queue control module determines that the second cache queue whose full state is empty and whose write state is unwritten is the second write target cache queue.

[0177] Optionally, the second queue control module can maintain three state vectors, namely, the second queue state vector, the write state vector and the read state vector, each of which contains a second preset number of bits, and each bit corresponds to a second cache queue; wherein, the second preset number can be set according to the number of second cache queues, for example, if the number of second cache queues is 256, then the second preset number is 256, that is, the width of the second queue state vector, the write state vector and the read state vector are all 256 bits; for the second queue state vector, the value of the bit is 1, indicating that the empty and full state of the corresponding second cache state is full, and the value of the bit is 0, indicating that the empty and full state of the corresponding second cache queue is empty. For the write state vector, the value of the bit is 1, indicating that the write state of the corresponding second cache state is write-in-progress, and the value of the bit is 0, indicating that the write state of the corresponding second cache queue is not written. For the read state vector, the value of the bit is 1, indicating that the read state of the corresponding second cache state is read-in-progress, and the value of the bit is 0, indicating that the read state of the corresponding second cache queue is not read. Status_que[i] represents the i-th bit of the second queue state vector, status_wr[i] represents the i-th bit of the write state vector, and status_rd[i] represents the i-th bit of the read state vector. The range of i is [0,255], as shown in representation 1:

[0178] Table 1 Status definition table

[0179]

[0180] Assume that the initial value of the second queue state vector is [00000000…0], the initial value of the write state vector is [00000000…0], and the initial value of the read state vector is [00000000…0]. The highest bit of the three state vectors, that is, the 255th bit, corresponds to the second cache queue with index number 255, and the lowest bit, that is, the 0th bit, corresponds to the second cache queue with index number 0.

[0181] Optionally, in a possible implementation: the second queue control module is specifically used to obtain, in order of bits from high to low, the first second cache queue that satisfies both the empty and full states in the second queue state vector and the unwritten state in the write state vector as the second write target cache queue.

[0182] The index number of the second write target cache queue is the sum of the sequence number of the second write target cache queue in the second queue state vector plus the value of the second queue shift counter.

[0183] Combined with the above example, the first second cache queue that simultaneously satisfies the empty and full states in the second queue state vector and the unwritten state in the write state vector is the 255th bit, that is, the sequence number of the second write target cache queue in the second queue state vector is 255, and the current value of the second queue shift counter is 0, so the index number of the second write target cache queue is 255.

[0184] In another possible implementation: the second queue control module is specifically used to obtain the first writable second cache queue in the writable queue index vector as the second write target cache queue in the order of bits from high to low, wherein the writable queue index vector is determined based on the second queue state vector and the write state vector.

[0185] The index value of the second write target cache queue is the sum of the sequence number of the second write target cache queue in the writable queue index vector plus the value of the second queue shift counter.

[0186] Among them, the writable queue index vector is:

[0187] vector_wr=~status_que&~status_wr (1)

[0188] Among them, vector_wr represents the writable queue index vector, status_que represents the second queue status vector, status_wr represents the write status vector, vector_wr = ~status_que&~status_wr, indicating that when the empty and full status of the second cache queue is empty, and the write status is not written, the second cache queue is a writable queue. For example, the second queue status vector is [00000000…0], and the write status vector is [00000000…0]. Based on the above formula (1), the writable queue index vector [11111111…1] can be obtained. The first index position of the writable queue index vector that is 1 from the high bit is found, and the corresponding second cache queue is the second write target cache queue. Combined with the above example, the first index position that is 1 from the high bit is the 255th bit. The value of the second queue shift counter is 0. Therefore, the index number of the second write target cache queue is 255.

[0189] The second write target cache queue may be determined by searching the writable queue index vector through a hardware module.

[0190] Based on the sequence number of the second write target cache queue in the writable queue index vector and the value of the second queue shift counter, the index number of the second write target cache queue can be obtained, as shown in formula (2):

[0191] ori_index_w=cur_index_w+que_cnt (2)

[0192] Among them, ori_index_w represents the index number of the second write target cache queue, cur_index_w represents the sequence number of the second write target cache queue in the writable queue index vector, and que_cnt represents the value of the second queue shift counter. If ori_index is greater than 255, oir_index is subtracted by 255, so that the original index number of the queue will be obtained without causing index confusion.

[0193] S9122: When the second data packet received by the second write control module is an independent data packet, the second queue control module determines the base address of the second write target cache queue based on the index number of the second write target and cache queue and the size of the second cache queue; when the second data packet received by the second write control module is a subpacket of the target node, the starting address for writing the second data packet is determined by the base address of the second write target cache queue corresponding to the target node and the length of the subpacket that has been written.

[0194] Optionally, when the second data packet received by the second write control module is an independent data packet or the first subpacket of the target node, the base address of the second write target cache queue can be obtained by multiplying the index number of the second write target cache queue and the size of the second write target cache queue. For example: the size of the second write target cache queue is S bytes, the index number of the second write target cache queue is 0, then the base address of the second write target cache queue is 0, the index number of the second write target cache queue is 1, then the base address of the second write target cache queue is S, the index number of the second write target cache queue is 2, then the base address of the second write target cache queue is 2S,... and so on. If the index number of the second write target cache queue is 255, then the base address of the second write target cache queue is 255S.

[0195] Optionally, when the second data packet received by the second write control module is not the first subpacket of the target node, that is, any subpacket from the second subpacket to the last subpacket, the second queue control module obtains the base address of the second write target cache queue corresponding to the target node based on the index number of the second write target cache queue corresponding to the target node and the size of the second write target cache queue corresponding to the target node, and then determines the starting address for writing the second data packet according to the length of the subpackets already written to the target node. Among them, the second write target cache queue corresponding to the target node is the second write target cache queue determined by the second queue control module for the second write control module when the second write control module receives the first subpacket of the target node, and all subpackets of the same target node are written to the same second write target cache queue.

[0196] Based on the above example, the size of the second write target cache queue corresponding to the target node is S bytes, the index number of the second write target cache queue corresponding to the target node is 0, and the length of the subpacket written to the target node is L. The base address of the second write target cache queue corresponding to the target node is 0, and the starting address for writing the second data packet is 0; the index number of the second write target cache queue corresponding to the target node is 1, and the base address of the second write target cache queue corresponding to the target node is S, and the starting address for writing the second data packet is S+L. The index number of the second write target cache queue corresponding to the target node is 2, and the base address of the second write target cache queue corresponding to the target node is 2S, and the starting address for writing the second data packet is 2S+L, ..., and so on. The index number of the second write target cache queue corresponding to the target node is 255, and the base address of the second write target cache queue corresponding to the target node is 255S, and the starting address for writing the second data packet is 255S+L.

[0197] S9123: The second queue control module sends the base address of the second write target cache queue and the start address of writing the second data packet of the second write cache queue corresponding to the target node to the second write control module.

[0198] Optionally, the second queue control module can send the base address of the second write target cache queue to the second write control module; the second queue control module can also send the index number of the second write target cache queue to the second write control module, and the second queue control module determines the base address of the second write target cache queue based on the index number and the size of the second cache queue; the second queue control module can send the starting address of writing the second data packet to the second write target cache queue corresponding to the target node to the second write control module; the second queue control module can also send the index number of the second write target cache queue corresponding to the target node and the length of the subpacket already written to the target node to the second write control module, and the second queue control module determines the base address of the second write target cache queue corresponding to the target node based on the index number and the size of the second cache queue, and then determines the starting address of writing the second data packet based on the base address of the second write target cache queue corresponding to the target node and the length of the subpacket already written to the target node.

[0199] Accordingly, a possible implementation of S913 is shown in S913':

[0200] S913': When the second data packet received by the second write control module is an independent data packet, the second write control module writes the second data packet to the second write target cache queue according to the base address of the second write target cache queue; when the second data packet received by the second write control module is a subpacket of the target node, the second write control module writes the second data packet to the second write target cache queue corresponding to the target node starting from the starting address of writing the second data packet.

[0201] S914: After the second queue control module controls the second write control module to write the second data packet into the second write target cache queue, the empty and full states of the second write target cache queue are set to full, and the write state corresponding to the second write target cache queue in the write state vector is set to not written.

[0202] When the second data packet is an independent data packet or the first subpacket, before the second write control module writes the second data packet to the second write target cache queue, the write state corresponding to the second write target cache queue in the write state vector is set to write in progress. For example, the index number of the second write target cache queue is 255, and the write state vector is changed to [10000000…0].

[0203] When the second data packet is an intermediate subpacket, the second queue state vector, the write state vector and the read state vector are not changed during the writing process.

[0204] When the second data packet is an independent data packet or the last subpacket, the second write control module completes writing the second data packet to the second write target cache queue, then the empty and full states corresponding to the second write target cache queue in the second queue state vector are set to full, and the write state corresponding to the second write target cache queue in the write state vector is set to not written. For example, the index number of the second write target cache queue is 255. After the second write control module completes writing the second data packet to the second write target cache queue, the 255th bit position is set to 1, and the second queue state vector is changed to [10000000…0], and the write state vector is changed to [10000000…0]. The value of the shift counter of the second queue is controlled to be increased by 1. The value of the shift counter can be stored in the shift count register. For example, the first right circular shift of 1 bit causes the value of the shift counter of the second queue to be 1.

[0205] A possible implementation of S921 is as follows: Description of S9211-S9213:

[0206] S9211: The second queue control module determines that the second cache queue whose empty or full state is full and whose read state is unread is the second read target cache queue.

[0207] Among them, a possible implementation method is: in the order of bits from low to high, the first second cache queue that satisfies both the empty and full states in the second queue state vector as full, and the read state in the read state vector as unread is obtained as the second read target cache queue; the index number of the second read target cache queue is the sum of the sequence number of the second read target cache queue in the second queue state vector plus the value of the second queue shift counter. For example: the second queue state vector is changed to [01000000…0], the read state vector is [00000000…0], and the value of the second queue shift counter is 1. Then the first second cache queue that satisfies both the empty and full states in the second queue state vector as full, and the read state in the read state vector as unread corresponds to the 254th bit, that is, the sequence number of the second read target cache queue in the second queue state vector is 254, and the current value of the second queue shift counter is 1, so the index number of the second read target cache queue is 255.

[0208] Another possible implementation is: in order of bits from low to high, obtaining the first readable second cache queue in the readable queue index vector as the second read target cache queue, wherein the readable queue index vector is determined based on the second queue state vector and the read state vector.

[0209] The index number of the second read target cache queue is the sum of the sequence number of the second read target cache queue in the readable queue vector plus the value of the second queue shift counter.

[0210] Among them, the readable queue index vector is:

[0211] vector_rd=status_que&~status_rd (3)

[0212] Wherein, vector_rd represents the readable queue index vector, status_que represents the second queue status vector, status_rd represents the read status vector, vector_rd=status_que&~status_rd, indicating that when the empty and full status of the second cache queue is full, and the read status is unread, the second cache queue is a readable queue. For example, the second queue status vector is [01000000…0], and the read status vector is [00000000…0]. Based on the above formula (3), it can be obtained that Go to the readable queue index vector [01000000…0], find the first index position of 1 starting from the low bit in the readable queue index vector, and the corresponding second cache queue is the second read target cache queue. It can be seen that starting from the low bit in the readable queue index vector, the first bit that is 1 is the 254th bit. In the second queue state vector, the value of the 254th bit is 1, that is, the sequence number of the second read target cache queue in the readable queue index vector is 254, and the current value of the second queue shift counter is 1. Therefore, the index number of the second read target cache queue is 255.

[0213] Optionally, the same hardware module as the writable queue index vector can be used to search for the readable queue index vector to determine the second read target cache queue: the high and low bits of the readable queue index vector are reversed and then input into the hardware search module part, and finally the index number is converted to obtain the index number of the second read target cache queue.

[0214] Based on the sequence number of the second read target cache queue in the readable queue index vector and the value of the second queue shift counter, the index number of the second read target cache queue can be obtained, as shown in formula (4):

[0215] ori_index_r=cur_index_r+que_cnt (4)

[0216] Among them, ori_index_r represents the index number of the second read target cache queue, cur_index_r represents the sequence number of the second read target cache queue in the readable queue index vector, and que_cnt represents the value of the second queue shift counter. If ori_index is greater than 255, oir_index is subtracted by 255, so that the original index number of the queue will be obtained without causing index confusion.

[0217] S9212: The second queue control module determines a base address of the second read target cache queue based on the index number of the second read target cache queue and the size of the second cache queue.

[0218] This step can be described in detail in S9122 and will not be repeated here.

[0219] S9213: The second queue control module sends the base address of the second read target cache queue to the second read control module.

[0220] Accordingly, a possible implementation of S922 is shown in S922':

[0221] S922': The second read control module reads the second data packet from the second read target cache queue according to the base address of the second read target cache queue.

[0222] In combination with the above example, the index number of the second read target cache queue is determined to be 255. When the second data packet is an independent data packet or the first subpacket, before the second read control module reads the second data packet from the second read target cache queue, the read state corresponding to the second read target cache queue in the read state vector is set to read in progress. For example, the read state vector is changed to [01000000…0].

[0223] S923: After the second queue control module controls the second read control module to complete reading the second data packet from the second read target cache queue, the full and empty status of the second read target cache queue is set to empty, and the read status of the second read target cache queue is set to unread.

[0224] When the second data packet is an intermediate subpacket, the second queue state vector, the write state vector and the read state vector are not changed during the reading process.

[0225] When the second data packet is an independent data packet or the last subpacket, the second read-out control module completes reading the second data packet from the second read target cache queue, and then sets the empty and full states corresponding to the second read target cache queue in the second queue state vector to empty, and sets the read state corresponding to the second read target cache queue in the read state vector to unread. In combination with the above example, the second queue state vector is changed to [00000000…0], and the read state vector is changed to [00000000…0].

[0226] In this embodiment, the empty and full states, write states and read states of the second cache queue are maintained based on the second queue state vector, the write state vector and the read state vector, and the second write target cache queue is determined in order from high bits to low bits, and the second read target cache queue is determined in order from low bits to high bits, thereby improving the search efficiency and reducing the communication delay.

[0227] Fig.12 A schematic diagram of the structure of an Ethernet and AUTBUS communication chip provided in an embodiment of the present application, such as Fig.12 As shown, it includes: a write control module, a queue control module, a read control module and a buffer, wherein the buffer includes: a plurality of buffer queues;

[0228] The write control module is used to receive and parse the data packet sent by the sender, and write the data packet into the write target cache queue determined by the queue control module, wherein the write target cache queue is a cache queue in the cache;

[0229] The read control module is used to read the data packet from the read target cache queue determined by the queue control module and send it to the receiving end after encapsulation, wherein the read target cache queue is a cache queue in the cache;

[0230] The queue control module is used to determine the write target cache queue for the write control module and determine the read target cache queue for the read control module.

[0231] The Ethernet and AUTBUS communication chips of this embodiment are used to execute the technical solutions of the above-mentioned method embodiments. The implementation principles and technical effects are similar and will not be repeated here.

[0232] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosed concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other to form a technical solution.

[0233] In addition, although each operation is described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or to be performed in a sequential order. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although some specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the application. Some features described in the context of a separate embodiment can also be implemented in a single embodiment in combination. On the contrary, the various features described in the context of a single embodiment can also be implemented in multiple embodiments individually or in any suitable sub-combination mode.

[0234] Although the subject matter has been described in language specific to structural features and / or methodological logical actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. On the contrary, the specific features and actions described above are merely example forms of implementing the claims.

Claims

1. An Ethernet and AUTBUS communication system, characterized in that: include: A write control module, a queue control module, a read control module and a buffer, wherein the buffer comprises: a plurality of buffer queues; The write control module is used to receive and parse the data packet sent by the sender, and write the data packet into the write target cache queue determined by the queue control module, wherein the write target cache queue is a cache queue in the cache; The read control module is used to read the data packet from the read target cache queue determined by the queue control module and send it to the receiving end after encapsulation, wherein the read target cache queue is a cache queue in the cache; The queue control module is used to determine the write target cache queue for the write control module and determine the read target cache queue for the read control module.

2. The communication system according to claim 1, characterized in that The queue control module is specifically used to maintain a queue state vector, a write state vector and a read state vector, and determine the write target cache queue and / or the read target cache queue based on the queue state vector, the write state vector and the read state vector; Among them, each vector contains the multiple bits, each bit corresponds to a cache queue, the queue state vector is used to characterize the empty and full states of each cache queue, the write state vector is used to characterize the write state of each cache queue, and the read state vector is used to characterize the read state of each cache queue.

3. The communication system according to claim 1, characterized in that: The write control module is also used to maintain the packet assembly state information corresponding to the node, and the packet assembly state information is used to record the target cache queue corresponding to the node in the packet assembly state and the length of the written data; When the write control module receives a data packet from AUTBUS, if the data packet is an independent packet or the first subpacket, it applies to the queue control module for allocation of a write target cache queue, and writes the data packet into the write target cache queue; and based on the node information of the first subpacket, records the packet assembly status information corresponding to the node; if the data packet is an intermediate subpacket or the last subpacket, based on the target cache queue corresponding to the node of the data packet and the length of the written data, writes the data packet to the end of the previous subpacket of the node in the write target cache queue, and updates the write status information corresponding to the node.

4. The communication system according to claim 1, characterized in that: The read control module is specifically used to determine that the length of the data packet in the read target cache queue is less than or equal to a first preset length, then read the data packet from the read target cache queue and encapsulate it according to the AUTBUS protocol and then send it to the AUTBUS; If it is determined that the length of the data packet in the read target cache queue is greater than the first preset length, the data packet in the read target cache queue is sub-packeted and read in sequence according to the second preset length, and each sub-packet is encapsulated according to the AUTBUS protocol and sent to the AUTBUS, wherein the second preset length is less than or equal to the first preset length.

5. The communication system according to claim 2, characterized in that: The queue control module is specifically used to obtain, in order of bits from high to low, the first cache queue that satisfies both the empty and full states in the queue status vector and the unwritten state in the write status vector as the write target cache queue; and to obtain, in order of bits from low to high, the first cache queue that satisfies both the empty and full states in the queue status vector and the unread state in the read status vector as the read target cache queue.

6. The communication system according to claim 5, characterized in that: The index number of the write target cache queue is the sum of the sequence number of the write target cache queue in the queue state vector plus the value of the queue shift counter; the index number of the read target cache queue is the sum of the sequence number of the read target cache queue in the queue state vector plus the value of the queue shift counter.

7. The communication system according to claim 6, characterized in that: The write control module is specifically used to complete writing a data packet to the write target cache queue, then set the empty and full states corresponding to the write target cache queue in the queue state vector to full, set the write state corresponding to the write target cache queue in the write state vector to unwritten, and circularly shift all bits of the queue state vector, the write state vector and the read state vector to the right once, and control the value of the queue shift counter to increase by 1; The read control module is specifically used to complete reading a data packet from a read target cache queue, then set the empty and full states corresponding to the read target cache queue in the queue state vector to empty, and set the read state corresponding to the read target cache queue in the read state vector to unread.

8. The communication system according to claim 3, characterized in that: The packet assembly state information corresponding to the node includes: the index number or base address of the write target cache queue storing the data packet of the node, and the length of the written data; The write control module is specifically used to determine the base address of the write target cache queue based on the index number or base address of the write target cache queue, and determine the write start address of the data packet based on the base address and the length of the written data.

9. The communication system according to claim 4, characterized in that: The queue control module is further used to send the address information of the read target cache queue and the length information of the data packet to the read control module, and the address information of the data packet includes: an index number or a base address.

10. A communication chip for Ethernet and AUTBUS, characterized in that: include: A write control module, a queue control module, a read control module and a buffer, wherein the buffer comprises: a plurality of buffer queues; The write control module is used to receive and parse the data packet sent by the sender, and write the data packet into the write target cache queue determined by the queue control module, wherein the write target cache queue is a cache queue in the cache; The read control module is used to read the data packet from the read target cache queue determined by the queue control module and send it to the receiving end after encapsulation, wherein the read target cache queue is a cache queue in the cache; The queue control module is used to determine the write target cache queue for the write control module and determine the read target cache queue for the read control module.

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