Digital-analog collaborative test method

Abstract

The invention discloses a digital-analog collaborative test method, which comprises the following steps of: in a parameter configuration stage, embedding a trigger mark into a preset vector row to generate a test vector, and writing the test vector into a digital board card; configuring a trigger event corresponding to the trigger signal and first delay time; in the test stage, the digital board card detects whether a to-be-executed vector line has a trigger mark or not; a trigger signal corresponding to the trigger mark is sent to the system board card; the system board card sends the trigger signal to a corresponding simulation board card, and the simulation board card determines first delay time and a trigger event according to the trigger signal; delaying the trigger event for a first delay time and then triggering; the digital board card delays a second delay time after sending the trigger signal and sends test data corresponding to the vector line to the to-be-tested device; in the triggering process of the triggering event, the end time of the second delay time is aligned with the end time of the first delay time. According to the invention, the efficiency of digital-analog collaborative testing can be improved.

Description

Technical Field

[0001] The present invention relates to the field of testing technology, and in particular to a digital-analog collaborative testing method. Background Art

[0002] In automatic test systems, such as automatic test equipment (ATE), digital-analog collaborative work technology is the key to ensuring the reliability of test results and test efficiency. Through precise time synchronization and data synchronization, digital-analog collaborative work technology can avoid errors caused by time differences and ensure the accuracy and consistency of data analysis. Therefore, the introduction of digital-analog collaborative work technology is of great significance to improving the performance and reliability of automatic test equipment.

[0003] In the related technology, the collaborative work of digital resources and analog resources is realized based on trigger pulses. For example, a specific synchronization pulse sequence is embedded in the digital test vector. When the pulse sequence receives the synchronization pulse, the preset response action will be executed, thereby realizing the digital-analog collaborative test process. Although this method solves the problem of collaborative testing between digital resources and analog resources, it still has certain limitations in dealing with complex test processes, especially in test scenarios involving multiple boards and multiple events.

[0004] In the related art, after completing a test process, it is necessary to pause the test process, extract the required data, and then reconfigure and execute the next collaborative event. This method of repeatedly starting and stopping the test equipment significantly reduces the overall test efficiency. Summary of the invention

[0005] The present invention provides a digital-analog collaborative testing method to improve the efficiency of the digital-analog collaborative testing.

[0006] According to one aspect of the present invention, a digital-analog collaborative testing method is provided, which is applied to an automatic testing system, wherein the automatic testing system comprises a digital board, a system board and at least one analog board; the digital board and the analog board are both communicatively connected to the system board;

[0007] The digital-analog collaborative testing method comprises:

[0008] In the parameter configuration stage, a trigger mark is embedded in a preset vector row to generate a test vector, and the test vector is written into the digital board; a trigger event and a first delay time corresponding to a trigger signal are configured and written into the analog board;

[0009] In the test phase, the digital board detects whether the vector line to be executed has the trigger mark; if the vector line to be executed has the trigger mark, a trigger signal corresponding to the trigger mark is sent to the system board;

[0010] The system board sends the trigger signal to the corresponding analog board; the analog board determines a first delay time and a trigger event according to the trigger signal, and triggers the trigger event after delaying the trigger event by the first delay time;

[0011] The digital board sends the test data corresponding to the vector row to the device under test by delaying a second delay time after sending the trigger signal; during the triggering process of a trigger event, the end time of the second delay time is aligned with the end time of the first delay time.

[0012] Optionally, the digital board detects whether the vector row to be executed has the trigger mark, including:

[0013] The digital board detects whether the trigger flag of the vector row to be executed is a preset value. If the trigger flag is the preset value, it is determined that the vector row to be executed has the trigger mark.

[0014] Optionally, the first delay time corresponding to the configuration trigger signal includes:

[0015] Determining a transmission time of the trigger signal from the digital board to the analog board;

[0016] Determine the preparation time for the analog board to respond to the trigger event according to the trigger event type corresponding to the trigger signal;

[0017] Determine the first delay time according to the second delay time, the transmission time and the preparation time; and / or,

[0018] The analog board determines the trigger event according to the trigger signal, including:

[0019] determining a trigger sequence according to the trigger signal;

[0020] Determine the storage address of the trigger event corresponding to the trigger signal according to the trigger sequence;

[0021] The trigger event corresponding to the trigger sequence is read from the storage address.

[0022] Optionally, the analog board determines a first delay time and a trigger event according to the trigger signal, and triggers the trigger event after delaying the trigger event by the first delay time, further comprising:

[0023] The analog board determines a third delay time according to the trigger signal;

[0024] The analog board delays the first delay time, then delays the third delay time, and then triggers the corresponding trigger event.

[0025] Optionally, before the digital board sends the test data corresponding to the vector row to the device under test for a second delay time after sending the trigger signal, the digital board further includes:

[0026] Determining a transmission time of the trigger signal from the digital board to the analog board;

[0027] Determine the preset preparation time required for the analog board to prepare to respond to and complete the trigger event with the highest complexity among the trigger events;

[0028] The second delay time is determined according to the transmission time and the preset preparation time.

[0029] Optionally, before embedding the trigger mark into the preset vector line to generate the test vector, the method further includes:

[0030] generating a trigger mark corresponding to the trigger sequence;

[0031] The sending of the trigger signal corresponding to the trigger mark to the system board comprises:

[0032] Parsing the trigger sequence corresponding to the trigger mark;

[0033] Encapsulating the trigger sequence into the trigger signal in a preset data format;

[0034] Sending the trigger signal to the system board;

[0035] and / or,

[0036] The parameter configuration stage also includes:

[0037] Configure the second delay time corresponding to the trigger mark and write it into the digital board;

[0038] and / or,

[0039] The parameter configuration stage also includes:

[0040] A trigger matrix of the system board is configured; wherein the trigger matrix is ​​used to represent the routing relationship between the trigger channels of the digital board and the analog board.

[0041] According to another aspect of the present invention, a digital-analog collaborative testing method is provided, which is applied to a digital board, and comprises:

[0042] receiving a test vector, wherein a preset vector row of the test vector is embedded with a trigger mark;

[0043] Detecting whether the vector line to be executed has the trigger mark, and if the vector line to be executed has the trigger mark, sending a trigger signal corresponding to the trigger mark to the system board;

[0044] After sending the trigger signal, delaying the second delay time to send the test data corresponding to the vector row to the device under test;

[0045] The second delay time is equal to the sum of the transmission time from the digital board to the analog board and the preset preparation time required for the analog board to prepare and respond to the trigger event with the highest complexity among the trigger events.

[0046] Optionally, the detecting whether the vector row to be executed has the trigger mark includes:

[0047] It is detected whether the trigger flag of the vector row to be executed is a preset value. If the trigger flag is the preset value, it is determined that the vector row to be executed has the trigger flag.

[0048] According to another aspect of the present invention, a digital-analog collaborative testing method is provided, which is applied to an analog board, and comprises:

[0049] receiving a trigger signal;

[0050] Determine a first delay time and a trigger event according to the trigger signal;

[0051] The triggering event is delayed by the first delay time before being triggered.

[0052] Optionally, determining the first delay time and the trigger event according to the trigger signal includes:

[0053] Determining the first delay time includes:

[0054] determining a trigger sequence according to the trigger signal;

[0055] Determining a transmission time of the trigger signal from the digital board to the analog board;

[0056] Determine the preparation time for the analog board to respond to the trigger event according to the trigger event type corresponding to the trigger sequence;

[0057] Determine the first delay time according to the second delay time, the transmission time and the preparation time;

[0058] Determining a trigger event according to the trigger signal includes:

[0059] determining a trigger sequence according to the trigger signal;

[0060] Determine the storage address of the trigger event corresponding to the trigger signal according to the trigger sequence;

[0061] The trigger event corresponding to the trigger sequence is read from the storage address.

[0062] Optionally, before delaying the trigger event by the first delay time and performing triggering, the method further includes:

[0063] determining a third delay time according to the trigger signal;

[0064] The step of delaying the triggering event preparation by the first delay time to trigger the event further includes:

[0065] The analog board delays the first delay time, then delays the third delay time, and then triggers the corresponding trigger event.

[0066] Optionally, before receiving the trigger signal, the method further comprises:

[0067] Write the trigger event corresponding to the trigger signal and the corresponding first delay time.

[0068] The technical solution of the embodiment of the present invention adopts a digital-analog collaborative testing method, which includes: in the parameter configuration stage, embedding a trigger tag into a preset vector row to generate a test vector, and writing the test vector into a digital board; configuring the trigger event and the first delay time corresponding to the trigger tag and writing them into the analog board; in the test stage, the digital board detects whether there is a trigger tag in the vector row to be executed; if there is a trigger tag in the vector row to be executed, the trigger signal corresponding to the trigger tag is sent to the system board; the system board sends the trigger signal to the corresponding analog board, and the analog board determines the first delay time and the trigger event according to the trigger signal; the trigger event is delayed by the first delay time and then triggered; the digital board delays the second delay time after sending the trigger signal and sends the test data corresponding to the vector row to the device under test; in the triggering process of a trigger event, the end time of the second delay time is aligned with the end time of the first delay time. By embedding the trigger tag in the test vector, each trigger tag corresponds to a trigger sequence, and different trigger tags correspond to different trigger sequences. Therefore, multiple different trigger events in the same analog board can be controlled in a test process, thereby improving the efficiency and flexibility of the test. In the analog board, different analog boards can also execute different trigger events for different trigger marks. Therefore, not only can the collaborative testing of digital boards and analog boards be realized, but also different trigger events corresponding to different analog boards can be controlled in a test process, further improving the flexibility of the test. In addition, by setting the second delay time for the digital board and the first delay time for the analog board, the triggering time of the triggering event is aligned with the output time of the test data, ensuring the delay consistency of the digital board when processing various triggering events, thereby improving the accuracy of the test.

[0069] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0071] Figure 1 A flowchart of a digital-analog collaborative testing method for an automatic testing system provided by an embodiment of the present invention;

[0072] Figure 2 A schematic diagram of the structure of an automatic testing system provided by an embodiment of the present invention;

[0073] Figure 3 A schematic diagram of trigger mark mapping in a digital board and an analog board provided by an embodiment of the present invention;

[0074] Figure 4 A schematic diagram of a corresponding relationship between a second delay time and a first delay time provided in an embodiment of the present invention;

[0075] Figure 5 A schematic diagram of the digital-analog collaborative working principle of an automatic test system provided by an embodiment of the present invention;

[0076] Figure 6 A corresponding diagram of the working steps of a digital-analog collaborative testing method and an automatic testing system provided by an embodiment of the present invention;

[0077] Figure 7 A flowchart of another digital-analog collaborative testing method provided by an embodiment of the present invention;

[0078] Figure 8 A flowchart of another digital-analog collaborative testing method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0079] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0080] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0081] Figure 1 A flowchart of a digital-analog collaborative testing method for an automatic testing system provided by an embodiment of the present invention, Figure 2 A schematic diagram of the structure of an automatic test system provided by an embodiment of the present invention, referring to Figure 1 and Figure 2 The automatic test system comprises a digital board 1 , a system board 2 and at least one analog board 3 ; the digital board 1 and the analog board 3 are both connected to the system board 2 for communication.

[0082] Digital-analog collaborative testing methods include:

[0083] Step S110, in the parameter configuration stage, embed the trigger mark into the preset vector line to generate a test vector, and write the test vector into the digital board; configure the trigger event and the first delay time corresponding to the trigger signal and write them into the analog board.

[0084] Specifically, the digital board 1 can load a test vector and send the corresponding test sequence in the test vector to the device under test (DUT) 4. The specific format of the test vector is well known to those skilled in the art and will not be repeated here. The test vector in this embodiment can be a digital test vector. Before testing the device under test, it is necessary to configure the parameters of the automatic test system. For example, write a test vector, etc. The test vector includes multiple vector rows, and the digital board loads each vector row in sequence, and performs corresponding actions according to the meaning of the vector row, such as outputting test data to the device under test 4. In this embodiment, when writing a test vector, a trigger mark can be embedded in the preset vector row, and the trigger mark is used to indicate whether the vector row needs to trigger a trigger event, and the sequence corresponding to the triggered trigger event. Among them, the trigger event can be an analog event occurring in an analog board. In the digital board 1, the total number of sequences corresponding to the trigger mark can be greater than or equal to 1, that is, different sequences may correspond to different trigger events, and of course, they can also correspond to the same trigger event (specifically related to the definition of the trigger mark in the analog board). The number of trigger markers configured in the test vector is not limited, for example, one trigger marker may be embedded, or multiple trigger markers may be embedded.

[0085] After the digital vector embedded with the trigger mark is written, it can be written into the digital board 1.

[0086] For the analog board 3, the analog board 3 needs to respond to the trigger mark to execute the corresponding trigger event. The trigger mark in the digital board 1 is sent to the analog board in the form of a trigger signal, that is, each trigger mark corresponds to a trigger signal. Further, the trigger signal includes a trigger sequence, and the analog board 3 will parse the trigger sequence after receiving the trigger signal, and each trigger sequence corresponds to a trigger event. In other words, the trigger event corresponding to the configuration trigger signal can specifically be the trigger event corresponding to the configuration trigger sequence. The analog board 3 includes various types of analog devices, such as waveform generators, waveform collectors, etc. Before testing the device under test, the analog board 3 is parameterized. In the analog board 3, each trigger mark corresponds to one or a group of trigger events, and different trigger marks can correspond to different trigger events. In some embodiments, the automatic test system may have multiple analog boards, and the trigger events required to be executed by different analog boards may be different. In this embodiment, the trigger events corresponding to the same trigger mark in different analog boards may be different.

[0087] During the testing phase, the digital-analog collaborative testing methods include:

[0088] Step S120, the digital board detects whether there is a trigger mark in the vector line to be executed; if there is a trigger mark in the vector line to be executed, a trigger signal corresponding to the trigger mark is sent to the system board;

[0089] Specifically, when executing the test vector, the digital board continuously detects whether the vector line to be executed has a trigger mark. If the vector line to be executed has a trigger mark, it indicates that the analog board 3 needs to act, so the trigger signal corresponding to the trigger mark is first sent to the system board 2.

[0090] Step S130, the system board sends a trigger signal to the corresponding analog board, and the analog board determines a first delay time and a trigger event according to the trigger signal; and triggers the trigger event after delaying the trigger event by the first delay time;

[0091] Specifically, the system board 2 sends the trigger signal to the corresponding analog board according to the predetermined routing rule, for example, the trigger signal can be sent to the corresponding one or more analog boards 3, so that the corresponding analog board can receive the trigger signal. After receiving the trigger signal, the analog boards 3 each execute the corresponding trigger event according to the self-defined corresponding relationship. Among them, the analog board 3 executes the corresponding trigger event according to the trigger event corresponding to the trigger mark configured internally, and the trigger events triggered by different analog boards for the same trigger mark may be different, thereby realizing the collaborative test of the digital board and the analog board. The trigger mark is defined in the digital board and the analog board respectively, which can more intuitively show the binding relationship between the test vector and the trigger event, so as to achieve the purpose of optimizing the test process.

[0092] The analog board receives the trigger signal and enters the stage of preparing to respond to the trigger event. The trigger event can only be triggered after the preparation response of the trigger event is completed. The completion of the preparation response of the trigger event means that the analog board can be triggered from the time when the trigger signal is received to the time when the preparation of the trigger event is completed. This period of time is defined as the preparation time. The preparation time mainly includes the time required for the analog board to parse the trigger signal and map the corresponding trigger event. Because the processing flow corresponding to different trigger events is different, the preparation time corresponding to different trigger events is different; the preparation time corresponding to the trigger event with high complexity is longer, and the preparation time corresponding to the trigger event with low complexity is shorter. In this embodiment, if the trigger event is triggered immediately after the preparation is completed, then due to the different preparation times corresponding to different trigger events, the triggering moments of the trigger events of different analog boards will not be aligned when there are multiple analog boards. In this embodiment, by setting the first delay time, the first delay times corresponding to different trigger events are different, and the triggering event is triggered after the preparation response of the trigger event is completed, and the first delay time is delayed before the triggering of the trigger event, so that the triggering moments of different analog boards responding to the trigger event are finally aligned.

[0093] In addition, since the trigger mark embedded in the test vector is in the form of a sequence, different sequences can correspond to different trigger events. Therefore, multiple trigger events can be controlled in one test process. This overcomes the limitation of the related technology that can only handle a single trigger event and improves the flexibility of the test. Different analog boards can trigger different trigger events for the same trigger mark. Therefore, in one test process, multiple analog boards can be coordinated to trigger different trigger events without repeated start and stop, so the test efficiency is greatly improved.

[0094] Step S140, the digital board sends the test data corresponding to the vector row to the device under test for a second delay time after sending the trigger signal; during the triggering process of a trigger event, the end time of the second delay time is aligned with the end time of the first delay time.

[0095] Specifically, the trigger mark needs to be sent from the digital board 1 to the system board 2, and then forwarded by the system board 2 to the analog board 3, and then triggered and executed by the analog board 3. The test data corresponding to the vector row is sent directly to the device under test by the digital board 1. If the trigger signal and the test data are output by the digital board at the same time, the trigger signal needs to pass through a longer transmission path, and the analog board also needs a certain amount of time to process the trigger signal. When the trigger event corresponding to the trigger signal is triggered, a certain delay will be generated relative to the moment when the test data is sent to the device under test, making the test result inaccurate. In this embodiment, each trigger mark corresponds to a second delay time. In the same application scenario, the second delay times corresponding to different trigger marks are consistent; it can be understood that the second delay times corresponding to different application scenarios may be different. By setting the second delay time for the digital board and setting the first delay time for the analog board, the triggering moment of the triggering event and the output moment of the data under test are aligned, thereby improving the accuracy of the test. In addition, when multiple trigger events need to be triggered simultaneously, the response time of all trigger events is aligned with the output time of the test data, that is, the response time of each trigger event is the same, thereby ensuring the delay consistency of the digital board when processing various trigger events, and further improving the accuracy of the test. It should be noted that, in this embodiment, the start time of the trigger process of a trigger event can be the time when the trigger signal is sent from the digital board to the system board, the start time of the second delay time is the same as the start time of the trigger process, and the start time of the first delay time is later than the start time of the trigger process.

[0096] It should be noted that in this embodiment, the digital board acts as the initiator, sending the trigger signal to the system board, which then sends it to the corresponding analog board. In other embodiments, the initiator of the trigger signal is not limited to the digital board. Any board that has the ability to send a trigger signal (and the ability to store corresponding information) can serve as the initiator of the trigger signal, such as an analog board or other types of boards. There is no specific limitation on this and it can be set according to needs.

[0097] The technical solution of this embodiment adopts a digital-analog collaborative test method, which includes: in the parameter configuration stage, embedding a trigger tag into a preset vector row to generate a test vector, and writing the test vector into a digital board; configuring the trigger event and the first delay time corresponding to the trigger tag and writing them into the analog board; in the test stage, the digital board detects whether there is a trigger tag in the vector row to be executed; if there is a trigger tag in the vector row to be executed, the trigger signal corresponding to the trigger tag is sent to the system board; the system board sends the trigger signal to the corresponding analog board, and the analog board determines the first delay time and the trigger event according to the trigger signal, and triggers the trigger event after delaying the first delay time; the digital board delays the second delay time after sending the trigger signal to send the test data corresponding to the vector row to the device under test; in the triggering process of a trigger event, the end time of the second delay time is aligned with the end time of the first delay time. By embedding the trigger tag in the test vector, each trigger tag corresponds to a trigger sequence, and different trigger tags correspond to different trigger sequences. Therefore, multiple different trigger events in the same analog board can be controlled in a test process, thereby improving the efficiency and flexibility of the test. In the analog board, different analog boards can also execute different trigger events for different trigger marks. Therefore, not only can the collaborative testing of digital boards and analog boards be realized, but also different trigger events corresponding to different analog boards can be controlled in a test process, further improving the flexibility of the test. In addition, by setting the second delay time for the digital board and the first delay time for the analog board, the triggering time of the triggering event is aligned with the output time of the test data, ensuring the delay consistency of the digital board when processing various triggering events, thereby improving the accuracy of the test.

[0098] It should be noted that in some other implementations, the trigger target of the digital-analog collaborative test method may be other boards besides the analog board, such as a system board or a power board, etc. In some implementations, the duration of the trigger mark may be configured by configuring the parameter configuration of the synchronization event.

[0099] Optionally, the digital board detects whether a trigger mark exists in a vector row to be executed, including:

[0100] The digital board detects whether the trigger flag of the vector row to be executed is a preset value. If the trigger flag is the preset value, it is determined that the vector row to be executed has a trigger mark.

[0101] Specifically, each vector row is configured with a trigger flag, and the trigger flag can be represented by 1-bit data. For example, the preset value can be "1". If the data of the trigger flag is 1, it means that there is a trigger mark for the vector row. If the data of the trigger flag is 0, it means that there is no trigger mark for the vector row. In this embodiment, by setting a trigger flag on each vector row, it is possible to quickly detect whether there is a trigger mark for each vector row, so that the digital board can quickly perform corresponding actions on the vector rows with trigger marks and the vector rows without trigger marks, thereby further improving the test efficiency.

[0102] Optionally, in the parameter configuration stage, before embedding the trigger mark into the preset vector line to generate the test vector, the following step is further included:

[0103] generating a trigger mark corresponding to the trigger sequence;

[0104] Specifically, the trigger sequence exists in a coded form, and each trigger sequence may be multi-bit, such as 2 bits or more. The trigger tag is obtained by encapsulating the trigger sequence, such as a string. In this embodiment, each trigger tag corresponds to a unique trigger sequence, thereby ensuring the uniqueness of the trigger tag in the automatic test system, so that the trigger tag can be accurately identified by the digital board and the analog board.

[0105] Sending a trigger signal corresponding to the trigger mark to the system board includes:

[0106] Analyze the trigger sequence corresponding to the trigger tag;

[0107] Specifically, after detecting the trigger mark, the digital board 1 first parses the trigger mark to parse out the trigger sequence in the trigger mark, that is, parses out the code corresponding to the trigger mark.

[0108] Encapsulate the trigger sequence into a trigger signal in a preset data format;

[0109] Specifically, the format of the trigger signal is a format that can be sent to the system board. The trigger signal may specifically include a start bit, a trigger sequence, and a check bit. By setting the start bit and the check bit, the system board and the analog board can check whether the received trigger signal is correct. Of course, the trigger signal can also be data in other formats.

[0110] Send the trigger signal to the system board.

[0111] Specifically, the trigger signal may include a clock signal during transmission and be transmitted in a serial coding manner, thereby reducing the trigger signal decoding error and saving wiring resources. Preferably, the coding transmission protocol of the trigger signal can be implemented by customizing, which has the advantage of being simple to implement. Of course, the coding transmission protocol of the trigger signal can also use existing transmission protocols, such as SPI, I2C or UART. It is understandable that after the system board 2 forwards the trigger signal to the corresponding analog board 3, the analog board 3 receives the serially transmitted trigger signal, performs serial-to-parallel conversion, and identifies the corresponding trigger event according to the trigger sequence in the trigger signal, and executes the corresponding action.

[0112] Optionally, continue to refer to Figure 2 The digital board 1 includes a digital controller 11, a digital vector memory 12, a trigger sending module 13 and a test data sending module 14; the digital controller 11 is used to detect whether there is a trigger mark in the vector row to be executed; the trigger sending module 13 is used to parse the trigger sequence corresponding to the trigger mark, encapsulate the trigger sequence into a trigger signal in a preset format, and send the trigger signal to the system board 2 through the trigger sending module 13; the digital vector memory 12 is used to store test vectors; the test data sending module 14 is used to send test data.

[0113] Specifically, in some embodiments, the automatic test system further includes a vector editor 15. The vector editor 15 can be used to write a test vector and store the test vector in the digital vector memory 12. It can be understood that since the test vector contains a trigger mark, the trigger mark in the digital board is also stored in the digital vector memory. In the test phase, the digital controller 11 loads the test vector in the digital vector memory 12 and continuously monitors whether the vector row to be executed has a trigger mark. If there is a trigger mark, the digital controller 12 will send the trigger mark to the trigger sending module 13, and send the test data corresponding to the vector row to the test data sending module 14 after delaying the second delay time. The trigger sending module 13 parses the trigger mark, encodes it into a trigger signal, and sends it to the system board 2. The test data sending module 14 parses the received vector row into test data and sends it to the device under test 4. In this embodiment, a dedicated trigger channel is configured in the digital board, and the trigger signal output by the trigger sending module 13 is sent to the system board 2 through the dedicated trigger channel, which has the effect of high speed and not being easily interfered.

[0114] Optionally, the parameter configuration stage further includes: configuring a trigger matrix of a system board; wherein the trigger matrix is ​​used to represent the routing relationship between the trigger channels of the digital board and the analog board.

[0115] Specifically, in some embodiments, the automatic test system may include multiple digital boards and multiple analog boards. The system board 2 may configure the routing relationship of the trigger channels between different digital boards and different analog boards. The system board 2 may receive the trigger signals of each digital board and send the trigger signals to the corresponding analog board according to the trigger matrix. By setting the trigger matrix, it is ensured that all trigger signals can be correctly forwarded to the analog board according to the predetermined routing relationship, thereby ensuring that the digital board and the analog board can work together correctly.

[0116] Optionally, configuring a first delay time corresponding to the trigger signal includes:

[0117] Determining a transmission time of the trigger signal from the digital board to the analog board;

[0118] Specifically, after the trigger of the digital board is initiated, that is, after the trigger signal is output, the analog board needs to respond after the second delay time Td, that is, trigger the corresponding trigger event. When the first delay time is determined, the transmission time of the trigger signal from the digital board to the analog board is first determined, which can also be understood as the transmission delay. The transmission delay is mainly caused by physical transmission and system routing in the system board; that is, the transmission delay is the time for the trigger signal to be transmitted from the digital board to the analog board, which mainly includes the time for the digital board to transmit to the system board, the time required for routing in the system board, and the time for the system board to send the trigger signal to the analog board.

[0119] Determine the preparation time for the analog board to respond to the trigger event according to the trigger event type corresponding to the trigger signal;

[0120] Specifically, the preparation time refers to the time from when the analog board receives the trigger signal to when the trigger event is ready and can be triggered. It is mainly generated by the analog board parsing the trigger signal and mapping the corresponding trigger event. Because different trigger events have different processing flows, the preparation time for different trigger events is different; the preparation time for a trigger event with high complexity is longer, and the preparation time for a trigger event with low complexity is shorter.

[0121] The first delay time is determined according to the second delay time, the transmission time and the preparation time.

[0122] Specifically, the second delay time is equal to the sum of the first delay time, the transmission time and the preparation time. Therefore, after the second delay time, the transmission time and the preparation time are obtained, the first delay time can be obtained. In this embodiment, the first delay time can be configured in the simulation board during the parameter configuration stage. Different trigger signals correspond to different first delay times. When the simulation board needs to determine the first delay time, it can be directly called from the inside of the simulation board. Of course, in some other implementations, the first delay time can be determined as the trigger event is established.

[0123] In addition, in the analog board, the correspondence between the first delay time and the trigger signal can be the correspondence between the first delay time and the trigger sequence. That is, the analog board stores the correspondence between the trigger sequence and the first delay time. After receiving the trigger signal, the analog board first parses the trigger sequence from the trigger signal, and then obtains the corresponding first delay time through the trigger sequence.

[0124] Additionally, optionally, Figure 2 As shown, the system board 2 can also provide the same source clock CLK for the digital board 1 and the analog board 3, thereby ensuring that the digital board 1 and the analog board 3 work under the same source clock.

[0125] In addition, the system board 2 can optionally provide multiple trigger paths for the analog board and the digital board, and each trigger path can correspond to a number. In some embodiments, the system board can implement the switching of the trigger matrix through FPGA or ASIC, thereby realizing the routing of the trigger signal.

[0126] Optionally, the analog board determines a corresponding trigger event according to the trigger signal, including:

[0127] Determine a trigger sequence according to the trigger signal;

[0128] Determine, according to the trigger signal, a storage address of a trigger event corresponding to the trigger signal;

[0129] Read the trigger event corresponding to the trigger signal from the storage address.

[0130] Optionally, continue to refer to Figure 2 The simulation board 3 includes a trigger receiving module 31 and a trigger event memory; the trigger receiving module 31 is used to receive a trigger signal and determine the storage address of the corresponding trigger event according to the trigger signal; the trigger event memory is used to store the trigger event; configuring the trigger event corresponding to the trigger signal and writing it into the simulation board includes: writing the trigger event corresponding to the trigger sequence corresponding to the trigger mark into the address of the trigger event memory corresponding to the trigger mark, and in addition, the actual meaning of the trigger event stored in the trigger event memory can also be defined.

[0131] Specifically, Figure 3A schematic diagram of trigger tag mapping in an analog board provided by an embodiment of the present invention, with reference to Figure 3 . In the digital vector, there are N vector rows, namely Step1, Step2, ... StepN. And trigger tags are embedded in multiple vector rows, such as embedding tag 1 in vector row Step1 (corresponding to sequence 0); embedding tag 2 in vector row Step4 (corresponding to sequence 1); embedding tag 3 in vector row Step6 (corresponding to sequence 2); embedding the same tag as vector row Step1 in vector row Step7, namely tag 1 (corresponding to sequence 0), that is, trigger tags with the same meaning can be reused; embedding tag n in vector row StepN (corresponding to sequence n-1). When configuring the trigger events corresponding to the trigger tags and writing them into the analog board, different trigger tags are mapped to different storage addresses. Different storage addresses correspond to different trigger tags, such as storage address 0 corresponds to sequence 0, storage address 1 corresponds to sequence 1, storage address 2 corresponds to sequence 2, and storage address n-1 corresponds to sequence n-1. The data stored in the storage address represents the corresponding trigger event, such as the data in storage address 0 represents the trigger event numbered 1; the data in storage address 1 represents the trigger event numbered 2; the data in storage address 2 represents the trigger event numbered 3; the data in storage address n-1 represents the trigger event numbered n. In the analog board, after the trigger signal is decoded, the analog board identifies the corresponding trigger event by querying the corresponding address. When the number of the trigger event is read out, the analog board matches the number of the trigger event with the actual trigger event, thereby realizing the mapping of the trigger mark in the digital board and the trigger event in the analog board. Optionally, the mapping of the trigger event and the trigger mark can be updated and defined in real time by software.

[0132] In addition, optionally, when the trigger signal includes a start bit, a trigger sequence and a check bit, the trigger receiving module in the analog board can continuously monitor the trigger signal from the system board; after detecting the start bit, the trigger receiving module checks the received trigger sequence. If the check passes, the trigger signal is received correctly, and the analog board can perform subsequent actions; if the check fails, it means that the trigger signal is received incorrectly, and the analog board can record the error information for subsequent troubleshooting.

[0133] Optionally, the correspondence between the trigger signal and the trigger event can be stored in an on-chip storage resource in the analog board, such as a random access memory (RAM) or a non-volatile memory such as an EEPROM. Thus, when the trigger event occurs randomly and multiple times, the corresponding trigger event can be accurately triggered.

[0134] For example, Figure 2As shown, in some embodiments, the analog board 3 also includes a waveform memory 32, a waveform generator 35, a waveform collector 34 and a digital signal processing unit 33. After the trigger receiving module 31 parses the corresponding trigger event, it sends the trigger instruction to each structure in the analog board. For example, if the trigger event is the occurrence of an arbitrary waveform and the acquisition of an analog signal, the trigger receiving module 31 controls the waveform generator 35 to read the corresponding waveform from the waveform memory 32 and output it to the device under test 4, and the waveform collector 34 collects the waveform output by the device under test. The digital signal processing unit 33 can modify the waveform stored in the waveform memory 32, etc.

[0135] Optionally, the analog board determines a first delay time and a trigger event according to the trigger signal; and delaying the trigger event by the first delay time before triggering further comprises:

[0136] The analog board determines a third delay time according to the trigger signal;

[0137] The analog board delays the first delay time, then delays the third delay time, and then triggers the corresponding trigger event.

[0138] Specifically, in the analog board, the trigger event can be delayed for a third delay time after the first delay time before being triggered. In some embodiments, there may be delays between different trigger events, that is, the triggering moment of some triggering events may not be aligned with the output moment of the measured data, such as the measured data is output after a delay of a period of time, and the delay can also be adjusted by the third delay time. For example, when the waveform generator and the waveform collector are required to work, the waveform collector may need to lag behind the start of the waveform generator. The start time of the waveform collector can be delayed by the third delay time to meet the needs of various tests, realize more diverse digital-analog collaborative delay combinations, and further enhance the scalability and flexibility of the test.

[0139] Optionally, after the digital board sends the trigger signal, before delaying the second delay time to send the test data, the method further includes:

[0140] Determine the transmission time of the trigger signal from the digital board to the analog board;

[0141] Specifically, Figure 4 As shown, Figure 4A schematic diagram of the corresponding relationship between the second delay time and the first delay time provided for an embodiment of the present invention. After the trigger of the digital board is initiated, that is, after the trigger signal is output, the triggering process of the trigger event begins, and the second delay time Td is required before the analog board can have an analog output, that is, triggering the corresponding trigger event. When the second delay time Td is determined, the transmission time of the trigger signal from the digital board to the analog board is first determined, that is, Tc, which can also be understood as the transmission delay. The transmission delay is mainly caused by physical transmission and system routing in the system board; that is, the transmission delay is the time for the trigger signal to be transmitted from the digital board to the analog board, mainly including the time for the digital board to transmit to the system board, the time required for routing in the system board, and the time for the system board to send the trigger signal to the analog board.

[0142] Determine the preset preparation time required for the analog board to prepare to respond to the trigger event with the highest complexity among the completed trigger events;

[0143] Specifically, the preset trigger event is, for example, the trigger event with the highest complexity among the trigger events, and of course, it can also be other trigger events. The preparation time corresponding to the trigger event with the highest complexity is also the preset preparation time, which is represented by Ta1_max. The higher the complexity, the longer the preparation time required; the lower the complexity, the shorter the preparation time required.

[0144] The second delay time is determined according to the transmission time and the preset preparation time.

[0145] Specifically, in this embodiment, the second delay time Td is set equal to the sum of the transmission time Tc and the preset preparation time Ta1_max, and preferably Ta1_max is the preparation time corresponding to the trigger event with the highest complexity. Therefore, the second delay time Td can be guaranteed to be greater than or equal to the sum of the preparation time and transmission time corresponding to any trigger event, and can ensure that when the measured data is output, any trigger event can be prepared and triggered.

[0146] In addition, it should be noted that the second delay time Td can be configured by the host computer during the parameter configuration stage, that is, the host computer executes the above-mentioned step of determining the second delay time Td and writes it into the digital board; or the above-mentioned step of determining the second delay time Td can be executed on the digital board, which is not specifically limited in this embodiment.

[0147] In addition, in the above embodiment, the first delay time may be determined according to the second delay time, the transmission time and the preparation time. Specifically, after determining Td, Ta1 and Tc, the first delay time Ta2 may be obtained, where Ta2=Td-Ta1-Tc.

[0148] It should be noted that, in other embodiments, the calculation of the second delay time Td of the digital board can also take the preparation time of the digital output into consideration, that is, a new second delay time Td' (actual delay time of the digital board) is obtained, which is equal to the second delay time Td set in the above embodiment minus the preparation time of the digital board, that is, the second delay time Td is equal to the second delay time Td' plus the preparation time of the digital board. In other words, the setting of the second delay time Td is not limited to the setting in the above embodiment, and can be set according to the needs of the user without specific limitation.

[0149] Alternatively, if Figure 4 As shown, in the analog board, the third delay time of each trigger event is Ta3. In some implementations, the default initial value of the third delay time is 0.

[0150] In summary, Figure 5 and Figure 6 The complete implementation process of the present invention is described by taking the example of Figure 5 A schematic diagram of the digital-analog collaborative working principle of an automatic test system provided by an embodiment of the present invention, Figure 6 A corresponding diagram of the working steps of a digital-analog collaborative testing method and an automatic testing system provided in an embodiment of the present invention.

[0151] First, the host computer, such as a PC, configures the system board, analog board, and digital board. That is, configure the trigger matrix of the system board; configure the trigger event and delay information (such as the first delay time and the third delay time) of the analog board; configure the test vector of the digital board, that is, the vector line and the trigger mark; and also configure the second delay time of the digital board.

[0152] During the test phase, the digital controller in the digital board runs the test vector, and each vector row runs in sequence. The delay time of the first delay unit is set to the second delay time, that is, regardless of whether there is a trigger mark, the test data corresponding to the vector row is output after the second delay time. For the vector row with a trigger mark, the trigger mark does not pass through the first delay unit, but is directly output. If the trigger mark is detected, the trigger sending module generates a trigger signal to the system board. After the system board inputs the trigger signal, it is routed and forwarded according to the trigger matrix, thereby outputting the trigger signal to the corresponding analog board. After the trigger receiving module of the analog board inputs the trigger signal, it decodes and maps, and determines the first delay time. Then, after the second delay unit delays the first delay time, the trigger event is executed, and finally the digital output (i.e., the test data) is aligned with the analog output (i.e., the trigger event). Trigger events include, for example, starting to collect data, stopping collecting data, saving data, and sending signals.

[0153] Exemplarily, the specific implementation of the present invention is described by taking the IDD (Supply Current Test, a test method for detecting the maximum input current of a power module) test, that is, the power current test, as an example. Among them, the IDD test is an important method for integrated circuit (IC) testing, and its main purpose is to measure the power consumption of the integrated circuit under different working conditions. The IDD test measures the supply current (Supply Current) under specific input data (Data) and clock (Clock) conditions to identify potential design defects or manufacturing defects. In digital-to-analog conversion chips, dynamic IDD tests usually focus on two types of power supply currents: AISS (Analog IDD) and AIDD (Digital IDD). The following further takes the dynamic IDD test of the digital-to-analog conversion chip (DAC) as an example, and analyzes the dynamic power consumption of the digital-to-analog conversion chip by testing AISS and AIDD under different digital codes.

[0154] The first step is to write a digital test vector.

[0155] Specifically, DAC uses the SPI (Serial Peripheral Interface) communication format, so it is necessary to use a digital vector editor to generate digital test vectors that conform to the DAC communication format. According to the minimum test conditions, configure 9 digital output code values, namely: code1, code2, code3, code4, code5, code5, code7, code8, code9. After each digital code value is output for 10us (Settling time), set trigger event 1 to start the analog board to collect the current of the AISS and AIDD pins, and the trigger code is configured to 1; after 10us, set trigger event 2 to stop the collection of the current of the AISS and AIDD pins, and the trigger code is configured to 2.

[0156] The second step is to configure the digital board.

[0157] Specifically, the test vector consists of 9 DAC output code values ​​and their corresponding 18 trigger events. In this step, the generated digital test vector needs to be loaded into the digital vector memory of the digital board. At the same time, it is also necessary to configure the delayed output time of the digital test vector relative to the trigger signal. That is, configure the value of Td, more specifically, Td = Tc + Ta1_max.

[0158] The third step is to configure the system board.

[0159] For example, in the test system, if the digital board that outputs SPI signals is located in slot 1, and the analog board used to test IDD is located in slot 2. In order to ensure that the analog board can receive the trigger signal, the trigger signal of the board in slot 1 needs to be routed to slot 2 when configuring the system board trigger matrix to achieve the trigger signal connection between the two.

[0160] The fourth step is to configure the analog board.

[0161] Specifically, according to the first step, the actual meaning of trigger code 1 is to start collecting current (Start Measure), and the actual meaning of trigger code 2 is to stop current collection (Stop Measure IDD). Define these two events in the analog board and write them into the trigger event storage space at the same time. The data in address 1 indicates to start collecting current (Start Measure), and the data in address 2 indicates to stop collecting current (Stop Measure). In this way, the analog board can perform the corresponding trigger action according to the received trigger code.

[0162] It should be noted that the order of the first to fourth steps is not limited.

[0163] Step 5: Start the test.

[0164] Step 1: After the digital board is started, the digital code value 0 is configured to the DAC device according to the pre-loaded digital test vector. Step 2: After the digital board loads the digital code value 0 to the DAC device, the DAC chip performs analog-to-digital conversion (setup time 10us). During this period, the digital board is in a waiting state and needs to wait for the output of the DAC chip to stabilize before initiating the trigger current test. Step 3: The digital board sends the trigger code "1". The digital board continuously monitors the trigger flag. When the digital board runs to the vector row where the current acquisition event is located, it outputs the trigger code "1" to the system board. Step 4: The system board routes the trigger signal sent by the digital board in slot 1 to the analog board in slot 2 responsible for collecting AISS and AIDD currents. Step 5: The analog board starts current acquisition. After receiving the trigger signal, the analog board performs trigger event mapping. The trigger signal for starting the current test is decoded into the trigger sequence "1", the data in the trigger event storage address 1 is read, and the data at address 1 is mapped into the current acquisition event, and the AISS and AIDD currents are started to be collected. Step 6: The digital board waits for the analog board to collect data for a period of time. According to the design of the sampling points of 10 and the sampling interval of 100ns, a total sampling time of 1 microsecond is required. Step 7: After the collection time is met, the digital board sends the trigger code "2" to stop the current collection of the analog board (Stop MeasureIDD). Step 8: Repeat steps 1 to 6 until all DAC output code values ​​are traversed: 0, 8192, 16384, 24576, 32678, 40960, 49152, 57344, 65535. Step 9: After the test is completed, the host computer reads the current values ​​on the AISS and AIDD channels collected by the analog board. Each code value has 10 sampling values, a total of 9 code values, and a total of 90 current sampling values. An average value is calculated for every 10 points to obtain the AISS and AIDD current values ​​corresponding to different digital code values.

[0165] Based on the same inventive concept, the present invention also provides a digital-analog collaborative testing method, such as Figure 7 As shown, Figure 7 A flowchart of another digital-analog collaborative testing method provided by an embodiment of the present invention. In this embodiment, the digital-analog collaborative testing method is applied to a digital board. The digital-analog collaborative testing method includes:

[0166] Step S210, receiving a test vector, wherein a trigger mark is embedded in a preset vector row of the test vector;

[0167] Specifically, the digital board 1 can load a test vector and send the corresponding test sequence in the test vector to the device under test (DUT) 4. The specific format of the test vector is well known to those skilled in the art and will not be repeated here. The test vector in this embodiment can be a digital test vector. Before testing the device under test, it is necessary to configure the parameters of the automatic test system. For example, write a test vector, etc. The test vector includes multiple vector rows, and the digital board loads each vector row in sequence, and performs corresponding actions according to the meaning of the vector row, such as outputting test data to the device under test 4. In this embodiment, when writing a test vector, a trigger mark can be embedded in the preset vector row, and the trigger mark is used to indicate whether the vector row needs to trigger a trigger event, and the sequence corresponding to the triggered trigger event. Among them, the trigger event can be an analog event occurring in an analog board. In the digital board 1, the total number of sequences corresponding to the trigger mark can be greater than or equal to 1, that is, different sequences may correspond to different trigger events, and of course, they can also correspond to the same trigger event (specifically related to the definition of the trigger mark in the analog board). The number of trigger markers configured in the test vector is not limited, for example, one trigger marker may be embedded, or multiple trigger markers may be embedded.

[0168] Step S220, detecting whether there is a trigger mark in the vector row to be executed, and if there is a trigger mark in the vector row to be executed, sending a trigger signal corresponding to the trigger mark to the system board;

[0169] Specifically, when executing the test vector, the digital board continuously detects whether the vector line to be executed has a trigger mark. If the vector line to be executed has a trigger mark, it indicates that the analog board 3 needs to act, so the trigger signal corresponding to the trigger mark is first sent to the system board 2.

[0170] Step S230, delaying the second delay time to send the test data corresponding to the vector row to the device under test after sending the trigger signal; wherein the second delay time is equal to the sum of the transmission time from the digital board to the analog board and the preset preparation time required for the analog board to prepare to respond to the trigger event with the highest complexity among the trigger events.

[0171] Specifically, during the triggering process of a trigger event, the end time of the second delay time is aligned with the end time of the first delay time, wherein the first delay time is the time configured in the analog board and delayed after the preparation response of the trigger event is completed. The trigger mark needs to be sent from the digital board 1 to the system board 2, and then forwarded by the system board 2 to the analog board 3, and then triggered and executed by the analog board 3. The test data corresponding to the vector row is sent directly to the device under test by the digital board 1. If the trigger signal and the test data are output by the digital board at the same time, the trigger signal needs to pass through a longer transmission path, and the analog board also needs a certain amount of time to process the trigger signal. When the trigger event corresponding to the trigger signal is triggered, a certain delay will be generated relative to the moment when the test data is sent to the device under test, making the test result inaccurate. In this embodiment, each trigger mark corresponds to a second delay time. In the same application scenario, the second delay times corresponding to different trigger marks are consistent; it can be understood that the second delay times corresponding to different application scenarios may be different. By setting the second delay time for the digital board and the first delay time for the analog board, the triggering time of the triggering event is aligned with the output time of the tested data, thereby improving the accuracy of the test. In addition, when multiple triggering events need to be triggered at the same time, the response time of all the triggering events is aligned with the output time of the test data, that is, the response time of each triggering event is the same, thereby ensuring the delay consistency of the digital board when processing various triggering events, further improving the accuracy of the test.

[0172] It should be noted that, in this embodiment, the starting time of the triggering process of a triggering event may be the time when the trigger signal is sent from the digital board to the system board, the starting time of the second delay time is the same as the starting time of the triggering process, and the starting time of the first delay time is later than the starting time of the triggering process.

[0173] The technical solution of this embodiment can control multiple different trigger events in the same analog board in a test process, thereby improving the efficiency and flexibility of the test. In the analog board, different analog boards can also execute different trigger events for different trigger marks, so not only can the collaborative test of the digital board and the analog board be realized, but also different trigger events corresponding to different analog boards can be controlled in a test process, further improving the flexibility of the test. In addition, by setting the second delay time for the digital board and setting the first delay time for the analog board, the triggering time of the triggering event is aligned with the output time of the test data, ensuring the delay consistency of the digital board when processing various triggering events, thereby improving the accuracy of the test.

[0174] Optionally, detecting whether a vector row to be executed has a trigger mark includes:

[0175] It is detected whether the trigger flag of the vector row to be executed is a preset value. If the trigger flag is the preset value, it is determined that the vector row to be executed has a trigger mark.

[0176] Specifically, the digital-analog collaborative testing method applied to the digital board described in this embodiment is the same as the steps and principles executed by the digital board in the digital-analog collaborative testing method applied to the automatic testing system. The relevant process can refer to the description of the digital-analog collaborative testing method applied to the automatic testing system in the present invention, and will not be repeated here.

[0177] Based on the same inventive concept, the present invention also provides a digital-analog collaborative testing method, which is applied to analog boards. Figure 8 As shown, Figure 8 A flowchart of another digital-analog collaborative testing method provided by an embodiment of the present invention. The digital-analog collaborative testing method includes:

[0178] Step S310, receiving a trigger signal;

[0179] Specifically, the trigger signal is sent from the digital card to the system card, and is routed from the system card to the analog card.

[0180] Step S320, determining a first delay time and a trigger event according to the trigger signal;

[0181] Specifically, the analog board stores the first delay time and trigger events corresponding to the trigger signal, each trigger event corresponds to a first delay time, different trigger signals correspond to different trigger events, and correspondingly different trigger events correspond to different first delay times.

[0182] Step S330, delaying the triggering event by a first delay time before triggering.

[0183] Specifically, after receiving the trigger signal, the analog board prepares to respond to the trigger event, and after the preparation for the response is completed, the corresponding trigger event is triggered after a delay of the first delay time. At this time, the digital board also starts to output the measured data, so that the time when the digital board outputs the measured data is aligned with the time when the analog board triggers the corresponding trigger event.

[0184] The solution of this embodiment can control multiple different trigger events in the same analog board in a test process, thereby improving the efficiency and flexibility of the test. In the analog board, different analog boards can also execute different trigger events for different trigger marks, so not only can the collaborative test of the digital board and the analog board be realized, but also different trigger events corresponding to different analog boards can be controlled in a test process, further improving the flexibility of the test. In addition, by setting the second delay time for the digital board and setting the first delay time for the analog board, the triggering time of the triggering event is aligned with the output time of the test data, ensuring the delay consistency of the digital board when processing various triggering events, thereby improving the accuracy of the test.

[0185] Optionally, determining the first delay time and the trigger event according to the trigger signal includes:

[0186] Determining the first delay time includes:

[0187] Determine a trigger sequence according to the trigger signal;

[0188] Determine the transmission time of the trigger signal from the digital board to the analog board;

[0189] Determine the preparation time for the analog board to respond to the trigger event according to the trigger event type corresponding to the trigger sequence;

[0190] Determine the first delay time according to the second delay time, the transmission time and the preparation time;

[0191] Determining the trigger event based on the trigger signal includes:

[0192] Determine a trigger sequence according to the trigger signal;

[0193] Determine the storage address of the trigger event corresponding to the trigger signal according to the trigger sequence;

[0194] Read the trigger event corresponding to the trigger sequence from the storage address; and / or,

[0195] Before the trigger event is delayed for the first delay time and then triggered, the following steps are also included:

[0196] determining a third delay time according to the trigger signal;

[0197] The triggering event is prepared to be triggered after the first delay time, and further includes:

[0198] The analog board delays the first delay time, then the third delay time, and then triggers the corresponding trigger event.

[0199] Optionally, before receiving the trigger signal, the method further includes:

[0200] A trigger event corresponding to the trigger signal and a corresponding first delay time are written.

[0201] Specifically, the digital-analog collaborative testing method applied to the analog board described in this embodiment is the same as the steps and principles executed by the analog board in the digital-analog collaborative testing method applied in the automatic testing system. The relevant process can refer to the description of the digital-analog collaborative testing method applied in the automatic testing system of the present invention, and will not be repeated here.

[0202] The digital-analog collaboration method of the present invention brings at least the following beneficial effects:

[0203] 1) The present invention is a trigger tag method based on digital vectors. By embedding trigger tags in digital vectors, accurate digital-analog collaborative control is achieved. Each trigger tag carries specific information that defines the trigger events that other analog boards in the system should execute when the digital board executes the test vector with the trigger tag. By binding the trigger event to the trigger tag, the flexibility of digital-analog collaborative testing is improved, and the trigger event can be flexibly adjusted according to the test requirements.

[0204] 2) The present invention encodes the trigger signal and associates a specific trigger code with a clear analog action, thereby realizing precise coordinated control between resource modules of different boards in mixed signal testing. The use of the coded trigger mechanism breaks through the limitation of a single event of the traditional pulse trigger mechanism, is applicable to more complex digital-analog collaborative testing requirements, and improves the resource management capability and event processing efficiency of the test system in the face of complex test processes.

[0205] 3) The present invention adds a delay unit in the digital board, so that the digital vector lags behind the trigger coding output, eliminating the influence of trigger coding and transmission time on the trigger accuracy. The alignment method provided by the present invention improves the collaborative testing capability of the digital board and the analog board, and improves the accuracy of the test. In addition, it also supports the delay time adjustment of the analog event relative to the digital event, provides the ability to dynamically adjust the trigger moment, and further enhances the flexibility and adaptability of the digital-analog test method.

[0206] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0207] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A digital-analog collaborative testing method, applied to an automatic testing system, characterized in that: The automatic test system comprises a digital board, a system board and at least one analog board; the digital board and the analog board are both communicatively connected to the system board; The digital-analog collaborative testing method comprises: In the parameter configuration stage, a trigger mark is embedded in a preset vector row to generate a test vector, and the test vector is written into the digital board; a trigger event and a first delay time corresponding to a trigger signal are configured and written into the analog board; In the test phase, the digital board detects whether the vector line to be executed has the trigger mark; if the vector line to be executed has the trigger mark, a trigger signal corresponding to the trigger mark is sent to the system board; The system board sends the trigger signal to the corresponding analog board; the analog board determines a first delay time and a trigger event according to the trigger signal, and triggers the trigger event after delaying the trigger event by the first delay time; The digital board sends the test data corresponding to the vector row to the device under test by delaying a second delay time after sending the trigger signal; during the triggering process of a trigger event, the end time of the second delay time is aligned with the end time of the first delay time.

2. The digital-analog collaborative testing method according to claim 1, characterized in that: The digital board detects whether the vector line to be executed has the trigger mark, including: The digital board detects whether the trigger flag of the vector row to be executed is a preset value. If the trigger flag is the preset value, it is determined that the vector row to be executed has the trigger mark.

3. The digital-analog collaborative testing method according to claim 1, characterized in that: The first delay time corresponding to the configuration trigger signal includes: Determining a transmission time of the trigger signal from the digital board to the analog board; Determine the preparation time for the analog board to respond to the trigger event according to the trigger event type corresponding to the trigger signal; Determine the first delay time according to the second delay time, the transmission time and the preparation time; and / or, The analog board determines the trigger event according to the trigger signal, including: determining a trigger sequence according to the trigger signal; Determine the storage address of the trigger event corresponding to the trigger signal according to the trigger sequence; The trigger event corresponding to the trigger sequence is read from the storage address.

4. The digital-analog collaborative testing method according to claim 1, characterized in that: The analog board determines a first delay time and a trigger event according to the trigger signal, and triggers the trigger event after delaying the trigger event by the first delay time, further comprising: The analog board determines a third delay time according to the trigger signal; The analog board delays the first delay time, then delays the third delay time, and then triggers the corresponding trigger event.

5. The digital-analog collaborative testing method according to claim 1, characterized in that: Before the digital board sends the test data corresponding to the vector row to the device under test after delaying the second delay time after sending the trigger signal, the digital board also includes: Determining a transmission time of the trigger signal from the digital board to the analog board; Determine the preset preparation time required for the analog board to prepare to respond to and complete the trigger event with the highest complexity among the trigger events; The second delay time is determined according to the transmission time and the preset preparation time.

6. The digital-analog collaborative testing method according to claim 1, characterized in that: Before embedding the trigger marker into the preset vector line to generate the test vector, it also includes: generating a trigger mark corresponding to the trigger sequence; The sending of the trigger signal corresponding to the trigger mark to the system board comprises: Parsing the trigger sequence corresponding to the trigger mark; Encapsulating the trigger sequence into the trigger signal in a preset data format; Sending the trigger signal to the system board; and / or, The parameter configuration stage also includes: Configure the second delay time corresponding to the trigger mark and write it into the digital board; and / or, The parameter configuration stage also includes: A trigger matrix of the system board is configured; wherein the trigger matrix is ​​used to represent the routing relationship between the trigger channels of the digital board and the analog board.

7. A digital-analog collaborative testing method, applied to a digital board, characterized in that: include: receiving a test vector, wherein a preset vector row of the test vector is embedded with a trigger mark; Detecting whether the vector line to be executed has the trigger mark, and if the vector line to be executed has the trigger mark, sending a trigger signal corresponding to the trigger mark to the system board; Sending the test data corresponding to the vector row to the device under test after delaying a second delay time after sending the trigger signal; The second delay time is equal to the sum of the transmission time from the digital board to the analog board and the preset preparation time required for the analog board to prepare to respond to the trigger event with the highest complexity among the trigger events.

8. The digital-analog collaborative testing method according to claim 7, characterized in that: The detecting whether the vector row to be executed has the trigger mark comprises: It is detected whether the trigger flag of the vector row to be executed is a preset value. If the trigger flag is the preset value, it is determined that the vector row to be executed has the trigger flag.

9. A digital-analog collaborative testing method, applied to analog boards, characterized in that: include: receiving a trigger signal; Determine a first delay time and a trigger event according to the trigger signal; The triggering event is prepared to be triggered after delaying the first delay time.

10. The digital-analog collaborative testing method according to claim 9, characterized in that: Determining the first delay time and the trigger event according to the trigger signal includes: Determining the first delay time includes: Determine a trigger sequence according to the trigger signal; Determining the transmission time of the trigger signal from the digital board to the analog board; Determine the preparation time for the analog board to respond to the trigger event according to the trigger event type corresponding to the trigger sequence; Determine the first delay time according to the second delay time, the transmission time and the preparation time; Determining a trigger event according to the trigger signal includes: Determine a trigger sequence according to the trigger signal; Determine the storage address of the trigger event corresponding to the trigger signal according to the trigger sequence; The trigger event corresponding to the trigger sequence is read from the storage address.

11. The digital-analog collaborative testing method according to claim 9, characterized in that: Before delaying the trigger event by the first delay time and then triggering, the method further includes: determining a third delay time according to the trigger signal; The step of delaying the triggering event preparation by the first delay time to trigger the event further includes: The analog board delays the first delay time, then delays the third delay time, and then triggers the corresponding trigger event.

Images