Display device

Abstract

The display device may include: a pixel coupled to a first scan line, a second scan line, an emission control line, and a data line; a first scan driver providing a first scan signal to the first scan line in a first period and a second period; a second scan driver providing a second scan signal to the second scan line in the first period and not providing the second scan signal to the second scan line in the second period; a transmission driver providing a transmission control signal to the transmission control line in a first period and a second period; a data driver configured to provide the data signal to the data line in a first period and not to provide the data signal to the data line in a second period; and a power supply section that supplies a first initialization power supply to the pixels through the first power line and supplies a second initialization power supply to the pixels through the second power line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0178321, filed on December 30, 2019, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0003] Exemplary embodiments of the present invention generally relate to electronic devices, and more particularly, to a display device capable of improving display quality when the display device operates using a low frequency. Background Art

[0004] The display device displays an image on a display panel using a control signal applied from an external device.

[0005] The display device may include a plurality of pixels. Each pixel may include a plurality of transistors, a light emitting element electrically connected to the transistor, and a capacitor. The transistor may be turned on in response to a corresponding signal provided by the line, thereby generating a drive current. The light emitting element may emit light in response to the drive current.

[0006] Recently, there has been a demand for display devices corresponding to various driving frequencies (or image refresh rates) in order to achieve the purposes of high-resolution driving, low-power driving, three-dimensional image driving, and the like.

[0007] In particular, a method of driving a display device using a low frequency has been used to improve driving efficiency of the display device and to minimize power consumption. Therefore, a method of improving display quality of a display device operating using a low frequency is needed.

[0008] The above information disclosed in this Background section is only for understanding the background of the present inventive concept and therefore it may contain information that does not constitute prior art. Summary of the invention

[0009] The applicant has found that when a display device operates using a low frequency, a flicker phenomenon may occur due to a hysteresis characteristic in the low frequency driving operation, which degrades image quality.

[0010] The display device constructed according to the principles and exemplary embodiments of the present invention can periodically control the driving transistor included in each pixel to have a conducting bias state or a cut-off bias state by providing different initialization power supplies to the first pixel row and the second pixel row, thereby improving the hysteresis variation and deviation in the driving transistor characteristics. Therefore, the flicker phenomenon caused by the hysteresis characteristics in the low-frequency driving operation can be alleviated, and the step efficiency in the high-frequency driving operation can be improved. As a result, the image quality can be improved.

[0011] Additional features of the inventive concept will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the inventive concept.

[0012] According to aspects of the present invention, a display device includes: pixels connected to a first scan line, a second scan line, an emission control line and a data line; a first scan driver providing a first scan signal to each of the first scan lines in a first time period and a second time period; a second scan driver providing a second scan signal to each of the second scan lines in the first time period, and not providing the second scan signal to the second scan lines in the second time period; an emission driver providing an emission control signal to each of the emission control lines in the first time period and the second time period; a data driver configured to provide a data signal to each of the data lines in the first time period, and not providing the data signal to the data lines in the second time period; and a power supply unit providing a first initialization power supply to each of the pixels through the first power line, and providing a second initialization power supply to each of the pixels through the second power line.

[0013] The power supply section may be configured to output the first initialization power alternately at a high level and a low level in the first period.

[0014] The power supply section may be configured to output the second initialization power alternately at a high level and a low level in the first period.

[0015] The power supply part may be configured to output a high level of the second initialization power source overlapping with a low level of the first initialization power source and output a low level of the second initialization power source overlapping with the high level of the first initialization power source.

[0016] The first period may correspond to two horizontal periods.

[0017] The pixels arranged on the i-th (i is a natural number) pixel row may include: a light-emitting element; a first transistor, including a first electrode connected to a first node electrically connected to a first power source to control a driving current based on a voltage at a second node; a second transistor, connected between one of the data lines and the first node to be turned on by a first scan signal provided to the i-th first scan line; a third transistor, connected between the second node and the third node to be turned on by a second scan signal provided to the i-th second scan line, the third node being connected to the second electrode of the first transistor; a fourth transistor, connected between the first node and the first power line or between the third node and the first power line to be turned on by the first scan signal; a seventh transistor, connected between the second node and the first power line to be turned on by the second scan signal; and an eighth transistor, connected between the first electrode of the light-emitting element and the second power line to be turned on by the first scan signal.

[0018] The pixel arranged on the i-th pixel row may also include: a fifth transistor connected between the first power supply and the first node to be turned off by the emission control signal provided to the i-th emission control line; and a sixth transistor connected between the third node and the first electrode of the light emitting element to be turned off by the emission control signal.

[0019] The fourth transistor and the seventh transistor may be configured to be turned on at different time points.

[0020] When the first initialization power is supplied at a high level, the fourth transistor may be turned on. When the first initialization power is supplied at a low level, the seventh transistor may be turned on.

[0021] A gate of the fourth transistor may be coupled to the (i-2)th first scan line.

[0022] A gate of the seventh transistor may be coupled to the (i-3)th second scan line.

[0023] When the second initialization power is supplied at a low level, the eighth transistor may be turned on.

[0024] A gate of the eighth transistor may be coupled to the i-th first scan line.

[0025] A gate of the eighth transistor may be coupled to the (i-2)th first scan line.

[0026] The second power line may be coupled to the fourth transistor and the seventh transistor included in the pixel disposed on the i+1th pixel row among the pixels. The first power line may be coupled to the eighth transistor of the pixel disposed on the i+1th pixel row.

[0027] When the second initialization power is provided at a high level, the fourth transistor included in the pixel arranged on the i+1th pixel row may be turned on. When the second initialization power is provided at a low level, the seventh transistor included in the pixel arranged on the i+1th pixel row may be configured to be turned on. When the second initialization power is provided at a low level, the eighth transistor included in the pixel arranged on the i+1th pixel row may be turned on.

[0028] The first power line or the second power line may be disposed between the ith pixel row and the (i+1)th pixel row.

[0029] The first power line may extend in the pixel row direction between the i-th pixel row and the i+1-th pixel row. The second power line may extend in the pixel row direction between the i+1-th pixel row and the i+2-th pixel row.

[0030] The first power line may be coupled to the fourth transistor and the seventh transistor of the pixel disposed on the i-th pixel row and the eighth transistor of the pixel disposed on the (i+1)-th pixel row.

[0031] The first power lines and the second power lines may be alternately arranged in a pixel column direction.

[0032] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the inventive concept.

[0034] Figure 1 is a block diagram of an embodiment of a display device constructed according to the principles of the present invention.

[0035] Figure 2 is included in Figure 1 A circuit diagram of an embodiment of a representative pixel in a display device of .

[0036] Figure 3 It is shown Figure 2 A timing diagram of an embodiment of the operation of a pixel.

[0037] Figure 4 It is shown Figure 2 A timing diagram of another embodiment of the operation of a pixel.

[0038] Figure 5 is included in Figure 1 A circuit diagram of another embodiment of a representative pixel in a display device of FIG.

[0039] Figure 6 The first power line and the second power line are included in Figure 1 FIG. 1 is a diagram of an embodiment of the connection of pixels in a display device.

[0040] Figures 7 to 10 is included in Figure 1 Circuit diagrams of other embodiments of representative pixels in a display device. DETAILED DESCRIPTION

[0041] In the following description, for the purpose of illustration, many specific details are set forth to provide a thorough understanding of various embodiments or embodiments of the present invention. As used herein, "embodiment" and "embodiment" are interchangeable words, which are non-limiting examples of devices or methods using one or more inventive concepts disclosed herein. However, it is apparent that various embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagram form to avoid unnecessary obscurity of various embodiments. In addition, various embodiments may be different, but do not have to be exclusive. For example, without departing from the inventive concept, the specific shape, configuration and characteristics of the embodiment may be used or implemented in another embodiment.

[0042] Unless otherwise specified, the described embodiments should be understood as providing exemplary features of different details of some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of various embodiments may be combined, separated, interchanged and / or rearranged in other ways without departing from the inventive concept.

[0043] The use of cross hatching and / or shading in the drawings is generally used to make the boundaries between adjacent elements clear. Therefore, unless otherwise stated, the presence or absence of cross hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, ratio, commonality between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. When the embodiment can be implemented differently, a specific process sequence can be performed differently from the described sequence. For example, two processes described in succession can be performed substantially simultaneously, or in an order opposite to the described order. In addition, the same reference numerals represent the same elements.

[0044] When an element such as a layer is referred to as being on another element or layer, being connected to or being coupled to another element or layer, it can be directly on this other element or layer, being directly connected to or being directly coupled to this other element or layer, or there can be an intervening element or layer. However, when an element or layer is referred to as being directly on another element or layer, being directly connected to or being directly coupled to another element or layer, there is no intervening element or layer. For this reason, the term "connection" can refer to physical connection, electrical connection and / or fluid connection with or without an intervening element. In addition, the D1 axis, the D2 axis and the D3 axis are not limited to the three axes of a rectangular coordinate system, such as an x-axis, a y-axis and a z-axis, and can be explained in a broader sense. For example, the D1 axis, the D2 axis and the D3 axis can be perpendicular to each other, or different directions that are not perpendicular to each other can be represented. For the purpose of this disclosure, "at least one of X, Y and Z" and "at least one selected from X, Y and Z" can be interpreted as any combination of only X, only Y, only Z or two or more of X, Y and Z, such as, for example, XYZ, XYY, YZ and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0045] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0046] Spatially relative terms, such as "below," "beneath," "under," "down," "above," "up," "above," "higher," "side" (e.g., as in "sidewall"), and the like, may be used herein for descriptive purposes, and thereby describe the relationship of one element to another element(s) shown in the accompanying drawings. Spatially relative terms are intended to also include different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is flipped, elements described as being below or below other elements or features will be oriented to be above the other elements or features. Thus, the exemplary term "below" can include both above and below orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and thus, the spatially relative descriptors used herein should be interpreted accordingly.

[0047] The terms used herein are used for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to also include the plural forms. In addition, the terms "comprises", "comprising", "include", and / or "including" when used in this specification specify the stated features, wholes, steps, operations, elements, components, and / or the presence of their groups, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their groups. It should also be noted that, as used herein, the terms "substantially", "about", and other similar terms are used as approximate terms, not as terms of degree, and are thus used to allow for the inherent deviations of measured values, calculated values, and / or provided values ​​that will be recognized by a person of ordinary skill in the art.

[0048] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. Terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0049] Figure 1 is a block diagram of an embodiment of a display device 1000 constructed in accordance with the principles of the present invention.

[0050] Reference Figure 1 , the display device 1000 may include a pixel part 100 , scan drivers 200 and 300 , an emission driver 500 , a data driver 600 , and a timing controller 700 . The display device 1000 may include a power supply part 800 .

[0051] The scan drivers 200 and 300 may be implemented as a first scan driver 200 and a second scan driver 300. However, the embodiments of the present invention are not limited thereto, as the division of the scan drivers 200 and 300 is only for illustration. For example, at least part of the scan drivers 200 and 300 may be integrated into a single drive circuit, module, etc., according to design.

[0052] The display device 1000 may display images at various driving frequencies (or various image refresh rates) according to driving conditions. The driving frequency may be the frequency at which a data signal is substantially applied to a driving transistor of a pixel PX. For example, the driving frequency may also be referred to as a "scan rate" or a "refresh rate" and indicates the number of images displayed per second.

[0053] The image refresh rate may be an output frequency of the data driver 600 and / or the second scan driver 300. For example, the image refresh rate for driving a video may be a frequency of about 60 Hz or higher (eg, 120 Hz).

[0054] According to the driving conditions, the display device 1000 can adjust the output frequency of the second scan driver 300 and the output frequency of the data driver 600 corresponding to the output frequency of the second scan driver 300. For example, the display device 1000 can display images in response to various image refresh rates ranging from 1 Hz to 120 Hz. However, the embodiments of the present invention are not limited thereto. For example, the display device 1000 can also display images at an image refresh rate greater than 120 Hz (e.g., 240 Hz or 480 Hz).

[0055] The pixel portion 100 may include pixels PX disposed to be connected to the data line D, the scan lines S1 and S2, and the emission control line E. The pixels PX may be supplied with voltages of a first power source VDD and a second power source VSS from an external device. In an embodiment, each of the pixels PX may also be supplied with a voltage of a first initialization power source Vint1 or a second initialization power source Vint2. In an embodiment, referring to Figure 4 , the pixel PX may be provided with a signal for displaying an image during the first period P1, and may maintain the image displayed in the first period P1 during the second period P2. For example, the pixel PX may be driven in a first mode during the first period P1, and display an image at a first frequency (e.g., high frequency) in the first period P1. In addition, the pixel PX may be driven in a second mode during the second period P2, and display an image in a low-frequency driving manner in the second period P2.

[0056] The timing controller 700 may generate a first scan drive control signal SCS1, a second scan drive control signal SCS2, an emission drive control signal ECS, and a data drive control signal DCS in response to a synchronization signal provided from an external device. The first scan drive control signal SCS1 may be provided to the first scan driver 200. The second scan drive control signal SCS2 may be provided to the second scan driver 300. The emission drive control signal ECS may be provided to the emission driver 500. The data drive control signal DCS may be provided to the data driver 600. The timing controller 700 may rearrange the image data RGB provided from the external device and provide the image data RGB to the data driver 600.

[0057] The data drive control signal DCS may include a source start pulse and a clock signal. The source start pulse may control the time point at which data sampling starts. The clock signal may be used to control the sampling operation.

[0058] The timing controller 700 may generate a power control signal PCS for controlling the operation of the power supply 800. The power control signal PCS may control the supply timing and / or voltage level of at least one of the first power VDD, the second power VSS, the first initialization power Vint1, and the second initialization power Vint2.

[0059] The data driver 600 may convert the rearranged image data RGB into an analog data signal. The data driver 600 may provide a data signal to the data line D in response to a data driving control signal DCS.

[0060] The data driver 600 may provide a data signal to the data line D during a frame period in response to an image refresh rate. For example, the data driver 600 may provide a data signal to the data line D at a frequency corresponding to the image refresh rate. Here, the data signal to be provided to the data line D may be synchronized with the scan signal to be provided to the first scan line S1.

[0061] The second scan driver 300 may provide a scan signal to the second scan line S2 based on the second scan drive control signal SCS2. For example, the second scan driver 300 may sequentially provide a scan signal to the second scan line S2 (such as Figure 2 , Figure 3 and Figure 4 Here, each second scanning signal may be set to a gate-on voltage so that a transistor included in a pixel PX can be turned on. For example, the gate-on voltage of the second scanning signal may be a logic high level to turn on a transistor such as Figure 2 The third transistor M3 and the seventh transistor M7 shown in FIG. 1 are N-type transistors.

[0062] like Figure 3 and Figure 4 As shown in , the second scan driver 300 may provide the second scan signal to the second scan line S2 during the first period P1. The first period P1 may be repeated at the same frequency (e.g., the first frequency) as the frequency of the image refresh rate. Therefore, the second scan driver 300 may provide the second scan signal at the same frequency as the image refresh rate. For example, when the first frequency is 120 Hz, the first period P1 may be repeated at 120 Hz.

[0063] The first period P1 may include an emission period EP and a non-emission period NEP, and may be a period in which a data signal corresponding to an image is written into the pixel PX.

[0064] The first scan driver 200 may provide a scan signal to the first scan line S1 based on the first scan drive control signal SCS1. For example, the first scan driver 200 may continuously provide a scan signal to the first scan line S1 (such as Figure 2 , Figure 3 and Figure 4 Here, each of the first scanning signals may be set to a gate-on voltage so that a transistor included in a pixel PX can be turned on. For example, the gate-on voltage of the first scanning signal may be used to turn on a transistor such as Figure 2 The logic low level of the P-type transistors of the second transistor M2, the fourth transistor M4 and the eighth transistor M8 shown in FIG.

[0065] That is, the gate-on voltage of the scan signal to be provided to the P-type transistor among the first scan signal and the second scan signal can have a logic low level, and the gate-on voltage of the scan signal to be provided to the N-type transistor among the first scan signal and the second scan signal can have a logic high level.

[0066] like Figure 3 and Figure 4 As shown in FIG. 1 , the first scan driver 200 may provide the first scan signal to the first scan line S1 during the first period P1 and the second period P2. Therefore, regardless of the image refresh rate, the first scan driver 200 may provide the first scan signal to the first scan line S1.

[0067] The second period P2 may be enabled during the low-frequency driving operation of the display device 1000. For example, in the case where the image refresh rate is less than the first frequency, the second period P2 may be enabled at least once immediately after the first period P1.

[0068] For example, refer to Figure 4 , the second period P2 may include an emission period EP' and a non-emission period NEP', and the non-emission period NEP' may include a bias period BP', in which a bias is applied to the pixel PX in response to the first scan signal. For example, in response to the first scan signal, a predetermined voltage (e.g., a bias voltage) may be applied to the driving transistor (i.e., Figure 2 The source and / or drain of M1, M1') of the first period P1 and the driving transistor may be turned on and biased. The second period P2 may be a driving period applied to the low-frequency driving operation. Since the second period P2 is a period in which the image displayed during the first period P1 is retained, the second period P2 may be defined as a holding subframe. In other words, the pixel PX may be driven in the second mode during the second period P2 in which the image is displayed in a low-frequency driving manner.

[0069] According to the image refresh rate, the number of times the second period P2 is continuously repeated (or the total length of the continuous second period P2) may vary.

[0070] The emission driver 500 may receive the emission driving control signal ECS from the timing controller 700 and provide the emission control signal to the emission control line E based on the emission driving control signal ECS. For example, the emission driver 500 may provide the emission control signal to the emission control line E sequentially.

[0071] The pixels PX may not be emitted on a horizontal line basis when the emission control signals are sequentially supplied to the emission control lines E. To this end, each emission control signal may be set to a gate-off voltage (e.g., a logic high level) so that some transistors (e.g., P-type transistors) included in the corresponding pixel PX may be turned off.

[0072] The emission control signal is used to control the emission time of the pixel PX. In an embodiment, the emission control signal may be set to have a width greater than a width of the first scan signal or the second scan signal.

[0073] The emission driver 500 may provide the emission control signal during the first period P1 and the second period P2 to the emission control line E. In other words, the emission driver 500 may output the emission control signal at the second frequency regardless of the image refresh rate (eg, the first frequency).

[0074] For example, when the second frequency (i.e., the output frequency of the emission control signal) is 120 Hz and the first frequency (i.e., the image refresh rate) is 60 Hz, one first period P1 and one second period P2 may be repeated alternately. When the second frequency is 120 Hz and the first frequency is 30 Hz, one first period P1 and two consecutive second periods P2 may be repeated alternately.

[0075] In an embodiment, if the first frequency is equal to the second frequency, only the first period P1 may be repeated.

[0076] The power supply unit 800 may provide at least one of the first power VDD, the second power VSS, the first initialization power Vint1, and the second initialization power Vint2 to the pixel unit 100 based on the power control signal PCS. The power supply unit 800 may provide the first initialization power Vint1 to some pixels PX through the first power line IL1, and may provide the second initialization power Vint2 to other pixels PX through the second power line IL2.

[0077] like Figure 3 and Figure 4As shown in , the first initialization power source Vint1 and the second initialization power source Vint2 may alternately output a high level voltage and a low level voltage.

[0078] The power supply unit 800 may generate a high potential voltage or a low potential voltage for determining whether the scan signal or the emission control signal has a logic low level or a logic high level. The high level of each of the first initialization power supply Vint1 and the second initialization power supply Vint2 may be set to a value equal to or different from the high potential voltage. Similarly, the low level of each of the first initialization power supply Vint1 and the second initialization power supply Vint2 may be set to a value equal to or different from the low potential voltage.

[0079] Regarding the circuit structure of the pixel PX, the pixel PX disposed on the current horizontal line (or current pixel row) may be additionally connected to a scan line disposed on the previous horizontal line (or previous pixel row) and / or a scan line disposed on the next horizontal line (or next pixel row). To this end, the pixel portion 100 may include additional virtual scan lines and / or virtual emission control lines not shown.

[0080] Figure 2 is included in Figure 1 A circuit diagram of an embodiment of a representative pixel in a display device of .

[0081] Reference Figure 2 , the i-th pixel PXi arranged on the i-th pixel row (i-th horizontal line) and the i+1-th pixel PXi+1 arranged on the i+1-th pixel row (i+1-th horizontal line) may have substantially the same pixel structure.

[0082] The i-th pixel PXi and the i+1-th pixel PXi+1 may be coupled to the j-th data line Dj. Hereinafter, a pixel structure will be described based on the configuration of the i-th pixel PXi.

[0083] The pixel 10 (eg, the i-th pixel PXi) may include a light emitting element LD, first to eighth transistors M1 to M8 , and a storage capacitor Cst.

[0084] The light emitting element LD may include a first electrode (anode electrode or cathode electrode) coupled to the fourth node N4 and a second electrode (the other of the cathode electrode and the anode electrode) coupled to the second power supply VSS. The light emitting element LD may emit light having a predetermined brightness corresponding to the current supplied from the first transistor M1.

[0085] The light emitting element LD may be an organic light emitting diode including an organic light emitting layer. In an embodiment, the light emitting element LD may be an inorganic light emitting element formed of an inorganic material. The light emitting element LD may have a structure in which a plurality of inorganic light emitting elements are connected in parallel and / or in series between the second power source VSS and the fourth node N4.

[0086] The first transistor (or driving transistor) M1 may include a first electrode coupled to the first node N1 and a second electrode coupled to the third node N3. The gate of the first transistor M1 is coupled to the second node N2. The first transistor M1 may control the amount of current flowing from the first power supply VDD to the second power supply VSS via the light emitting element LD in response to the voltage of the second node N2. To this end, the first power supply VDD may be set to a voltage higher than the second power supply VSS.

[0087] The second transistor M2 may be coupled between the jth data line Dj and the first node N1. A gate of the second transistor M2 may be coupled to the i-th first scan line S1i. When the first scan signal is supplied to the i-th first scan line S1i, the second transistor M2 may be turned on to electrically couple the j-th data line Dj to the first node N1.

[0088] The third transistor M3 may be coupled between the second electrode (i.e., the third node N3) and the second node N2 of the first transistor M1. The gate of the third transistor M3 may be coupled to the i-th second scan line S2i. When the second scan signal is supplied to the i-th second scan line S2i, the third transistor M3 may be turned on to electrically connect the second electrode of the first transistor M1 to the second node N2. Therefore, when the third transistor M3 is turned on, the first transistor M1 may be connected in the form of a diode.

[0089] The third transistor M3 may be formed of an oxide semiconductor transistor. For example, the third transistor M3 may be an N-type oxide semiconductor transistor and may include an oxide semiconductor layer as an active layer. Therefore, a gate-on voltage for turning on the third transistor M3 may have a logic high level.

[0090] The oxide semiconductor transistor can be manufactured by a low temperature process and has a low charge mobility compared to a polysilicon semiconductor transistor. In other words, the oxide semiconductor transistor can have excellent current interception characteristics. Therefore, if the third transistor M3 is formed by an oxide semiconductor transistor, the leakage current from the second node N2 can be minimized, thereby improving the display quality of the display device.

[0091] However, the embodiments of the present invention are not limited thereto. For example, the third transistor M3 may be formed of a P-type polysilicon semiconductor transistor.

[0092] The storage capacitor Cst may be coupled between the first power source VDD and the second node N2. The storage capacitor Cst may store a voltage corresponding to the data signal.

[0093] The fourth transistor M4 may be turned on by the first scan signal provided from the i-2 first scan line S1 (i-2), so that a bias voltage may be provided to the first node N1 (e.g., the source of the first transistor M1). In an embodiment, the fourth transistor M4 may be coupled between the first node N1 and the first power line IL1. The voltage of the first initialization power supply Vint1 may be provided to the first power line IL1. The gate of the fourth transistor M4 may be coupled to the i-2 first scan line S1 (i-2).

[0094] The fifth transistor M5 may be coupled between the first power supply VDD and the first node N1. A gate of the fifth transistor M5 may be coupled to the i-th emission control line Ei. The fifth transistor M5 may be turned off when the emission control signal is supplied to the i-th emission control line Ei, and may be turned on in other cases.

[0095] The sixth transistor M6 may be coupled between the second electrode (i.e., the third node N3) of the first transistor M1 and the first electrode (i.e., the fourth node N4) of the light emitting element LD. The gate of the sixth transistor M6 may be coupled to the i-th emission control line Ei. The sixth transistor M6 may be turned off when the emission control signal is supplied to the i-th emission control line Ei, and may be turned on in other cases.

[0096] In an implementation, each of the fifth transistor M and the sixth transistor M6 may be formed of a P-type polysilicon semiconductor transistor.

[0097] The seventh transistor M7 may be coupled between the second node N2 and the first power line IL1. A gate of the seventh transistor M7 may be coupled to the i-3 th second scan line S2 (i-3). When the second scan signal is supplied to the i-3 th second scan line S2 (i-3), the seventh transistor M7 may be turned on so that the voltage of the first initialization power supply Vint1 may be supplied to the second node N2.

[0098] In an implementation, the seventh transistor M7 may be formed of an oxide semiconductor transistor.

[0099] The fourth transistor M4 and the seventh transistor M7 may be turned on during different periods. For example, the seventh transistor M7 and the fourth transistor M4 may be turned on sequentially. In an embodiment, when the fourth transistor M4 is turned on, the first initialization power supply Vint1 may have a high level. When the seventh transistor M7 is turned on, the first initialization power supply Vint1 may have a low level.

[0100] In an embodiment, the low level of the first initialization power supply Vint1 can be set to a value lower than the lowest voltage of the data signal to be provided to the j-th data line Dj. Therefore, the gate voltage of the first transistor M1 can be initialized to the low level of the first initialization power supply Vint1 by turning on the seventh transistor M7, and the voltage to be stored in the storage capacitor Cst can also be initialized. However, the embodiments of the present invention are not limited to this. For example, the low level of each of the first initialization power supply Vint1 and the second initialization power supply Vint2 can be set to a value higher than the voltage of the second power supply VSS.

[0101] For example, if the low level of each of the first initialization power supply Vint1 and the second initialization power supply Vint2 is too low, the bias variation (or hysteresis variation) of the first transistor M1 may be increased. Such hysteresis may cause a flicker phenomenon in a low-frequency driving operation. Therefore, the low level of each of the first initialization power supply Vint1 and the second initialization power supply Vint2 may be set to a value higher than a predetermined voltage level according to the operating conditions of the display device 1000. Therefore, the flicker phenomenon in the low-frequency driving can be alleviated, and the step efficiency can be improved.

[0102] In an embodiment, the high level of the first initialization power supply Vint1 may be set to a value similar to the voltage of the first power supply VDD. For example, the high level of the first initialization power supply Vint1 may be in the range of about 5V to about 8V. When the fourth transistor M4 is turned on, the high level of the first initialization power supply Vint1 may be provided to the first node N1, and the first transistor M1 may have an on-bias state (i.e., on-biased). Therefore, since the high level of the first initialization power supply Vint1 has a substantially constant size provided to the first transistor M1, the hysteresis characteristic of the first transistor M1 may be improved, and the bias difference (hysteresis deviation) between the first transistors M1 of the pixel 10 may be reduced.

[0103] The eighth transistor M8 may be coupled between the second power line IL2 and the fourth node N4. In an embodiment, a gate of the eighth transistor M8 may be coupled to the i-th first scan line S1i. A voltage of the second initialization power source Vint2 may be supplied to the second power line IL2.

[0104] When the first scan signal is provided, the eighth transistor M8 is turned on, so that the voltage of the second initialization power supply Vint2 can be provided to the first electrode (e.g., the fourth node N4) of the light emitting element LD. In an embodiment, when the eighth transistor M8 is turned on, the low level of the second initialization power supply Vint2 can be provided to the first electrode of the light emitting element LD through the second power line IL2.

[0105] When the low level of the second initialization power supply Vint2 is supplied to the first electrode of the light emitting element LD, the parasitic capacitor of the light emitting element LD can be discharged. When the residual voltage charged in the parasitic capacitor is discharged (removed), undesired fine emission can be prevented. Therefore, the black performance of the pixel 10 can be improved.

[0106] In an embodiment, each of the transistors M1, M2, M4, M5, M6, and M8 except the third transistor M3 and the seventh transistor M7 may be formed by a polysilicon transistor and include a polysilicon semiconductor layer as an active layer (channel). For example, the active layer may be formed by a low temperature polysilicon process. For example, the polysilicon transistor may be a P-type polysilicon transistor.

[0107] Since polycrystalline silicon semiconductor transistors have the advantage of high response speed, polycrystalline silicon semiconductor transistors can be applied to switching elements that require high-speed switching operations.

[0108] However, the embodiments of the present invention are not limited thereto. For example, at least some of the first to eighth transistors M1 to M8 may each be formed of an oxide semiconductor transistor, and the other transistors may each be formed of a polysilicon transistor.

[0109] In an embodiment, the i+1th pixel PXi+1 may include a light emitting element LD', first to eighth transistors M1' to M8', and a storage capacitor Cst'. The gates of the first to eighth transistors M1' to M8' of the i+1th pixel PXi+1 may be coupled to a scan line and an emission control line after the scan line and the emission control line coupled to the i-th pixel PXi. The operation of the i+1th pixel PXi+1 may be similar to that of the i-th pixel PXi.

[0110] In an embodiment, the fourth transistor M4' of the i+1th pixel PXi+1 may be coupled between the first node N1' and the second power line IL2. When the first scan signal is supplied to the i-1th first scan line S1(i-1), the fourth transistor M4' may be turned on so that the high level of the second initialization power supply Vint2 may be supplied to the first node N1'. In other words, when the fourth transistor M4' of the i+1th pixel PXi+1 is turned on, the second initialization power supply Vint2 may be supplied to the first node N1' at a high level. Therefore, the high level of the second initialization power supply Vint2 may be supplied to the first node N1' of the i+1th pixel PXi+1, and the first transistor M1' of the i+1th pixel PXi+1 may be turned on and biased.

[0111] In an embodiment, the seventh transistor M7' of the i+1th pixel PXi+1 may be coupled between the second node N2' and the second power line IL2. When the second scan signal is supplied to the i-2th second scan line S2(i-2), the seventh transistor M7' may be turned on so that the low level of the second initialization power supply Vint2 may be supplied to the second node N2'. In other words, when the seventh transistor M7' of the i+1th pixel PXi+1 is turned on, the second initialization power supply Vint2 may be supplied to the second node N2' at a low level. Therefore, the gate voltage of the first transistor M1' of the i+1th pixel PXi+1 may be initialized.

[0112] In an embodiment, the eighth transistor M8' of the i+1th pixel PXi+1 may be coupled between the fourth node N4' and the first power line IL1. When the first scan signal is supplied to the i+1th first scan line S1(i+1), the eighth transistor M8' may be turned on so that the low level of the first initialization power supply Vint1 may be supplied to the fourth node N4'. In other words, when the eighth transistor M8' of the i+1th pixel PXi+1 is turned on, the first initialization power supply Vint1 may be supplied to the second node N2' at a low level. Therefore, the anode voltage of the light emitting element LD' of the i+1th pixel PXi+1 may be initialized.

[0113] As mentioned above, refer to Figure 2 , the first power line IL1 can be connected to the fourth transistor M4 and the seventh transistor M7 of the i-th pixel PXi and the eighth transistor M8' of the i+1-th pixel PXi+1. The second power line IL2 can be connected to the eighth transistor M8 of the i-th pixel PXi and the fourth transistor M4' and the seventh transistor M7' of the i+1-th pixel PXi+1. In addition, the first initialization power supply Vint1 and the second initialization power supply Vint2 can alternately have a high level (or a low level). Therefore, a conduction bias can be periodically applied to the first transistor M1 by the swing of the first initialization power supply Vint1 and the second initialization power supply Vint2, and the gate voltage of the first transistor M1 can be periodically initialized. Therefore, the flicker phenomenon in the low-frequency driving operation can be alleviated, and the step efficiency in the high-frequency driving operation can be improved.

[0114] In addition, the initialization and conduction bias operations can be performed by periodically changing the voltages of the first initialization power source Vint1 and the second initialization power source Vint2 without using an additional line or an additional power supply for applying a bias voltage. Therefore, the production cost can be reduced, and unnecessary complexity in the display panel can be avoided. Therefore, the image quality of the display device 1000 can be improved.

[0115] Figure 3 yes Figure 2 A timing diagram of an embodiment of the operation of a pixel.

[0116] Reference Figures 1 to 3 During the first period P1, the pixel 10 may be provided with a signal for displaying an image. The first period P1 may include a period in which a data signal substantially corresponding to an output image is input.

[0117] Pixel 10 (eg Figure 2 The operation of the display device 1000 may be divided into an operation in an emission period EP and an operation in a non-emission period NEP.

[0118] Figure 3 The operation of the pixel 10 during the first period P1 is shown. For example, the display device 1000 may be driven in a first mode of displaying an image at a first frequency.

[0119] In the case where the display device 1000 is driven in the first mode, the first scanning signal and the second scanning signal may be provided at the first frequency to the pixel 10. The emission control signal may also be provided at the first frequency.

[0120] A period during which the emission control signal is supplied to the i-th emission control line Ei (i.e., a period during which the emission control signal having a logic high level is supplied) may correspond to the non-emission period NEP of the pixel 10. A period during which the emission control signal is not supplied to the i-th emission control line Ei (i.e., a period during which the emission control signal having a logic low level is supplied) may correspond to the emission period EP of the pixel 10.

[0121] During the non-emission period NEP, the fifth transistor M5 and the sixth transistor M6 are turned off by the emission control signal so that the pixel 10 does not emit light.

[0122] The non-emission period NEP may include an initialization period IP, a bias period BP, and a writing period WP. Here, a first scan signal may be provided during the bias period BP and the writing period WP. A second scan signal may be provided during the initialization period IP and the writing period WP.

[0123] The initialization period IP, the bias period BP, and the writing period WP may each correspond to approximately one horizontal period 1 H. In addition, the pulse widths of the first scan signal and the second scan signal may each correspond to approximately one horizontal period 1 H.

[0124] For each first cycle 1C, the power supply unit 800 may alternately output the first initialization power Vint1 at a high level and a low level. For example, the first cycle 1C may correspond to approximately two horizontal periods 2H. Figure 3As shown in , when the second scan signal is supplied to the i-3 th second scan line S2 (i-3), the first initialization power source Vint1 may be output at a low level. Figure 3 As shown, when the first scan signal is supplied to the i-2 th first scan line S1(i-2) (or the i th first scan line S1i), the first initialization power Vint1 may be output at a high level.

[0125] Similarly, for each first cycle 1C, the power supply unit 800 may alternately output the second initialization power supply Vint2 at a high level and a low level. The power supply unit 800 may output a high level of the second initialization power supply Vint2 overlapping with the low level of the first initialization power supply Vint1, and output a low level of the second initialization power supply Vint2 overlapping with the high level of the first initialization power supply Vint1. Therefore, the operation of the i-th pixel PXi and the i+1-th pixel PXi+1 may each have an initialization period IP, a bias period BP, and a write period WP, ​​and the operation of the i-th pixel PXi and the i+1-th pixel PXi+1 has a difference of one horizontal period 1H.

[0126] After the emission control signal has been supplied to the i-th emission control line Ei, the second scan signal may be supplied to the i-3-th second scan line S2(i-3) during the initialization period IP. The second scan signal may be a signal for controlling an N-type transistor and may have a logic high level.

[0127] During the initialization period IP, the seventh transistor M7 may be turned on in response to the second scan signal. When the seventh transistor M7 is turned on, the low level of the first initialization power supply Vint1 may be provided to the second node N2. Therefore, the gate voltage of the first transistor M1 (eg, the voltage to be charged to the storage capacitor Cst) may be initialized.

[0128] The first scan signal may be provided to the i-2 th first scan line S1(i-2) during the bias period BP. The first scan signal may be a signal for controlling a P-type transistor and may have a logic low level.

[0129] During the bias period BP, the fourth transistor M4 may be turned on in response to the first scan signal. When the fourth transistor M4 is turned on, the high level of the first initialization power supply Vint1 may be provided to the first node N1, and the first transistor M1 may have a turn-on bias. In an embodiment, the high level of the first initialization power supply Vint1 may be in the range of about 5V to about 8V. According to the driving condition of the display device 1000, the high levels of the first initialization power supply Vint1 and the second initialization power supply Vint2 may be easily adjusted. Since a voltage having a constant level is provided to the first node N1, the bias difference between the respective first transistors M1 of the pixel PX may be reduced.

[0130] Next, during the writing period WP, ​​the first scan signal may be supplied to the i-th first scan line S1i, and the second scan signal may be supplied to the i-th second scan line S2i.

[0131] When the first scan signal is supplied to the i-th first scan line S1i, the second transistor M2 may be turned on. When the second transistor M2 is turned on, the data signal may be supplied to the first node N1.

[0132] When the second scan signal is supplied to the i-th second scan line S2i, the third transistor M3 may be turned on. When the third transistor M3 is turned on, the first transistor M1 may be connected in the form of a diode and the threshold voltage of the first transistor M1 may be compensated. The storage capacitor Cst may store a voltage corresponding to the data signal.

[0133] When the first scan signal is supplied to the i-th first scan line S1i, the eighth transistor M8 may be turned on. When the eighth transistor M8 is turned on, the low level of the second initialization power supply Vint2 is supplied to the fourth node N4. Therefore, the low level of the second initialization power supply Vint2 is supplied to the first electrode of the light emitting element LD, and the parasitic capacitor of the light emitting element LD may be discharged.

[0134] However, the embodiments of the present invention are not limited thereto. For example, the gate of the eighth transistor M8 may be coupled to the i-2 th first scan line S1 (i-2). In this case, the fourth transistor M4 and the eighth transistor M8 may be turned on at the same time.

[0135] Next, the emission control signal provided to the i-th emission control line Ei may be suspended. When the emission control signal provided to the i-th emission control line Ei is suspended, the fifth transistor M5 and the sixth transistor M5 may be turned on. Here, the first transistor M1 may control the driving current flowing to the light emitting element LD in response to the voltage of the second node N2. During the emission period EP, the light emitting element LD may generate light having a brightness corresponding to the driving current.

[0136] As described above, the display device 1000 can alternately provide the first initialization power supply Vint1 and the second initialization power supply Vint2 having a high level (or a low level) to the pixel PX. Therefore, the initialization operation or the on-bias operation can be performed without using an additional line or an additional power supply unit for applying a bias voltage, etc. Therefore, the production cost can be reduced, and unnecessary complexity in the display panel can be avoided. As a result, the image quality of the display device 1000 can be improved.

[0137] Figure 4 yes Figure 2 A timing diagram of another embodiment of the operation of a pixel.

[0138] Reference Figures 1 to 4 , the pixel 10 may be provided with a signal for displaying an image during the first period P1, and may maintain the image displayed in the first period P1 during the second period P2.

[0139] Figure 4 An example of a low-frequency driving operation of the display device 1000 is shown. For example, the display device 1000 may be driven in the second mode of displaying an image in a low-frequency driving manner.

[0140] The second scanning signal may be provided to the pixel 10 at a frequency corresponding to the image refresh rate. The first scanning signal and the emission control signal may be provided at a frequency corresponding to the image refresh rate. Figure 3 The scanning signal and the emission control signal are provided to the pixel 10 at the same timing (eg, frequency) as that of the supply of the scanning signal and the emission control signal, regardless of the image refresh rate.

[0141] The operation of the first period P1 can be Figure 3 The operation of pixel 10 is basically the same.

[0142] During the second period P2, the same emission control signal as that of the first period P1 may be provided. In other words, the second period P2 may include an emission period EP' and a non-emission period NEP'. During the second period P2 as a holding subframe, the second scan signal is not provided.

[0143] In an embodiment, a data signal corresponding to an image to be displayed may not be provided during the second period P2. For example, a data signal having a predetermined constant voltage level may be provided during the second period P2, or the data signal may have a state suitable for minimizing power consumption.

[0144] The non-emission period NEP' of the second period P2 may include a bias period BP' and an initialization period IP'. The first scan signal may be supplied to the i-2 th first scan line S1 (i-2) during the bias period BP'.

[0145] When the first scan signal is supplied to the i-2 th first scan line S1(i-2), the fourth transistor M4 may be turned on. When the fourth transistor M4 is turned on, the high level of the first initialization power source Vint1 is supplied to the first node N1. Therefore, the first transistor M1 may be turned on and biased.

[0146] In an embodiment, the degree to which the first transistor M1 is turned on can be controlled by adjusting the magnitude of the low level of the first initialization power supply Vint1. For example, if the low level of the first initialization power supply Vint1 increases, the turn-on bias to be applied to the first transistor M1 can be reduced. Thus, the bias degree of the first transistor M1 in the emission period EP or EP' can become similar to the bias degree of the first transistor M1 in other periods. Therefore, the step efficiency can be improved.

[0147] During the initialization period IP′, the first scan signal may be provided to the i-th first scan line S1 i .

[0148] When the first scan signal is supplied to the i-th first scan line S1i, the second transistor M2 and the eighth transistor M8 may be turned on.

[0149] When the second transistor M2 is turned on, a predetermined voltage (e.g., a bias voltage) provided from the j-th data line Dj may be provided to the first node N1. The bias voltage may be a relatively high voltage for a turn-on bias. The turn-on bias may be applied to the first transistor M1 by a driving operation in the initialization period IP'. Therefore, the hysteresis characteristic may be improved.

[0150] When the eighth transistor M8 is turned on, the low level of the second initialization power Vint2 is supplied to the fourth node N4. Therefore, the low level of the second initialization power Vint2 is supplied to the first electrode of the light emitting element LD, and the parasitic capacitor of the light emitting element LD can be discharged.

[0151] In this way, since the conduction bias is applied to the first transistor M1 during the second period P2 to maintain the image, the image flickering phenomenon and the afterimage phenomenon caused by the hysteresis characteristic of the first transistor M1 during the low-frequency driving operation can be alleviated. In addition, since the voltage of the first electrode of the light emitting element LD is initialized during the second period P2, the image quality in the low-frequency driving operation can be improved.

[0152] The number of times the second period P2 is continuously repeated may be changed according to the image refresh rate.

[0153] Figure 5 is included in Figure 1 A circuit diagram of another embodiment of a representative pixel in a display device of FIG.

[0154] exist Figure 5 In the present invention, the same reference numerals will be used to indicate the same Figure 2 The same elements as those described above are omitted to avoid redundancy. In addition to the fourth transistor, Figure 5 The pixels can be Figure 2 The pixels are substantially the same or similar. Specifically, Figure 5 The fourth transistor M4 has Figure 2 The fourth transistor M4 is connected differently.

[0155] Reference Figure 1 and Figure 5 , the pixel 11 may include a light emitting element LD, first to eighth transistors M1 to M8, and a storage capacitor Cst.

[0156] The pixel 11 may be a pixel disposed on the i-th pixel row (i-th horizontal line).

[0157] The fourth transistor M4 may be coupled between the third node N3 and the first power line IL1. The fourth transistor M4 may be turned on in response to the first scan signal supplied to the i-2 th first scan line S1 (i-2), so that the high level of the first initialization power source Vint1 may be supplied to the third node N3 (e.g., the drain of the first transistor M1). Therefore, the first transistor M1 may be turned on and biased, the hysteresis characteristic of the first transistor M1 may be improved, and the hysteresis deviation with the first transistors of other pixels may be reduced.

[0158] When the first scan signal is supplied to the i-2 first scan line S1(i-2) or the i-th first scan line S1i, the second initialization power source Vint2 may have a low level. Therefore, the gate electrode of the eighth transistor M8 may be coupled to the i-2 first scan line S1(i-2) or the i-th first scan line S1i.

[0159] In the case where the pixel 11 is arranged on the i-1th pixel row or the i+1th pixel row, one electrode of each of the fourth transistor M4, the seventh transistor M7 and the eighth transistor M8 can be connected to an initialization power supply different from the initialization power supply to which the pixel arranged on the i-th pixel row is connected. For example, one electrode of each of the fourth transistor M4 and the seventh transistor M7 of the pixel 11 arranged on the i+1th pixel row can be connected to the second power line IL2 for providing the second initialization power supply Vint2, but not to the first power line IL1. In addition, one electrode of the eighth transistor M8 of the pixel 11 arranged on the i+1th pixel row can be connected to the first power line IL1 for providing the first initialization power supply Vint1, but not to the second power line IL2.

[0160] All pixel rows can be similar to the reference by alternately providing a high level and a low level first initialization power Vint1 and a second initialization power Vint2 Figure 3 or Figure 4 The drive mode described is operated in the manner described.

[0161] Figure 6 The first power line and the second power line are included in Figure 1 FIG. 1 is a diagram of an embodiment of the connection of pixels in a display device.

[0162] Reference Figure 1 , Figure 2 and Figure 6 , the first power line IL1 and the second power line IL2 may each extend between predetermined pixel rows PXRi, PXRi+1, and PXRi+2, and may be coupled to the pixels PXi, PXi+1, and PXi+2.

[0163] The i-th pixel PXi may be disposed on the i-th pixel row PXRi. The i-th pixel row PXRi may be defined as an imaginary row extending in the first direction DR1. Similarly, the i+1-th pixel PXi+1 may be disposed on the i+1-th pixel row PXRi+1, and the i+2-th pixel PXi+2 may be disposed on the i+2-th pixel row PXRi+2.

[0164] The first power line IL1 may transmit a voltage of a first initialization power source Vint1, and the second power line IL2 may transmit a voltage of a second initialization power source Vint2.

[0165] In an embodiment, the first power line IL1 or the second power line IL2 may be disposed between the i-th pixel row PXRi and the i+1-th pixel row PXRi+1. Figure 6 As shown in , the first power line IL1 may extend in the first direction DR1 between the i-th pixel row PXRi and the i+1-th pixel row PXRi+1. In this case, the second power line IL2 may extend in the first direction DR1 between the i+1-th pixel row PXRi+1 and the i+2-th pixel row PXRi+2. In addition, the second power line IL2 may also extend in the first direction DR1 between the i-1-th pixel row and the i-th pixel row PXRi.

[0166] Thus, in an embodiment, the first power line IL1 and the second power line IL2 may be alternately disposed in the second direction DR2 corresponding to the pixel column direction. Therefore, the number of lines or conductive patterns for transmitting the first initialization power Vint1 and the second initialization power Vint2 may not be increased.

[0167] In an embodiment, a first power line IL1 disposed between the i-th pixel row PXRi and the i+1-th pixel row PXRi+1 may be coupled to a fourth transistor M4 and a seventh transistor M7 of an i-th pixel PXi disposed on the i-th pixel row PXRi and an eighth transistor M8 of an i+1-th pixel PXi+1 disposed on the i+1-th pixel row PXRi+1. Similarly, a second power line IL2 disposed between the i+1-th pixel row PXRi+1 and the i+2-th pixel row PXRi+2 may be coupled to a fourth transistor M4 and a seventh transistor M7 of an i+1-th pixel PXi+1 disposed on the i+1-th pixel row PXRi+1 and an eighth transistor M8 of an i+2-th pixel PXi+2 disposed on the i+2-th pixel row PXRi+2.

[0168] In this way, the first power line IL1 and the second power line IL2 that alternately provide a high level and a low level at different times can be alternately set for each pixel row. Therefore, the line structure for providing the first initialization power Vint1 and the second initialization power Vint2 can be simplified. In addition, the first initialization power Vint1 and the second initialization power Vint2 only have different supply timings, so no additional driver for power supply is required. Therefore, the production cost of the display device 1000 can be reduced.

[0169] Figures 7 to 10 is included in Figure 1 Circuit diagrams of other embodiments of representative pixels in a display device.

[0170] exist Figures 7 to 10 In the present invention, the same reference numerals will be used to indicate the same Figure 2 The same elements as those described above will be omitted from repeated descriptions of these elements. In addition to the structures of the fourth transistor and the seventh transistor, Figures 7 to 10 The pixels can be Figure 2 or Figure 5 The pixels are the same or substantially similar. Specifically, Figures 7 to 10 The fourth transistor M4 and the seventh transistor M7 have Figure 2 or Figure 5 The fourth transistor M4 and the seventh transistor M7 are connected differently.

[0171] Reference Figure 1 as well as Figures 7 to 10 , each of the pixels 20 , 21 , 22 , and 23 may include a light emitting element LD, first to eighth transistors M1 to M8 , and a storage capacitor Cst.

[0172] In an embodiment, the first initialization power supply Vint1 and the second initialization power supply Vint2 may be provided to the pixels 20, 21, 22, 23 at a constant voltage level. For example, the first initialization power supply Vint1 may have a voltage level for initializing the gate voltage of the first transistor M1. The second initialization power supply Vint2 may have a voltage level for initializing the voltage of the first electrode of the light emitting element LD.

[0173] In an embodiment, each of the third transistor M3, the fourth transistor M4, and the seventh transistor M7 is formed of an oxide semiconductor transistor. For example, each of the third transistor M3, the fourth transistor M4, and the seventh transistor M7 may be an N-type oxide semiconductor transistor, and may include an oxide semiconductor layer as an active layer. Therefore, a gate-on voltage for turning on the third transistor M3, the fourth transistor M4, or the seventh transistor M7 may have a logic high level.

[0174] In an embodiment, if Figure 7 and Fig. 9 As shown in , the fourth transistor M4 may be coupled between the first initialization power source Vint1 and the first node N1. The seventh transistor M7 may be coupled between the second node N2 and the first initialization power source Vint1. The gates of the fourth transistor M4 and the seventh transistor M7 may be commonly coupled to the i-1th second scan line S2 (i-1). However, Fig. 9 One electrode of the fourth transistor M4 shown in FIG. 1 can be electrically coupled to the first initialization power source Vint1 via the seventh transistor M7. Figure 7 , the first electrode (eg, source) of the fourth transistor M4 is connected to the second electrode (eg, drain) of the seventh transistor M7. Fig. 9 , a first electrode (eg, source) of the fourth transistor M4 is connected to a first electrode (eg, source) of the seventh transistor M7.

[0175] The fourth transistor M4 and the seventh transistor M7 may be turned on at the same time by the second scan signal. Therefore, the same voltage may be provided to the gate (or second node N2) and the source (or first node N1) of the first transistor M1. Then, the gate-source voltage (e.g., Vgs) of the first transistor M1 may become 0V, so that the first transistor M1 may have a cut-off bias state.

[0176] In this way, the bias level of the first transistor M1 in the period when the second transistor M2 is turned on to write data and the bias level of the first transistor M1 in the period when the fourth transistor M4 and the seventh transistor M7 are turned on can be controlled to be similar to each other. Thus, the hysteresis characteristic of the first transistor M1 of the pixel 20, 22 can be improved. Therefore, the flicker phenomenon in the low-frequency driving operation can be reduced.

[0177] In an embodiment, if Figure 8 and Fig.10 As shown in , the fourth transistor M4 may be coupled between the first initialization power source Vint1 and the third node N3. The seventh transistor M7 may be coupled between the second node N2 and the first initialization power source Vint1. The gates of the fourth transistor M4 and the seventh transistor M7 may be commonly coupled to the i-1th second scan line S2 (i-1). However, Fig.10 One electrode of the fourth transistor M4 shown in FIG. 1 can be electrically coupled to the first initialization power source Vint1 via the seventh transistor M7. Figure 8 , the first electrode (eg, source) of the fourth transistor M4 is connected to the second electrode (eg, drain) of the seventh transistor M7. Fig.10 , a first electrode (eg, source) of the fourth transistor M4 is connected to a first electrode (eg, source) of the seventh transistor M7.

[0178] When the fourth transistor M4 and the seventh transistor M7 are turned on at the same time, the voltage of the first initialization power supply Vint1 may be provided to the second node N2 and the third node N3. Here, the drain voltage of the first transistor M1 may be similar to the voltage of the first initialization power supply Vint1, and the source voltage of the first transistor M1 may have a level corresponding to the difference between the voltage of the first initialization power supply Vint1 and the threshold voltage of the first transistor M1. Therefore, the first transistor M1 of the pixel 21, 23 may have a cut-off bias state.

[0179] In this way, according to Figures 7 to 10 In the pixels 20, 21, 22, and 23, since a cut-off bias is applied to the first transistor M1 during the gate voltage initialization operation of the first transistor M1, similar stress can be applied to the first transistor M1 during the initialization period IP and the writing period WP. Therefore, the hysteresis characteristic of the first transistor M1 can be improved. Therefore, the flicker phenomenon in the low-frequency driving operation can be alleviated, and the step efficiency in the high-frequency driving operation can be improved.

[0180] As described above, the first transistor M1 can be controlled to periodically have an on bias state or an off bias state. Therefore, the hysteresis variation or deviation of the first transistor M1 can be mitigated or reduced. Therefore, the flicker phenomenon caused by the hysteresis characteristic in the low-frequency driving operation can be mitigated, and the step efficiency in the high-frequency driving operation can be improved. As a result, the image quality can be improved.

[0181] Although certain embodiments and examples have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to such embodiments, but to the broader scope of the appended claims and various obvious modifications and equivalent arrangements as will be apparent to those of ordinary skill in the art.

Claims

1. A display device, comprising: A pixel connected to a first scan line and a second scan line; A first scan driver, providing a first scan signal to the first scan line in a first period and a second period; a second scan driver, which provides a second scan signal to the second scan line in the first period, and does not provide the second scan signal to the second scan line in the second period; as well as a power supply unit that supplies a first initialization voltage to the pixel through a first initialization power line and supplies a second initialization voltage to the pixel through a second initialization power line, Wherein, at least one of the pixels comprises: a first transistor connected between a first node and a second node and having a gate electrode connected to a third node, the first node being connected to a first power source; a second transistor connected between the data line and the first node and having a gate electrode connected to one of the first scan lines; a third transistor connected between the second node and the third node and having a gate electrode connected to one of the second scan lines; and a light emitting element having a first electrode connected to the second node and a second electrode connected to a second power source, and The first node or the second node is connected to the first initialization power line, and the first electrode of the light emitting element is connected to the second initialization power line.

2. The display device according to claim 1, wherein: The first transistor and the second transistor are polysilicon semiconductor transistors, and the third transistor is an oxide semiconductor transistor.

3. The display device according to claim 1, wherein: The first transistor and the second transistor are P-type transistors, and the third transistor is an N-type transistor.

4. The display device according to claim 1, wherein: The at least one of the pixels further includes a fourth transistor connected between the first electrode of the light emitting element and the second initialization power line and having a gate electrode connected to the one of the first scan lines.

5. The display device according to claim 4, wherein: The at least one of the pixels further includes a fifth transistor connected between the first node and the first initialization power line and having a gate electrode connected to another first scan line of the first scan lines.

6. The display device according to claim 4, wherein: The at least one of the pixels further includes a fifth transistor connected between the third node and the first initialization power line and having a gate electrode connected to another second scan line of the second scan lines.

7. The display device according to claim 1, further comprising: an emission driver, providing an emission control signal to an emission control line in the first period and the second period; as well as a data driver that provides a data signal to the data line in the first period and does not provide the data signal to the data line in the second period, Wherein, the pixel is also connected to the emission control line and the data line, and One of the data lines is the data line connected to the second transistor.

8. A display device, comprising: Pixels; A first initialization power line, providing a first initialization voltage; as well as A second initialization power line, providing a second initialization voltage; Wherein, at least one of the pixels comprises: a first transistor connected between a first node and a second node and having a gate electrode connected to a third node, the first node being connected to a first power source; a second transistor turned on in response to a first scanning signal, the second transistor being connected between the data line and the first node; a third transistor, turned on in response to a second scan signal, the third transistor being connected between the second node and the third node; a light emitting element having a first electrode connected to the second node and a second electrode connected to a second power source; a fourth transistor connected between the third node and the first initialization power line to transmit the first initialization voltage of the first initialization power line to the third node; and A fifth transistor is connected between the first electrode of the light emitting element and the second initialization power line to transmit the second initialization voltage of the second initialization power line to the first electrode of the light emitting element.

9. The display device according to claim 8, wherein: The first transistor, the second transistor, and the fifth transistor are polysilicon semiconductor transistors, and the third transistor and the fourth transistor are oxide semiconductor transistors.

10. The display device according to claim 8, wherein: The first transistor, the second transistor, and the fifth transistor are P-type transistors, and the third transistor and the fourth transistor are N-type transistors.

11. The display device according to claim 8, wherein: At least one of the pixels further includes a sixth transistor including a first terminal receiving a power voltage and a second terminal connected to the first node to provide a given voltage level of the power voltage to the first node.

12. The display device according to claim 11, wherein: The fourth transistor and the sixth transistor are configured to be turned on in response to different control signals.

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