Chip multilayer heterogeneous integration method and device, equipment and storage medium

Through deep learning analysis and graph neural network dynamically adjusting chip design parameters, combining micro-convex arrays and through-silicon structures for multi-layer stacking, the problems of uneven resource allocation and reduced computing efficiency in heterogeneous integration technology are solved, and the chip performance and integration efficiency are improved.

CN119812023AActive Publication Date: 2025-04-11YIXIN MICRO SEMICON TECH (SHENZHEN) CO LTD +1
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Patent Information

Application Number
CN202510290559.0
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-03-12
Publication Date
2025-04-11
Estimated Expiration
2045-03-12

AI Technical Summary

Technical Problem

The existing heterogeneous integration technology lacks a dynamic optimization mechanism for chip computing tasks and data storage, resulting in uneven resource allocation and reduced computing efficiency.

Method used

By conducting deep learning analysis of the design parameters of the memory-based integrated chip, a chip layout scheme is generated, and the graph neural network is used to dynamically adjust the computing task allocation and data storage functions, combining micro-convex arrays and through-silicon structures for multi-layer stacking to form a multi-layer heterogeneous integrated structure.

Benefits of technology

Dynamic optimization of chip computing tasks and storage locations is realized, the chip performance and integration efficiency are improved, and the problems of uneven resource allocation and reduced computing efficiency are solved.

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Abstract

The invention provides a chip multilayer heterogeneous integration method, device and equipment and a storage medium, and the method comprises the steps: carrying out the deep learning analysis of design parameters of a storage and calculation integrated chip, generating a chip layout scheme, and dynamically adjusting the calculation task distribution and data storage functions through a graph neural network, and obtaining an optimized chip design scheme; carrying out deep learning modeling on the micro salient points based on the design scheme, and designing and forming a micro salient point array through an electroplating process; generating a silicon through hole distribution scheme of the silicon wafer based on the chip design scheme, and forming a silicon through hole structure on the silicon wafer; and carrying out inversion processing on the chip, and carrying out multi-layer stacking on the chip and the silicon wafer with the silicon through hole to form a multi-layer heterogeneous integrated structure. According to the method, chip multi-layer heterogeneous integration is carried out by combining the micro bump array and the silicon through hole after the calculation task distribution and data storage functions are adjusted, the dynamic optimization of the calculation task and the storage position of the chip is realized, and the performance and the integration efficiency of the chip are improved.
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