Signal distortion compensation method, chip, communication system and vehicle

Abstract

The invention relates to the technical field of communication, in particular to a signal distortion compensation method, a chip, a communication system and a vehicle. The method comprises the following steps: when a chip is in a communication mode, if a to-be-compensated differential signal is received, converting the to-be-compensated differential signal into a first digital signal; performing data processing according to the first digital signal; driving a first ideal current source to generate a first ideal differential signal corresponding to the first digital signal; and obtaining a PWM compensation value, determining a compensated output signal according to the PWM compensation value and the first ideal differential signal, and outputting the compensated output signal. According to the invention, signal distortion caused by environmental loss or transmission interference and the like can be compensated, so that the signal distortion is avoided, and the signal transmission process is stable and reliable.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a signal distortion compensation method, a chip, a communication system and a vehicle. Background Art

[0002] At present, the BMS (BATTERY MANAGEMENT SYSTEM) of electric vehicles has functions such as battery voltage acquisition, temperature acquisition, current acquisition, balancing control, total pressure detection, state estimation and fault diagnosis. The BMS exchanges data with the upper controller through wired communication, and the daisy chain communication method is the main communication method currently used between the BMS and the upper controller. Among them, the daisy chain adopts the transmission method of differential signals. The signal is sent from the first chip in the BMS, converted into a differential signal by the communication box, and routed through the differential circuit, or through the through hole in the middle, and reaches the receiving end of the next chip through the coupling point capacitor. In this process, the differential signal line may be lost and the signal may be distorted due to changes in the environment. After long-distance transmission or interference during the transmission process, the distortion of the differential signal on the differential signal line is likely to be more serious. Summary of the invention

[0003] The embodiments of the present invention provide a signal distortion compensation method, a chip, a communication system and a vehicle to solve the problem of signal distortion when a differential signal is transmitted between different chips.

[0004] The present invention provides a signal distortion compensation method, comprising:

[0005] When the chip is in the communication mode, if a differential signal to be compensated is received, the differential signal to be compensated is converted into a first digital signal;

[0006] performing data processing according to the first digital signal;

[0007] driving a first ideal current source to generate a first ideal differential signal corresponding to the first digital signal;

[0008] A PWM compensation value is obtained, and a compensated output signal is determined according to the PWM compensation value and the first ideal differential signal and outputted.

[0009] The present invention also provides a chip, comprising a signal conversion circuit, a data processing circuit, a first ideal current source, a compensation circuit and an output circuit; the data processing circuit is electrically connected between the output end of the signal conversion circuit and the input end of the first ideal current source; the output end of the first ideal current source and the compensation circuit are both electrically connected to the output circuit;

[0010] When the chip is in communication mode, the signal conversion circuit converts the received differential signal to be compensated into a first digital signal and outputs it to the data processing circuit. The data processing circuit performs data processing according to the received first digital signal and outputs it to the first ideal current source. The first ideal current source generates a first ideal differential signal corresponding to the first digital signal and outputs it. After the compensation circuit determines the compensation signal according to the PWM compensation value, the output circuit determines the compensated output signal according to the compensation signal and the first ideal differential signal and outputs it.

[0011] The present invention also provides a communication system, comprising at least two chips connected via daisy chain communication, wherein the chips are the above chips.

[0012] The present invention also provides a vehicle, comprising the above chip.

[0013] The present invention provides a signal distortion compensation method, a chip, a communication system and a vehicle, wherein the signal distortion compensation method comprises: when the chip is in a communication mode, if a differential signal to be compensated is received, the differential signal to be compensated is converted into a first digital signal; data processing is performed according to the first digital signal; a first ideal current source is driven to generate a first ideal differential signal corresponding to the first digital signal; a PWM compensation value is obtained, and a compensated output signal is determined according to the PWM compensation value and the first ideal differential signal and outputted.

[0014] In the present invention, when the chip is in communication mode and receives a differential signal to be compensated, if the differential signal to be compensated generates signal distortion due to environmental loss or transmission interference before entering the chip, a first ideal differential signal corresponding to the differential signal to be compensated (i.e., the first digital signal) can be directly generated by a first ideal current source, so that the differential signal to be compensated can be compensated to a standard rectangular differential signal (i.e., the first ideal differential signal) by the first ideal current source, that is, the threshold distortion and slope distortion of the differential signal to be compensated are compensated, so as to achieve compensation for the signal distortion caused by environmental loss or transmission interference before the differential signal to be compensated enters the chip; and, after obtaining the first ideal differential signal, the first ideal differential signal can be further compensated according to the PWM compensation value, and the compensated output signal is output to the next chip, so as to compensate for the signal distortion caused by environmental loss or transmission interference in the transmission line of the differential signal to be compensated from the chip to the next chip, thereby avoiding signal distortion of the differential signal entering the next chip, and making the signal transmission process stable and reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0016] Figure 1 is a flow chart of a signal distortion compensation method in one embodiment of the present invention;

[0017] Figure 2 is a flow chart of a signal distortion compensation method according to another embodiment of the present invention;

[0018] Figure 3 is a structural block diagram of a chip in one embodiment of the present invention;

[0019] Figure 4 is a schematic diagram of a chip in a communication mode according to an embodiment of the present invention;

[0020] Figure 5 is a communication schematic diagram of a chip in one embodiment of the present invention;

[0021] Figure 6 is a schematic diagram of a chip in a calibration mode according to an embodiment of the present invention;

[0022] Figure 7 Schematic diagram of a chip in one embodiment of the present invention. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] In one embodiment, if Figure 1 , Figure 4 and Figure 5 As shown, the present invention provides a signal distortion compensation method, comprising the following steps:

[0025] S10, when the chip is in communication mode, if a differential signal to be compensated is received, the differential signal to be compensated is converted into a first digital signal; in the present invention, it is assumed that the communication system includes multiple chips, and the multiple chips are connected by differential signal communication (for example, by daisy chain communication, the daisy chain adopts a differential signal transmission method, and this communication method can effectively reduce the interference of common mode signals), and the chips in the communication system can be controlled in at least two different modes, such as communication mode and calibration mode; wherein, in the communication mode, different chips exchange data through differential signals, and the signal distortion compensation method of the present invention can be used to compensate for the distorted differential signal; and in the calibration mode, a fixed differential signal to be calibrated for calibration can be used to train to obtain a PWM (Pulse-width modulation) compensation value, and then in the communication mode, the PWM compensation value is used to compensate for the distorted differential signal. The chip in the present invention can be any chip connected by differential signal communication in the above-mentioned communication system.

[0026] In one embodiment, the chip is a BMS chip in a battery management system; the receiving of the differential signal to be compensated includes: receiving the differential signal to be compensated sent by the bridge chip adjacent to the chip or the adjacent previous BMS chip in the battery management system. Specifically, when the communication system is a battery management system (BMS), if the battery management system needs to send a command, it is necessary to first transmit the standard four-wire SPI (Serial Peripheral Interface, i.e., SPI communication protocol) communication signal from the computer or MCU (microcontroller unit, Micro controller Unit) of the battery management system to the communication interface of the bridge chip or BMS chip for reception, and convert the communication signal into a differential signal to be compensated in the bridge chip or BMS chip and send it to the next BMS chip. In this embodiment, the chip can be one of the multiple BMS chips connected by daisy chain communication in the battery management system, that is, the chip used to execute the signal distortion compensation method in the present invention is the BMS chip in the battery management system, which can receive the differential signal to be compensated and compensate the distorted differential signal to be compensated by the signal distortion compensation method of the present invention. It is understandable that when a differential signal from a BMS chip in a battery management system (the chip used to perform the signal distortion compensation method in the present invention may be the BMS chip in the battery management system) is sent back to a computer or MCU, the differential signal is received by a bridge chip or other BMS chip on a communication interface close to the BMS chip and signal conversion is performed, and then the converted standard four-wire SPI signal is sent to the computer or MCU. Different BMS chips in a battery management system transmit signals via differential signals. Specifically, a differential signal is sent from a first BMS chip to a communication interface of a second BMS chip, and then the differential signal is converted, identified, and processed by the second BMS chip, and then reconverted into a differential signal and sent to a third BMS chip. Therefore, in the present invention, if the second BMS chip is the chip used to perform the signal distortion compensation method, the first BMS chip is the previous BMS chip of the chip, and the third BMS chip is the next BMS chip of the chip. In summary, the chip used to execute the signal distortion compensation method in this embodiment can be one of the BMS chips in the battery management system connected through differential signal communication. The chip can receive the differential signal to be compensated and compensate the distorted differential signal to be compensated through the signal distortion compensation method of the present invention.

[0027] In step S10, the differential signal to be compensated is first received. Taking the battery management system as an example, the differential signal to be compensated may be a differential signal sent by a bridge chip or a BMS chip adjacent to the chip (for example, the chip is the BMS chip in the battery management system). When the differential signal to be compensated is received through the hardware communication interface of the chip, the differential signal to be compensated has been distorted due to environmental loss or transmission interference during the process of being sent from the previous chip (adjacent chip) to the chip. At this time, the differential signal to be compensated must first be identified as a first digital signal 0 / 1 by the signal conversion circuit 100 of the chip, and then the next step S20 is entered for further processing.

[0028] In one embodiment, specifically, the differential signal to be compensated corresponds to a preset recognition threshold, and the recognition threshold is set according to the demand. The differential signal to be compensated is identified as a digital signal 0 / 1 as follows: the differential signal to be compensated has three states: a half-negative pulse reaches the recognition threshold, a half-positive pulse reaches the recognition threshold, and a half-negative pulse and a half-positive pulse do not reach the recognition threshold. The responses corresponding to these three states are: -1, 1, and 0. When a half-negative pulse that does not reach the recognition threshold and a half-positive pulse that does not reach the recognition threshold are identified, they are converted into a digital signal 0. When a half-positive pulse that reaches the recognition threshold and a half-negative pulse that reaches the recognition threshold are identified, they are converted into a digital signal 1. It can be understood that the amplitude of the first ideal differential signal is set to 1.2 times the recognition threshold in the following text, which can improve the accuracy of the state response corresponding to the half-negative pulse and the half-positive pulse.

[0029] S20, data processing is performed according to the first digital signal; that is, in this step, the data processing circuit 200 of the chip performs data processing and data updating operations on the data and commands corresponding to the first digital signal (i.e., the differential signal to be compensated); specifically, data processing may include but is not limited to: writing registers, reading registers, operating instructions, etc., writing registers (usually referring to writing configuration registers, etc.) refers to writing the information corresponding to the first digital signal into the corresponding register, and the information corresponding to the first digital signal usually follows the instruction corresponding to the differential signal to be compensated; and reading registers refers to the chip outputting the information corresponding to the above-mentioned first digital signal; and the operating instruction may refer to performing ADC (Analog-to-Digital Converter, analog / digital converter) conversion operations, etc., and data updating mainly refers to that after the register reading instruction, each chip will output the corresponding information at the corresponding timing, and this timing depends on the communication protocol of the chip. The output information includes but is not limited to battery voltage registers, GPIO (General-purpose input / output) registers, status registers, etc.

[0030] S30, driving the first ideal current source 300 to generate a first ideal differential signal corresponding to the first digital signal; that is, after data processing is performed according to the first digital signal, the first ideal current source 300 can be driven by the first digital signal to generate a standard rectangular differential signal (that is, the first ideal differential signal) to compensate for the signal distortion (including compensation for the slope distortion and threshold distortion of the differential signal to be compensated) caused by environmental loss or transmission interference before the differential signal to be compensated enters the chip. In the present invention, the first ideal current source 300 is an ideal current source, which can supply electric power to the external circuit with a current of constant size and waveform without changing with changes in the load (or external circuit), which will not be repeated here. It is understandable that the first ideal current source 300 can select a current source with a small internal resistance of the power supply, or an ideal current source with a power supply internal resistance less than 1% of the load resistance, so as to facilitate the output of an ideal differential signal; it is understandable that the above-mentioned first ideal differential signal refers to a signal rising or falling slope (the slope of the first ideal differential signal) that is infinite, and the slope is close to 0 after the amplitude reaches 1.2 times the recognition threshold (that is, the first ideal differential signal is a standard rectangular differential signal).

[0031] S40, obtaining a PWM compensation value, determining a compensated output signal according to the PWM compensation value and the first ideal differential signal, and outputting the compensated output signal. In this embodiment, the PWM compensation value can also be used to compensate for a distorted differential signal, and the PWM compensation value can be obtained by training with a fixed differential signal to be calibrated when the chip is in a calibration mode. When the PWM compensation value is not trained in the calibration mode, the PWM compensation value is 0, and if it is trained, the PWM compensation value is not 0.

[0032] In one embodiment, the chip is a BMS chip in a battery management system; the determining and outputting the compensated output signal according to the PWM compensation value and the first ideal differential signal includes: determining the compensated output signal according to the PWM compensation value and the first ideal differential signal, and outputting the compensated output signal to the next BMS chip adjacent to the chip in the battery management system. It can be understood that when the communication system is a battery management system (BMS), since the chip is a BMS chip in a battery management system, and different BMS chips in the battery management system transmit signals through differential signals, specifically, the previous BMS chip sends the differential signal to be compensated to the chip for executing the signal distortion compensation method, and the chip converts the differential signal to be compensated into a first digital signal, and then drives the first ideal current source 300 to generate a first ideal differential signal corresponding to the first digital signal after data processing according to the first digital signal, and finally determines the compensated output signal according to the PWM compensation value and the first ideal differential signal, and then sends the output signal to the next BMS chip.

[0033] In one embodiment, the step S40, i.e., determining and outputting the compensated output signal according to the PWM compensation value and the first ideal differential signal, includes: when the PWM compensation value is determined to be 0, outputting the first ideal differential signal as the compensated output signal. That is, when the PWM compensation value is not trained in the calibration mode, the initial value of the PWM compensation value is 0, and at this time, the compensation signal generated corresponding to the PWM compensation value is also 0, so even if the first ideal differential signal is compensated by the PWM compensation value, the compensation effect corresponding to the compensation signal is also 0, so the first ideal differential signal after the slope distortion and threshold distortion compensation can be directly output as the compensated output signal to the next chip, and at this time, the first ideal differential signal output by the first ideal current source 300 itself can compensate the signal distortion caused by environmental loss or transmission interference before the differential signal to be compensated enters the chip to a certain extent.

[0034] In one embodiment, the step S40, i.e., determining and outputting the compensated output signal according to the PWM compensation value and the first ideal differential signal, includes: when it is determined that the PWM compensation value is not 0, pre-compensating the first ideal differential signal according to the PWM compensation value, and outputting the first ideal differential signal after pre-compensation as the output signal. It can be understood that if the PWM compensation value has been trained in the calibration mode, the PWM compensation value is no longer the initial value 0. At this time, after obtaining the first ideal differential signal, the first ideal differential signal can be further pre-compensated according to the PWM compensation value, and the pre-compensated output signal is output to the next chip, so that a part of the signal loss value (the part of the signal loss value is used to compensate for the signal distortion caused by the environmental loss or transmission interference in the transmission line from the chip to the next chip) is reserved in the output signal entering the next chip, so as to compensate for the signal distortion caused by the environmental loss or transmission interference in the transmission line from the chip to the next chip, thereby avoiding the differential signal entering the next chip from generating signal distortion, and making the signal transmission process stable and reliable. That is, in this embodiment, not only is a standard rectangular differential signal generated by the first ideal current source 300 to compensate for the signal distortion caused by environmental loss or transmission interference before the differential signal to be compensated enters the chip (including compensation for the slope distortion and threshold distortion of the differential signal to be compensated), but the first ideal differential signal is further pre-compensated by the PWM compensation value, thereby pre-compensating the signal distortion caused by environmental loss or transmission interference in the transmission line of the differential signal to be compensated from the chip to the next chip, thereby further improving the compensation effect.

[0035] Furthermore, the pre-compensation of the first ideal differential signal according to the PWM compensation value, and outputting the pre-compensated first ideal differential signal as an output signal, includes: driving the second ideal current source 401 to generate a compensation signal corresponding to the PWM compensation value, and pre-compensating the first ideal differential signal by the compensation signal, and then outputting the pre-compensated first ideal differential signal as an output signal. In this embodiment, the second ideal current source 401 is an ideal current source, which can supply electric power to the external circuit with a current of constant size and waveform without changing with changes in the load (or external circuit), which will not be described in detail here. Figure 4As shown, at the moment of receiving the differential signal to be compensated, it is considered that the chip is in a non-idle moment. At this time, if the PWM compensation value is not 0, the second ideal current source 401 is driven by the PWM compensation value to generate a corresponding compensation signal, and the compensation signal generated by the PWM compensation value is also not 0; at this time, the compensation signal is superimposed on the first ideal differential signal output by the first ideal current source 300 to obtain a compensated output signal, and the amplitude of the output signal is increased compared to the first ideal differential signal to compensate for the signal distortion caused by environmental loss or transmission interference in the transmission line from the chip to the next chip, so that when it arrives at the next chip, it still has an amplitude and phase sufficient to be identified by the recognition threshold.

[0036] Further, the driving second ideal current source 401 generates a compensation signal corresponding to the PWM compensation value, and pre-compensates the first ideal differential signal by using the compensation signal, including:

[0037] The second ideal current source 401 is driven by the PWM compensation value to generate a corresponding compensation signal, and the compensation signal is equal to the product of the PWM compensation value, the differential signal response value and the second ideal current source 401; the differential signal response value refers to the signal response value corresponding to the pulse state of the differential signal to be compensated at the moment when the differential signal to be compensated is received; that is, at the moment when the differential signal to be compensated is received, it is considered that the chip is in a non-idle moment. If the PWM compensation value is not 0, the second ideal current source 401 is driven by the PWM compensation value to generate a corresponding compensation signal, and the compensation signal is equal to the product of the PWM compensation value, the differential signal response value and the second ideal current source 401; and since at the moment when the differential signal to be compensated is received, the differential signal to be compensated is in a pulse state in which a half-positive pulse or a half-negative pulse reaches a recognition threshold, at this time, the differential signal response value corresponding to the pulse state is 1 or -1, that is, the differential signal response value corresponding to the differential signal to be compensated is not 0, and therefore, the compensation signal generated by the PWM compensation value is also not 0.

[0038] The sum of the compensation signal and the first ideal differential signal is output as the output signal after pre-compensation. That is, the compensation signal is superimposed on the first ideal differential signal output by the first ideal current source 300 to obtain the compensated output signal, that is, the compensated output signal is the sum of the first ideal differential signal (current) output by the first ideal current source 300 and the compensation signal (current) output by the second ideal current source 401, and the amplitude of the output signal is increased compared with the first ideal differential signal to compensate for the signal distortion caused by environmental loss or transmission interference in the transmission line from the chip to the next chip, so that when it reaches the next chip, it still has an amplitude and phase sufficient to be identified by the identification threshold.

[0039] It can be understood that in the above embodiment, at idle times (idle times refer to times when no differential signal to be compensated is received, or times between two differential signals to be compensated), even if the PWM compensation value is not 0, the second ideal current source 401 will not be driven to generate a compensation signal; and when the PWM compensation value is 0, the second ideal current source 401 will not be driven to generate a compensation signal.

[0040] In the above embodiment of the present invention, when the chip is in the communication mode and receives the differential signal to be compensated, if the differential signal to be compensated generates signal distortion due to environmental loss or transmission interference before entering the chip, the first ideal current source 300 can directly generate a first ideal differential signal corresponding to the differential signal to be compensated (that is, the first digital signal), so that the differential signal to be compensated can be compensated to a standard rectangular differential signal (that is, the first ideal differential signal) through the first ideal current source 300, that is, the threshold distortion and slope distortion of the differential signal to be compensated are compensated, so as to achieve compensation for the signal distortion caused by environmental loss or transmission interference before the differential signal to be compensated enters the chip; and after obtaining the first ideal differential signal, the first ideal differential signal can be further compensated according to the PWM compensation value, and the compensated output signal is output to the next chip, so as to compensate for the signal distortion caused by environmental loss or transmission interference during the transmission of the differential signal to be compensated from the chip to the next chip, thereby avoiding signal distortion and making the signal transmission process stable and reliable.

[0041] In one embodiment, if Figure 2 , Figure 5 and Figure 6 As shown, the signal distortion compensation method also includes:

[0042] S50, when the chip is in the calibration mode, if a first differential signal to be calibrated is received, the first differential signal to be calibrated is converted into a second digital signal; that is, in the calibration mode, a PWM compensation value can be obtained by training with a fixed differential signal to be calibrated for calibration, and then in the communication mode, the PWM compensation value is used to compensate for the distorted differential signal. When the PWM compensation value is not trained in the calibration mode, the PWM compensation value is 0, and if it is trained, the PWM compensation value is not 0.

[0043] Among them, in the present invention, the time difference between the first moment when the differential signal to be calibrated is input into the chip and the second moment when the chip outputs the second ideal differential signal in the next step S60 needs to be equal to one or two times the time difference between two consecutive differential signals to be calibrated, etc. In this way, by setting multiple consecutively input differential signals to be calibrated to be fixed as: 00000000, 11111111, 10101010, etc., the differential signal to be calibrated input at the first moment (that is, the first differential signal to be calibrated in this embodiment) is the same as the differential signal to be calibrated input at the second moment (that is, the second differential signal to be calibrated), thereby realizing the determination and training of the PWM compensation value.

[0044] Specifically, when the time difference between the first moment and the second moment is equal to the time difference between two consecutive input differential signals to be calibrated, at this time, the multiple consecutive input differential signals to be calibrated can be fixed to: 00000000 (N consecutive 0s), 11111111 (N consecutive 1s), so that the first differential signal to be calibrated input at the first moment can be the same as the second differential signal to be calibrated input at the second moment; and when the time difference between the first moment and the second moment is equal to twice the time difference between two consecutive input differential signals to be calibrated, the multiple consecutive input differential signals to be calibrated can be fixed to: 00000000 (N consecutive 0s), 11111111 (N consecutive 1s), 10101010 (alternating input of 1 and 0), 01010101 (alternating input of 0 and 1), at this time, the first differential signal to be calibrated input at the first moment can be the same as the second differential signal to be calibrated input at the second moment.

[0045] In this step, the first differential signal to be calibrated (and the subsequent second differential signal to be calibrated) is also a differential signal sent by a chip adjacent to the chip (for example, the chip is the BMS chip in the above-mentioned battery management system) (for example, the bridge chip or the BMS chip in the above-mentioned battery management system). Therefore, when the first differential signal to be calibrated is received through the hardware communication interface of the chip, the first differential signal to be calibrated (and the subsequent second differential signal to be calibrated) has been distorted due to environmental loss or transmission interference in the process of being sent from the previous chip (adjacent chip) to the chip. At this time, the first differential signal to be calibrated must first be identified as the second digital signal 0 / 1 by the signal conversion circuit 100 of the chip, and then enter the next step S60 for further processing.

[0046] S60, data processing is performed according to the second digital signal, and the first ideal current source 300 is driven to generate a second ideal differential signal corresponding to the second digital signal; that is, in this step, the data processing circuit 200 of the chip performs data processing and data updating operations on the data and commands corresponding to the second digital signal (that is, the differential signal to be calibrated); specifically, data processing may include but is not limited to: writing registers, reading registers, operating instructions, etc., writing registers (usually referring to writing configuration registers, etc.) refers to writing information corresponding to the second digital signal into corresponding registers, and the information corresponding to the second digital signal usually follows the instructions corresponding to the differential signal to be calibrated; reading registers refers to the chip outputting the information corresponding to the above-mentioned second digital signal; and the operating instructions may refer to performing ADC conversion operations, etc.; and data updating mainly refers to that after the read register instruction, each chip will output the corresponding information at the corresponding timing, and this timing depends on the communication protocol of the chip. The output information includes but is not limited to battery voltage registers, GPIO registers, status registers, etc.

[0047] After data processing is performed according to the second digital signal, the first ideal current source 300 can be driven by the second digital signal to generate a standard rectangular differential signal (that is, a second ideal differential signal) to compensate for the signal distortion (including compensation for the slope distortion and threshold distortion of the differential signal to be calibrated) caused by environmental loss or transmission interference before the first differential signal to be calibrated enters the chip; it can be understood that the above-mentioned second ideal differential signal refers to a signal rising or falling slope (the slope of the second ideal differential signal) that is infinite, and the slope is close to 0 after the amplitude reaches 1.2 times the recognition threshold (that is, the second ideal differential signal is a standard rectangular differential signal).

[0048] S70, determining the PWM compensation value according to the second ideal differential signal and the second differential signal to be calibrated received by the chip; the second differential signal to be calibrated is the same as the first differential signal to be calibrated. That is, as can be seen from the above, the first differential signal to be calibrated input at the first moment is the same as the second differential signal to be calibrated input at the second moment, and the second ideal differential signal refers to a standard rectangular differential signal after the slope distortion and threshold distortion of the first differential signal to be calibrated are compensated, therefore, the second ideal differential signal actually has no distortion, but has completed the compensation of the signal distortion caused by environmental loss or transmission interference before the differential signal to be calibrated enters the chip; and the second ideal differential signal has generated signal distortion due to environmental loss or transmission interference in the process of being sent from the previous chip (adjacent chip) to the chip, and has not yet been compensated for distortion at the second moment of its input, therefore, there is still signal distortion caused by environmental loss or transmission interference before entering the chip, therefore, the PWM compensation value can be determined according to the difference between the second ideal differential signal and the second differential signal to be calibrated.

[0049] In one embodiment, in step S70, determining the PWM compensation value according to the second ideal differential signal and the second differential signal to be calibrated received by the chip includes: inputting the second ideal differential signal and the second differential signal to be calibrated into the comparator 404 of the chip, and allowing the comparator 404 to determine the PWM compensation value according to the difference between the second ideal differential signal and the second differential signal to be calibrated. That is, in this embodiment, the second ideal differential signal generated by the first ideal current source 300 at the second moment and the second differential signal to be calibrated sent from the adjacent chip at the second moment can be input into the comparator 404 of the chip, and the comparator 404 performs comparison and calculation, that is, determining the PWM compensation value according to the difference between the second ideal differential signal and the second differential signal to be calibrated.

[0050] It is understandable that in some embodiments, the PWM compensation value can be determined by inputting only two consecutive differential signals to be calibrated (i.e., the first differential signal to be calibrated and the second differential signal to be calibrated), that is, the difference between the second ideal differential signal and the second differential signal to be calibrated is the PWM compensation value.

[0051] In some other embodiments, the step of causing the comparator 404 to determine the PWM compensation value according to the difference between the second ideal differential signal and the second differential signal to be calibrated includes:

[0052] The comparator 404 is instructed to determine the difference between the second ideal differential signal and the second differential signal to be calibrated as the initial compensation value; that is, in this embodiment, in the calibration mode, multiple continuous differential signals to be calibrated (such as the first differential signal to be calibrated, the second differential signal to be calibrated, and the continuous calibration differential signal continuously input at a fixed time in the following text) can be continuously input. At this time, the difference between the second ideal differential signal and the second differential signal to be calibrated is first determined as the initial compensation value, which is not necessarily the final PWM compensation value, but needs to be further confirmed according to the continuous calibration differential signal that continues to be input subsequently.

[0053] When the chip continues to receive the continuous calibration differential signal, the received continuous calibration differential signal is input into the comparator 404 of the chip, so that the comparator 404 determines the difference between the second ideal differential signal and the continuous calibration differential signal as the comparison compensation value; wherein the continuous calibration differential signal refers to a differential signal to be calibrated that is received at a fixed time after the second differential signal to be calibrated and is the same as the first differential signal to be calibrated, and the first time difference between the second differential signal to be calibrated and the first differential signal to be calibrated is equal to the second time difference between the first received continuous calibration differential signal and the second differential signal to be calibrated; and the third time difference between two adjacent continuous differential signals to be calibrated is also equal to the first time difference.

[0054] That is, in this embodiment, multiple differential signals to be calibrated are continuously input in the calibration mode, and the multiple differential signals to be calibrated include a first differential signal to be calibrated, a second differential signal to be calibrated, and one or more continuous calibration differential signals, and the first differential signal to be calibrated, the second differential signal to be calibrated, and the continuous calibration differential signal are all the same, and the time difference between each adjacent signal (that is, the first time difference, the second time difference, and the third time difference) are all equal. In this way, after obtaining the initial compensation value, it is necessary to continuously and regularly input the continuous calibration differential signal, and at this time, a corresponding comparison compensation value can be obtained through the comparator 404, and a comparison compensation value is the difference between the second ideal differential signal and a continuous calibration differential signal.

[0055] When the continuous calibration differential signal is no longer received, the last comparison compensation value or the average compensation value is determined as the PWM compensation value; the average compensation value refers to the average value between the initial compensation value and all the comparison compensation values. That is, after all the continuous calibration differential signals are input, the average compensation value between all the comparison compensation values ​​obtained above is used as the final PWM compensation value obtained when the calibration mode is turned on. Of course, in some embodiments, the last comparison compensation value obtained can also be used as the final PWM compensation value obtained when the calibration mode is turned on.

[0056] In one embodiment, the signal distortion compensation method further includes:

[0057] A switching instruction is received, and a target mode and a mode to be switched are determined, wherein the target mode refers to the calibration mode or the communication mode currently in which the chip is located; and the mode to be switched refers to another mode of the calibration mode and the communication mode other than the target mode. That is, when the target mode is the current calibration mode, the mode to be switched is the communication mode; when the target mode is the current communication mode, the mode to be switched is the calibration mode.

[0058] The target mode is switched to the mode to be switched. Understandably, in this embodiment, the calibration mode and communication mode of the chip can be switched at any time according to demand. Specifically, when a switching instruction is received, the current calibration mode (target mode) of the chip can be switched to the communication mode (to be switched mode), or the current communication mode (target mode) of the chip can be switched to the calibration mode (to be switched mode). After each calibration mode is turned on, regardless of whether the previous PWM compensation value is 0, the previous PWM compensation value will be iteratively updated.

[0059] It should be understood that the order of execution of the steps in the above embodiment does not necessarily mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present invention.

[0060] In one embodiment, if Figure 3 As shown, a chip is provided, which corresponds to the signal distortion compensation method in the above embodiment. The chip includes a signal conversion circuit 100, a data processing circuit 200, a first ideal current source 300, a compensation circuit 400 and an output circuit 500; the data processing circuit 200 is electrically connected between the output end of the signal conversion circuit 100 and the input end of the first ideal current source 300; the output end of the first ideal current source 300 and the compensation circuit 400 are both electrically connected to the output circuit 500.

[0061] When the chip is in communication mode, the signal conversion circuit 100 converts the received differential signal to be compensated into a first digital signal and outputs it to the data processing circuit 200. The data processing circuit 200 performs data processing according to the received first digital signal and outputs it to the first ideal current source 300. The first ideal current source 300 generates a first ideal differential signal corresponding to the first digital signal and outputs it. After the compensation circuit 400 determines the compensation signal according to the PWM compensation value, the output circuit 500 determines the compensated output signal according to the compensation signal and the first ideal differential signal and outputs it. Among them, the PWM compensation value can be determined by the compensation circuit 400 in the calibration mode according to the above-mentioned signal distortion compensation method. When the PWM compensation value is not determined by the above-mentioned signal distortion compensation method, the PWM compensation value is 0. In this embodiment, when the chip is in communication mode, the output end of the compensation circuit 400 is electrically connected to the output circuit 500. At this time, the compensation signal determined by the compensation circuit 400 according to the PWM compensation value can be sent to the output circuit 500 to compensate the first ideal differential signal, thereby obtaining the compensated output signal and outputting it.

[0062] In the above embodiment of the present invention, when the chip is in the communication mode and receives the differential signal to be compensated, if the differential signal to be compensated generates signal distortion due to environmental loss or transmission interference before entering the chip, the first ideal current source 300 can directly generate a first ideal differential signal corresponding to the differential signal to be compensated (that is, the first digital signal), so that the differential signal to be compensated can be compensated to a standard rectangular differential signal (that is, the first ideal differential signal) through the first ideal current source 300, that is, the threshold distortion and slope distortion of the differential signal to be compensated are compensated, so as to achieve compensation for the signal distortion caused by environmental loss or transmission interference before the differential signal to be compensated enters the chip; and after obtaining the first ideal differential signal, the first ideal differential signal can be further compensated according to the PWM compensation value, and the compensated output signal is output to the next chip, so as to compensate for the signal distortion caused by environmental loss or transmission interference during the transmission of the differential signal to be compensated from the chip to the next chip, thereby avoiding signal distortion and making the signal transmission process stable and reliable.

[0063] In one embodiment, if Figure 4As shown, the compensation circuit 400 includes a first switch 402, a second switch 403 and a second ideal current source 401, the input end of the second ideal current source 401 is connected to the output end of the data processing circuit 200 through the first switch 402, and the output end of the second ideal current source 401 is connected to the output circuit 500 through the second switch 403; when the compensation circuit 400 determines that the PWM compensation value is not 0, the first switch 402 and the second switch 403 are controlled to be turned on, so as to generate a compensation signal corresponding to the PWM compensation value through the second ideal current source 401, and the output circuit 500 pre-compensates the first ideal differential signal sent by the first ideal current source 300 according to the compensation signal, and outputs the first ideal differential signal after pre-compensation as an output signal.

[0064] That is, in this embodiment, the first switch 402 and the second switch 403 can control whether the second ideal current source 401 is turned on. It can be understood that in one embodiment, since the compensation signal generated by the second ideal current source 401 is equal to the product of the PWM compensation value, the differential signal response value and the second ideal current source 401; and since at the moment of receiving the differential signal to be compensated, the differential signal to be compensated is in a pulse state where a half-positive pulse or a half-negative pulse reaches the recognition threshold, at this time, the differential signal response value corresponding to the pulse state is 1 or -1, that is, the differential signal response value corresponding to the differential signal to be compensated is not 0, and therefore, the compensation signal generated by the PWM compensation value is also not 0. Therefore, since the compensation signal is not 0, when the PWM compensation value is not 0, it is necessary to control the first switch 402 and the second switch 403 to be turned on, and at this time, the second current source starts to work, and the second ideal current source 401 is driven by the PWM compensation value to generate a corresponding compensation signal and send it to the output circuit 500, and the compensation signal is equal to the product of the PWM compensation value, the differential signal response value and the second ideal current source 401. After the output circuit 500 receives the compensation signal and the first ideal differential signal output by the first ideal current source 300, the compensation signal is superimposed on the first ideal differential signal output by the first ideal current source 300 to obtain a compensated output signal. Specifically, the compensated output signal output by the output circuit 500 is the sum of the first ideal differential signal (current) output by the first ideal current source 300 and the compensation signal (current) output by the second ideal current source 401. In this way, the amplitude of the output signal is increased compared to the first ideal differential signal to compensate for the signal distortion caused by environmental loss or transmission interference in the transmission line from the chip to the next chip. At this time, the output signal output by the output circuit 500 still has an amplitude and phase sufficient to be identified by the identification threshold when it arrives at the next chip.

[0065] In a further embodiment, when the compensation circuit 400 determines that the PWM compensation value is not 0, the first switch 402 and the second switch 403 are controlled to be turned on, so as to drive the second ideal current source 401 to generate a corresponding compensation signal through the PWM compensation value, and output the sum of the compensation signal and the first ideal differential signal as the output signal after pre-compensation; wherein the compensation signal is equal to the product of the PWM compensation value, the differential signal response value and the second ideal current source; and the differential signal response value refers to the signal response value corresponding to the pulse state of the differential signal to be compensated at the moment when the differential signal to be compensated is received. That is, at the moment of receiving the differential signal to be compensated, it is considered that the chip is in a non-idle moment. If the PWM compensation value is not 0, the second ideal current source 401 is driven by the PWM compensation value to generate a corresponding compensation signal, and the compensation signal is equal to the product of the PWM compensation value, the differential signal response value and the second ideal current source 401. However, since at the moment of receiving the differential signal to be compensated, the differential signal to be compensated is in a pulse state in which a half-positive pulse or a half-negative pulse reaches the recognition threshold, at this time, the differential signal response value corresponding to the pulse state is 1 or -1, that is, the differential signal response value corresponding to the differential signal to be compensated is not 0, and therefore, the compensation signal generated by the PWM compensation value is also not 0. At this time, in this embodiment, the compensation signal is superimposed on the first ideal differential signal output by the first ideal current source 300 to obtain a compensated output signal, that is, the compensated output signal is the sum of the first ideal differential signal (current) output by the first ideal current source 300 and the compensation signal (current) output by the second ideal current source 401. The amplitude of the output signal is increased compared to the first ideal differential signal to compensate for the signal distortion caused by environmental loss or transmission interference in the transmission line from the chip to the next chip, so that when it arrives at the next chip, it still has an amplitude and phase sufficient to be identified by the recognition threshold.

[0066] In one embodiment, if Figure 4As shown, the compensation circuit 400 includes a first switch 402, a second switch 403 and a second ideal current source 401, the input end of the second ideal current source 401 is connected to the output end of the data processing circuit 200 through the first switch 402, and the output end of the second ideal current source 401 is connected to the output circuit 500 through the second switch 403; when the compensation circuit 400 determines that the PWM compensation value is 0, the first switch 402 and the second switch 403 are controlled to be disconnected, and the output circuit 500 outputs the first ideal differential signal sent by the first ideal current source 300 as the compensated output signal. That is, in this embodiment, the first switch 402 and the second switch 403 can control whether the second ideal current source 401 is turned on or not. It can be understood that in one embodiment, since the compensation signal generated by the second ideal current source 401 is equal to the product of the PWM compensation value, the differential signal response value and the second ideal current source 401; and when the PWM compensation value is 0, the compensation signal generated corresponding to the PWM compensation value is also 0, so even if the PWM compensation value is used to compensate the first ideal differential signal, the compensation effect corresponding to the compensation signal is also 0. At this time, the first switch 402 and the second switch 403 are controlled to be disconnected to control the second ideal current source 401 not to work, and then, the output circuit 500 will directly output the first ideal differential signal after the slope distortion and the threshold distortion compensation as the compensated output signal to the next chip. At this time, the first ideal differential signal itself as the output signal can compensate for the signal distortion caused by environmental loss or transmission interference before the differential signal to be compensated enters the chip.

[0067] In one embodiment, if Figure 5 As shown, the compensation circuit 400 includes a second switch 403, and the input end of the compensation circuit 400 is electrically connected to the output end of the first ideal current source 300; the output end of the compensation circuit 400 is connected to the output circuit 500 through the second switch 403; when the chip is in the calibration mode, the second switch 403 is controlled to be disconnected, the signal conversion circuit 100 converts the received first differential signal to be calibrated into a second digital signal and outputs it to the data processing circuit 200, the data processing circuit 200 performs data processing according to the received second digital signal and outputs it to the first ideal current source 300, the first ideal current source 300 generates a second ideal differential signal corresponding to the second digital signal and outputs it to the compensation circuit 400; the compensation circuit 400 determines the PWM compensation value according to the second ideal differential signal and the second differential signal to be calibrated received by the chip; the second differential signal to be calibrated is the same as the first differential signal to be calibrated.

[0068] In this embodiment, the second switch 403 can control the on-off between the output end of the compensation circuit 400 and the output circuit 500, and further control whether the compensation circuit 400 generates a compensation signal according to the PWM compensation value and outputs it to the output circuit 500 to compensate for the ideal differential signal output by the first ideal current source 300; understandably, when the chip is in the calibration mode, it is only necessary to determine the PWM compensation value through the compensation circuit 400, and the input is the signal to be calibrated (rather than the signal to be compensated that needs to be compensated). Therefore, at this time, it is not necessary for the compensation circuit 400 to generate a compensation signal according to the PWM compensation value and output it to the output circuit 500 to compensate for the ideal differential signal output by the first ideal current source 300. Therefore, it is necessary to control the second switch 403 to disconnect the connection between the output circuit 500 and the compensation circuit 400. Furthermore, at this time, the compensation circuit 400 only determines and maintains the PWM compensation value according to the second ideal differential signal sent by the first ideal current source 300 and the second differential signal to be calibrated received by the chip.

[0069] In one embodiment, if Figure 5 and Figure 6 As shown, the compensation circuit 400 includes a comparator 404, a first input terminal of the comparator 404 is connected to the output terminal of the first ideal current source 300; the output terminal of the comparator 404 is connected to the output circuit 500 through the second switch 403; further, as Figure 5 As shown, when the compensation circuit 400 further includes a second ideal current source 401, the second current source is connected between the output terminal of the comparator 404 and the input terminal of the second switch 403; and when the compensation circuit 400 further includes a first switch 402, one end of the first switch 402 away from the data processing circuit 200 is connected between the output terminal of the comparator 404 and the second ideal current source 401. When the second input terminal of the comparator 404 receives the second differential signal to be calibrated, the comparator 404 determines the PWM compensation value according to the difference between the second ideal differential signal input by the first ideal current source 300 and the received second differential signal to be calibrated.

[0070] In this embodiment, when the chip is in the calibration mode, only the compensation circuit 400 needs to determine the PWM compensation value, and the compensation circuit 400 does not need to generate a compensation signal according to the PWM compensation value and output it to the output circuit 500. Therefore, it is necessary to control the second switch 403 to disconnect the connection between the output end of the comparator 404 and the output circuit 500 (at this time, the first switch 402 can be disconnected synchronously with the second switch 403, and the actual working state of each circuit in the chip after disconnection is as follows: Figure 6Furthermore, at this time, the compensation circuit 400 only determines and maintains the PWM compensation value according to the second ideal differential signal sent by the first ideal current source 300 and the second differential signal to be calibrated received by the chip.

[0071] In one embodiment, if Figure 5 and Figure 6 As shown, the compensation circuit 400 includes a comparator 404 , a first input terminal of the comparator 404 is connected to the output terminal of the first ideal current source 300 ; and an output terminal of the comparator 404 is connected to the output circuit 500 via the second switch 403 . Further, when the second differential signal to be calibrated is received at the second input end of the comparator, the comparator 404 determines the difference between the second ideal differential signal input by the first ideal current source and the received second differential signal to be calibrated as the initial compensation value; thereafter, when the chip continues to receive continuous calibration differential signals, the comparator 404 determines the difference between the second ideal differential signal and the received continuous calibration differential signal as the comparison compensation value, and then when the continuous calibration differential signal is no longer received, the comparator 404 determines the last comparison compensation value or the average compensation value as the PWM compensation value; wherein the continuous calibration differential signal refers to a differential signal to be calibrated that is received at a fixed time after the second differential signal to be calibrated and is the same as the first differential signal to be calibrated, and the first time difference between the second differential signal to be calibrated and the first differential signal to be calibrated is equal to the second time difference between the first received continuous calibration differential signal and the second differential signal to be calibrated; the third time difference between two adjacent continuous differential signals to be calibrated is also equal to the first time difference; and the average compensation value refers to the average value between the initial compensation value and all the comparison compensation values. Specifically, multiple differential signals to be calibrated are continuously input in the calibration mode, and the multiple differential signals to be calibrated include a first differential signal to be calibrated, a second differential signal to be calibrated, and one or more continuous calibration differential signals, and the above-mentioned first differential signal to be calibrated, the second differential signal to be calibrated and the continuous calibration differential signal are all the same, and the time difference between each adjacent signal (that is, the first time difference, the second time difference, and the third time difference) are also all equal.

[0072] In this embodiment, in the calibration mode, multiple continuous differential signals to be calibrated (such as the above-mentioned first differential signal to be calibrated, the second differential signal to be calibrated, and the continuous calibration differential signal inputted continuously and regularly) can be continuously inputted. At this time, the difference between the second ideal differential signal and the second differential signal to be calibrated is first determined as the initial compensation value, and is not necessarily the final PWM compensation value. In this way, after obtaining the initial compensation value, it is necessary to continuously and regularly input the continuous calibration differential signal. At this time, a corresponding comparison compensation value can be obtained through the comparator 404, and a comparison compensation value is the difference between the second ideal differential signal and a continuous calibration differential signal; further, after inputting all the continuous calibration differential signals, the average compensation value between all the comparison compensation values ​​obtained above is used as the final PWM compensation value obtained when the calibration mode is started. Of course, in some embodiments, the last comparison compensation value obtained can also be used as the final PWM compensation value obtained when the calibration mode is started.

[0073] In one embodiment, the chip is a BMS chip in a battery management system; in the battery management system, after the chip receives the differential signal to be compensated sent by the adjacent bridge chip or the previous BMS chip, the chip converts the differential signal to be compensated into a first digital signal, and after performing data processing according to the first digital signal, drives the first ideal current source to generate a first ideal differential signal corresponding to the first digital signal, and after determining the compensated output signal according to the PWM compensation value and the first ideal differential signal, the compensated output signal is output to the next BMS chip adjacent to the chip in the battery management system. It can be understood that when the communication system is a battery management system (BMS), since the chip is a BMS chip in the battery management system, and different BMS chips in the battery management system transmit signals through differential signals, specifically, the previous BMS chip sends the differential signal to be compensated to the chip used to execute the signal distortion compensation method, and the chip converts the differential signal to be compensated into a first digital signal, and then drives the first ideal current source 300 to generate a first ideal differential signal corresponding to the first digital signal after data processing according to the first digital signal, and finally determines the compensated output signal according to the PWM compensation value and the first ideal differential signal, and then sends the output signal to the next BMS chip.

[0074] In one embodiment, in one embodiment, if Figure 4As shown, the compensation circuit 400 includes a first switch 402, a second switch 403, a comparator 404 and a second ideal current source 401, wherein the first input end of the comparator 404 is connected to the output end of the first ideal current source 300; the output end of the comparator 404 is connected to the second switch 403 through the second ideal current source 401, and one end of the second switch 403 away from the second ideal current source 401 is connected to the output circuit 500; the input end of the second ideal current source 401 is connected to the output end of the data processing circuit 200 through the first switch 402;

[0075] When receiving the switching instruction, if the target mode currently in which the chip is located is the calibration mode, the first switch 402 and the second switch 403 are controlled to be turned on to switch the calibration mode to the communication mode; if the target mode currently in which the chip is located is the communication mode, the first switch 402 and the second switch 403 are controlled to be turned off to switch the communication mode to the calibration mode. That is, in this embodiment, if the target mode is the calibration mode currently located, the communication mode is the mode to be switched to; if the target mode is the communication mode currently located, the calibration mode is the mode to be switched to. It can be understood that in this embodiment, the calibration mode and the communication mode of the chip can be switched at any time according to demand. Specifically, when receiving the switching instruction, the current calibration mode (target mode) of the chip can be switched to the communication mode (to be switched mode) or the current communication mode (target mode) of the chip can be switched to the calibration mode (to be switched mode) by turning on or off the first switch 402 and the second switch 403. Among them, after each calibration mode is turned on, no matter whether the previous PWM compensation value is 0 or not, the previous PWM compensation value will be iteratively updated.

[0076] For the specific definition of the chip, please refer to the detailed description of the signal distortion compensation method above, which will not be repeated here. Each module in the above chip can be implemented in whole or in part by software, hardware and their combination. Each module can be embedded in or independent of the processor in the chip in hardware form, or can be stored in the memory in the chip in software form, so that the processor can call and execute the operations corresponding to each module above. Further, if Figure 7As shown, the chip includes a processor, a memory, a network interface and a database connected through a system bus. Among them, the processor of the chip is used to provide computing and control capabilities. The memory of the chip includes a readable storage medium and an internal memory. The readable storage medium stores an operating system, computer-readable instructions and a database. The internal memory provides an environment for the operation of the operating system and computer-readable instructions in the readable storage medium. When the computer-readable instructions are executed by the processor, a signal distortion compensation method is implemented. The readable storage medium provided in this embodiment includes a non-volatile readable storage medium and a volatile readable storage medium. In one embodiment, a chip is provided, including a memory, a processor and a computer-readable instruction stored on the memory and executable on the processor, and the steps of the above-mentioned signal distortion compensation method are implemented when the processor executes the computer-readable instructions.

[0077] The present invention also provides a communication system, comprising at least two chips connected by daisy chain communication, wherein the chip is the above chip. Further, the communication system is a battery management system, and the chip is a BMS chip in the battery management system. For the specific definition of the communication system, please refer to the detailed description of the signal distortion compensation method and the chip above, which will not be repeated here.

[0078] In the communication system of the above embodiment of the present invention, when the chip in the communication system is in the communication mode and receives the differential signal to be compensated, if the differential signal to be compensated generates signal distortion due to environmental loss or transmission interference before entering the chip, the first ideal current source 300 can directly generate a first ideal differential signal corresponding to the differential signal to be compensated (that is, the first digital signal), so that the differential signal to be compensated can be compensated to a standard rectangular differential signal (that is, the first ideal differential signal) through the first ideal current source 300, that is, the threshold distortion and slope distortion of the differential signal to be compensated are compensated, so as to achieve compensation for the signal distortion caused by environmental loss or transmission interference before the differential signal to be compensated enters the chip; and after obtaining the first ideal differential signal, the first ideal differential signal can be further compensated according to the PWM compensation value, and the compensated output signal is output to the next chip, so as to compensate for the signal distortion caused by environmental loss or transmission interference during the transmission of the differential signal to be compensated from the chip to the next chip, thereby avoiding signal distortion and making the signal transmission process stable and reliable.

[0079] The present invention further provides a vehicle, comprising the above chip. The specific definition of the vehicle can be found in the above detailed description of the signal distortion compensation method and the chip, which will not be repeated here. In the vehicle of the above-mentioned embodiment of the present invention, when the chip of the vehicle is in the communication mode and receives the differential signal to be compensated, if the differential signal to be compensated generates signal distortion due to environmental loss or transmission interference before entering the chip, the first ideal current source 300 can directly generate a first ideal differential signal corresponding to the differential signal to be compensated (that is, the first digital signal), so that the differential signal to be compensated can be compensated to a standard rectangular differential signal (that is, the first ideal differential signal) through the first ideal current source 300, that is, the threshold distortion and slope distortion of the differential signal to be compensated are compensated, so as to achieve compensation for the signal distortion caused by environmental loss or transmission interference before the differential signal to be compensated enters the chip; and, after obtaining the first ideal differential signal, the first ideal differential signal can be further compensated according to the PWM compensation value, and the compensated output signal is output to the next chip, so as to compensate for the signal distortion caused by environmental loss or transmission interference during the transmission of the differential signal to be compensated from the chip to the next chip, thereby avoiding signal distortion and making the signal transmission process stable and reliable.

[0080] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through computer-readable instructions, and the computer-readable instructions can be stored in a non-volatile readable storage medium or a volatile readable storage medium. When the computer-readable instructions are executed, they can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided by the present invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), memory bus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0081] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units or modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional units or modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0082] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A signal distortion compensation method, characterized in that: include: When the chip is in the communication mode, if a differential signal to be compensated is received, the differential signal to be compensated is converted into a first digital signal; performing data processing according to the first digital signal; driving a first ideal current source to generate a first ideal differential signal corresponding to the first digital signal; A PWM compensation value is obtained, and a compensated output signal is determined according to the PWM compensation value and the first ideal differential signal and outputted.

2. The signal distortion compensation method according to claim 1, characterized in that: The step of determining and outputting a compensated output signal according to the PWM compensation value and the first ideal differential signal comprises: When it is determined that the PWM compensation value is not 0, pre-compensation is performed on the first ideal differential signal according to the PWM compensation value, and the first ideal differential signal after pre-compensation is output as an output signal.

3. The signal distortion compensation method according to claim 2, characterized in that: The pre-compensating the first ideal differential signal according to the PWM compensation value, and outputting the pre-compensated first ideal differential signal as an output signal, comprises: The second ideal current source is driven to generate a compensation signal corresponding to the PWM compensation value, and after pre-compensating the first ideal differential signal by using the compensation signal, the first ideal differential signal after pre-compensation is output as an output signal.

4. The signal distortion compensation method according to claim 3, characterized in that: The driving of the second ideal current source to generate a compensation signal corresponding to the PWM compensation value, and pre-compensating the first ideal differential signal by the compensation signal, and then outputting the pre-compensated first ideal differential signal as an output signal, comprising: The second ideal current source is driven by the PWM compensation value to generate a corresponding compensation signal, wherein the compensation signal is equal to the product of the PWM compensation value, the differential signal response value and the second ideal current source; the differential signal response value refers to a signal response value corresponding to a pulse state of the differential signal to be compensated at the moment when the differential signal to be compensated is received; The sum of the compensation signal and the first ideal differential signal is output as an output signal after pre-compensation.

5. The signal distortion compensation method according to claim 1, characterized in that: The step of determining and outputting a compensated output signal according to the PWM compensation value and the first ideal differential signal comprises: When the PWM compensation value is determined to be 0, the first ideal differential signal is output as a compensated output signal.

6. The signal distortion compensation method according to claim 1, characterized in that: The signal distortion compensation method further includes: When the chip is in a calibration mode, if a first differential signal to be calibrated is received, converting the first differential signal to be calibrated into a second digital signal; Performing data processing according to the second digital signal, and driving the first ideal current source to generate a second ideal differential signal corresponding to the second digital signal; A PWM compensation value is determined according to the second ideal differential signal and a second differential signal to be calibrated received by the chip; the second differential signal to be calibrated is the same as the first differential signal to be calibrated.

7. The signal distortion compensation method according to claim 6, characterized in that: The determining of the PWM compensation value according to the second ideal differential signal and the second differential signal to be calibrated received by the chip comprises: The second ideal differential signal and the second differential signal to be calibrated are input into the comparator of the chip, and the comparator is enabled to determine a PWM compensation value according to a difference between the second ideal differential signal and the second differential signal to be calibrated.

8. The signal distortion compensation method according to claim 7, characterized in that: The step of causing the comparator to determine a PWM compensation value according to a difference between the second ideal differential signal and the second differential signal to be calibrated comprises: Instructing the comparator to determine the difference between the second ideal differential signal and the second differential signal to be calibrated as an initial compensation value; When the chip continues to receive the continuous calibration differential signal, the received continuous calibration differential signal is input into the comparator of the chip, so that the comparator determines the difference between the second ideal differential signal and the continuous calibration differential signal as the comparison compensation value; wherein the continuous calibration differential signal refers to a differential signal to be calibrated that is received in a timely manner after the second differential signal to be calibrated and is the same as the first differential signal to be calibrated, and the first time difference between the second differential signal to be calibrated and the first differential signal to be calibrated is equal to the second time difference between the first received continuous calibration differential signal and the second differential signal to be calibrated; and the third time difference between two adjacent continuous differential signals to be calibrated is also equal to the first time difference; When the continuous calibration differential signal is no longer received, the last comparison compensation value or the average compensation value is determined as the PWM compensation value; the average compensation value refers to the average value between the initial compensation value and all the comparison compensation values.

9. The signal distortion compensation method according to claim 1, characterized in that: The chip is a BMS chip in a battery management system; The receiving of the differential signal to be compensated comprises: Receiving a differential signal to be compensated sent by a bridge chip adjacent to the chip or an adjacent previous BMS chip in the battery management system; The step of determining and outputting a compensated output signal according to the PWM compensation value and the first ideal differential signal comprises: A compensated output signal is determined according to the PWM compensation value and the first ideal differential signal, and the compensated output signal is output to a next BMS chip adjacent to the chip in the battery management system.

10. The signal distortion compensation method according to claim 1, characterized in that: The signal distortion compensation method further includes: receiving a switching instruction, determining a target mode and a mode to be switched, wherein the target mode refers to a calibration mode or a communication mode currently in which the chip is located; and the mode to be switched refers to another mode of the calibration mode and the communication mode except the target mode; The target mode is switched to the mode to be switched.

11. A chip, characterized in that: The invention comprises a signal conversion circuit, a data processing circuit, a first ideal current source, a compensation circuit and an output circuit; the data processing circuit is electrically connected between the output end of the signal conversion circuit and the input end of the first ideal current source; the output end of the first ideal current source and the compensation circuit are both electrically connected to the output circuit; When the chip is in communication mode, the signal conversion circuit converts the received differential signal to be compensated into a first digital signal and outputs it to the data processing circuit; the data processing circuit performs data processing according to the received first digital signal and outputs it to the first ideal current source; the first ideal current source generates a first ideal differential signal corresponding to the first digital signal and outputs it; After the compensation circuit determines the compensation signal according to the PWM compensation value, the output circuit determines and outputs the compensated output signal according to the compensation signal and the first ideal differential signal.

12. The chip according to claim 11, characterized in that: The compensation circuit comprises a first switch, a second switch and a second ideal current source, the input end of the second ideal current source is connected to the output end of the data processing circuit through the first switch, and the output end of the second ideal current source is connected to the output circuit through the second switch; When the compensation circuit determines that the PWM compensation value is not 0, the first switch and the second switch are controlled to be turned on, so as to generate a compensation signal corresponding to the PWM compensation value through the second ideal current source, and the output circuit pre-compensates the first ideal differential signal sent by the first ideal current source according to the compensation signal, and outputs the first ideal differential signal after pre-compensation as an output signal.

13. The chip according to claim 11, characterized in that: The compensation circuit comprises a first switch, a second switch and a second ideal current source, the input end of the second ideal current source is connected to the output end of the data processing circuit through the first switch, and the output end of the second ideal current source is connected to the output circuit through the second switch; When the compensation circuit determines that the PWM compensation value is not 0, the first switch and the second switch are controlled to be turned on, so as to drive the second ideal current source to generate a corresponding compensation signal through the PWM compensation value, and output the sum of the compensation signal and the first ideal differential signal as the output signal after pre-compensation; wherein the compensation signal is equal to the product of the PWM compensation value, the differential signal response value and the second ideal current source; and the differential signal response value refers to the signal response value corresponding to the pulse state of the differential signal to be compensated at the moment when the differential signal to be compensated is received.

14. The chip according to claim 11, characterized in that: The compensation circuit comprises a first switch, a second switch and a second ideal current source, the input end of the second ideal current source is connected to the output end of the data processing circuit through the first switch, and the output end of the second ideal current source is connected to the output circuit through the second switch; When the compensation circuit determines that the PWM compensation value is 0, the first switch and the second switch are controlled to be disconnected, and the output circuit outputs the first ideal differential signal sent by the first ideal current source as a compensated output signal.

15. The chip according to claim 11, characterized in that: The compensation circuit comprises a second switch, the input end of the compensation circuit is electrically connected to the output end of the first ideal current source; the output end of the compensation circuit is connected to the output circuit through the second switch; When the chip is in the calibration mode, the second switch is controlled to be disconnected, the signal conversion circuit converts the received first differential signal to be calibrated into a second digital signal and outputs it to the data processing circuit, the data processing circuit performs data processing according to the received second digital signal and outputs it to the first ideal current source, the first ideal current source generates a second ideal differential signal corresponding to the second digital signal and outputs it to the compensation circuit; the compensation circuit determines the PWM compensation value according to the second ideal differential signal and the second differential signal to be calibrated received by the chip; the second differential signal to be calibrated is the same as the first differential signal to be calibrated.

16. The chip according to claim 15, characterized in that The compensation circuit comprises a comparator, a first input terminal of the comparator is connected to the output terminal of the first ideal current source; the output terminal of the comparator is connected to the output circuit through the second switch; When the second differential signal to be calibrated is received at the second input terminal of the comparator, the comparator determines a PWM compensation value according to a difference between the second ideal differential signal input by the first ideal current source and the received second differential signal to be calibrated.

17. The chip according to claim 15, characterized in that: The compensation circuit comprises a comparator, a first input terminal of the comparator is connected to the output terminal of the first ideal current source; the output terminal of the comparator is connected to the output circuit through the second switch; When the second differential signal to be calibrated is received at the second input end of the comparator, the comparator determines the difference between the second ideal differential signal input by the first ideal current source and the received second differential signal to be calibrated as the initial compensation value; thereafter, when the chip continues to receive continuous calibration differential signals, the comparator determines the difference between the second ideal differential signal and the received continuous calibration differential signal as the comparison compensation value, and then when the continuous calibration differential signal is no longer received, the comparator determines the last comparison compensation value or the average compensation value as the PWM compensation value; wherein the continuous calibration differential signal refers to a differential signal to be calibrated that is received at a fixed time after the second differential signal to be calibrated and is the same as the first differential signal to be calibrated, and the first time difference between the second differential signal to be calibrated and the first differential signal to be calibrated is equal to the second time difference between the first received continuous calibration differential signal and the second differential signal to be calibrated; the third time difference between two adjacent continuous differential signals to be calibrated is also equal to the first time difference; and the average compensation value refers to the average value between the initial compensation value and all the comparison compensation values.

18. The chip according to claim 11, characterized in that: The chip is a BMS chip in a battery management system; In the battery management system, after the chip receives the differential signal to be compensated sent by the adjacent bridge chip or the previous BMS chip, the chip converts the differential signal to be compensated into a first digital signal, performs data processing according to the first digital signal, drives the first ideal current source to generate a first ideal differential signal corresponding to the first digital signal, and determines the compensated output signal according to the PWM compensation value and the first ideal differential signal, and then outputs the compensated output signal to the next BMS chip adjacent to the chip in the battery management system.

19. The chip according to claim 11, characterized in that: The compensation circuit comprises a first switch, a second switch, a comparator and a second ideal current source, wherein the first input end of the comparator is connected to the output end of the first ideal current source; the output end of the comparator is connected to the second switch through the second ideal current source, and the end of the second switch away from the second ideal current source is connected to the output circuit; the input end of the second ideal current source is connected to the output end of the data processing circuit through the first switch; When receiving the switching instruction, if the current target mode of the chip is the calibration mode, controlling the first switch and the second switch to be turned on to switch the calibration mode to the communication mode; If the target mode currently in which the chip is located is the communication mode, the first switch and the second switch are controlled to be disconnected to switch the communication mode to the calibration mode.

20. A communication system, characterized in that: The method comprises at least two chips connected by daisy chain communication, wherein the chip is the chip according to any one of claims 11 to 19.

21. The communication system according to claim 20, characterized in that The communication system is a battery management system, and the chip is a BMS chip in the battery management system.

22. A vehicle, characterized in that: Comprising a chip as claimed in any one of claims 11 to 19.

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