Semiconductor device structure and method of fabricating the same

Abstract

This invention relates to a semiconductor device structure and its fabrication method. The semiconductor device structure includes a substrate and a stacked structure of alternating interlayer dielectric layers and conductive layers on the substrate, at least one through-hole penetrating the stacked structure, and a first word line, a first channel layer, a second word line, a second channel layer, and a conductive connection layer disposed within the through-hole; wherein the first word line and the second word line both extend along a second direction perpendicular to the substrate and are spaced apart along a first direction parallel to the substrate; the first channel layer surrounds the sidewall of the first word line and is interrupted between adjacent conductive layers; the second channel layer surrounds the sidewall of the second word line and is interrupted between adjacent conductive layers; the conductive connection layer is located between adjacent conductive layers and is integrally connected to both the first word line and the second word line along a first direction. The semiconductor device structure of this invention can increase the driving current.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device structure and its fabrication method. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] Based on this, the present invention provides a semiconductor device structure and a method for fabricating the same.

[0005] In a first aspect, the present invention provides a semiconductor device structure, comprising: a substrate and a stacked structure of alternating interlayer dielectric layers and conductive layers on the substrate, at least one via penetrating the stacked structure, wherein a first word line, a first channel layer, a second word line, a second channel layer, and a conductive interconnect layer are disposed within the via; wherein...

[0006] Both the first character line and the second character line extend along a second direction perpendicular to the substrate and are spaced apart along a first direction parallel to the substrate;

[0007] The first channel layer surrounds the sidewall of the first word line and is broken between adjacent conductive layers;

[0008] The second channel layer surrounds the sidewall of the second word line and is disconnected between adjacent conductive layers;

[0009] The conductive connection layer is located between adjacent conductive layers and is integrally connected to both the first character line and the second character line along the first direction.

[0010] The aforementioned semiconductor device structure includes: a substrate and a stacked structure of alternating interlayer dielectric layers and conductive layers on the substrate, at least one through-hole penetrating the stacked structure, and a first word line, a first channel layer, a second word line, a second channel layer, and a conductive connection layer disposed within the through-hole; wherein the first word line and the second word line both extend along a second direction perpendicular to the substrate and are spaced apart along a first direction parallel to the substrate; the first channel layer surrounds the sidewall of the first word line and is interrupted between adjacent conductive layers; the second channel layer surrounds the sidewall of the second word line and is interrupted between adjacent conductive layers; the conductive connection layer is located between adjacent conductive layers and is integrally connected to both the first word line and the second word line along the first direction. Because the through-hole contains the first word line and the second word line, and the first channel layer surrounds the sidewall of the first word line and the second channel layer surrounds the sidewall of the second word line, multiple channels can be formed within the first channel layer and the second channel layer. The arrangement of multiple channels can increase the driving current.

[0011] In one embodiment, the semiconductor device structure further includes: a first gate dielectric layer and a second gate dielectric layer;

[0012] The first gate dielectric layer is located at least between the first channel layer and the first word line;

[0013] The second gate dielectric layer is located at least between the second channel layer and the second word line.

[0014] In one embodiment, the semiconductor device structure further includes multiple conductive layers arranged parallel to each other along the second direction; each of the conductive layers includes:

[0015] A first extension extends along the first direction, and the first extension serves as a bit line;

[0016] Multiple second extensions are located on opposite sides of the first extension and are integrally connected to the first extension; each second extension extends along a third direction parallel to the substrate, and multiple second extensions located on the same side of the first extension are arranged parallel to each other along the first direction.

[0017] The number of through holes is multiple, and the multiple through holes are respectively located at one end of the multiple second extensions near the first extension.

[0018] In one embodiment, the semiconductor device structure further includes a capacitor region located at one end of the second extension away from the first extension.

[0019] In one embodiment, the semiconductor device structure further includes a frame located on the side of the capacitor region away from the first extension and in contact with the capacitor region.

[0020] In one embodiment, the semiconductor device structure further includes a plurality of isolation structures located between the first word line and the second word line, and between adjacent conductive interconnect layers and on the top conductive interconnect layer.

[0021] Secondly, the present invention also provides a method for fabricating a semiconductor device structure, comprising:

[0022] Provide substrate;

[0023] A stacked structure is formed on the substrate, the stacked structure comprising conductive layers and interlayer dielectric layers arranged alternately from bottom to top.

[0024] Form at least one through-hole through the stacked structure;

[0025] A first word line, a second word line, a first channel layer, a second channel layer, and multiple conductive connection layers are formed within the via; wherein the first word line and the second word line both extend along a second direction perpendicular to the substrate and are spaced apart along a first direction parallel to the substrate; the first channel layer surrounds the sidewall of the first word line and is interrupted between adjacent conductive layers; the second channel layer surrounds the sidewall of the second word line and is interrupted between adjacent conductive layers; the conductive connection layers are located between adjacent conductive layers and are integrally connected to both the first word line and the second word line along the first direction.

[0026] The method for fabricating the above-described semiconductor device structure involves forming a stacked structure on the substrate, the stacked structure comprising conductive layers and interlayer dielectric layers alternately stacked from bottom to top; forming at least one through-hole penetrating the stacked structure; and forming a first word line, a second word line, a first channel layer, a second channel layer, and multiple conductive interconnect layers within the through-hole; wherein the first word line and the second word line extend along a second direction perpendicular to the substrate and are spaced apart along a first direction parallel to the substrate; the first channel layer surrounds the sidewall of the first word line and is interrupted between adjacent conductive layers; the second channel layer surrounds the sidewall of the second word line and is interrupted between adjacent conductive layers; and the conductive interconnect layers are located between adjacent conductive layers and are integrally connected to both the first word line and the second word line along the first direction. Because the through-hole contains the first word line and the second word line, and the first channel layer surrounds the sidewall of the first word line and the second channel layer surrounds the sidewall of the second word line, multiple channels can be formed within the first and second channel layers. The multiple channels increase the driving current.

[0027] In one embodiment, forming a stacked structure on the substrate includes:

[0028] Multiple interlayer dielectric layers are formed on the substrate at intervals along the second direction;

[0029] Multiple conductive layers are formed between the interlayer dielectric layers and spaced apart along the second direction. The interlayer dielectric layers and the conductive layers are stacked sequentially from bottom to top to form a stacked structure. Each conductive layer includes a first extension extending along the first direction and a plurality of second extensions extending along the third direction. Each second extension is located on opposite sides of the first extension and is integrally connected to the first extension. The plurality of second extensions located on the same side of the first extension are arranged parallel to each other along the first direction. The end of each second extension near the first extension serves as a channel region, and the channel region has an isolation structure.

[0030] In one embodiment, forming multiple interlayer dielectric layers spaced apart along the second direction on the substrate includes:

[0031] An initial stacked structure is formed on the substrate, the initial stacked structure including an interlayer dielectric layer and a sacrificial layer stacked sequentially from bottom to top; each interlayer dielectric layer includes: a third extension extending along the first direction and a plurality of fourth extensions extending along the third direction; wherein each of the fourth extensions is located on opposite sides of the third extension and is integrally connected to the third extension, and the plurality of fourth extensions located on the same side of the third extension are arranged in parallel and spaced apart along the first direction; one end of each fourth extension near the third extension serves as a predetermined channel region.

[0032] A first trench and a second trench are formed within the initial stacked structure, penetrating the preset channel region of each layer along the second direction, and the first trench and the second trench are arranged at intervals along the first direction;

[0033] A dielectric layer is filled in the first trench and the second trench;

[0034] Each of the sacrificial layers is removed to form multiple interlayer dielectric layers arranged in parallel and spaced along the second direction, and each of the sacrificial layers located between the sacrificial layers in the preset channel region is retained as the isolation structure, such that each isolation structure is arranged at intervals along the second direction in the preset channel region.

[0035] In one embodiment, after forming a first word line, a second word line, a first channel layer, a second channel layer, and multiple conductive interconnect layers within the via, the method further includes:

[0036] A capacitor is formed at one end of the stacked structure away from the via along a third direction parallel to the substrate, wherein the third direction intersects the first direction.

[0037] In one embodiment, before forming multiple interlayer dielectric layers spaced apart along the second direction on the substrate, the method further includes:

[0038] A frame is formed on the opposite sides of the stacked structure.

[0039] In one embodiment, forming at least one through-hole through the stacked structure includes:

[0040] A dielectric layer is formed in the gap region of the stacked structure;

[0041] Remove the dielectric layer in the first trench and the second trench;

[0042] Lateral etching is performed based on the first trench and the second trench to remove the dielectric layer located between adjacent isolation structures and a portion of the interlayer dielectric layer located between each conductive layer, thereby obtaining the via.

[0043] In one embodiment, forming a first letter line, a second letter line, a first channel layer, a second channel layer, and a multilayer conductive connection layer within the through-hole includes:

[0044] A channel material layer and a word line conductive layer are sequentially deposited on the inner wall of the through hole; wherein, the word line conductive layer filled in the first trench serves as the first word line, the word line conductive layer filled in the second trench serves as the second word line, and the word line conductive layer filled in the through hole between adjacent conductive layers serves as the conductive connection layer.

[0045] A third trench is formed in the gap region of the stacked structure, penetrating the dielectric layer. The third trench exposes the channel material layers that are spaced apart along the second direction on the sidewalls of each dielectric layer. The sidewalls of each exposed channel material layer correspond one-to-one with each interlayer dielectric layer.

[0046] The exposed channel material layers are removed based on the third trench to obtain a channel layer that corresponds one-to-one with each conductive layer; wherein the channel layer located in the first trench is the first channel layer, and the channel layer located in the second trench is the second channel layer. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of the present invention or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 This is a flowchart of a method for fabricating a semiconductor device structure provided in one embodiment;

[0049] Figure 2 This is a flowchart of step S20 in the method for fabricating a semiconductor device structure provided in one embodiment;

[0050] Figure 3 This is a flowchart of step S201 in the method for fabricating a semiconductor device structure provided in one embodiment;

[0051] Figure 4 This is a 3D structural schematic diagram of the structure obtained in step S2011 of the semiconductor device structure fabrication method provided in one embodiment;

[0052] Figure 5 This is a top view of the structure obtained in step S2011 of the semiconductor device structure fabrication method provided in one embodiment.

[0053] Figure 6 This is a schematic diagram of the cross-sectional structure of the structure obtained in step S2011 of one embodiment, wherein (a) is a cross-sectional view along... Figure 5 The diagram shown is along the AA' direction. (b) The diagram is along the AA' direction. Figure 5 A schematic diagram showing the BB' direction;

[0054] Figure 7 This is a schematic diagram of the 3D structure of the structure obtained in step S2012 of the method for fabricating a semiconductor device structure provided in one embodiment.

[0055] Figure 8 This is a top view of the structure obtained in step S2012 of the semiconductor device structure fabrication method provided in one embodiment;

[0056] Figure 9 This is a schematic diagram of the cross-sectional structure of the structure obtained in step S2012 of one embodiment, wherein (a) is a cross-sectional view along... Figure 8 The diagram shown is along the AA' direction. (b) The diagram is along the AA' direction. Figure 8 A schematic diagram showing the BB' direction;

[0057] Figure 10This is a 3D structural schematic diagram of the structure obtained in step S2013 of the semiconductor device structure fabrication method provided in one embodiment;

[0058] Figure 11 This is a top view of the structure obtained in step S2013 of the semiconductor device structure fabrication method provided in one embodiment;

[0059] Figure 12 This is a schematic diagram of the cross-sectional structure of the structure obtained in step S2013 of one embodiment, wherein (a) is a cross-sectional view along... Figure 11 The diagram shown is along the AA' direction. (b) The diagram is along the AA' direction. Figure 11 A schematic diagram showing the BB' direction;

[0060] Figure 13 This is a 3D structural schematic diagram of the structure obtained in step S2014 of the semiconductor device structure fabrication method provided in one embodiment;

[0061] Figure 14 This is a top view of the structure obtained in step S2014 of the semiconductor device structure fabrication method provided in one embodiment.

[0062] Figure 15 This is a schematic diagram of the cross-sectional structure of the structure obtained in step S2014 of one embodiment, wherein (a) is a cross-sectional view along... Figure 14 The diagram shown is along the AA' direction. (b) The diagram is along the AA' direction. Figure 14 A schematic diagram showing the BB' direction;

[0063] Figure 16 This is a schematic diagram of the 3D structure of the structure obtained in step S202 of the method for fabricating a semiconductor device structure provided in one embodiment.

[0064] Figure 17 This is a top view of the structure obtained in step S202 of the semiconductor device structure fabrication method provided in one embodiment;

[0065] Figure 18 This is a schematic diagram of the cross-sectional structure of the structure obtained in step S202 of one embodiment, wherein (a) is a cross-sectional view along... Figure 17 The diagram shown is along the AA' direction. (b) The diagram is along the AA' direction. Figure 17 A schematic diagram showing the BB' direction;

[0066] Figure 19 This is a flowchart of step S30 in the method for fabricating a semiconductor device structure provided in one embodiment;

[0067] Figure 20 This is a 3D structural schematic diagram of the structure obtained in step S301 of the semiconductor device structure fabrication method provided in one embodiment;

[0068] Figure 21 This is a top view of the structure obtained in step S301 of the semiconductor device structure fabrication method provided in one embodiment;

[0069] Figure 22 This is a schematic diagram of the cross-sectional structure of the structure obtained in step S301 of one embodiment, wherein (a) is a cross-sectional view along... Figure 21 The diagram shown is along the AA' direction. (b) The diagram is along the AA' direction. Figure 21 A schematic diagram showing the BB' direction;

[0070] Figure 23 This is a schematic diagram of the 3D structure of the structure obtained in step S302 of the method for fabricating a semiconductor device structure provided in one embodiment.

[0071] Figure 24 This is a top view of the structure obtained in step S302 of the semiconductor device structure fabrication method provided in one embodiment.

[0072] Figure 25 This is a schematic diagram of the cross-sectional structure of the structure obtained in step S302 of one embodiment, wherein (a) is a cross-sectional view along... Figure 24 The diagram shown is along the AA' direction. (b) The diagram is along the AA' direction. Figure 24 A schematic diagram showing the BB' direction;

[0073] Figure 26 This is a 3D structural schematic diagram of the structure obtained in step S303 of the semiconductor device structure fabrication method provided in one embodiment;

[0074] Figure 27 This is a top view of the structure obtained in step S303 of the semiconductor device structure fabrication method provided in one embodiment;

[0075] Figure 28 This is a schematic diagram of the cross-sectional structure of the structure obtained in step S303 of one embodiment, wherein (a) is a cross-sectional view along... Figure 27 The diagram shown is along the AA' direction. (b) The diagram is along the AA' direction. Figure 27 A schematic diagram showing the BB' direction;

[0076] Figure 29 This is a flowchart of step S40 in the method for fabricating a semiconductor device structure provided in one embodiment;

[0077] Figure 30 This is a 3D structural schematic diagram of the structure obtained in step S401 of the semiconductor device structure fabrication method provided in one embodiment;

[0078] Figure 31This is a top view of the structure obtained in step S401 of the semiconductor device structure fabrication method provided in one embodiment.

[0079] Figure 32 This is a schematic diagram of the cross-sectional structure of the structure obtained in step S401 of one embodiment, wherein (a) is a cross-sectional view along... Figure 31 The diagram shown is along the AA' direction. (b) The diagram is along the AA' direction. Figure 31 A schematic diagram showing the BB' direction;

[0080] Figure 33 This is a schematic diagram of the 3D structure of the structure obtained in step S402 of the method for fabricating a semiconductor device structure provided in one embodiment.

[0081] Figure 34 This is a top view of the structure obtained in step S402 of the semiconductor device structure fabrication method provided in one embodiment;

[0082] Figure 35 This is a schematic diagram of the cross-sectional structure of the structure obtained in step S402 of one embodiment, wherein (a) is a cross-sectional view along... Figure 34 The diagram shown is along the AA' direction. (b) The diagram is along the AA' direction. Figure 34 A schematic diagram showing the BB' direction;

[0083] Figure 36 This is a 3D structural schematic diagram of the structure obtained in step S403 of the semiconductor device structure fabrication method provided in one embodiment;

[0084] Figure 37 This is a top view of the structure obtained in step S403 of the semiconductor device structure fabrication method provided in one embodiment;

[0085] Figure 38 This is a schematic diagram of the cross-sectional structure of the structure obtained in step S403 of one embodiment, wherein (a) is a cross-sectional view along... Figure 37 The diagram shown is along the AA' direction. (b) The diagram is along the AA' direction. Figure 37 A schematic diagram showing the BB' direction;

[0086] Figure 39 This is a 3D structural schematic diagram of a semiconductor device structure provided in one embodiment;

[0087] Figure 40 This is a top view schematic diagram of a semiconductor device structure provided in one embodiment;

[0088] Figure 41 This is a schematic cross-sectional view of a semiconductor device structure provided in one embodiment, wherein (a) is a cross-sectional view along... Figure 40 The diagram shown is along the AA' direction. (b) The diagram is along the AA' direction. Figure 40A schematic diagram showing the BB' direction.

[0089] Explanation of reference numerals in the attached drawings: 10-substrate, 101-first trench, 102-second trench, 103-third trench, 11-via, 20-interlayer dielectric layer, 201-dielectric layer, 30-sacrificial layer, 301-third extension, 302-fourth extension, 303-preset channel region, 304-isolation structure, 40-conductive layer, 401-first extension, 402-second extension, 403-channel region, 50-fill layer, 601-channel material layer, 602-gate dielectric layer, 603-word line conductive layer, 604-channel layer, 61-first word line, 62-second word line, 63-conductive interconnect layer, 70-capacitor region, 80-frame. Detailed Implementation

[0090] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the invention will be thorough and complete.

[0091] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0092] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.

[0093] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0094] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0095] Embodiments of the invention are described herein with reference to cross-sectional views illustrating preferred embodiments (and intermediate structures), thus allowing for the expectation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.

[0096] Please see Figure 1 This invention provides a method for fabricating a semiconductor device structure, comprising the following steps:

[0097] S10: Provides a substrate;

[0098] S20: A stacked structure is formed on the substrate, the stacked structure including conductive layers and interlayer dielectric layers arranged alternately from bottom to top;

[0099] S30: Form at least one through-hole through the stacked structure;

[0100] S40: A first word line, a second word line, a first channel layer, a second channel layer, and a multilayer conductive connection layer are formed within the via; wherein the first word line and the second word line extend along a second direction perpendicular to the substrate and are spaced apart along a first direction parallel to the substrate; the first channel layer surrounds the sidewall of the first word line and is interrupted between adjacent conductive layers; the second channel layer surrounds the sidewall of the second word line and is interrupted between adjacent conductive layers; the conductive connection layer is located between adjacent conductive layers and is integrally connected to both the first word line and the second word line along the first direction.

[0101] Among them, such as Figures 36-38 The diagram shown is a schematic representation of the semiconductor device structure prepared through steps S10-S40 in one embodiment. Figure 36 This is a 3D structural diagram of a semiconductor device. Figure 37 This is a top view schematic diagram of a semiconductor device structure. Figure 38 Figure (a) shows the route along Figure 37 A schematic diagram of the cross-sectional structure in the AA' direction. Figure 38 Figure (b) shows the route along Figure 37 A schematic diagram of the cross-sectional structure along the BB' direction. Of course, Figures 36-38 The example given is a semiconductor structure prepared by the method of preparing semiconductor device structure of the present invention. Other suitable examples of semiconductor structures prepared by the method of preparing semiconductor structure of the present invention are also possible, and the present invention does not limit them.

[0102] Furthermore, for ease of understanding, the first direction involved in this invention can be the X direction in the accompanying drawings, the second direction can be the Y direction in the accompanying drawings, and the third direction can be the Z direction in the accompanying drawings. Of course, in other suitable application scenarios, the first direction, the second direction, and the third direction can have other definitions, which are not limited here.

[0103] The above-described method for fabricating a semiconductor device structure involves forming a stacked structure on a substrate, the stacked structure including conductive layers and interlayer dielectric layers arranged alternately from bottom to top; forming at least one through-hole penetrating the stacked structure; and forming a first word line, a second word line, a first channel layer, a second channel layer, and multiple conductive interconnect layers within the through-hole. The first word line and the second word line extend along a second direction perpendicular to the substrate and are spaced apart along a first direction parallel to the substrate. The first channel layer surrounds the sidewall of the first word line and is interrupted between adjacent conductive layers. The second channel layer surrounds the sidewall of the second word line and is interrupted between adjacent conductive layers. The conductive interconnect layers are located between adjacent conductive layers and are integrally connected to both the first and second word lines along the first direction. Because the through-hole contains the first and second word lines, and the first channel layer surrounds the sidewall of the first word line, and the second channel layer surrounds the sidewall of the second word line, multiple channels can be formed within the first and second channel layers. Compared to the dual-channel configuration in related technologies, the multi-channel configuration can increase the driving current.

[0104] like Figures 3-5 As shown, in step S10, a substrate 10 is provided.

[0105] The substrate 10 can be any suitable substrate material known in the art, such as at least one of the following: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), silicon on insulator (SSOI), silicon on insulator (S-SiGeOI), silicon on insulator (SiGeOI), and germanium on insulator (GeOI), or it can be a double-side polished wafer (DSP), or a ceramic substrate such as alumina, quartz, or glass substrate, etc., which are not limited in this embodiment.

[0106] like Figures 3-18 As shown, in step S20, a stacked structure is formed on the substrate 10. The stacked structure includes a conductive layer 40 and an interlayer dielectric layer 20 that are alternately stacked from bottom to top.

[0107] In one embodiment, such as Figure 2 As shown, step S20 above includes:

[0108] S201: Multiple interlayer dielectric layers are formed on the substrate at intervals along the second direction.

[0109] S202: Multiple conductive layers are formed between the interlayer dielectric layers and arranged at intervals along the second direction. The interlayer dielectric layers and the conductive layers are stacked sequentially from bottom to top to form a stacked structure.

[0110] In one embodiment, such as Figure 3 As shown, step S201 above includes:

[0111] S2011: An initial stacked structure is formed on the substrate 10. The initial stacked structure includes an interlayer dielectric layer 20 and a sacrificial layer 30 stacked sequentially from bottom to top.

[0112] like Figures 4-6 As shown, each interlayer dielectric layer 20 includes: a third extension 301 extending along a first direction and a plurality of fourth extensions 302 extending along a third direction; wherein each fourth extension 302 is located on opposite sides of the third extension 301 and is integrally connected to the third extension 301, and the plurality of fourth extensions 302 located on the same side of the third extension 301 are arranged in parallel at intervals along the first direction; the end of each fourth extension 302 near the third extension 301 serves as a preset channel region 303.

[0113] By accurately defining the photolithographic pattern and manufacturing the corresponding photomask, and then undergoing processes such as deposition, photolithography, and polishing, a final product can be formed. Figure 4 The structure shown is based on a relatively mature process, and will not be described in detail here.

[0114] The material of the interlayer dielectric layer 20 may include a suitable dielectric material, such as an oxide material or a nitride material; the material of the sacrificial layer 30 may include a suitable insulating material, such as an oxide material or a nitride material. However, it should be noted that the material of the interlayer dielectric layer 20 is different from the material of the sacrificial layer 30. For example, the material of the interlayer dielectric layer 20 may be silicon oxide and the material of the sacrificial layer 30 may be silicon nitride, or the material of the interlayer dielectric layer 20 may be silicon nitride and the material of the sacrificial layer 30 may be silicon oxide.

[0115] S2012: A first trench 101 and a second trench 102 are formed within the initial stacked structure, penetrating the predetermined channel region 303 of each layer along the second direction. The first trench 101 and the second trench 102 are arranged at intervals along the first direction, such as... Figures 7-9 As shown.

[0116] S2013: A dielectric layer 201 is filled in the first trench 101 and the second trench 102, such as... Figures 10-12 As shown.

[0117] The dielectric layer 201 may be made of an oxide material or a nitride material. Optionally, the material of the dielectric layer 201 may be the same as the material of the interlayer dielectric layer 20. For example, both the dielectric layer 201 and the interlayer dielectric layer 20 may be made of silicon oxide or silicon nitride.

[0118] S2014: Remove each sacrificial layer 30 to form multiple interlayer dielectric layers 20 arranged parallel to each other along the second direction, and retain the sacrificial layer 30 between the first trench 101 and the second trench 102 as an isolation structure 304, such that each isolation structure 304 is arranged at intervals along the second direction within a predetermined trench region 303, as follows. Figures 13-15 As shown.

[0119] In this process, selective etching can be used to remove each sacrificial layer 30 while preserving the interlayer dielectric layers 20. Furthermore, due to the supporting effect of the dielectric layers 201, the structure of each interlayer dielectric layer 20 is completely preserved to form a structure as described above. Figures 13-15 The structure shown. In addition, the sacrificial layer 30 located in the preset channel region 303 of each layer is not removed due to the protection of the dielectric layer 201, and is thus retained to form the isolation structure 304.

[0120] In this embodiment, the purpose of forming the initial stacked structure in steps S2011-S2014 is to form an isolation structure 304 located in the preset channel region 303 of each layer, and to remove the sacrificial layers 30 of each layer by selective removal, so as to retain the interlayer dielectric layers 20. Simultaneously, after selective removal, since some sacrificial layers 30 are sandwiched between the dielectric layers 201, the isolation structure 304 is formed, and the supporting effect of the dielectric layers 201 is used to form a structure such as... Figures 13-15 The interlayer dielectric layer 20 shown is designed to meet the requirements of subsequent processes.

[0121] Of course, further, the formation in step S201 as... Figures 13-15 The interlayer dielectric layers 20 shown can also be formed using other suitable fabrication processes. The above steps S2011-S2014 are only an example. In other suitable application scenarios, other suitable fabrication processes can also be used to prepare the morphology of the structure in step S201. This embodiment does not impose any limitations on this.

[0122] In step S202, please refer to Figures 16-18 Multiple conductive layers 40 are formed between the interlayer dielectric layers 20 and spaced apart along the second direction. The interlayer dielectric layers 20 and the conductive layers 40 are stacked sequentially from bottom to top to form a stacked structure.

[0123] Each conductive layer 40 includes: a first extension 401 extending along a first direction and a plurality of second extensions 402 extending along a third direction. Each second extension 402 is located on opposite sides of the first extension 401 and is integrally connected to the first extension 401. The plurality of second extensions 402 located on the same side of the first extension 401 are arranged in parallel and spaced apart along the first direction. The end of each second extension 402 near the first extension 401 serves as a channel region 403, and the channel region 403 has an isolation structure 304.

[0124] The material of the conductive layer 40 may include any suitable conductive material, such as metals such as tungsten, copper, gold, titanium, silver, and aluminum, or multilayer metals composed of the above-mentioned materials, or metal alloys, etc. This embodiment does not impose any limitations.

[0125] contrast Figure 17 and Figure 11 It can be seen that the position of the channel region 403 corresponds to the position of the preset channel region 303, or it can be said that the position of the channel region 403 is the same as the position of the preset channel region 303. Therefore, the dielectric layer 201 and the isolation structure 304 are located within each channel region 403, and are combined with... Figure 18 As can be seen in Figure (a), the isolation structure 304 and part of the interlayer dielectric layer 20 are stacked alternately along the second direction.

[0126] Optionally, an initial conductive material layer can be deposited in the gap region of the structure obtained in step S201 using a deposition process, and then formed as shown in the figure through photolithography, etching, and other process steps. Figures 16-18 The structure shown allows for the reuse of the photomask used in the photolithography process to form the initial stacked structure, thereby saving on process costs. The deposition process may, for example, include atomic layer deposition.

[0127] like Figures 26-28 As shown, in step S30, at least one through hole 11 is formed through the stacked structure.

[0128] In one embodiment, such as Figure 19 As shown, step S30 above includes:

[0129] S301: A filling layer 50 is formed in the gap area of ​​the stacked structure.

[0130] like Figures 20-22 As shown, a deposition process can be used to deposit a filling layer 50 in one step. The deposition process may include, for example, atomic layer deposition, physical vapor deposition, chemical vapor deposition, etc.

[0131] The filler layer 50 may be made of nitride or oxide materials, such as silicon oxide, and the filler layer 50 serves to further support the stacked structure.

[0132] S302: Remove the dielectric layer 201 in the first trench 101 and the second trench 102, such as Figures 23-25 As shown.

[0133] S303: Lateral etching is performed based on the first trench 101 and the second trench 102 to remove the dielectric layer 201 located between adjacent isolation structures 304 and part of the interlayer dielectric layer 20 located between each conductive layer 40, to obtain the via 11, such as Figures 26-28 As shown.

[0134] The lateral etching can include wet etching or vapor etching. After lateral etching, the two ends of each isolation structure 304 make corresponding contact with each conductive layer 40, such as... Figure 28 As shown.

[0135] like Figures 30-32 As shown, in step S40, a first word line, a second word line, a first channel layer, a second channel layer, and a multilayer conductive connection layer are formed in the through hole.

[0136] The first word line and the second word line both extend along a second direction perpendicular to the substrate and are spaced apart along a first direction parallel to the substrate; the first channel layer surrounds the sidewall of the first word line and is disconnected between adjacent conductive layers; the second channel layer surrounds the sidewall of the second word line and is disconnected between adjacent conductive layers; the conductive connection layer is located between adjacent conductive layers and is integrally connected to both the first word line and the second word line along the first direction.

[0137] In one embodiment, such as Figure 29 As shown, step S40 above includes:

[0138] S401: A channel material layer and a word line conductive layer are sequentially deposited on the inner wall of the through hole; wherein, the word line conductive layer filled in the first trench serves as the first word line, the word line conductive layer filled in the second trench serves as the second word line, and the word line conductive layer filled in the through hole between adjacent conductive layers serves as the conductive connection layer.

[0139] like Figures 30-32 As shown, a continuously distributed channel material layer 601 and a word line conductive layer can be sequentially deposited using a deposition process. The deposition process can include atomic layer deposition, physical vapor deposition, chemical vapor deposition, etc.

[0140] The channel material layer 601 may be made of a metal oxide semiconductor material, such as indium gallium zinc oxide (IGZO). When the metal oxide semiconductor material is IGZO, the leakage current of the transistor is small (leakage current is not greater than or equal to 10-15A), thereby ensuring the low refresh rate of the dynamic memory. It should be noted that the metal oxide semiconductor material can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx, etc., as long as the leakage current of the transistor meets the requirements. The specific materials can be adjusted according to the actual situation.

[0141] The material of the word line conductive layer 603 may include ITO, polysilicon, metal, or other suitable conductive materials.

[0142] In addition, such as Figure 32 As shown in Figures (a) and (b), each word line conductive layer 603, which is filled between each conductive layer 40 and extends along the first direction, serves as a conductive connection layer 63.

[0143] Optional, such as Figures 30-32 As shown, the gate dielectric layer 602 can be formed simultaneously with the formation of the channel material layer and the word line conductive layer.

[0144] The material of the gate dielectric layer 602 may include a suitable dielectric material, such as a high-k dielectric material.

[0145] Furthermore, the gate dielectric layer 602 includes a first gate dielectric layer and a second gate dielectric layer, wherein the first gate dielectric layer is located above the first channel layer and between the first word line, and the second gate dielectric layer is located at least between the second channel layer and the second word line.

[0146] Additionally, it should be noted that the channel material layer 601 and the gate dielectric layer 602 are essentially continuously distributed on the inner wall of the via 11. This is in conjunction with... Figure 32 The difference is quite obvious in Figures (a) and (b).

[0147] S402: A third trench is formed in the gap region of the stacked structure, penetrating the dielectric layer. The third trench exposes the channel material layers arranged at intervals along the second direction on the sidewalls of each dielectric layer, wherein the sidewalls of each exposed channel material layer correspond one-to-one with each interlayer dielectric layer.

[0148] like Figures 33-35 As shown, the morphology of the third trench 103 can be determined by the design of the photomask. The purpose of forming the third trench 103 is to expose the surface of the channel material layer 601 of the interlayer dielectric layer 20 surrounding each channel region 403 by using the sidewall of the third trench 103, and the channel material layer 601 located in each channel region 403 will not be exposed by the sidewall of the third trench 103.

[0149] Furthermore, the formation of the third trench 103 can selectively remove only the filler layer 50 and the interlayer dielectric layer 20. The filler layer 50 and the interlayer dielectric layer 20 can be made of the same material, for example, both can be silicon oxide. The conductive layers 40 can remain intact during the formation of the third trench 103. Figure 35 The third groove 103 shown in Figure (b) can be arranged at intervals along the second direction.

[0150] S403: Based on the third trench, remove the exposed channel material layers to obtain a channel layer that corresponds one-to-one with each conductive layer; wherein, the channel layer located in the first trench is the first channel layer, and the channel layer located in the second trench is the second channel layer.

[0151] like Figures 36-38 As shown, since in step S402, the positions of the exposed channel material layers 601 on the sidewall of the third trench 103 correspond to the positions of the interlayer dielectric layers 20 and the positions of the filling layers 50 correspond to the positions of the conductive layers 40, the exposed channel material layers 601 on the sidewall of the third trench 103 can be removed by selective etching, and the remaining channel material layers 601 corresponding to the conductive layers 40 can be used as channel layers 604.

[0152] In addition, in the above embodiments, since the channel material layer 601 is continuously distributed, it will also be partially distributed on the sidewalls of the interlayer dielectric layer 20. From the perspective of device design, this embodiment only needs to form the channel material layer 601 on the sidewalls of each conductive layer 40. The channel material layer 601 located on the sidewalls of the interlayer dielectric layer 20 will bring about the problem of parasitic MOS. Therefore, this embodiment can also remove the channel material layer 601 exposed on the sidewall of the third trench 103, thereby achieving the purpose of removing parasitic MOS.

[0153] Optionally, in other suitable application scenarios, a method similar to any embodiment provided by the present invention can be used to achieve that the word line structure corresponding to each layer of channel region 403 has multiple word lines spaced apart along the first direction, and is not limited to having only two word lines. For example, in step S2012 above, multiple trenches spaced apart along the first direction can be formed in the initial stacked structure, and the multiple trenches can all penetrate each layer of preset channel region 303 along the first direction. Then, combined with other embodiments of the present invention, more word lines are formed in a through hole, and more channels are formed accordingly, thereby further improving the driving current of the semiconductor device structure.

[0154] In one embodiment, such as Figures 39-41 As shown, after step S40, the method for fabricating the semiconductor device structure further includes:

[0155] A capacitor is formed at the end of the stacked structure away from the via 11 along a third direction parallel to the substrate 10, wherein the third direction intersects with the first direction.

[0156] In one embodiment, such as Figures 39-41 As shown, prior to step S201, the method for fabricating the semiconductor device structure further includes:

[0157] A frame 80 is formed on the side of the capacitor region 70 away from the first extension 401, and the frame 80 is in contact with the capacitor region 70.

[0158] Optionally, the frame 80 can be formed after step S2011 and before step S2012, and the frame 80 can be formed in subsequent figures. Optionally, other figures in this invention can also include... Figures 39-41 The framework 80, combined with Figures 39-41 Other accompanying drawings forming the frame 80 can be obtained, which will not be described in detail here.

[0159] The present invention also provides a semiconductor device structure, such as Figures 36-38 As shown, the semiconductor device structure includes: a substrate 10 and a stacked structure of alternating interlayer dielectric layers 20 and conductive layers 40 on the substrate 10, at least one through-hole 11 penetrating the stacked structure, and a first word line 61, a first channel layer, a second word line 62, a second channel layer, and a conductive connection layer 63 disposed within the through-hole 11; wherein, the first word line 61 and the second word line 62 both extend along a second direction perpendicular to the substrate 10 and are spaced apart along a first direction parallel to the substrate 10; the first channel layer surrounds the sidewall of the first word line 61 and is interrupted between adjacent conductive layers 40; the second channel layer surrounds the sidewall of the second word line 62 and is interrupted between adjacent conductive layers 40; the conductive connection layer 63 is located between adjacent conductive layers 40 and is integrally connected to both the first word line and the second word line along the first direction.

[0160] The aforementioned semiconductor device structure includes a substrate 10 and a stacked structure of alternating interlayer dielectric layers 20 and conductive layers 40 on the substrate 10, at least one through-hole 11 penetrating the stacked structure, and a first word line 61, a first channel layer, a second word line 62, a second channel layer, and a conductive connection layer 63 disposed within the through-hole 11; wherein, the first word line 61 and the second word line 62 both extend along a second direction perpendicular to the substrate 10 and are spaced apart along a first direction parallel to the substrate 10; the first channel layer surrounds the sidewall of the first word line 61 and is interrupted between adjacent conductive layers 40; the second channel layer surrounds the sidewall of the second word line 62 and is interrupted between adjacent conductive layers 40; the conductive connection layer 63 is located between adjacent conductive layers 40 and is integrally connected to both the first word line and the second word line along the first direction. Since the through hole 11 is provided with a first word line 61 and a second word line 62, and the first channel layer is provided around the side wall of the first word line 61 and the second channel layer is provided around the side wall of the second word line 62, multiple channels can be formed in the first channel layer and the second channel layer. Compared with the dual channel in the related technology, the multi-channel arrangement can increase the driving current.

[0161] In one embodiment, such as Figures 36-38 As shown, the semiconductor device structure further includes: a first gate dielectric layer and a second gate dielectric layer; the first gate dielectric layer is located at least between the first channel layer and the first word line 61; the second gate dielectric layer is located at least between the second channel layer and the second word line 62.

[0162] In one embodiment, such as Figures 36-38 As shown, each conductive layer 40 includes: a first extension 401 extending along a first direction, the first extension 401 serving as a bit line; a plurality of second extensions 402 located on opposite sides of the first extension 401 and integrally connected to the first extension 401; each second extension 402 extending along a third direction parallel to the substrate 10, and the plurality of second extensions 402 located on the same side of the first extension 401 are arranged in parallel at intervals along the first direction;

[0163] There are multiple through holes 11, and the multiple through holes 11 are located at one end of the multiple second extensions 402 near the first extension 401.

[0164] In one embodiment, such as Figures 39-41 As shown, the semiconductor device structure also includes a capacitor region 70, which is located at the end of the second extension 402 away from the first extension 401.

[0165] In one embodiment, such as Figures 39-41 As shown, the semiconductor device structure also includes a frame 80, which is located on the side of the capacitor region 70 away from the first extension 401 and is in contact with the capacitor region 70.

[0166] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0167] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this patent should be determined by the appended claims.

Claims

1. A semiconductor device structure, characterized in that, include: A substrate and a stacked structure of alternating interlayer dielectric and conductive layers on the substrate, comprising at least one via penetrating the stacked structure, wherein a first word line, a first channel layer, a second word line, a second channel layer, and a conductive interconnect layer are disposed within the via; wherein, Both the first character line and the second character line extend along a second direction perpendicular to the substrate and are spaced apart along a first direction parallel to the substrate; The first channel layer surrounds the sidewall of the first word line and is broken between adjacent conductive layers; The second channel layer surrounds the sidewall of the second word line and is disconnected between adjacent conductive layers; The conductive connection layer is located between adjacent conductive layers and is integrally connected to both the first character line and the second character line along the first direction.

2. The semiconductor device structure according to claim 1, characterized in that, The semiconductor device structure further includes: a first gate dielectric layer and a second gate dielectric layer; The first gate dielectric layer is located at least between the first channel layer and the first word line; The second gate dielectric layer is located at least between the second channel layer and the second word line.

3. The semiconductor device structure according to claim 1, characterized in that, Each of the conductive layers comprises: A first extension extends along the first direction, and the first extension serves as a bit line; Multiple second extensions are located on opposite sides of the first extension and are integrally connected to the first extension; each second extension extends along a third direction parallel to the substrate, and multiple second extensions located on the same side of the first extension are arranged parallel to each other along the first direction. The number of through holes is multiple, and the multiple through holes are respectively located at one end of the multiple second extensions near the first extension.

4. The semiconductor device structure according to claim 3, characterized in that, The semiconductor device structure further includes a capacitor region located at the end of the second extension away from the first extension.

5. The semiconductor device structure according to claim 4, characterized in that, The semiconductor device structure further includes a frame located on the side of the capacitor region away from the first extension and in contact with the capacitor region.

6. The semiconductor device structure according to any one of claims 1 to 5, characterized in that, The semiconductor device structure further includes multiple isolation structures located between the first word line and the second word line, and between adjacent conductive interconnect layers and on the top conductive interconnect layer.

7. A method for fabricating a semiconductor device structure, characterized in that, include: Provide substrate; A stacked structure is formed on the substrate, the stacked structure comprising conductive layers and interlayer dielectric layers arranged alternately from bottom to top; Form at least one through-hole through the stacked structure; A first word line, a second word line, a first channel layer, a second channel layer, and multiple conductive connection layers are formed within the via; wherein the first word line and the second word line both extend along a second direction perpendicular to the substrate and are spaced apart along a first direction parallel to the substrate; the first channel layer surrounds the sidewall of the first word line and is interrupted between adjacent conductive layers; the second channel layer surrounds the sidewall of the second word line and is interrupted between adjacent conductive layers; the conductive connection layers are located between adjacent conductive layers and are integrally connected to both the first word line and the second word line along the first direction.

8. The method for fabricating a semiconductor device structure according to claim 7, characterized in that, The formation of the stacked structure on the substrate includes: Multiple interlayer dielectric layers are formed on the substrate at intervals along the second direction; Multiple conductive layers are formed between the interlayer dielectric layers and spaced apart along the second direction. The interlayer dielectric layers and the conductive layers are stacked sequentially from bottom to top to form a stacked structure. Each conductive layer includes a first extension extending along the first direction and a plurality of second extensions extending along the third direction. Each second extension is located on opposite sides of the first extension and is integrally connected to the first extension. The plurality of second extensions located on the same side of the first extension are arranged parallel to each other along the first direction. The end of each second extension near the first extension serves as a channel region, and the channel region has an isolation structure.

9. The method for fabricating a semiconductor device structure according to claim 8, characterized in that, The formation of multiple interlayer dielectric layers spaced apart along the second direction on the substrate includes: An initial stacked structure is formed on the substrate, the initial stacked structure including an interlayer dielectric layer and a sacrificial layer stacked sequentially from bottom to top; each interlayer dielectric layer includes: a third extension extending along the first direction and a plurality of fourth extensions extending along the third direction; wherein each of the fourth extensions is located on opposite sides of the third extension and is integrally connected to the third extension, and the plurality of fourth extensions located on the same side of the third extension are arranged in parallel and spaced apart along the first direction; one end of each fourth extension near the third extension serves as a predetermined channel region. A first trench and a second trench are formed within the initial stacked structure, penetrating the preset channel region of each layer along the second direction, and the first trench and the second trench are arranged at intervals along the first direction; A dielectric layer is filled in the first trench and the second trench; The sacrificial layers are removed to form multiple interlayer dielectric layers that are arranged in parallel intervals along the second direction, and the sacrificial layers between the first trench and the second trench are retained as the isolation structures, such that each isolation structure is arranged at intervals along the second direction within the preset trench area.

10. The method for fabricating a semiconductor device structure according to claim 7, characterized in that, After forming a first word line, a second word line, a first channel layer, a second channel layer, and multiple conductive interconnect layers within the via, the method further includes: A capacitor is formed at one end of the stacked structure away from the via along a third direction parallel to the substrate, wherein the third direction intersects the first direction.

11. The method for fabricating a semiconductor device structure according to claim 8, characterized in that, Before forming multiple interlayer dielectric layers spaced apart along the second direction on the substrate, the method further includes: A frame is formed on the opposite sides of the stacked structure.

12. The method for fabricating a semiconductor device structure according to claim 9, characterized in that, The process of forming at least one through-hole through the stacked structure includes: A filling layer is formed in the gap region of the stacked structure; Remove the dielectric layer in the first trench and the second trench; Lateral etching is performed based on the first trench and the second trench to remove the dielectric layer located between adjacent isolation structures and a portion of the interlayer dielectric layer located between each conductive layer, thereby obtaining the via.

13. The method for fabricating a semiconductor device structure according to claim 12, characterized in that, The formation of a first letter line, a second letter line, a first channel layer, a second channel layer, and multiple conductive interconnect layers within the through-hole includes: A channel material layer and a word line conductive layer are sequentially deposited on the inner wall of the through hole; wherein, the word line conductive layer filled in the first trench serves as the first word line, the word line conductive layer filled in the second trench serves as the second word line, and the word line conductive layer filled in the through hole between adjacent conductive layers serves as the conductive connection layer. A third trench is formed in the gap region of the stacked structure, penetrating the dielectric layer. The third trench exposes the channel material layers that are spaced apart along the second direction on the sidewalls of each dielectric layer. The sidewalls of each exposed channel material layer correspond one-to-one with each interlayer dielectric layer. The exposed channel material layers are removed based on the third trench to obtain a channel layer that corresponds one-to-one with each conductive layer; wherein the channel layer located in the first trench is the first channel layer, and the channel layer located in the second trench is the second channel layer.

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