Thin film transistor substrate and electronic device including same

Abstract

The invention discloses a thin film transistor substrate and an electronic device including the same. The thin film transistor substrate comprises a substrate, a first metal layer arranged on the substrate, a second metal layer arranged on the first metal layer, a semiconductor arranged between the substrate and the first metal layer, and a first insulating layer arranged between the first metal layer and the second metal layer. The first metal layer includes a gate pattern, the second metal layer includes a scan line pattern, the semiconductor includes an active region, and the first insulating layer includes a first opening. The gate pattern overlaps the active region, and the scan line pattern of the second metal layer is electrically connected to the gate pattern of the first metal layer through the first opening of the first insulating layer.

Description

Technical Field

[0001] The invention relates to a semiconductor technology, and in particular to a thin film transistor substrate. Background Art

[0002] Liquid crystal display (LCD) has the advantages of low radiation, small size and low energy consumption, and has gradually replaced the traditional cathode ray tube display (CRT), and is widely used in information products such as notebook computers, personal digital assistants (PDA), flat-screen TVs, or mobile phones. However, large-size LCDs have the disadvantage of insufficient pixel charging due to excessive scan line loading. Summary of the invention

[0003] The invention provides a thin film transistor substrate and an electronic device comprising the same.

[0004] According to some embodiments of the present invention, a thin film transistor substrate is provided. The thin film transistor substrate comprises: a substrate, a first metal layer disposed on the substrate, a second metal layer disposed on the first metal layer, a semiconductor disposed between the substrate and the first metal layer, and a first insulating layer disposed between the first metal layer and the second metal layer. The first metal layer comprises a gate pattern, the second metal layer comprises a scan line pattern, the semiconductor comprises an active region, and the first insulating layer comprises a first opening. The gate pattern overlaps the active region, and the scan line pattern of the second metal layer is electrically connected to the gate pattern of the first metal layer through the first opening of the first insulating layer.

[0005] According to some embodiments of the present invention, an electronic device including a thin film transistor substrate is provided. The thin film transistor substrate includes: a substrate, a first metal layer disposed on the substrate, a second metal layer disposed on the first metal layer, a semiconductor disposed between the substrate and the first metal layer, and a first insulating layer disposed between the first metal layer and the second metal layer. The first metal layer includes a gate pattern, the second metal layer includes a scan line pattern, the semiconductor includes an active region, and the first insulating layer includes a first opening. The gate pattern overlaps the active region, and the scan line pattern of the second metal layer is electrically connected to the gate pattern of the first metal layer through the first opening of the first insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0007] Figure 1is a partial top view schematic diagram of a thin film transistor substrate according to an embodiment of the present invention;

[0008] Figure 2 yes Figure 1 A partial cross-sectional schematic diagram of a thin film transistor substrate taken along line II' is shown;

[0009] Figure 3a is a partial top view schematic diagram of a structure in which a light shielding layer is formed on a substrate according to an embodiment of the present invention;

[0010] Figure 3b is an embodiment of the present invention, in Figure 3a A partial top view schematic diagram of a structure in which a semiconductor is further formed on the structure;

[0011] Figure 3c is an embodiment of the present invention, in Figure 3b A partial top view schematic diagram of a structure in which a first metal layer is further formed on the structure;

[0012] Figure 3d is an embodiment of the present invention, in Figure 3c A partial top view schematically showing a structure in which a first insulating layer is further formed on the structure;

[0013] Figure 3e is an embodiment of the present invention, in Figure 3d A partial top view schematically showing a structure in which a second metal layer is further formed on the structure;

[0014] Figure 4 yes Figure 3e The structure shown is a partial cross-sectional schematic diagram taken along line II-II';

[0015] Figure 5a is a partial top view schematic diagram of a thin film transistor substrate according to an embodiment of the present invention;

[0016] Figure 5b yes Figure 5a The structure shown is a partial cross-sectional schematic diagram taken along line III-III';

[0017] Figure 6a is a partial top view schematic diagram of a thin film transistor substrate according to an embodiment of the present invention;

[0018] Figure 6b yes Figure 6a The structure shown is a partial cross-sectional schematic diagram taken along line IV-IV';

[0019] Figure 7 is a partial top view schematic diagram of a thin film transistor substrate according to an embodiment of the present invention;

[0020] Figure 8FIG. 1 is a partial top view of a thin film transistor substrate according to an embodiment of the present invention.

[0021] Explanation of symbols

[0022] 10:Substrate

[0023] 11: First metal layer

[0024] 111: Gate pattern

[0025] 113: first conductive pattern

[0026] 12: Light-shielding layer

[0027] 13: Second metal layer

[0028] 131: Scan line pattern

[0029] 133: second conductive pattern

[0030] 133A: Part 1

[0031] 133B: Part 2

[0032] 133C: Part 3

[0033] 15: Semiconductors

[0034] 151:Ontology

[0035] 151G: Active area

[0036] 151D: Source / drain region

[0037] 153:End

[0038] 16: First interlayer insulation layer

[0039] 17: First insulation layer

[0040] 18: Second interlayer insulation layer

[0041] 19: Second insulation layer

[0042] 20: Thin Film Transistor

[0043] VH1, VH2, VH3, VH4, VH5: Open

[0044] 31: First electrode layer

[0045] 33: Second electrode layer

[0046] 35: The third insulation layer DETAILED DESCRIPTION

[0047] The following is a detailed description of the electronic device of an embodiment of the present invention. It should be understood that the following description provides many different embodiments or examples for implementing different modes of some embodiments of the present invention. The specific components and arrangements described below are only for simple and clear description of some embodiments of the present invention. Of course, these are only for example and not for limitation of the present invention. In addition, repeated numbers or marks may be used in different embodiments. These repetitions are only for simple and clear description of some embodiments of the present invention, and do not represent any correlation between the different embodiments and / or structures discussed.

[0048] Here, the terms "about", "approximately", and "generally" generally mean within 10%, within 5%, within 3%, within 2%, within 1%, or within 0.5% of a given value or range. The quantities given here are approximate quantities, that is, in the absence of specific description of "about", "approximately", and "generally", the meaning of "about", "approximately", and "generally" can still be implied. Here, the term "a to b" means greater than or equal to a and less than or equal to b.

[0049] It is understood that although the terms "first", "second", "third", etc. may be used herein to describe various components, constituents, regions, layers, and / or parts, these components, constituents, regions, layers, and / or parts should not be limited by these terms, and these terms are only used to distinguish different components, constituents, regions, layers, and / or parts. Therefore, a first component, component, region, layer, and / or part discussed below may be referred to as a second component, component, region, layer, and / or part without departing from the teachings of some embodiments of the present invention.

[0050] In some embodiments of the present invention, relative terms such as "lower", "upper", "horizontal", "vertical", "below", "above", "top", "bottom", etc. should be understood as the orientations depicted in the paragraph and the related drawings. Such relative terms are only for the convenience of explanation and do not mean that the device described therein must be manufactured or operated in a specific orientation. It is understood that if the device in the drawings is turned upside down, the components described on the "lower" side will become components on the "upper" side. The embodiments of the present invention can be used in conjunction with the attached drawings. Figure 1 It is also understood that the drawings of the present invention are also considered as part of the specification. It should be understood that the drawings of the present invention are not drawn according to scale, and in fact, the size of the components may be arbitrarily enlarged or reduced to clearly show the features of the present invention.

[0051] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as those commonly understood by those skilled in the art to which this disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present invention, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present invention.

[0052] Certain words are used in the specification and claims of the present invention to refer to specific components. It should be understood by those skilled in the art that electronic equipment manufacturers may refer to the same components by different names. This document does not intend to distinguish between components that have the same function but different names. In the following specification and claims, the words "including" and "comprising" are open-ended words and should be interpreted as "including but not limited to..."

[0053] The electronic device of the present invention may include a display device, an antenna device, a sensing device, a touch display, a packaging device, a curved display or a non-rectangular electronic device (free shape display), but is not limited thereto. The electronic device may be a bendable or flexible electronic device. The antenna device may be, for example, a liquid crystal antenna, but is not limited thereto. The antenna device may, for example, include an antenna splicing device, but is not limited thereto. The packaging device may be a packaging device suitable for wafer-level packaging (WLP) technology or panel-level packaging (PLP) technology, such as a chip first manufacturing process or a chip later manufacturing process. It should be noted that the electronic device may be any combination of the foregoing, but is not limited thereto. In addition, the appearance of the electronic device may be rectangular, circular, polygonal, a shape with curved edges or other suitable shapes. The electronic device may include electronic components. The electronic components may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. The diode may include a light emitting diode or a photodiode. The light emitting diode may include, for example, an organic light emitting diode (OLED), a sub-millimeter light emitting diode (mini LED), a micro LED, or a quantum dot light emitting diode (quantum dot LED), but is not limited thereto. The electronic device may have a peripheral system such as a drive system, a control system, a light source system, a shelf system, etc. to support a display device, an antenna device, or a splicing device.

[0054] Figure 1FIG. 1 is a partial top view of a thin film transistor substrate according to an embodiment of the present invention. Figure 2 yes Figure 1 The thin film transistor substrate shown is a partial cross-sectional schematic diagram taken along line II'. The thin film transistor substrate of the present invention includes a substrate 10, a first metal layer 11 disposed on the substrate 10, a second metal layer 13 disposed on the first metal layer 11, a semiconductor 15 disposed between the substrate 10 and the first metal layer 11, and a first insulating layer 17 disposed between the first metal layer 11 and the second metal layer 13. The first metal layer 11 includes a gate pattern 111, the second metal layer 13 includes a scan line pattern 131, the semiconductor 15 includes an active region 151G, and the first insulating layer 17 includes a first opening VH1. The gate pattern 111 can overlap the active region 151G, and the thin film transistor 20 includes a semiconductor 15 to be connected to the gate pattern 111. The scan line pattern 131 of the second metal layer 13 is electrically connected to the gate pattern 111 of the first metal layer 11 through the first opening VH1 of the first insulating layer 17. In some embodiments, the thin film transistor substrate may further include a light shielding layer 12 disposed between the substrate 10 and the semiconductor 15, and the light shielding layer 12 may overlap the active region 151G. In some embodiments, the thin film transistor substrate may further include a second insulating layer 19 disposed on the second metal layer 13, a first electrode layer 31 disposed on the second insulating layer 19, a second electrode layer 33 disposed on the first electrode layer 31, and a third insulating layer 35 disposed between the first electrode layer 31 and the second electrode layer 33, as shown in FIG. Figure 1 as well as Figure 2 As shown in the figure, "overlap" in this article refers to the overlap in the normal direction of the substrate.

[0055] The material of the second insulating layer 19 may include nitride, oxide, oxynitride, perfluoroalkoxyalkane (PFA), resin, photosensitive polyimide (PSPI), polyimide (PI), Ajinomoto build-up film (ABF), polybenzoxazole (PBO), other suitable materials, or any combination thereof, but the present invention is not limited thereto. The second insulating layer 19 may have a single-layer structure or a multi-layer stacked structure. For example, the second insulating layer 19 may include a single-layer silicon oxide, or the second insulating layer 19 may include a silicon nitride layer and a silicon oxide layer stacked along the normal direction of the substrate, but is not limited thereto. In some embodiments, the second insulating layer 19 may include a third opening VH3. The third opening VH3 exposes a portion of the second metal layer 13.

[0056] The first electrode layer 31 is disposed on the second insulating layer 19 and may include a fourth opening VH4. In some embodiments, the fourth opening VH4 may be larger than the third opening VH3 and may be located in the fourth opening VH4 together with the third opening VH3. In some embodiments, the fourth opening VH4 may expose a portion of the second metal layer 13. The material of the first electrode layer 31 may include a transparent conductive metal oxide. Examples of the transparent conductive metal oxide may include indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), indium tin oxide (ITO), indium zinc oxide (IZO), fluorine-doped tin oxide, graphene nanoribbons, or metal nanowires, but the present invention is not limited thereto.

[0057] The material of the third insulating layer 35 may include nitride, oxide, oxynitride, perfluoroalkoxyalkane (PFA), resin, photosensitive polyimide (PSPI), polyimide (PI), Ajinomoto build-up film (ABF), polybenzoxazole (PBO), other suitable materials, or any combination thereof, but the present invention is not limited thereto. The third insulating layer 35 may have a single-layer structure or a multi-layer stacked structure. For example, the third insulating layer 35 may include a single-layer silicon nitride, or the third insulating layer 35 may include a silicon nitride layer and a silicon oxide layer stacked along the normal direction of the substrate, but is not limited thereto. The third insulating layer 35 may have a fifth opening VH5. In some embodiments, the fifth opening VH5 may be smaller than the fourth opening VH4 and the third opening VH3 and be located in the third opening VH3 and the fourth opening VH4, such as Figure 2 The fifth opening VH5 may expose a portion of the second metal layer 13 .

[0058] The material of the second electrode layer 33 may include a transparent conductive metal oxide. Examples of the transparent conductive metal oxide may include indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), indium tin oxide (ITO), indium zinc oxide (IZO), fluorine-doped tin oxide, graphene nanoribbons or metal nanowires, but the present invention is not limited thereto. The materials of the first electrode layer 31 and the second electrode layer 33 may be the same or different. In some embodiments, the second electrode layer 33 has a grid-like structure, that is, in a top view of the thin film transistor substrate, the second electrode layer 33 has a grid-like structure, such as Figure 1 In some embodiments, the second electrode layer 33 is electrically connected to the semiconductor 15 through the fifth opening VH5 and the second metal layer 13 .

[0059] Figures 3a to 3eIt is a partial top view of a structure in which a light shielding layer 12 , a semiconductor 15 , a first metal layer 11 , a first insulating layer 17 , and a second metal layer 13 are sequentially formed on a substrate 10 according to an embodiment of the present invention. Figure 4 yes Figure 3e The structure shown is a schematic cross-sectional view taken along line II-II'. Figures 3a to 3e as well as Figure 4 The structure of a thin film transistor substrate according to an embodiment of the present invention is further described.

[0060] Figure 3a 1 is a schematic top view of a structure in which a light shielding layer 12 is formed on a substrate 10 according to an embodiment of the present invention. The light shielding layer 12 may include a plurality of island patterns, such as Figure 3a As shown, but the present invention is not limited thereto. In some embodiments, the substrate 10 may include a transparent or opaque organic material or an inorganic material, and may also include a hard material or a flexible material. Examples of organic materials may include polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), liquid crystal polymer (LCP), other known suitable materials or combinations thereof, but the present invention is not limited thereto. Examples of inorganic materials may include dielectric materials or metal materials, but the present invention is not limited thereto. Examples of hard materials may include glass, quartz, sapphire, ceramics or plastics, or any suitable material. The "flexible material" herein refers to a material that can be bent, bent, folded, rolled, flexed, stretched and / or other similar deformations. Examples of flexible materials may include one of the above-mentioned organic materials, but the flexible materials referred to in the present invention are not limited to the above-mentioned materials. The substrate may further include a through hole penetrating the substrate along the normal direction of the substrate, and a driving circuit, a compensation circuit, an optical fiber or a wire material may be disposed in the through hole, but the present invention is not limited thereto. The light shielding layer 12 may include a black matrix, a metal, wherein the material of the black matrix may include an organic insulating material (e.g., a photosensitive resin) or a metal material, but the present invention is not limited thereto.

[0061] The semiconductor 15 is formed on Figure 3a and at least partially overlap the light shielding layer 12, such as Figure 3b As shown. The semiconductor 15 may include a body 151 and an end 153. The body 151 may have various shapes. In some embodiments, the body 151 may have an L-shaped structure, such as Figure 3bAs shown, but the present invention is not limited thereto. In some embodiments, the body 151 may have an I-shaped structure, a U-shaped structure, a Y-shaped structure, or a T-shaped structure, but the present invention is not limited thereto. The "L-shaped structure", "I-shaped structure", "U-shaped structure", "Y-shaped structure", or "T-shaped structure" herein refers to an L-shape, an I-shape, a U-shape, a Y-shape, or a T-shape in a top view perpendicular to the thin film transistor substrate. The body 151 is connected to the end 153 along an extension direction. In one embodiment, in a direction perpendicular to the extension direction, the width of the end 153 of the semiconductor 15 is greater than the width of the body 151 of the semiconductor 15, but the present invention is not limited thereto. Specifically, in some embodiments, in an embodiment where the body 151 has an L-shaped structure, the semiconductor 15 may include a body 151 having a horizontal portion extending along a first direction D1 and an end 153 connected to the horizontal portion and a vertical portion extending along a second direction D2 and an end 153 connected to the vertical portion, such as Figure 3b As shown. In the second direction D2 perpendicular to the first direction D1, the width W1 of the end portion 153 connected to the horizontal portion of the body 151 is greater than the width W2 of the horizontal portion of the body 151. In the first direction D1 perpendicular to the second direction D2, the width W1' of the end portion 153 connected to the vertical portion of the body 151 is greater than the width W2' of the vertical portion of the body 151. The width W1 of the end portion 153 connected to the horizontal portion of the body 151 may be the same as or different from the width W1' of the end portion 153 connected to the vertical portion of the body 151. The width W2 of the horizontal portion of the body 151 may be the same as or different from the width W2' of the vertical portion of the body 151.

[0062] The body 151 of the semiconductor 15 may include a source / drain region 151D and an active region 151G disposed between the source / drain region 151D. The body 151 of the semiconductor 15 may include a plurality of active regions 151G according to the overlapped portions with the first metal layer 11 and the second metal layer 13. For example, Figure 1A semiconductor 15 of the thin film transistor substrate shown includes two active regions 151G, but the present invention is not limited thereto. The semiconductor 15 may include amorphous silicon (A-Si), low temperature polysilicon (LTPS), indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), or other metal oxide semiconductor materials commonly used in the art, or any combination thereof, but the present invention is not limited thereto. The source / drain region 151D may be doped with n-type dopants (e.g., phosphorus, arsenic) and / or p-type dopants (e.g., boron or BF2). The source / drain region 151D may be formed by implanting dopant atoms, in-situ doping epitaxial growth, other suitable techniques, or a combination of the foregoing.

[0063] In some embodiments, a first interlayer insulating layer 16 is further formed between the semiconductor 15 and the light shielding layer 12. Figure 1 as well as Figure 4 As shown. In some embodiments, the material of the first interlayer insulating layer 16 may include nitride, oxide, oxynitride, perfluoroalkoxyalkane (PFA), resin, photosensitive polyimide (PSPI), polyimide (PI), Ajinomoto build-up film (ABF), polybenzoxazole (PBO), other suitable materials, or any combination thereof, but the present invention is not limited thereto. The first interlayer insulating layer 16 may have a single-layer structure or a multi-layer stacked structure. For example, the first interlayer insulating layer 16 may include a single layer of silicon oxide, or the first interlayer insulating layer 16 may include a silicon nitride layer and a silicon oxide layer stacked along the normal direction of the substrate, but is not limited thereto.

[0064] The first metal layer 11 is formed on Figure 3b In terms of structure, Figure 3c The first metal layer 11 includes a gate pattern 111 and a first conductive pattern 113 that at least partially overlaps the active region 151G of the semiconductor 15. The gate pattern 111 may have various shapes. In some embodiments, the gate pattern 111 may have a U-shaped structure, such as Figure 3c As shown, the present invention is not limited thereto. The gate pattern 111 may have an I-shaped structure, an L-shaped structure, a Y-shaped structure, or a T-shaped structure. The first conductive pattern 113 and the gate pattern 111 are electrically insulated from each other and are spaced apart by a distance. In some embodiments, the first conductive pattern 113 does not overlap with the semiconductor 15. The first conductive pattern 113 may have various shapes. In some embodiments, the first conductive pattern 113 may have an I-shaped structure, such as Figure 3c As shown, the present invention is not limited thereto. The first conductive pattern 113 may have a U-shaped structure, an L-shaped structure, a Y-shaped structure, or a T-shaped structure. The definition of "L-shaped structure", "I-shaped structure", "U-shaped structure", "Y-shaped structure", or "T-shaped structure" herein is the same as the above definition.

[0065] The gate pattern 111 constitutes a gate electrode of the thin film transistor 20. The semiconductor 15 constitutes an active layer of the thin film transistor 20. That is, the thin film transistor 20 at least includes a portion of the semiconductor 15 and the gate pattern 111 of the first metal layer 11.

[0066] In some embodiments, the material of the first metal layer 11 may include copper (Cu), aluminum (Al), molybdenum (Mo), tungsten (W), gold (Au), chromium (Cr), nickel (Ni), platinum (Pt), titanium (Ti), other suitable metal materials or combinations thereof. In some embodiments, the first metal layer 11 may have a single-layer structure or a multi-layer stacked structure. For example, the first metal layer 11 may include a single layer of metal copper, or the first metal layer 11 may include a metal titanium layer and a metal copper layer stacked along the normal direction of the substrate, but is not limited thereto.

[0067] In some embodiments, a second interlayer insulating layer 18 is further formed between the semiconductor 15 and the first metal layer 11 to electrically insulate the first metal layer 11 from the semiconductor 15. Figure 1 as well as Figure 4 As shown. In some embodiments, the material of the second interlayer insulating layer 18 may include nitride, oxide, oxynitride, perfluoroalkoxyalkane (PFA), resin, photosensitive polyimide (PSPI), polyimide (PI), Ajinomoto build-up film (ABF), polybenzoxazole (PBO), other suitable materials, or any combination thereof, but the present invention is not limited thereto. The second interlayer insulating layer 18 may have a single-layer structure or a multi-layer stacked structure. For example, the second interlayer insulating layer 18 may include a single layer of silicon oxide, or the second interlayer insulating layer 18 may include a silicon nitride layer and a silicon oxide layer stacked along the normal direction of the substrate, but is not limited thereto.

[0068] The first insulating layer 17 is formed on Figure 3c The structure is covered with the first metal layer 11, such as Figure 3c as well as Figure 4As shown. The first insulating layer 17 includes a first opening VH1. The first opening VH1 penetrates the first insulating layer 17. In some embodiments, the first opening VH1 may overlap a portion of the first metal layer 11. The portion of the first metal layer 11 is exposed through the first opening VH1. In some embodiments, the thin film transistor substrate includes a second opening VH2. The second opening VH2 penetrates the first insulating layer 17 and the second interlayer insulating layer 18. In some embodiments, the second opening VH2 may overlap an end portion 153 of the semiconductor 15. The end portion 153 of the semiconductor 15 is exposed through the second opening VH2.

[0069] In some embodiments, the material of the first insulating layer 17 may include nitride, oxide, oxynitride, perfluoroalkoxyalkane (PFA), resin, photosensitive polyimide (PSPI), polyimide (PI), Ajinomoto build-up film (ABF), polybenzoxazole (PBO), other suitable materials, or any combination thereof, but the present invention is not limited thereto. The first insulating layer 17 may have a single-layer structure or a multi-layer stacked structure. For example, the first insulating layer 17 may include a single-layer silicon oxide, or the first insulating layer 17 may include a silicon nitride layer and a silicon oxide layer stacked along the normal direction of the substrate, but is not limited thereto.

[0070] The second metal layer 13 is formed on Figure 3d In terms of structure, Figure 3e The second metal layer 13 includes a scan line pattern 131 and a second conductive pattern 133. The scan line pattern 131 and the second conductive pattern 133 are electrically insulated from each other and are spaced apart by a distance. The scan line pattern 131 at least partially overlaps with the active region 151G of the semiconductor 15 and the gate pattern 111 of the first metal layer 11. In some embodiments, the scan line pattern 131 at least partially overlaps with the first conductive pattern 113 of the first metal layer 11 (see Figure 1 ). In some embodiments, the scan line pattern 131 extends along an extension direction. In a direction perpendicular to the extension direction, the width of at least the portion of the scan line pattern 131 overlapping the gate pattern 111 is greater than the width of the remaining portion of the scan line pattern 131. Figure 4 As shown, the scan line pattern 131 is electrically connected to the gate pattern 111 of the first metal layer 11 through the first opening VH1 of the first insulating layer 17 .

[0071] In some embodiments, the second conductive pattern 133 includes a first portion 133A overlapping the first metal layer 11 but not overlapping the semiconductor 15, a second portion 133B overlapping the semiconductor 15 but not overlapping the first metal layer 11, and a third portion 133C overlapping the first metal layer 11 and the semiconductor 15. In some embodiments, the first portion 133A is electrically connected to the first conductive pattern 113 of the first metal layer 11 through the first opening VH1 of the first insulating layer 17. The second portion 133B is electrically connected to the semiconductor 15 through the second opening VH2. More specifically, the second portion 133B of the second conductive pattern 133 is electrically connected to the source / drain region 151D of the semiconductor 15 through the second opening VH2, as shown in FIG. Figure 4 The third portion 133C is electrically connected to the first conductive pattern 113 and the semiconductor 15 through the first opening VH1 and the second opening VH2, respectively. Figure 4 As shown, the first portion 133A and the third portion 133C of the second conductive pattern 133 are electrically connected through the first conductive pattern 113 of the first metal layer 11. In some embodiments, the second conductive pattern 133 may include a portion of a data line to provide a data signal to the semiconductor layer 15. In some embodiments, the first portion 133A and a portion of the third portion 133C of the second conductive pattern 133 may be used as a data line to provide a data signal to the semiconductor layer 15.

[0072] In some embodiments, the material of the second metal layer 13 may include a metal material having a resistance greater than 0 and less than 7 μΩ·m. The material of the second metal layer 13 may include aluminum (Al). The material of the second metal layer 13 may be the same as or different from the material of the first metal layer 11. In some embodiments, the second metal layer 13 may have a single-layer structure or a multi-layer stacked structure. For example, the second metal layer 13 may include a single layer of metal aluminum, but is not limited thereto.

[0073] The second insulating layer 19, the first electrode layer 31 disposed on the second insulating layer 19, the second electrode layer 33 disposed on the first electrode layer 31, and the third insulating layer 35 disposed between the first electrode layer 31 and the second electrode layer 33 may be further formed on the Figure 3e The thin film transistor substrate is prepared by using a structure of, but the present invention is not limited thereto. In some embodiments, the second insulating layer 19, the first electrode layer 31, the second electrode layer 33, the third insulating layer 35 or any combination thereof may be omitted.

[0074] Above Figures 1 to 4 The example of a semiconductor having an L-shaped structure in a thin film transistor substrate having two active regions is used as an example, but the present invention is not limited thereto. In some embodiments, the body of the semiconductor may have a U-shaped structure. In some embodiments, the semiconductor may have three active regions. Figures 5a to 8 Other aspects of the thin film transistor substrate of the present invention are described.

[0075] Figure 5a FIG. 1 is a partial top view of a thin film transistor substrate according to an embodiment of the present invention. Figure 5b yes Figure 5a The structure shown is a partial cross-sectional schematic diagram taken along line III-III'. In addition to the first metal layer 11, the second metal layer 13, the semiconductor 15, and the first insulating layer 17 having a single-layer structure, the other components of the thin film transistor substrate are the same as those of the reference Figures 1 to 4 The thin film transistor substrates are substantially the same, so only the structures of the first metal layer 11 , the second metal layer 13 , and the semiconductor 15 are described below.

[0076] The semiconductor 15 is formed on the substrate 10, the first metal layer 11 is formed on the semiconductor 15, and the second metal layer 13 is formed on the first metal layer 11. Figure 5b shown.

[0077] like Figure 5a As shown, the body 151 of the semiconductor 15 has a U-shaped structure. The first metal layer 11 includes a gate pattern 111 and a first conductive pattern 113 that at least partially overlap the active region 151G of the semiconductor 15, and the gate pattern 111 has an I-shaped structure. The second metal layer 13 includes a scan line pattern 131 and a second conductive pattern 133, wherein a portion of the scan line pattern 131 overlaps the active region 151G of the semiconductor 15. According to the overlap of the semiconductor 15 with the first metal layer 11 and the second metal layer 13, the body 151 of the semiconductor 15 may include three active regions 151G, such as Figure 5a The gate pattern 111 and a portion of the scan line pattern 131 form a gate electrode of the thin film transistor 20. The semiconductor 15 forms an active layer of the thin film transistor 20. Figure 5a In the illustrated embodiment, the scan line pattern 131 of the second metal layer 13 is electrically connected to the gate pattern 111 of the first metal layer 11 through the first opening VH1 of the first insulating layer 17 .

[0078] Figure 6a FIG. 1 is a partial top view of a thin film transistor substrate according to an embodiment of the present invention. Figure 6b yes Figure 6a The structure shown is a cross-sectional schematic diagram taken along line IV-IV'. Except that the body 151 of the semiconductor 15 has a U-shaped structure, the gate pattern 111 of the first metal layer 11 has an L-shaped structure, and the first insulating layer 17 has a single-layer structure, the other components of the thin film transistor substrate are the same as those of the reference Figures 1 to 4 The thin film transistor substrates are substantially the same and will not be described in detail herein. Figure 71 is a partial top view of a thin film transistor substrate according to an embodiment of the present invention. Except that the body 151 of the semiconductor 15 has a U-shaped structure and the gate pattern 111 of the first metal layer 11 has an L-shaped structure, the other components of the thin film transistor substrate are the same as those of the reference Figures 1 to 4 The thin film transistor substrates are substantially the same and will not be described in detail herein. Figure 8 1 is a partial top view schematic diagram of a thin film transistor substrate according to an embodiment of the present invention. Except that the body 151 of the semiconductor 15 has an L-shaped structure and the gate pattern 111 of the first metal layer 11 has an L-shaped structure, the other components of the thin film transistor substrate are the same as those of the reference Figures 1 to 4 The thin film transistor substrates are substantially the same and will not be described in detail herein.

[0079] Another aspect of the present invention provides an electronic device including a thin film transistor substrate including a thin film transistor.

[0080] The structure of the thin film transistor substrate including the thin film transistor is similar to the structure of any of the above-mentioned thin film transistor substrates, so it is not described in detail here.

[0081] Through the above structure, the thin film transistor substrate according to the present invention can significantly reduce the scan line load and is suitable for large-size panels. In addition, the thin film transistor substrate of the present invention can be prepared with a smaller number of photomasks, thereby simplifying the manufacturing process or reducing the manufacturing cost. The electronic device including the thin film transistor substrate of the present invention can also have the advantages of low scan line load, low manufacturing cost, or simplified manufacturing process.

[0082] Although the embodiments of the present invention and their advantages have been disclosed as above, it should be understood that any person skilled in the art can make changes, substitutions and modifications without departing from the spirit and scope of the present invention. In addition, the scope of protection of the present invention is not limited to the manufacturing process, machine, manufacturing, material composition, device, method and steps in the specific embodiments described in the specification. Any person skilled in the art can understand the current or future developed manufacturing process, machine, manufacturing, material composition, device, method and steps from the disclosure of some embodiments of the present invention. As long as the same functions can be implemented in the embodiments described herein or the same results can be obtained, they can be used according to some embodiments of the present invention. Therefore, the scope of protection of the present invention includes the above-mentioned manufacturing process, machine, manufacturing, material composition, device, method and steps. In addition, each claim constitutes a separate embodiment, and the scope of protection of the present invention also includes the combination of each claim and embodiment. The features between the embodiments can be mixed and matched as much as they do not violate the spirit of the invention or conflict.

Claims

1. A thin film transistor substrate, characterized in that: The thin film transistor substrate comprises: substrate; A first metal layer, disposed on the substrate and comprising a gate pattern; A second metal layer, disposed on the first metal layer and comprising a scan line pattern; A semiconductor disposed between the substrate and the first metal layer and including an active region; and A first insulating layer, disposed between the first metal layer and the second metal layer and comprising a first opening; The gate pattern overlaps the active region, and The scan line pattern of the second metal layer is electrically connected to the gate pattern of the first metal layer through the first opening.

2. The thin film transistor substrate according to claim 1, wherein: The semiconductor includes a body and an end, wherein the body has an L-shaped structure, an I-shaped structure, a U-shaped structure, a Y-shaped structure, or a T-shaped structure.

3. The thin film transistor substrate according to claim 2, wherein: The body is connected to the end portion along an extending direction, and in a direction perpendicular to the extending direction, a width of the end portion of the semiconductor is greater than a width of the body of the semiconductor.

4. The thin film transistor substrate according to claim 1, wherein: The first metal layer further includes a first conductive pattern which is electrically insulated from the gate pattern and spaced apart by a distance, and the first conductive pattern does not overlap with the semiconductor.

5. The thin film transistor substrate according to claim 4, wherein: The second metal layer further includes a second conductive pattern, and the second conductive pattern includes a first portion overlapping the first metal layer but not the semiconductor, a second portion overlapping the semiconductor but not the first metal layer, and a third portion overlapping the first metal layer and the semiconductor.

6. The thin film transistor substrate according to claim 5, characterized in that: The first portion is electrically connected to the first conductive pattern of the first metal layer through the first opening of the first insulating layer.

7. The thin film transistor substrate according to claim 1, wherein: The thin film transistor substrate further comprises a first electrode layer disposed on the second metal layer and a second electrode layer disposed on the first electrode layer, wherein the second electrode layer is electrically connected to the semiconductor.

8. The thin film transistor substrate according to claim 1, wherein: The second metal layer includes a metal material with a resistance greater than 0 and less than 7 μΩ·m.

9. An electronic device comprising a thin film transistor substrate, characterized in that: The thin film transistor substrate comprises: substrate; A first metal layer, disposed on the substrate and comprising a gate pattern; A second metal layer, disposed on the first metal layer and comprising a scan line pattern; A semiconductor disposed between the substrate and the first metal layer and including an active region; and A first insulating layer, disposed between the first metal layer and the second metal layer and comprising a first opening; The gate pattern overlaps the active region, and The scan line pattern of the second metal layer is electrically connected to the gate pattern of the first metal layer through the first opening.

10. The electronic device according to claim 9, wherein: The second metal layer includes a metal material with a resistance greater than 0 and less than 7 μΩ·m.

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