Pixel circuit, display panel and display device

Abstract

The invention provides a pixel circuit, a display panel and display equipment, which can be applied to the technical field of display. The pixel circuit comprises: a driving sub-circuit configured to generate a driving current based on a first power supply voltage from a first power supply and a data signal from a data end under the control of a first control signal from a first control end and a second control signal from a second control end, and provide the driving current to a first node; the control sub-circuit is configured to provide driving current to at least one of the second node and the third node under the control of a third control signal from a third control end and a fourth control signal from a fourth control end; the first end of the first light-emitting element is electrically connected to the second node, and the second end of the first light-emitting element is electrically connected to a second power supply; the first end of the second light-emitting element is electrically connected to the third node, and the second end of the second light-emitting element is electrically connected to the second power supply.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and more specifically, to a pixel circuit, a display panel, and a display device. Background Art

[0002] With the development of display technology and semiconductor technology, the demand for display functions by end users has diversified. For example, in the use of in-vehicle display devices, mobile phones, tablets, computers and other electronic devices, end users require that the display panels of these devices can provide active anti-peeping, dual-viewing angle display and other functions. Summary of the invention

[0003] The present disclosure provides a pixel circuit, a display panel and a display device.

[0004] One aspect of the present disclosure provides a pixel circuit, including: a driving subcircuit, configured to generate a driving current based on a first power supply voltage from a first power supply and a data signal from a data terminal under the control of a first control signal from a first control terminal and a second control signal from a second control terminal, and provide the above-mentioned driving current to a first node; a control subcircuit, configured to provide the above-mentioned driving current to at least one of the second node and the third node under the control of a third control signal from a third control terminal and a fourth control signal from a fourth control terminal; a first light-emitting element, a first terminal of the first light-emitting element is electrically connected to the above-mentioned second node, and a second terminal of the first light-emitting element is electrically connected to the second power supply; and a second light-emitting element, a first terminal of the second light-emitting element is electrically connected to the above-mentioned third node, and a second terminal of the second light-emitting element is electrically connected to the above-mentioned second power supply.

[0005] According to an embodiment of the present disclosure, the control subcircuit includes a first transistor and a second transistor; wherein the gate of the first transistor is electrically connected to the third control terminal, the first pole of the first transistor is electrically connected to the first node, and the second pole of the first transistor is electrically connected to the third node; the gate of the second transistor is electrically connected to the fourth control terminal, the first pole of the second transistor is electrically connected to the third node, and the second pole of the second transistor is electrically connected to the second node.

[0006] According to an embodiment of the present disclosure, the control subcircuit includes a first transistor and a second transistor; wherein the gate of the first transistor is electrically connected to the third control terminal, the first pole of the first transistor is electrically connected to the first node, and the second pole of the first transistor is electrically connected to the third node; the gate of the second transistor is electrically connected to the fourth control terminal, the first pole of the second transistor is electrically connected to the first node, and the second pole of the second transistor is electrically connected to the second node.

[0007] According to an embodiment of the present disclosure, the above-mentioned control subcircuit is also electrically connected to the first reset terminal and the fifth control terminal, respectively; the above-mentioned control subcircuit is also configured to reset the potential of at least one of the above-mentioned second node and the above-mentioned third node using the first reset signal from the above-mentioned first reset terminal under the control of the fifth control signal from the above-mentioned fifth control terminal.

[0008] According to an embodiment of the present disclosure, the above-mentioned control subcircuit also includes a third transistor; the gate of the above-mentioned third transistor is electrically connected to the above-mentioned fifth control terminal, the first electrode of the above-mentioned third transistor is electrically connected to the above-mentioned second node, and the second electrode of the above-mentioned third transistor is electrically connected to the above-mentioned first reset terminal.

[0009] According to an embodiment of the present disclosure, the above-mentioned control subcircuit also includes a fourth transistor; the gate of the above-mentioned fourth transistor is electrically connected to the above-mentioned fifth control terminal, the first electrode of the above-mentioned fourth transistor is electrically connected to the above-mentioned third node, and the second electrode of the above-mentioned fourth transistor is electrically connected to the above-mentioned second node.

[0010] According to an embodiment of the present disclosure, the above-mentioned control subcircuit also includes a fourth transistor; the gate of the above-mentioned fourth transistor is electrically connected to the above-mentioned fifth control terminal, the first electrode of the above-mentioned fourth transistor is electrically connected to the above-mentioned third node, and the second electrode of the above-mentioned fourth transistor is electrically connected to the above-mentioned first reset terminal.

[0011] According to an embodiment of the present disclosure, the driving subcircuit includes a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor and a second capacitor; wherein the gate of the fifth transistor is electrically connected to the fourth node, the first electrode of the fifth transistor is electrically connected to the first power supply, and the second electrode of the fifth transistor is electrically connected to the first node; the gate of the sixth transistor is electrically connected to the second control terminal, the first electrode of the sixth transistor is electrically connected to the fourth node, and the second electrode of the sixth transistor is electrically connected to the first node; the gate of the seventh transistor is electrically connected to the first control terminal, the first electrode of the seventh transistor is electrically connected to the fifth node, and the second electrode of the seventh transistor is electrically connected to the data terminal; the first end of the first capacitor is electrically connected to the fourth node, and the second end of the first capacitor is electrically connected to the fifth node; and the first end of the second capacitor is electrically connected to the first power supply, and the second end of the second capacitor is electrically connected to the fourth node.

[0012] According to an embodiment of the present disclosure, the above-mentioned driving sub-circuit is also electrically connected to the second reset terminal and the sixth control terminal, respectively; the above-mentioned driving sub-circuit is also configured to reset the potential of the above-mentioned first capacitor using the second reset signal from the above-mentioned second reset terminal under the control of the sixth control signal from the above-mentioned sixth control terminal.

[0013] According to an embodiment of the present disclosure, the driving subcircuit further includes an eighth transistor; the gate of the eighth transistor is electrically connected to the sixth control terminal, the first electrode of the eighth transistor is electrically connected to the second reset terminal, and the second electrode of the eighth transistor is electrically connected to the fifth node.

[0014] According to an embodiment of the present disclosure, the driving subcircuit includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a first capacitor; wherein the gate of the fifth transistor is electrically connected to the first control terminal, the first electrode of the fifth transistor is electrically connected to the fourth node, and the second electrode of the fifth transistor is electrically connected to the data terminal; the gate of the sixth transistor is electrically connected to the fifth node, the first electrode of the sixth transistor is electrically connected to the fourth node, and the second electrode of the sixth transistor is electrically connected to the first node; the gate of the seventh transistor is electrically connected to the first control terminal, the first electrode of the seventh transistor is electrically connected to the fifth node, and the second electrode of the seventh transistor is electrically connected to the first node; the gate of the eighth transistor is electrically connected to the second control terminal, the first electrode of the eighth transistor is electrically connected to the first power supply, and the second electrode of the eighth transistor is electrically connected to the fourth node; and the first end of the first capacitor is electrically connected to the first power supply, and the second end of the first capacitor is electrically connected to the fifth node.

[0015] According to an embodiment of the present disclosure, the above-mentioned driving sub-circuit is also electrically connected to the second reset terminal and the sixth control terminal, respectively; the above-mentioned driving sub-circuit is also configured to reset the potential of the above-mentioned first capacitor using the second reset signal from the above-mentioned second reset terminal under the control of the sixth control signal from the above-mentioned sixth control terminal.

[0016] According to an embodiment of the present disclosure, the driving subcircuit further includes a ninth transistor; the gate of the ninth transistor is electrically connected to the sixth control terminal, the first electrode of the ninth transistor is electrically connected to the fifth node, and the second electrode of the ninth transistor is electrically connected to the second reset terminal.

[0017] Another aspect of the present disclosure provides a display panel including a display area and a non-display area, wherein a plurality of pixel circuits as described above are arranged in the display area.

[0018] Another aspect of the present disclosure provides a display device including the display panel as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0020] Figure 1A A schematic diagram of a unit pixel array arranged according to Real-RGB is shown.

[0021] Figure 1B A display schematic diagram of a segmented unit pixel is shown.

[0022] Figure 2 A schematic diagram of a pixel circuit according to an embodiment of the present disclosure is schematically shown.

[0023] Figure 3A The structural diagram of the control subcircuit according to the embodiment of the present disclosure is schematically shown.

[0024] Figure 3B The schematic diagram shows the structure of a control subcircuit according to another embodiment of the present disclosure.

[0025] Figure 4A A schematic diagram of a pixel circuit according to another embodiment of the present disclosure is schematically shown.

[0026] Figure 4B The schematic diagram shows the structure of a control subcircuit according to another embodiment of the present disclosure.

[0027] Figure 4C The schematic diagram shows the structure of a control subcircuit according to another embodiment of the present disclosure.

[0028] Figure 4D The schematic diagram shows the structure of a control subcircuit according to another embodiment of the present disclosure.

[0029] Figure 4E The schematic diagram shows the structure of a control subcircuit according to another embodiment of the present disclosure.

[0030] Figure 5A The schematic diagram shows the structure of a driving sub-circuit according to an embodiment of the present disclosure.

[0031] Figure 5B A schematic diagram of a pixel circuit according to another embodiment of the present disclosure is schematically shown.

[0032] Figure 5C The schematic diagram shows the structure of a driving sub-circuit according to another embodiment of the present disclosure.

[0033] Fig. 6A The schematic diagram shows the structure of a pixel circuit according to an embodiment of the present disclosure.

[0034] Figure 6B The working timing diagram of the pixel circuit according to the embodiment of the present disclosure is schematically shown.

[0035] Fig. 7AA schematic structural diagram of a pixel circuit according to another embodiment of the present disclosure is shown schematically.

[0036] Figure 7B The working timing diagram of the pixel circuit according to another embodiment of the present disclosure is schematically shown.

[0037] Fig. 8A A schematic structural diagram of a pixel circuit according to another embodiment of the present disclosure is shown schematically.

[0038] Figure 8B A schematic structural diagram of a pixel circuit according to another embodiment of the present disclosure is shown schematically.

[0039] Figure 8C A schematic structural diagram of a pixel circuit according to another embodiment of the present disclosure is shown schematically.

[0040] Fig.8D The working timing diagram of the pixel circuit according to another embodiment of the present disclosure is schematically shown.

[0041] Fig.9A The schematic diagram shows the structure of a driving sub-circuit according to another embodiment of the present disclosure.

[0042] Fig. 9B The schematic diagram shows the structure of a driving sub-circuit according to another embodiment of the present disclosure.

[0043] Fig. 10A A schematic structural diagram of a pixel circuit according to another embodiment of the present disclosure is shown schematically.

[0044] Fig. 10B The working timing diagram of the pixel circuit according to another embodiment of the present disclosure is schematically shown.

[0045] Fig. 10C A schematic structural diagram of a pixel circuit according to another embodiment of the present disclosure is shown schematically.

[0046] Fig. 10D A schematic structural diagram of a pixel circuit according to another embodiment of the present disclosure is shown schematically.

[0047] Fig. 10E A schematic structural diagram of a pixel circuit according to another embodiment of the present disclosure is shown schematically.

[0048] Fig.10F A schematic structural diagram of a pixel circuit according to another embodiment of the present disclosure is shown schematically.

[0049] Fig.11 A schematic diagram of a display panel according to an embodiment of the present disclosure is schematically shown.

[0050] Fig.12A schematic diagram of a display device according to an embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical scheme and advantages of the embodiments of the present disclosure clearer, the technical scheme in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of them. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work belong to the scope of protection of the present disclosure. It should be noted that throughout the drawings, the same elements are represented by the same or similar figure marks. In the following description, some specific embodiments are only used for descriptive purposes and should not be understood as any limitation to the present disclosure, but are only examples of the embodiments of the present disclosure. Conventional structures or configurations will be omitted when they may cause confusion in the understanding of the present disclosure. It should be noted that the shapes and sizes of the components in the figures do not reflect the actual size and proportion, but only illustrate the contents of the embodiments of the present disclosure.

[0052] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the usual meanings understood by those skilled in the art. The words "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components.

[0053] In addition, in the description of the embodiments of the present disclosure, the term "electrically connected" may refer to two components being directly connected, or may refer to two components being connected via one or more other components. In addition, the two components may be connected or coupled via a wired or wireless manner.

[0054] The source and drain of the switch transistor used in the embodiment of the present disclosure are symmetrical, so the source and drain can be interchanged. In the embodiment of the present disclosure, according to its function, one of the source and drain can be called the first electrode, and the other of the source and drain can be called the second electrode.

[0055] It should be noted that in the description of the embodiments of the present disclosure, the symbol VDD can represent both the first power supply and the first power supply voltage provided by the first power supply. Similarly, the symbol CON1 can represent both the first control terminal and the first control signal provided by the first control terminal; the symbol CON2 can represent both the second control terminal and the second control signal provided by the second control terminal; the symbol CON3 can represent both the third control terminal and the third control signal provided by the third control terminal; the symbol CON4 can represent both the fourth control terminal and the fourth control signal provided by the fourth control terminal; the symbol Vdata can represent both the data terminal and the data signal provided by the data terminal, and so on. The following embodiments are the same and will not be described in detail.

[0056] In order to realize active anti-peeping, dual-viewing angle display and other display functions, an optional implementation method is to divide the sub-pixels in the deployed unit pixel to form a unit pixel containing double the number of sub-pixels. For example, the unit pixel before division may include 3 sub-pixels for displaying red, green and blue, respectively, and the unit pixel after division may include 2 sub-pixels for displaying red, 2 sub-pixels for displaying green and 2 sub-pixels for displaying blue. Optionally, the sub-pixels in the unit pixel can also be divided into a shared sub-pixel and multiple anti-peeping sub-pixels. For example, the unit pixel before division may include a sub-pixel A for displaying red, and for the sub-pixel A, the sub-pixel A can be divided into sub-pixel A1, sub-pixel A2 and sub-pixel A3, wherein sub-pixel A1 can be emitted when realizing the shared display function, and sub-pixel A2 and sub-pixel A3 can be emitted when realizing dual-viewing angle display, active anti-peeping, and shared display functions. For example, sub-pixel A2 can provide a display function of displaying to the left and preventing peeping to the right, and sub-pixel A3 can provide a display function of displaying to the right and preventing peeping to the left. When sub-pixel A2 and sub-pixel A3 emit light based on the same screen, they can provide a shared display function. The scheme for dividing sub-pixels is not limited here.

[0057] The following describes the solution of the related art by taking the example of dividing a sub-pixel in a unit pixel into two sub-pixels.

[0058] Figure 1A A schematic diagram of a unit pixel array arranged according to Real-RGB is shown.

[0059] As shown in FIG1 , the unit pixel array may include a plurality of segmented unit pixels 110. Each segmented unit pixel 110 may include a sub-pixel 111, a sub-pixel 112, a sub-pixel 113, a sub-pixel 114, a sub-pixel 115, and a sub-pixel 116, wherein the sub-pixel 111 and the sub-pixel 112 may be used to display the same color, for example, red, the sub-pixel 113 and the sub-pixel 114 may be used to display the same color, for example, green, and the sub-pixel 115 and the sub-pixel 116 may be used to display the same color, for example, blue.

[0060] Sub-pixel 111, sub-pixel 112, sub-pixel 113, sub-pixel 114, sub-pixel 115, and sub-pixel 116 may be anti-peeping sub-pixels. When working in the anti-peeping display mode or the dual-view display mode, sub-pixel 111, sub-pixel 113, and sub-pixel 115 may be used to display image A in the first direction, but not to display image A in the second direction, and sub-pixel 112, sub-pixel 114, and sub-pixel 116 may be used to display image B in the second direction, but not to display image B in the first direction.

[0061] Alternatively, sub-pixel 111, sub-pixel 113, and sub-pixel 115 may be anti-peeping sub-pixels, and sub-pixel 112, sub-pixel 114, and sub-pixel 116 may be shared sub-pixels. When working in the shared display mode, only sub-pixel 111, sub-pixel 113, and sub-pixel 115 may be turned on, or sub-pixel 111, sub-pixel 112, sub-pixel 113, sub-pixel 114, sub-pixel 115, and sub-pixel 116 may be turned on at the same time, and sub-pixel 111, sub-pixel 112, sub-pixel 113, sub-pixel 114, sub-pixel 115, and sub-pixel 116 may display the same picture. When working in the anti-peeping display mode, only sub-pixel 112, sub-pixel 114, and sub-pixel 116 may be turned on.

[0062] A shielding layer may be provided above the sub-pixel, and the shielding layer may be provided with a black matrix. The number of black matrices provided in the shielding layer is not limited here. For example, the number of black matrices may be consistent with the number of sub-pixels included in the segmented unit pixel. For example, if the segmented unit pixel may include 6 sub-pixels, then the shielding layer may include 6 black matrices in the area opposite to the unit pixel. Alternatively, the number of black matrices provided in the shielding layer may also be consistent with the number of anti-peeping sub-pixels included in the segmented unit pixel, and so on.

[0063] The positive projection of the black matrix on the unit pixel array can be located on one side of the sub-pixel, so that the black matrix can prevent the light emitted by the sub-pixel from propagating in the direction of the side. For example, the positive projection of the black matrix a1 on the unit pixel array can be located on the left side of the sub-pixel a2, and the black matrix a1 can prevent the light emitted by the sub-pixel a2 from propagating to the left. According to the needs of the actual application scenario, the relative position relationship between the black matrix and the sub-pixel can be set by itself, and is not limited here.

[0064] Optionally, if the sub-pixels obtained by segmentation in the unit pixel include shared sub-pixels, an opening may be provided in the orthographic projection area of ​​the shared sub-pixels on the shielding layer so that light emitted by the shared sub-pixels can freely pass through the shielding layer without being blocked by the black matrix.

[0065] For example, the shielding layer includes six black matrices corresponding to sub-pixel 111, sub-pixel 112, sub-pixel 113, sub-pixel 114, sub-pixel 115, and sub-pixel 116, respectively. Figure 1B A display schematic diagram of a segmented unit pixel is shown.

[0066] like Figure 1BAs shown, the positive projections of three of the six black matrices corresponding to each segmented unit pixel 110 included in the shielding layer on the unit pixel array can be located on the right side of sub-pixel 111, sub-pixel 113, and sub-pixel 115, respectively. Therefore, the three black matrices can be used to prevent the light emitted by sub-pixel 111, sub-pixel 113, and sub-pixel 115 from propagating to the right, that is, sub-pixel 111, sub-pixel 113, and sub-pixel 115 can only display the picture A from the left perspective. The positive projections of the other three of the six black matrices corresponding to each segmented unit pixel 110 included in the shielding layer on the unit pixel array can be located on the left side of sub-pixel 112, sub-pixel 113, and sub-pixel 116, respectively. Therefore, the other three black matrices can be used to prevent the light emitted by sub-pixel 112, sub-pixel 114, and sub-pixel 116 from propagating to the left, that is, sub-pixel 112, sub-pixel 114, and sub-pixel 116 can only display the picture B from the right perspective. By segmenting the unit pixels and shielding the black matrix in the shielding layer, a left-right dual display effect can be achieved. The left side of the sub-pixel can be represented as one side along the row direction of the unit pixel array, and the right side of the sub-pixel can be represented as the other side along the row direction of the unit pixel array. Optionally, in other examples, the positive projection of the black matrix on the unit pixel array can also be located on one side or the other side of the sub-pixel along the column direction of the unit pixel array, or, it can also be located on one side or the other side of the sub-pixel in other directions different from the row and column directions of the unit pixel array, which will not be described in detail here.

[0067] In the related art, one sub-pixel is generally implemented by one pixel circuit, and the number of sub-pixels contained in the divided unit pixel is twice the number of sub-pixels contained in the original unit pixel. Without reducing the resolution, it is difficult to deploy more pixel circuits in the unit pixel. Therefore, in order to reduce the pixel circuits that need to be deployed, one pixel circuit can be used to implement multiple sub-pixels for displaying the same color.

[0068] In view of this, an embodiment of the present disclosure provides a pixel circuit, which may include: a driving subcircuit, configured to generate a driving current and provide the driving current to a first node based on a first power supply voltage from a first power supply and a data signal from a data terminal under the control of a first control signal from a first control terminal and a second control signal from a second control terminal; a control subcircuit, configured to provide the driving current to at least one of a second node and a third node under the control of a third control signal from a third control terminal and a fourth control signal from a fourth control terminal; a first light-emitting element, a first end of the first light-emitting element being electrically connected to the second node, and a second end of the first light-emitting element being electrically connected to the second power supply; and a second light-emitting element, a first end of the second light-emitting element being electrically connected to the third node, and a second end of the second light-emitting element being electrically connected to the second power supply.

[0069] Figure 2 A schematic diagram of a pixel circuit according to an embodiment of the present disclosure is schematically shown.

[0070] like Figure 2 As shown, the pixel circuit 200 may include a driving sub-circuit 10 , a control sub-circuit 20 , a first light-emitting element 30 , and a second light-emitting element 40 .

[0071] The driving sub-circuit 10 may be electrically connected to the first power supply VDD, the data terminal Vdata, the first control terminal CON1, and the second control terminal CON2, respectively, and may be electrically connected to the control sub-circuit 20 through the first node N1. Under the control of the first control signal CON1 from the first control terminal CON1 and the second control signal CON2 from the second control terminal CON2, the driving sub-circuit 10 may generate a driving current Id based on a first power supply voltage VDD from the first power supply VDD and a data signal Vdata from the data terminal Vdata, and provide the driving current Id to the first node N1.

[0072] The driving sub-circuit 10 may be configured with at least a driving transistor. By providing timing signals to the first control terminal CON1 and the second control terminal CON2, the driving sub-circuit 10 may form a driving current Id between the source and drain of the driving transistor based on the first power supply voltage VDD and the data signal Vdata, and provide the driving current Id to the first node N1.

[0073] The control subcircuit 20 may be electrically connected to the third control terminal CON3 and the fourth control terminal CON4, respectively, and electrically connected to the first light emitting element 30 through the second node N2, and electrically connected to the second light emitting element 40 through the third node N3. Under the control of the third control signal CON3 from the third control terminal CON3 and the fourth control signal CON4 from the fourth control terminal CON4, the control subcircuit 20 may provide the driving current Id to at least one of the second node N2 and the third node N3, thereby providing the driving current Id to at least one of the first light emitting element 30 and the second light emitting element 40.

[0074] The gating control logic for the driving current Id in the control subcircuit 20 is not limited herein. For example, the control subcircuit 20 may provide the driving current Id to the first light-emitting element 30 when the third control signal CON3 is valid, and provide the driving current Id to the second light-emitting element 40 when the fourth control signal CON4 is valid. For another example, the control subcircuit 20 may provide the driving current Id to the first light-emitting element 30 when the third control signal CON3 is valid, and provide the driving current Id to the second light-emitting element 40 when both the third control signal CON3 and the fourth control signal CON4 are valid.

[0075] The first end of the first light emitting element 30 may be electrically connected to the second node N2, and the second end may be electrically connected to the second power source VSS. The first end of the second light emitting element 40 may be electrically connected to the third node N3, and the second end may be electrically connected to the second power source VSS.

[0076] Compared with a first power supply voltage VDD provided by the first power supply VDD and a second power supply voltage VSS provided by the second power supply VSS, the first power supply voltage VDD may be a relatively high voltage and the second power supply voltage VSS may be a relatively low voltage.

[0077] The first light-emitting element 30 and the second light-emitting element 40 may be any current-driven light-emitting device, such as OLED (Organic Light-Emitting Diode), AMOLED (Active-matrix organic light-emitting diode), etc. Optionally, the first end of the first light-emitting element 30 or the second light-emitting element 40 may be represented as the anode of the first light-emitting element 30 or the second light-emitting element 40, and the second end of the first light-emitting element 30 or the second light-emitting element 40 may be represented as the cathode of the first light-emitting element 30 or the second light-emitting element 40.

[0078] According to an embodiment of the present disclosure, the driving subcircuit can generate a driving current based on the timing signals provided in the first control terminal and the second control terminal, and provide the driving current to the control subcircuit. The control subcircuit can provide the driving current to at least one of the first light-emitting element and the second light-emitting element based on the different potential states of the third control signal and the fourth control signal, so that the pixel circuit can control the first light-emitting element and the second light-emitting element to emit light synchronously or asynchronously, so that the pixel circuit can realize display functions such as anti-peeping and dual-viewing.

[0079] Optionally, in the embodiment of the present disclosure, the light-emitting elements included in the pixel circuit are the first light-emitting element 30 and the second light-emitting element 40, which is only an example. According to actual needs, by adjusting the control subcircuit, the control subcircuit can also control the drive current to be provided to three or more light-emitting elements, which is not described in detail here. The following takes the light-emitting elements included in the pixel circuit as the first light-emitting element 30 and the second light-emitting element 40 as an example to further illustrate the pixel circuit of the embodiment of the present disclosure.

[0080] Figure 3A The structural diagram of the control subcircuit according to the embodiment of the present disclosure is schematically shown.

[0081] like Figure 3AAs shown, the control subcircuit 20 may include a first transistor T1 and a second transistor T2. The first transistor T1 and the second transistor T2 may both be P-type switch transistors.

[0082] A gate of the first transistor T1 is electrically connected to the third control terminal CON3 , a first electrode of the first transistor T1 is electrically connected to the first node N1 , and a second electrode of the first transistor T1 is electrically connected to the third node N3 .

[0083] A gate of the second transistor T2 is electrically connected to the fourth control terminal CON4 , a first electrode of the second transistor T2 is electrically connected to the third node N3 , and a second electrode of the second transistor T2 is electrically connected to the second node N2 .

[0084] When the third control signal CON3 is at a low level and the fourth control signal CON4 is at a high level, the driving current Id can be transmitted from the first node N1 to the third node N3 via the first transistor T1, that is, the driving current Id can be provided to the second light emitting unit 40 to drive the second light emitting unit 40 to emit light. At this time, the first light emitting unit 30 is turned off, the second light emitting unit 40 is turned on, and the pixel circuit can work as an anti-peeping mode.

[0085] When the third control signal CON3 and the fourth control signal CON4 are both at low levels, the driving current Id can also be transmitted from the first node N1 to the second node N2 via the first transistor T1 and the second transistor T2, that is, the driving current Id can be provided to the second light emitting unit 40 and the first light emitting unit 30, respectively, to drive the second light emitting unit 40 and the first light emitting unit 30 to emit light. At this time, the first light emitting unit 30 and the second light emitting unit 40 are both turned on, and the pixel circuit can work as a dual-viewing display mode.

[0086] In such Figure 3A In the circuit structure of the control subcircuit 20 shown, the activation of the first light-emitting unit 30 and the second light-emitting unit 40 requires controlling the first transistor T1 to be turned on, so that the second light-emitting unit 40 cannot be turned on and off independently, that is, when the first light-emitting unit 30 needs to be turned on, the second light-emitting unit 40 will also be turned on, which affects the flexibility of the control of the pixel circuit, making the pixel circuit suitable for application scenarios dominated by the dual-viewing angle display mode.

[0087] Figure 3B The schematic diagram shows the structure of a control subcircuit according to another embodiment of the present disclosure.

[0088] like Figure 3B As shown, the control subcircuit 20 may include a first transistor T1 and a second transistor T2. The first transistor T1 and the second transistor T2 may both be P-type switch transistors.

[0089] The gate of the first transistor T1 is electrically connected to the third control terminal CON3 , the first electrode of the first transistor T1 is electrically connected to the first node N1 , and the second electrode of the first transistor T1 is electrically connected to the third node N3 .

[0090] A gate of the second transistor T2 is electrically connected to the fourth control terminal CON4 , a first electrode of the second transistor T2 is electrically connected to the first node N1 , and a second electrode of the second transistor T2 is electrically connected to the second node N2 .

[0091] When the third control signal CON3 is at a low level, the driving current Id can be transmitted from the first node N1 to the third node N3 via the first transistor T1, that is, the driving current Id can be provided to the second light-emitting unit 40 to drive the second light-emitting unit 40 to emit light. When the third control signal CON4 is at a low level, the driving current Id can be transmitted from the first node N1 to the second node N2 via the second transistor T2, that is, the driving current Id can be provided to the first light-emitting unit 30 to drive the first light-emitting unit 30 to emit light. Therefore, the first light-emitting unit 30 and the second light-emitting unit 40 can be controlled separately, and the pixel circuit can be applied to the application scenarios of anti-peeping and dual display, and the corresponding application scenarios can be switched arbitrarily.

[0092] The first light-emitting unit 30 and the second light-emitting unit 40 are usually light-emitting diode devices, and since diode devices have a capacitance effect, voltage usually remains in the first light-emitting unit 30 and the second light-emitting unit 40 after they finish emitting light. Optionally, in order to eliminate the residual voltage, a reset structure may be provided in the control subcircuit 20, and before the pixel circuit controls the first light-emitting unit 30 and / or the second light-emitting unit 40 to emit light, the reset structure may reset the potential at the first light-emitting unit 30 and / or the second light-emitting unit 40.

[0093] Figure 4A A schematic diagram of a pixel circuit according to another embodiment of the present disclosure is schematically shown.

[0094] like Figure 4A As shown, based on the pixel circuit 200, the control sub-circuit 20 of the pixel circuit 400 can also be electrically connected to the first reset terminal Vinit1 and the fifth control terminal CON5 respectively.

[0095] Under the control of the fifth control signal CON5 from the fifth control terminal CON5, the potential of at least one of the second node N2 and the third node N3 is reset using the first reset signal Vinit1 from the first reset terminal Vinit1.

[0096] The first reset signal Vinit1 may be a signal having a lower potential level with respect to the first power supply voltage VDD.

[0097] Figure 4B The schematic diagram shows the structure of a control subcircuit according to another embodiment of the present disclosure.

[0098] like Figure 4B As shown, Figure 3A The control subcircuit shown may further include a third transistor T3. The third transistor T3 may be a P-type switch transistor.

[0099] A gate of the third transistor T3 is electrically connected to the fifth control terminal CON5 , a first electrode of the third transistor T3 is electrically connected to the second node N2 , and a second electrode of the third transistor T3 is electrically connected to the first reset terminal Vinit1 .

[0100] When resetting the first light emitting element 30 , the fifth control signal CON5 is at a low level to control the third transistor T3 to be turned on, and the first reset signal Vinit1 is provided to the second node N2 via the third transistor T3 to reset the first light emitting element 30 .

[0101] When resetting the second light-emitting element 40, the fifth control signal CON5 is at a low level to control the third transistor T3 to be turned on, the fourth control signal CON4 is at a low level to control the second transistor T2 to be turned on, and the first reset signal Vinit1 can also be provided to the third node N3 via the third transistor T3 and the second transistor T2 to reset the second light-emitting element 40.

[0102] Figure 4C The schematic diagram shows the structure of a control subcircuit according to another embodiment of the present disclosure.

[0103] like Figure 4C As shown, similarly, Figure 3B The control subcircuit shown may further include a third transistor T3. The third transistor T3 may be a P-type switch transistor.

[0104] A gate of the third transistor T3 is electrically connected to the fifth control terminal CON5 , a first electrode of the third transistor T3 is electrically connected to the second node N2 , and a second electrode of the third transistor T3 is electrically connected to the first reset terminal Vinit1 .

[0105] When resetting the first light emitting element 30 , the fifth control signal CON5 is at a low level to control the third transistor T3 to be turned on, and the first reset signal Vinit1 is provided to the second node N2 via the third transistor T3 to reset the first light emitting element 30 .

[0106] When the second light-emitting element 40 is reset, the fifth control signal CON5 is at a low level and controls the third transistor T3 to be turned on, the fourth control signal CON4 is at a low level and controls the second transistor T2 to be turned on, the third control signal CON3 is at a low level and controls the first transistor T1 to be turned on, and the first reset signal Vinit1 can also be provided to the third node N3 via the third transistor T3, the second transistor T2 and the first transistor T1 to reset the second light-emitting element 40.

[0107] In the case of Figure 4B and Figure 4C When the control subcircuit shown performs a reset process, each light-emitting element is usually reset individually. Optionally, a transistor can be added to the control subcircuit so that the first light-emitting element 30 and the second light-emitting element 40 can be reset in the same period of time, thereby reducing the time required for resetting and extending the charging time of the device, thereby improving image quality and reducing afterimages.

[0108] Figure 4D The schematic diagram shows the structure of a control subcircuit according to another embodiment of the present disclosure.

[0109] like Figure 4D As shown, Figure 4C The control subcircuit shown may further include a fourth transistor T4. The fourth transistor T4 may be a P-type switching transistor.

[0110] A gate of the fourth transistor T4 is electrically connected to the fifth control terminal CON5 , a first electrode of the fourth transistor T4 is electrically connected to the third node N3 , and a second electrode of the fourth transistor T4 is electrically connected to the second node N2 .

[0111] When performing the reset process, the fifth control signal CON5 is at a high level and controls the third transistor T3 and the fourth transistor T4 to be turned on. The first reset signal Vinit1 can be provided to the second node N2 via the third transistor T3 to reset the first light-emitting element 30, and provided to the third node N3 via the third transistor T3 and the fourth transistor T4 to reset the second light-emitting element 40.

[0112] Figure 4E The schematic diagram shows the structure of a control subcircuit according to another embodiment of the present disclosure.

[0113] like Figure 4E As shown, Figure 4C The control subcircuit shown may further include a fourth transistor T4. The fourth transistor T4 may be a P-type switching transistor.

[0114] A gate of the fourth transistor T4 is electrically connected to the fifth control terminal CON5 , a first electrode of the fourth transistor T4 is electrically connected to the third node N3 , and a second electrode of the fourth transistor T4 is electrically connected to the first reset terminal Vinit1 .

[0115] When performing the reset process, the fifth control signal CON5 is at a high level and controls the third transistor T3 and the fourth transistor T4 to be turned on. The first reset signal Vinit1 can be provided to the second node N2 via the third transistor T3 to reset the first light-emitting element 30; the first reset signal Vinit1 can also be provided to the third node N3 via the fourth transistor T4 to reset the second light-emitting element 40.

[0116] Optionally, the driving sub-circuit 10 may be implemented based on a non-separation circuit.

[0117] Figure 5A The schematic diagram shows the structure of a driving sub-circuit according to an embodiment of the present disclosure.

[0118] like Figure 5A As shown, the non-separated driving sub-circuit may include a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8 and a first capacitor C1. The fifth transistor T5 to the eighth transistor T8 may all be P-type transistors, and the fifth transistor T5, the seventh transistor T7 and the eighth transistor T8 may be switch transistors, and the sixth transistor T6 may be a driving transistor.

[0119] A gate of the fifth transistor T5 is electrically connected to the first control terminal CON1 , a first electrode of the fifth transistor T5 is electrically connected to the fourth node N4 , and a second electrode of the fifth transistor T5 is electrically connected to the data terminal Vdata.

[0120] A gate electrode of the sixth transistor T6 is electrically connected to the fifth node N5 , a first electrode of the sixth transistor T6 is electrically connected to the fourth node N4 , and a second electrode of the sixth transistor T6 is electrically connected to the first node N1 .

[0121] A gate of the seventh transistor T7 is electrically connected to the first control terminal CON1 , a first electrode of the seventh transistor T7 is electrically connected to the fifth node N5 , and a second electrode of the seventh transistor T7 is electrically connected to the first node N1 .

[0122] A gate of the eighth transistor T8 is electrically connected to the second control terminal CON2 , a first electrode of the eighth transistor T8 is electrically connected to the first power source VDD, and a second electrode of the eighth transistor T8 is electrically connected to the fourth node N4 .

[0123] A first end of the first capacitor C1 is electrically connected to the first power source VDD, and a second end of the first capacitor C1 is electrically connected to the fifth node N5.

[0124] When the driving sub-circuit 10 is working, the first control signal CON1 is at a low level to control the fifth transistor T5 and the seventh transistor T7 to be turned on, and the data signal Vdata is charged to the first capacitor C1 through the transistor T5, the sixth transistor T6 and the transistor T7. After the charging of the first capacitor C1 is completed, the first control signal CON1 is at a high level to control the fifth transistor T5 and the seventh transistor T7 to be turned off, and the second control signal is at a low level to control the eighth transistor T8 to be turned on, and the charge stored in the first capacitor C1 can be applied to the gate of the sixth transistor T6, so that the sixth transistor T6 is turned on, thereby forming a driving current Id between the source and drain of the sixth transistor T6.

[0125] Optionally, similar to the control subcircuit 20, the first capacitor C1 usually has residual voltage after discharge. In order to eliminate the residual voltage, a reset structure can be provided in the driving subcircuit 10. Before the first capacitor C1 is charged next time, the reset structure can reset the potential of the first capacitor.

[0126] Figure 5B A schematic diagram of a pixel circuit according to another embodiment of the present disclosure is schematically shown.

[0127] like Figure 5B As shown, based on the pixel circuit 400, the driving sub-circuit 10 of the pixel circuit 500 can also be electrically connected to the second reset terminal Vinit2 and the sixth control terminal CON6 respectively.

[0128] Under the control of the sixth control signal CON6 from the sixth control terminal CON6, the driving sub-circuit 10 can use the second reset signal Vinit2 from the second reset terminal Vinit2 to reset the potential of the first capacitor C1.

[0129] The second reset signal Vinit2 may be a signal with a lower potential level than the first power supply voltage VDD. The second reset signal Vinit2 and the first reset signal Vinit1 may be the same signal or different signals, which is not limited here.

[0130] Optionally, in some embodiments, the second reset signal Vinit2 may also be used to perform a reset process for the second light emitting unit 40 and / or the first light emitting unit 30 .

[0131] Figure 5C The schematic diagram shows the structure of a driving sub-circuit according to another embodiment of the present disclosure.

[0132] like Figure 5C As shown, Figure 5A The driving subcircuit shown may further include a ninth transistor T9. The ninth transistor T9 may be a P-type switching transistor.

[0133] A gate of the ninth transistor T9 is electrically connected to the sixth control terminal CON6 , a first electrode of the ninth transistor T9 is electrically connected to the fifth node N5 , and a second electrode of the ninth transistor T9 is electrically connected to the second reset terminal Vinit2 .

[0134] Before the driving sub-circuit 10 works, the sixth control signal CON6 is at a low level to control the ninth transistor T9 to be turned on, and the second reset signal Vinit2 can be provided to the fifth node N5 via the ninth transistor T9 to reset the first capacitor C1.

[0135] The following combination Figure 3A to Figure 3B , Figure 4A to Figure 4E and Figure 5A to Figure 5C The circuit structures shown respectively are used to further illustrate the pixel circuit of the embodiment of the present disclosure.

[0136] Fig. 6A The schematic diagram shows the structure of a pixel circuit according to an embodiment of the present disclosure.

[0137] like Fig. 6A As shown, the pixel circuit 600 may include a first transistor T1 to a third transistor T3, a fifth transistor T5 to a ninth transistor T9, a first capacitor C1, a first light emitting diode LED1 and a second light emitting diode LED2. Among them, the first transistor T1 to the third transistor T3, the fifth transistor T5, the seventh transistor T7 to the ninth transistor T9 may be a P-type switching transistor, and the sixth transistor T6 may be a P-type driving transistor.

[0138] The gate of the first transistor T1 is electrically connected to the third control terminal CON3, the first electrodes of the first transistor T1 are electrically connected to the first node N1, and the second electrodes of the first transistor T1 are electrically connected to the third node N3. The gate of the second transistor T2 is electrically connected to the fourth control terminal CON4, the first electrode of the second transistor T2 is electrically connected to the third node N3, and the second electrode of the second transistor T2 is electrically connected to the second node N2. The gate of the third transistor T3 is electrically connected to the fifth control terminal CON5, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the first reset terminal Vinit1. The gate of the fifth transistor T5 is electrically connected to the first control terminal CON1, the first electrode of the fifth transistor T5 is electrically connected to the fourth node N4, and the second electrode of the fifth transistor T5 is electrically connected to the data terminal Vdata. The gate of the sixth transistor T6 is electrically connected to the fifth node N5, the first electrode of the sixth transistor T6 is electrically connected to the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected to the first node N1. The gate of the seventh transistor T7 is electrically connected to the first control terminal CON1, the first electrode of the seventh transistor T7 is electrically connected to the fifth node N5, and the second electrode of the seventh transistor T7 is electrically connected to the first node N1. The gate of the eighth transistor T8 is electrically connected to the second control terminal CON2, the first electrode of the eighth transistor T8 is electrically connected to the first power supply VDD, and the second electrode of the eighth transistor T8 is electrically connected to the fourth node N4. The gate of the ninth transistor T9 is electrically connected to the sixth control terminal CON6, the first electrode of the ninth transistor T9 is electrically connected to the fifth node N5, and the second electrode of the ninth transistor T9 is electrically connected to the second reset terminal Vinit2. The first end of the first capacitor C1 is electrically connected to the first power supply VDD, and the second end of the first capacitor C1 is electrically connected to the fifth node N5. The anode of the first light-emitting diode LED1 is electrically connected to the second node N2, and the cathode of the first light-emitting diode LED1 is electrically connected to the second power supply VSS. The anode of the second light-emitting diode LED2 is electrically connected to the third node N3, and the cathode of the second light-emitting diode LED2 is electrically connected to the second power supply VSS.

[0139] According to an embodiment of the present disclosure, when the pixel circuit 600 is required to work in a shared display mode, the first light-emitting diode LED1 and the second light-emitting diode LED2 can be controlled to emit light. When the pixel circuit 600 is required to work in an anti-peeping display mode, the first light-emitting diode LED1 can be controlled to be turned off, while the second light-emitting diode LED2 can be controlled to emit light. The pixel circuit 600 can use fewer transistors to implement functions such as shared display and anti-peeping display, thereby supporting higher image resolution, and can simplify the control logic of the reset process and reduce control costs.

[0140] Figure 6B The working timing diagram of the pixel circuit according to the embodiment of the present disclosure is schematically shown.

[0141] like Figure 6B As shown, in stages P1 to P3, the pixel circuit 600 can work based on the anti-peeping mode, and in stages P4 to P6, the pixel circuit 600 can work based on the dual-viewing mode.

[0142] In the P1 stage, the sixth control signal CON6 is at a low level and controls the ninth transistor T9 to be turned on, so as to pull the potential of the fifth node N5 down to the second reset signal Vinit2, so that the first capacitor C1 can be reset by the second reset signal Vinit2; the fifth control signal CON5 is at a low level and controls the third transistor T3 to be turned on, so as to pull the potential of the second node N2 down to the first reset signal Vinit1, so that the first light-emitting diode LED1 can be reset by the first reset signal Vinit1; the fourth control signal CON4 is at a low level and controls the second transistor T2 to be turned on, so as to pull the potential of the third node N3 down to the first reset signal Vinit1, so that the second light-emitting diode LED2 can be reset by the first reset signal Vinit1.

[0143] In the P2 phase, the fourth control signal CON4, the fifth control signal CON5 and the sixth control signal CON6 are all high level to control the second transistor T2, the third transistor T3 and the ninth transistor T9 to be turned off. The first control signal CON1 is low level to control the fifth transistor T5 and the seventh transistor T7 to be turned on, and the data signal Vdata is charged to the first capacitor C1 through the transistor T5, the sixth transistor T6 and the transistor T7. When Vgs of the driving transistor T6 = V(Q1)-V(Q2) = V(Q1)-Vdata = Vth, the sixth transistor T6 is turned off, and the voltage maintained by the first capacitor C1 is V(N5) = Vdata + Vth.

[0144] In the P3 phase, the first control signal CON1 is at a high level to control the fifth transistor T5 and the seventh transistor T7 to be turned off, the second control signal CON2 is at a low level to control the eighth transistor T8 to be turned on, and the third control signal CON3 is at a low level to control the first transistor T1 to be turned on. Driven by the first power supply voltage VDD and the voltage V(N5) of the first capacitor C1, a driving current Id is formed between the source and drain of the sixth transistor T6, and the driving current Id can be provided to the second light emitting diode LED2 via the first transistor T1 and the third node N3 to control the second light emitting diode LED2 to emit light, thereby realizing the anti-peeping display function of the pixel circuit 600.

[0145] In the P4 stage, the sixth control signal CON6 is at a low level and controls the ninth transistor T9 to be turned on, so as to pull the potential of the fifth node N5 down to the second reset signal Vinit2, so that the first capacitor C1 can be reset by the second reset signal Vinit2; the fifth control signal CON5 is at a low level and controls the third transistor T3 to be turned on, so as to pull the potential of the second node N2 down to the first reset signal Vinit1, so that the first light-emitting diode LED1 can be reset by the first reset signal Vinit1; the fourth control signal CON4 is at a low level and controls the second transistor T2 to be turned on, so as to pull the potential of the third node N3 down to the first reset signal Vinit1, so that the second light-emitting diode LED2 can be reset by the first reset signal Vinit1.

[0146] In the P5 phase, the fourth control signal CON4, the fifth control signal CON5 and the sixth control signal CON6 are all high level to control the second transistor T2, the third transistor T3 and the ninth transistor T9 to be turned off. The first control signal CON1 is low level to control the fifth transistor T5 and the seventh transistor T7 to be turned on, and the data signal Vdata is charged to the first capacitor C1 through the transistor T5, the sixth transistor T6 and the transistor T7. When Vgs of the driving transistor T6 = V(Q1)-V(Q2) = V(Q1)-Vdata = Vth, the sixth transistor T6 is turned off, and the voltage maintained by the first capacitor C1 is V(N5) = Vdata + Vth.

[0147] In the P6 phase, the first control signal CON1 is at a high level to control the fifth transistor T5 and the seventh transistor T7 to be turned off, the second control signal CON2 is at a low level to control the eighth transistor T8 to be turned on, the third control signal CON3 is at a low level to control the first transistor T1 to be turned on, and the fourth control signal CON4 is at a low level to control the second transistor T2 to be turned on. Driven by the first power supply voltage VDD and the voltage V(N5) of the first capacitor C1, a driving current Id is formed between the source and drain of the sixth transistor T6, and the driving current I can be provided to the second light emitting diode LED2 via the first transistor T1 and the third node N3, and provided to the first light emitting diode LED1 via the first transistor T2, the second transistor T2 and the second node N2, so as to control the first light emitting diode LED1 and the second light emitting diode LED2 to emit light, thereby realizing the dual-view display function of the pixel circuit 600.

[0148] Fig. 7A A schematic structural diagram of a pixel circuit according to another embodiment of the present disclosure is shown schematically.

[0149] like Fig. 7AAs shown, the pixel circuit 700 may include first to third transistors T1 to T3, fifth to ninth transistors T5 to T9, a first capacitor C1, a first light emitting diode LED1, and a second light emitting diode LED2. Among them, the first to third transistors T1 to T3, the fifth transistor T5, and the seventh to ninth transistors T7 to T9 may be P-type switch transistors, and the sixth transistor T6 may be a P-type driving transistor.

[0150] The gate of the first transistor T1 is electrically connected to the third control terminal CON3, the first electrodes of the first transistor T1 are electrically connected to the first node N1, and the second electrodes of the first transistor T1 are electrically connected to the third node N3. The gate of the second transistor T2 is electrically connected to the fourth control terminal CON4, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the second node N2. The gate of the third transistor T3 is electrically connected to the fifth control terminal CON5, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the first reset terminal Vinit1. The gate of the fifth transistor T5 is electrically connected to the first control terminal CON1, the first electrode of the fifth transistor T5 is electrically connected to the fourth node N4, and the second electrode of the fifth transistor T5 is electrically connected to the data terminal Vdata. The gate of the sixth transistor T6 is electrically connected to the fifth node N5, the first electrode of the sixth transistor T6 is electrically connected to the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected to the first node N1. The gate of the seventh transistor T7 is electrically connected to the first control terminal CON1, the first electrode of the seventh transistor T7 is electrically connected to the fifth node N5, and the second electrode of the seventh transistor T7 is electrically connected to the first node N1. The gate of the eighth transistor T8 is electrically connected to the second control terminal CON2, the first electrode of the eighth transistor T8 is electrically connected to the first power supply VDD, and the second electrode of the eighth transistor T8 is electrically connected to the fourth node N4. The gate of the ninth transistor T9 is electrically connected to the sixth control terminal CON6, the first electrode of the ninth transistor T9 is electrically connected to the fifth node N5, and the second electrode of the ninth transistor T9 is electrically connected to the second reset terminal Vinit2. The first end of the first capacitor C1 is electrically connected to the first power supply VDD, and the second end of the first capacitor C1 is electrically connected to the fifth node N5. The anode of the first light-emitting diode LED1 is electrically connected to the second node N2, and the cathode of the first light-emitting diode LED1 is electrically connected to the second power supply VSS. The anode of the second light-emitting diode LED2 is electrically connected to the third node N3, and the cathode of the second light-emitting diode LED2 is electrically connected to the second power supply VSS.

[0151] According to the embodiment of the present disclosure, in addition to the advantages of the pixel circuit 600, the pixel circuit 700 can also realize the separate control of the first light-emitting diode LED1 and the second light-emitting diode LED2, so the pixel circuit 700 can be applied to the application scenarios of active anti-peeping and dual display, and the corresponding application scenarios can be switched arbitrarily. For example, the first light-emitting diode LED1 and the second light-emitting diode LED2 can be used as pixels in the anti-peeping state or the shared state separately, and can be switched according to the application scenario, time, and brightness of the anti-peeping state / sharing state, so that the same pixel will not be in the anti-peeping state or the shared state throughout its life cycle, resulting in serious device attenuation, thereby affecting the life of the display panel, residual image, and brightness uniformity. Figure 7B The working timing diagram of the pixel circuit according to another embodiment of the present disclosure is schematically shown.

[0152] like Figure 7B As shown, in stages P1 to P3, the pixel circuit 700 can control the second light emitting diode LED2 to emit light, and in stages P4 to P6, the pixel circuit 700 can control the first light emitting diode LED1 to emit light.

[0153] In the P1 stage, the sixth control signal CON6 is at a low level and controls the ninth transistor T9 to be turned on, so as to pull the potential of the fifth node N5 down to the second reset signal Vinit2, so that the first capacitor C1 can be reset by the second reset signal Vinit2; the fifth control signal CON5 is at a low level and controls the third transistor T3 to be turned on, so as to pull the potential of the second node N2 down to the first reset signal Vinit1, so that the first light-emitting diode LED1 can be reset by the first reset signal Vinit1; the fourth control signal CON4 is at a low level and controls the second transistor T2 to be turned on, and the third control signal CON3 is at a low level and controls the first transistor T1 to be turned on, so as to pull the potential of the third node N3 down to the first reset signal Vinit1, so that the second light-emitting diode LED2 can be reset by the first reset signal Vinit1.

[0154] In the P2 phase, the third control signal CON3, the fourth control signal CON4, the fifth control signal CON5 and the sixth control signal CON6 are all high level to control the first transistor T1, the second transistor T2, the third transistor T3 and the ninth transistor T9 to be turned off. The first control signal CON1 is low level to control the fifth transistor T5 and the seventh transistor T7 to be turned on, and the data signal Vdata is charged to the first capacitor C1 through the transistor T5, the sixth transistor T6 and the transistor T7.

[0155] In the P3 phase, the first control signal CON1 is at a high level to control the fifth transistor T5 and the seventh transistor T7 to be turned off, the second control signal CON2 is at a low level to control the eighth transistor T8 to be turned on, and the third control signal CON3 is at a low level to control the first transistor T1 to be turned on. Driven by the first power supply voltage VDD and the voltage of the first capacitor C1, a driving current Id is formed between the source and drain of the sixth transistor T6, and the driving current Id can be provided to the second light emitting diode LED2 via the first transistor T1 and the third node N3 to control the second light emitting diode LED2 to emit light.

[0156] In the P4 stage, the sixth control signal CON6 is at a low level and controls the ninth transistor T9 to be turned on, so as to pull the potential of the fifth node N5 down to the second reset signal Vinit2, so that the first capacitor C1 can be reset by the second reset signal Vinit2; the fifth control signal CON5 is at a low level and controls the third transistor T3 to be turned on, so as to pull the potential of the second node N2 down to the first reset signal Vinit1, so that the first light-emitting diode LED1 can be reset by the first reset signal Vinit1.

[0157] In the P5 phase, the fifth control signal CON5 and the sixth control signal CON6 are both high level to control the third transistor T3 and the ninth transistor T9 to be turned off. The first control signal CON1 is low level to control the fifth transistor T5 and the seventh transistor T7 to be turned on, and the data signal Vdata is charged to the first capacitor C1 through the transistor T5, the sixth transistor T6 and the transistor T7.

[0158] In the P6 phase, the first control signal CON1 is at a high level to control the fifth transistor T5 and the seventh transistor T7 to be turned off, the second control signal CON2 is at a low level to control the eighth transistor T8 to be turned on, and the fourth control signal CON4 is at a low level to control the second transistor T2 to be turned on. Driven by the first power supply voltage VDD and the voltage of the first capacitor C1, a driving current Id is formed between the source and drain of the sixth transistor T6, and the driving current Id can be provided to the first light emitting diode LED1 via the second transistor T2 and the second node N2 to control the first light emitting diode LED1 to emit light.

[0159] According to the embodiments of the present disclosure, the pixel circuit 700 can realize independent control of two light-emitting diodes, and can switch the working mode, the on state and the brightness according to the needs, so that the same light-emitting diode will not be in the anti-peeping mode or the sharing mode throughout the entire life cycle, thereby improving the uniformity of the brightness of the light-emitting diodes and increasing the service life of the pixel circuit.

[0160] Fig. 8A A schematic structural diagram of a pixel circuit according to another embodiment of the present disclosure is shown schematically.

[0161] like Fig. 8A As shown, based on the pixel circuit 700, the pixel circuit 800A may further include a fourth transistor T4. The fourth transistor T4 may be a P-type switch transistor.

[0162] A gate of the fourth transistor T4 is electrically connected to the fifth control terminal CON5 , a first electrode of the fourth transistor T4 is electrically connected to the third node N3 , and a second electrode of the fourth transistor T4 is electrically connected to the second node N2 . Figure 8B A schematic structural diagram of a pixel circuit according to another embodiment of the present disclosure is shown schematically.

[0163] like Figure 8B As shown, based on the pixel circuit 700, the pixel circuit 800B may further include a fourth transistor T4. The fourth transistor T4 may be a P-type switch transistor.

[0164] A gate of the fourth transistor T4 is electrically connected to the fifth control terminal CON5 , a first electrode of the fourth transistor T4 is electrically connected to the third node N3 , and a second electrode of the fourth transistor T4 is electrically connected to the first reset terminal Vinit1 .

[0165] Optionally, different reset signals may be used to perform reset processing on the two light emitting diodes.

[0166] Figure 8C A schematic structural diagram of a pixel circuit according to another embodiment of the present disclosure is shown schematically.

[0167] like Figure 8C As shown, the control subcircuit 20 may also be connected to the third reset terminal Vinit3. Based on the pixel circuit 700, the pixel circuit 800C may further include a fourth transistor T4. The fourth transistor T4 may be a P-type switch transistor.

[0168] The third reset terminal Vinit3 can be used to provide a third reset signal Vinit3. The third reset signal Vinit3 can be the same signal as the first reset signal Vinit1 and the second reset signal Vinit2, or a signal different from the first reset signal Vinit1 or the second reset signal Vinit2, which is not limited here.

[0169] The gate of the fourth transistor T4 is electrically connected to the fifth control terminal CON5, the first electrode of the fourth transistor T4 is electrically connected to the third node N3, and the second electrode of the fourth transistor T4 is electrically connected to the third reset terminal Vinit3. When performing a reset process, the fifth control signal CON5 is at a high level to control the third transistor T3 and the fourth transistor T4 to be turned on, and the first reset signal Vinit1 can be provided to the second node N2 via the third transistor T3 to reset the anode of the first light emitting diode LED1; the third reset signal Vinit3 can be provided to the third node N3 via the fourth transistor T4 to reset the anode of the second light emitting diode LED2.

[0170] According to the embodiments of the present disclosure, since the second light emitting transistor LED2 is initialized synchronously when the first light emitting transistor LED1 is initialized, when it is necessary to turn on the second light emitting transistor LED2, there is no need to go through the process of initializing the second light emitting transistor LED2, thereby extending the charging time of the second light emitting transistor LED2, thereby effectively improving the display quality and the afterimage problem.

[0171] Fig.8D The working timing diagram of the pixel circuit according to another embodiment of the present disclosure is schematically shown.

[0172] like Fig.8D As shown, in stages P1 to P3, the pixel circuit 800A or the pixel circuit 800B can control the first light-emitting diode LED1 to emit light, and in stages P4 to P5, the pixel circuit 800A or the pixel circuit 800B can control the second light-emitting diode LED2 to emit light.

[0173] In the P1 stage, the sixth control signal CON6 is at a low level and controls the ninth transistor T9 to be turned on, so as to pull the potential of the fifth node N5 down to the second reset signal Vinit2, so that the first capacitor C1 can be reset by the second reset signal Vinit2; the fifth control signal CON5 is at a low level and controls the third transistor T3 and the fourth transistor T4 to be turned on, so as to pull the potential of the second node N2 and the third node N3 down to the first reset signal Vinit1, respectively, so that the first light-emitting diode LED1 and the second light-emitting diode LED2 can be reset by the first reset signal Vinit1.

[0174] In the P2 phase, the fifth control signal CON5 and the sixth control signal CON6 are both high level to control the third transistor T3, the fourth transistor T4 and the ninth transistor T9 to be turned off. The first control signal CON1 is low level to control the fifth transistor T5 and the seventh transistor T7 to be turned on, and the data signal Vdata is charged to the first capacitor C1 through the transistor T5, the sixth transistor T6 and the transistor T7.

[0175] In the P3 phase, the first control signal CON1 is at a high level to control the fifth transistor T5 and the seventh transistor T7 to be turned off, the second control signal CON2 is at a low level to control the eighth transistor T8 to be turned on, and the fourth control signal CON4 is at a low level to control the second transistor T2 to be turned on. Driven by the first power supply voltage VDD and the voltage of the first capacitor C1, a driving current Id is formed between the source and drain of the sixth transistor T6, and the driving current Id can be provided to the first light emitting diode LED1 via the second transistor T2 and the second node N2 to control the first light emitting diode LED1 to emit light.

[0176] In the P4 phase, the second control signal CON2 is at a high level to control the eighth transistor T8 to be turned off, and the fourth control signal CON4 is at a high level to control the second transistor T2 to be turned off. The first control signal CON1 is at a low level to control the fifth transistor T5 and the seventh transistor T7 to be turned on, and the data signal Vdata is charged to the first capacitor C1 via the transistor T5, the sixth transistor T6 and the transistor T7.

[0177] In the P5 phase, the first control signal CON1 is at a high level to control the fifth transistor T5 and the seventh transistor T7 to be turned off, the second control signal CON2 is at a low level to control the eighth transistor T8 to be turned on, and the third control signal CON3 is at a low level to control the first transistor T1 to be turned on. Driven by the first power supply voltage VDD and the voltage of the first capacitor C1, a driving current Id is formed between the source and drain of the sixth transistor T6, and the driving current Id can be provided to the second light emitting diode LED2 via the first transistor T1 and the third node N3 to control the second light emitting diode LED2 to emit light.

[0178] According to the embodiments of the present disclosure, by writing the first reset signal Vinit1 to the first light emitting diode LED1 for resetting, the first reset signal Vinit1 is also written to the second light emitting diode LED2 for resetting. Therefore, when the second light emitting diode LED2 is turned on, there is no need to perform reset processing, thereby reducing the reset process of the second light emitting diode LED2, extending the charging time of the second light emitting diode LED2, and further improving the image quality and reducing the impact of the afterimage.

[0179] Since the number of sub-pixels contained in the divided unit pixel is twice the number of sub-pixels in the unit pixel in the related art, its refresh frequency is doubled and the charging time is halved, which will affect the charging effect of the device, making it impossible to achieve a high refresh rate, and may cause short-term or medium-term afterimage problems, affecting the display effect. Optionally, the driving sub-circuit can be implemented by a separate circuit to separate the Vth compensation process of the driving transistor from the writing process of the data signal, thereby extending the duration of the Vth compensation and improving the display effect of low grayscale.

[0180] Fig.9A The schematic diagram shows the structure of a driving sub-circuit according to another embodiment of the present disclosure.

[0181] like Fig.9A As shown, the separate driving subcircuit may include a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a first capacitor C1 and a second capacitor C2. The fifth transistor T5 may be a P-type driving transistor, and the sixth transistor T6 and the seventh transistor T7 may be P-type switching transistors.

[0182] A gate electrode of the fifth transistor T5 is electrically connected to the fourth node N4 , a first electrode of the fifth transistor T5 is electrically connected to the first power source VDD, and a second electrode of the fifth transistor T5 is electrically connected to the first node N1 .

[0183] A gate of the sixth transistor T6 is electrically connected to the second control terminal CON2 , a first electrode of the sixth transistor T6 is electrically connected to the fourth node N4 , and a second electrode of the sixth transistor T6 is electrically connected to the first node N1 .

[0184] A gate of the seventh transistor T7 is electrically connected to the first control terminal CON1 , a first electrode of the seventh transistor T7 is electrically connected to the fifth node N5 , and a second electrode of the seventh transistor T7 is electrically connected to the data terminal Vdata.

[0185] A first end of the first capacitor C1 is electrically connected to a fourth node N4 , and a second end of the first capacitor C1 is electrically connected to a fifth node N5 .

[0186] A first end of the second capacitor C2 is electrically connected to the first power source VDD, and a second end of the second capacitor C2 is electrically connected to the fourth node N4.

[0187] Optionally, the driving subcircuit 10 may also be electrically connected to the second reset terminal Vinit2 and the sixth control terminal CON6 respectively. Under the control of the sixth control signal CON6 from the sixth control terminal CON6, the driving subcircuit 10 may use the second reset signal Vinit2 from the second reset terminal Vinit2 to reset the potential of the first capacitor C1.

[0188] Fig. 9B The schematic diagram shows the structure of a driving sub-circuit according to another embodiment of the present disclosure.

[0189] like Fig. 9B As shown, Fig.9A The driving subcircuit shown may further include an eighth transistor T8. The eighth transistor T8 may be a P-type switching transistor.

[0190] A gate of the eighth transistor T8 is electrically connected to the sixth control terminal CON6 , a first electrode of the eighth transistor T8 is electrically connected to the second reset terminal Vinit2 , and a second electrode of the eighth transistor T8 is electrically connected to the fifth node N5 .

[0191] Before the driving sub-circuit 10 works, the sixth control signal CON6 is at a low level to control the eighth transistor T8 to be turned on, and the second reset signal Vinit2 can be provided to the fifth node N5 via the eighth transistor T8 to reset the first capacitor C1.

[0192] The following combination Figure 3A to Figure 3B , Figure 4A to Figure 4E and FIG. 9A to FIG. 9B The circuit structures shown respectively are used to further illustrate the pixel circuit of the embodiment of the present disclosure.

[0193] Fig. 10A A schematic structural diagram of a pixel circuit according to another embodiment of the present disclosure is shown schematically.

[0194] like Fig. 10A As shown, the pixel circuit 1000A may include a first transistor T1 to a third transistor T3, a fifth transistor T5 to an eighth transistor T8, a first capacitor C1, a second capacitor C2, a first light emitting diode LED1 and a second light emitting diode LED2. Among them, the first transistor T1 to the third transistor T3, the sixth transistor T6 to the eighth transistor T8 may be a P-type switching transistor, and the fifth transistor T5 may be a P-type driving transistor.

[0195] The gate of the first transistor T1 is electrically connected to the third control terminal CON3, the first electrodes of the first transistor T1 are electrically connected to the first node N1, and the second electrodes of the first transistor T1 are electrically connected to the third node N3. The gate of the second transistor T2 is electrically connected to the fourth control terminal CON4, the first electrode of the second transistor T2 is electrically connected to the third node N3, and the second electrode of the second transistor T2 is electrically connected to the second node N2. The gate of the third transistor T3 is electrically connected to the fifth control terminal CON5, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the first reset terminal Vinit1. The gate of the fifth transistor T5 is electrically connected to the fourth node N4, the first electrode of the fifth transistor T5 is electrically connected to the first power supply VDD, and the second electrode of the fifth transistor T5 is electrically connected to the first node N1. The gate of the sixth transistor T6 is electrically connected to the second control terminal CON2, the first electrode of the sixth transistor T6 is electrically connected to the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected to the first node N1. The gate of the seventh transistor T7 is electrically connected to the first control terminal CON1, the first electrode of the seventh transistor T7 is electrically connected to the fifth node N5, and the second electrode of the seventh transistor T7 is electrically connected to the data terminal Vdata. The gate of the eighth transistor T8 is electrically connected to the sixth control terminal CON6, the first electrode of the eighth transistor T8 is electrically connected to the second reset terminal Vinit2, and the second electrode of the eighth transistor T8 is electrically connected to the fifth node N5. The first end of the first capacitor C1 is electrically connected to the fourth node N4, and the second end of the first capacitor C1 is electrically connected to the fifth node N5. The first end of the second capacitor C2 is electrically connected to the first power supply VDD, and the second end of the second capacitor C2 is electrically connected to the fourth node N4. The anode of the first light-emitting diode LED1 is electrically connected to the second node N2, and the cathode of the first light-emitting diode LED1 is electrically connected to the second power supply VSS. The anode of the second light-emitting diode LED2 is electrically connected to the third node N3, and the cathode of the second light-emitting diode LED2 is electrically connected to the second power supply VSS.

[0196] The following takes the operation of the pixel circuit 1000A based on the dual-view mode as an example to illustrate the operation timing of the pixel circuit 1000A.

[0197] Fig. 10B The working timing diagram of the pixel circuit according to another embodiment of the present disclosure is schematically shown.

[0198] like Fig. 10BAs shown, in the P1 phase, the fifth control signal CON5 is at a low level to control the third transistor T3 to be turned on, and the first reset signal Vinit1 can reset the first light emitting diode LED1; the fourth control signal CON4 is at a low level to control the second transistor T2 to be turned on, and the first reset signal Vinit1 can reset the second light emitting diode LED2; the sixth control signal CON6 is at a low level to control the eighth transistor T8 to be turned on, and the second reset signal Vinit2 can reset the first capacitor C1. The second control signal CON2 is at a low level to control the sixth transistor T6 to be turned on, and the first power supply VDD charges the second capacitor C2 through the fifth transistor T5 and the sixth transistor T6 to start Vth compensation.

[0199] In the P2 phase, the sixth control signal CON6 is at a high level to control the eighth transistor T8 to be turned off, the fifth control signal CON5 is at a high level to control the third transistor T3 to be turned off, and the fourth control signal CON4 is at a high level to control the second transistor T2 to be turned off. The first control signal CON1 is at a low level to control the seventh transistor T7 to be turned on, and the data signal Vdata is written to the fifth node N5. At this time, the second control signal CON2 is still at a low level to continue Vth compensation.

[0200] In the P3 phase, the first control signal CON1 is high and controls the seventh transistor T7 to be turned off, the second control signal CON2 is high and controls the sixth transistor T6 to be turned off, and the sixth control signal CON6 is low and controls the eighth transistor T8 to be turned on, so that the potential of the first capacitor C1 jumps.

[0201] In the P4 phase, the sixth control signal CON6 is at a high level to control the eighth transistor T8 to be turned off, the third control signal CON3 is at a low level to control the first transistor T1 to be turned on, and the fourth control signal CON4 is at a low level to control the second transistor T2 to be turned on. A driving current Id is formed between the source and drain of the fifth transistor T5, and the driving current Id can be provided to the first light emitting diode LED1 and the second light emitting diode LED2 to drive the first light emitting diode LED1 and the second light emitting diode LED2 to emit light respectively.

[0202] According to the embodiment of the present disclosure, through the separated circuit architecture, the pixel circuit 1000A can independently perform Vth charging and Vdata input, thereby increasing the Vth charging time to improve the afterimage problem existing in low grayscale display.

[0203] Fig. 10C A schematic structural diagram of a pixel circuit according to another embodiment of the present disclosure is shown schematically.

[0204] like Fig. 10CAs shown, the pixel circuit 1000C may include a first transistor T1 to a third transistor T3, a fifth transistor T5 to an eighth transistor T8, a first capacitor C1, a second capacitor C2, a first light emitting diode LED1, and a second light emitting diode LED2. Among them, the first transistor T1 to the third transistor T3, the sixth transistor T6 to the eighth transistor T8 may be a P-type switching transistor, and the fifth transistor T5 may be a P-type driving transistor.

[0205] The gate of the first transistor T1 is electrically connected to the third control terminal CON3, the first electrodes of the first transistor T1 are electrically connected to the first node N1, and the second electrodes of the first transistor T1 are electrically connected to the third node N3. The gate of the second transistor T2 is electrically connected to the fourth control terminal CON4, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the second node N2. The gate of the third transistor T3 is electrically connected to the fifth control terminal CON5, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the first reset terminal Vinit1. The gate of the fifth transistor T5 is electrically connected to the fourth node N4, the first electrode of the fifth transistor T5 is electrically connected to the first power supply VDD, and the second electrode of the fifth transistor T5 is electrically connected to the first node N1. The gate of the sixth transistor T6 is electrically connected to the second control terminal CON2, the first electrode of the sixth transistor T6 is electrically connected to the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected to the first node N1. The gate of the seventh transistor T7 is electrically connected to the first control terminal CON1, the first electrode of the seventh transistor T7 is electrically connected to the fifth node N5, and the second electrode of the seventh transistor T7 is electrically connected to the data terminal Vdata. The gate of the eighth transistor T8 is electrically connected to the sixth control terminal CON6, the first electrode of the eighth transistor T8 is electrically connected to the second reset terminal Vinit2, and the second electrode of the eighth transistor T8 is electrically connected to the fifth node N5. The first end of the first capacitor C1 is electrically connected to the fourth node N4, and the second end of the first capacitor C1 is electrically connected to the fifth node N5. The first end of the second capacitor C2 is electrically connected to the first power supply VDD, and the second end of the second capacitor C2 is electrically connected to the fourth node N4. The anode of the first light-emitting diode LED1 is electrically connected to the second node N2, and the cathode of the first light-emitting diode LED1 is electrically connected to the second power supply VSS. The anode of the second light-emitting diode LED2 is electrically connected to the third node N3, and the cathode of the second light-emitting diode LED2 is electrically connected to the second power supply VSS.

[0206] The working timing of the pixel circuit 1000C can be found in Figure 7B as well as Fig. 10B The working timing shown will not be described in detail here.

[0207] Fig. 10DA schematic structural diagram of a pixel circuit according to another embodiment of the present disclosure is shown schematically.

[0208] like Fig. 10D As shown, based on the pixel circuit 1000C, the pixel circuit 1000D may further include a fourth transistor T4. The fourth transistor T4 may be a P-type switch transistor.

[0209] A gate of the fourth transistor T4 is electrically connected to the fifth control terminal CON5 , a first electrode of the fourth transistor T4 is electrically connected to the third node N3 , and a second electrode of the fourth transistor T4 is electrically connected to the second node N2 .

[0210] The working timing of the pixel circuit 1000D can be found in Figure 8B as well as Fig. 10B The working timing shown will not be described in detail here.

[0211] Fig. 10E A schematic structural diagram of a pixel circuit according to another embodiment of the present disclosure is shown schematically.

[0212] like Fig. 10E As shown, based on the pixel circuit 1000C, the pixel circuit 1000D may further include a fourth transistor T4. The fourth transistor T4 may be a P-type switch transistor.

[0213] A gate of the fourth transistor T4 is electrically connected to the fifth control terminal CON5 , a first electrode of the fourth transistor T4 is electrically connected to the third node N3 , and a second electrode of the fourth transistor T4 is electrically connected to the first reset terminal Vinit1 .

[0214] The working timing of the pixel circuit 1000E can be found in Fig. 9B as well as Fig. 10B The working timing shown will not be described in detail here.

[0215] Optionally, different reset signals may be used to perform reset processing on the two light emitting diodes.

[0216] Fig.10F A schematic structural diagram of a pixel circuit according to another embodiment of the present disclosure is shown schematically.

[0217] like Fig.10F As shown, the control subcircuit 20 may also be connected to the third reset terminal Vinit3. Based on the pixel circuit 1000C, the pixel circuit 1000F may further include a fourth transistor T4. The fourth transistor T4 may be a P-type switch transistor.

[0218] A gate of the fourth transistor T4 is electrically connected to the fifth control terminal CON5 , a first electrode of the fourth transistor T4 is electrically connected to the third node N3 , and a second electrode of the fourth transistor T4 is electrically connected to the third reset terminal Vinit3 .

[0219] When performing the reset process, the fifth control signal CON5 is at a high level and controls the third transistor T3 and the fourth transistor T4 to be turned on. The first reset signal Vinit1 can be provided to the second node N2 via the third transistor T3 to reset the anode of the first light-emitting diode LED1; the third reset signal Vinit3 can be provided to the third node N3 via the fourth transistor T4 to reset the anode of the second light-emitting diode LED2.

[0220] Fig.11 A schematic diagram of a display panel according to an embodiment of the present disclosure is schematically shown.

[0221] like Fig.11 As shown, the display panel 1100 may include a display area 1110 and a non-display area 1120. A plurality of pixel circuits 1111 may be provided in the display area 1110, and the pixel circuit 1111 may be any one of the pixel circuits 200, 400, 500, 600, 700, 800A, 800B, 1000A, 1000C, 1000D, and 1000E as described above, which is not limited here.

[0222] Fig.12 A schematic diagram of a display device according to an embodiment of the present disclosure is schematically shown.

[0223] like Fig.12 As shown, the display device 1200 may include a display panel 1210, and a display area of ​​the display panel 1210 may be provided with a plurality of pixel circuits, and the pixel circuit may be any one of the pixel circuit 200, pixel circuit 400, pixel circuit 500, pixel circuit 600, pixel circuit 700, pixel circuit 800A, pixel circuit 800B, pixel circuit 1000A, pixel circuit 1000C, pixel circuit 1000D and pixel circuit 1000E as described above, without limitation herein.

[0224] It will be appreciated by those skilled in the art that the features described in the various embodiments of the present disclosure may be combined and / or combined in a variety of ways, even if such combinations or combinations are not explicitly described in the present disclosure. In particular, without departing from the spirit and teachings of the present disclosure, the features described in the various embodiments of the present disclosure may be combined and / or combined in a variety of ways. All of these combinations and / or combinations fall within the scope of the present disclosure.

[0225] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes and are not intended to limit the scope of the present disclosure. Although the embodiments are described above, this does not mean that the measures in the various embodiments cannot be used in combination to advantage. Without departing from the scope of the present disclosure, those skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A pixel circuit, comprising: a driving subcircuit configured to generate a driving current based on a first power supply voltage from a first power supply and a data signal from a data terminal under the control of a first control signal from a first control terminal and a second control signal from a second control terminal, and provide the driving current to a first node; a control subcircuit configured to provide the driving current to at least one of the second node and the third node under the control of a third control signal from the third control terminal and a fourth control signal from the fourth control terminal; a first light emitting element, wherein a first terminal of the first light emitting element is electrically connected to the second node, and a second terminal of the first light emitting element is electrically connected to a second power source; as well as A second light emitting element, wherein a first terminal of the second light emitting element is electrically connected to the third node, and a second terminal of the second light emitting element is electrically connected to the second power source.

2. The pixel circuit according to claim 1, wherein: The control subcircuit includes a first transistor and a second transistor; The gate of the first transistor is electrically connected to the third control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the third node; A gate of the second transistor is electrically connected to the fourth control terminal, a first electrode of the second transistor is electrically connected to the third node, and a second electrode of the second transistor is electrically connected to the second node.

3. The pixel circuit according to claim 1, wherein: The control subcircuit includes a first transistor and a second transistor; The gate of the first transistor is electrically connected to the third control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the third node; A gate of the second transistor is electrically connected to the fourth control terminal, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to the second node.

4. The pixel circuit according to claim 2 or 3, wherein: The control subcircuit is also electrically connected to the first reset terminal and the fifth control terminal respectively; The control subcircuit is further configured to reset the potential of at least one of the second node and the third node using a first reset signal from the first reset terminal under the control of a fifth control signal from the fifth control terminal.

5. The pixel circuit according to claim 4, wherein: The control subcircuit further includes a third transistor; A gate of the third transistor is electrically connected to the fifth control terminal, a first electrode of the third transistor is electrically connected to the second node, and a second electrode of the third transistor is electrically connected to the first reset terminal.

6. The pixel circuit according to claim 5, wherein: The control subcircuit further includes a fourth transistor; A gate of the fourth transistor is electrically connected to the fifth control terminal, a first electrode of the fourth transistor is electrically connected to the third node, and a second electrode of the fourth transistor is electrically connected to the second node.

7. The pixel circuit according to claim 5, wherein: The control subcircuit further includes a fourth transistor; A gate of the fourth transistor is electrically connected to the fifth control terminal, a first electrode of the fourth transistor is electrically connected to the third node, and a second electrode of the fourth transistor is electrically connected to the first reset terminal.

8. The pixel circuit according to any one of claims 1 to 7, wherein: The driving subcircuit includes a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor and a second capacitor; wherein the gate of the fifth transistor is electrically connected to the fourth node, the first electrode of the fifth transistor is electrically connected to the first power supply, and the second electrode of the fifth transistor is electrically connected to the first node; The gate of the sixth transistor is electrically connected to the second control terminal, the first electrode of the sixth transistor is electrically connected to the fourth node, and the second electrode of the sixth transistor is electrically connected to the first node; The gate of the seventh transistor is electrically connected to the first control terminal, the first electrode of the seventh transistor is electrically connected to the fifth node, and the second electrode of the seventh transistor is electrically connected to the data terminal; A first terminal of the first capacitor is electrically connected to the fourth node, and a second terminal of the first capacitor is electrically connected to the fifth node; and A first terminal of the second capacitor is electrically connected to the first power source, and a second terminal of the second capacitor is electrically connected to the fourth node.

9. The pixel circuit according to claim 8, wherein: The driving subcircuit is also electrically connected to the second reset terminal and the sixth control terminal respectively; The driving sub-circuit is further configured to reset the potential of the first capacitor using a second reset signal from the second reset terminal under the control of a sixth control signal from the sixth control terminal.

10. The pixel circuit according to claim 9, wherein: The driving sub-circuit further includes an eighth transistor; A gate of the eighth transistor is electrically connected to the sixth control terminal, a first electrode of the eighth transistor is electrically connected to the second reset terminal, and a second electrode of the eighth transistor is electrically connected to the fifth node.

11. The pixel circuit according to any one of claims 1 to 7, wherein: The driving subcircuit includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a first capacitor; wherein the gate of the fifth transistor is electrically connected to the first control terminal, the first electrode of the fifth transistor is electrically connected to the fourth node, and the second electrode of the fifth transistor is electrically connected to the data terminal; The gate of the sixth transistor is electrically connected to the fifth node, the first electrode of the sixth transistor is electrically connected to the fourth node, and the second electrode of the sixth transistor is electrically connected to the first node; The gate of the seventh transistor is electrically connected to the first control terminal, the first electrode of the seventh transistor is electrically connected to the fifth node, and the second electrode of the seventh transistor is electrically connected to the first node; The gate of the eighth transistor is electrically connected to the second control terminal, the first electrode of the eighth transistor is electrically connected to the first power supply, and the second electrode of the eighth transistor is electrically connected to the fourth node; and A first terminal of the first capacitor is electrically connected to the first power source, and a second terminal of the first capacitor is electrically connected to the fifth node.

12. The pixel circuit according to claim 11, wherein: The driving subcircuit is also electrically connected to the second reset terminal and the sixth control terminal respectively; The driving sub-circuit is further configured to reset the potential of the first capacitor using a second reset signal from the second reset terminal under the control of a sixth control signal from the sixth control terminal.

13. The pixel circuit according to claim 12, wherein: The driving sub-circuit further includes a ninth transistor; A gate of the ninth transistor is electrically connected to the sixth control terminal, a first electrode of the ninth transistor is electrically connected to the fifth node, and a second electrode of the ninth transistor is electrically connected to the second reset terminal.

14. A display panel, comprising a display area and a non-display area, wherein: A plurality of pixel circuits according to any one of claims 1 to 13 are arranged in the display area.

15. A display device comprising the display panel according to claim 14.

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