Memory, method of operating memory, and memory system

Abstract

This application provides a memory, a method for operating the memory, and a memory system. The memory includes a memory array and peripheral circuitry coupled to the memory array. The memory array includes multiple planes, each plane including multiple bit lines. The peripheral circuitry includes a gating circuit and multiple page buffers, with the gating circuit coupled to the multiple page buffers. The first bit line located at a first end of a plane is coupled to a first page buffer among the multiple page buffers via the gating circuit. The bit lines other than the first bit line are coupled to at least one page buffer other than the first page buffer among the multiple page buffers via the gating circuit, and at least two bit lines other than the first bit line are coupled to the same page buffer via the gating circuit. The first bit line located at the first end of the plane can be independently controlled during programming, thereby continuously pre-charging during the pre-charge process, which can solve the coupling problem between adjacent bit lines in adjacent bit planes.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a memory, a method of operating the memory, and a memory system. Background Technology

[0002] Among various types of non-volatile memory, NAND (Not-And) memory has become the mainstream product in the memory market due to its high storage density, controllable production costs, suitable erase / program speed, and retention characteristics. However, NAND memory can only perform read / program operations on one bit line at a time, resulting in slow read / write speeds. To improve read / write efficiency, the industry has proposed X-NAND memory. X-NAND memory can perform read / program operations on multiple bit lines simultaneously. However, during programming operations, bit lines on adjacent planes are prone to coupling problems. Summary of the Invention

[0003] The embodiments of this disclosure provide a memory, a method for operating the memory, and a memory system, which aim to solve the problem that bit lines of two adjacent planes are prone to coupling during programming operations of X-NAND memory.

[0004] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions:

[0005] In a first aspect, a memory is provided, comprising a memory array and peripheral circuitry. The memory array is coupled to the peripheral circuitry. The memory array comprises multiple planes. Each plane comprises multiple bit lines. The peripheral circuitry comprises a gating circuit and multiple page buffers. The gating circuit is coupled to the multiple page buffers. Of the multiple bit lines, the first bit line located at a first end of a plane is coupled to a first page buffer of the multiple page buffers via the gating circuit. The bit lines other than the first bit line are coupled to at least one page buffer of the multiple page buffers other than the first page buffer via the gating circuit, and at least two bit lines other than the first bit line are coupled to the same page buffer of the at least one page buffer via the gating circuit.

[0006] In this way, the first bit line located at the first end of the plane in the X-NAND memory can be independently controlled during programming operations, thereby continuously pre-charging during the data loading phase of the programming operation. Based on this, when pre-charging the bit line adjacent to the first bit line in an adjacent plane, the coupling problem between that bit line and the first bit line can be solved.

[0007] In one possible implementation, at least one page buffer described above includes a second page buffer. Specifically, among the plurality of bit lines, the second bit line located at the second end of the plane is coupled to the second page buffer via a gating circuit. In this manner, the second bit line located at the second end of the plane in the X-NAND memory can also be independently controlled during programming operations, thereby continuously pre-charging during the data loading phase of the programming process, better addressing the coupling problem between adjacent plane bit lines during pre-charging.

[0008] In one possible implementation, the at least one page buffer further includes a third page buffer. Specifically, of the multiple bit lines, all except the first and second bit lines are coupled to the third page buffer via gating circuits. In this way, except for the first and second bit lines which can be controlled independently, the remaining bit lines of each plane can be controlled uniformly through a single page buffer, thereby reducing the number of page buffers per plane in the X-NAND memory and lowering control costs.

[0009] In one possible implementation, the at least one page buffer further includes a third page buffer. Among the multiple bit lines, the bit lines other than the first and second bit lines comprise a first portion and a second portion. The bit lines in the first portion are coupled to the second page buffer via a gating circuit. The bit lines in the second portion are coupled to the third page buffer via a gating circuit. In this manner, the first bit line located at the first end of the plane can be independently controlled during programming operations; simultaneously, the utilization rate of the second page buffer can be improved.

[0010] In one possible implementation, the at least one page buffer further includes a third page buffer and a fourth page buffer. Of the multiple bit lines, the bit lines other than the first and second bit lines comprise a first portion and a second portion. The bit lines of the first portion are coupled to the third buffer via a gating circuit. The bit lines of the second portion are coupled to the fourth page buffer via a gating circuit. In this manner, during the data loading phase, the bit lines of each plane, excluding the first and second bit lines, can be pre-charged by two page buffers, thereby improving the programming efficiency of the X-NAND memory.

[0011] In one possible implementation, the bit lines in the first part described above include the (n+1)th bit line in the direction from the second bit line to the first bit line. The bit lines in the second part described above include the nth bit line in the direction from the second bit line to the first bit line. Here, n is an odd number. In this way, the bit lines of each plane, excluding the first and second bit lines, can be alternately precharged by two page buffers during the data loading phase, thereby reducing coupling issues between adjacent bit lines within each plane.

[0012] In one possible implementation, the bit lines in the first part mentioned above include the first to nth bit lines in the direction from the second bit line to the first bit line. The bit lines in the second part mentioned above include the (n+1)th to kth bit lines in the direction from the second bit line to the first bit line. The maximum value of k is the total number of bit lines between the first and second bit lines. In this way, multiple adjacent bit lines in the same plane can be pre-charged during the data loading phase using the same page buffer, thereby reducing routing complexity.

[0013] In one possible implementation, the gating circuit includes multiple gating switches. Each bit line is coupled to a corresponding page buffer via a gating switch. In this way, each page buffer can be precisely controlled to pre-charge each bit line using the individual gating switches.

[0014] Secondly, a method for operating a memory is provided, applied to a memory including a memory array and peripheral circuitry. The memory array is coupled to the peripheral circuitry. The memory array includes multiple planes, each plane including multiple bit lines. The peripheral circuitry includes a gating circuit and multiple page buffers, with the gating circuit coupled to the page buffers. The method can be executed by logic control circuitry in the peripheral circuitry. During the data loading phase of the programming operation, the logic control circuitry first receives a first indication signal. This first indication signal indicates the conduction timing between each bit line and its corresponding page buffer. Then, in response to the first indication signal, the gating circuitry is activated according to the conduction timing to precharge the multiple bit lines, and the first bit line located at the first end of the plane is continuously precharged during the precharging process. In this way, the first bit line always has a precharge voltage during the data loading phase. Therefore, even if a bit line adjacent to the first bit line in another plane is precharged, the first bit line will not experience coupling problems.

[0015] In one possible implementation, the method further includes: when pre-charging multiple bit lines according to the aforementioned conduction timing selection circuit, pre-charging is performed sequentially on all bit lines except the first bit line, from the first bit line to the second bit line. The second bit line is the bit line located at the second end of the plane. By means of this method, when resolving the coupling problem between adjacent bit lines of two adjacent planes, the remaining bit lines of each plane can be pre-charged in an orderly manner during the data loading phase.

[0016] In one possible implementation, the method further includes: when pre-charging multiple bit lines according to the aforementioned turn-on timing selection circuit, continuously pre-charging the second bit line located at the second end of the plane. In this way, during the data loading phase of the programming operation, both bit lines at both ends of the plane can be continuously pre-charged. Because X-NAND memory performs read / program operations in parallel across multiple planes, there are no coupling problems between adjacent bit planes.

[0017] In one possible implementation, the method further includes: when pre-charging multiple bit lines according to the aforementioned conduction timing selection circuit, pre-charging is performed sequentially from the first bit line to the second bit line, for all bit lines except the first and second bit lines. Alternatively, pre-charging is performed sequentially from the second bit line to the first bit line, for all bit lines except the first and second bit lines. In this manner, when pre-charging the first and second bit lines, the remaining bit lines in the plane can be pre-charged in an orderly manner.

[0018] In one possible implementation, the method further includes: when pre-charging multiple bit lines according to the aforementioned conduction timing selection circuit, pre-charging is performed sequentially on the bit lines other than the first bit line in the direction from the first bit line to the second bit line and in the direction from the second bit line to the first bit line. The second bit line is the bit line located at the second end of the plane. In this way, during the data loading phase, pre-charging can be performed sequentially from both ends of the plane to the bit line located in the middle of the plane, thereby improving the efficiency of pre-charging.

[0019] In one possible implementation, when precharging multiple bit lines according to the above-described turn-on timing selection circuit, the precharging timing of two adjacent bit lines (excluding the first bit line) partially overlaps. In this way, one of the two adjacent bit lines (excluding the first bit line) can apply a precharging voltage before the precharging voltage of the other bit line has finished being applied, thereby resolving the coupling problem between adjacent bit lines in the plane.

[0020] Thirdly, a memory system is provided, comprising: a memory controller and a memory coupled to the memory controller in any of the possible embodiments of the first aspect described above.

[0021] Fourthly, an electronic device is provided, including the memory system described in the third aspect above; and a host computer coupled to the memory system.

[0022] Fifthly, a computer-readable storage medium is provided that stores computer program instructions. When executed by a processor or logic control circuitry, the computer program instructions implement the method steps in any of the possible embodiments of the second aspect described above.

[0023] In a sixth aspect, a computer program product is provided, which, when executed by a processor or logic control circuit, implements the method steps in any of the possible embodiments of the second aspect described above.

[0024] It is understandable that the beneficial effects that can be achieved by the second to sixth aspects mentioned above can be referred to the beneficial effects of the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0026] Figure 1 This is a schematic diagram of the structure of an X-NAND memory.

[0027] Figure 2 A voltage timing diagram for performing a programming operation on an X-NAND memory;

[0028] Figure 3 for Figure 2 Timing diagram of X-NAND memory during the data loading phase;

[0029] Figure 4 This is a schematic diagram of another type of X-NAND memory.

[0030] Figure 5 This is a schematic diagram of another type of X-NAND memory.

[0031] Figure 6 For application Figure 5 A data loading timing diagram of X-NAND memory in [the context of the diagram].

[0032] Figure 7 This is a schematic diagram of the structure of the X-NAND memory provided in the embodiments of this application;

[0033] Figure 8 This application provides a schematic diagram of the structure of an X-NAND memory according to an embodiment of the present application.

[0034] Figure 9 For application Figure 8 A data loading timing diagram of X-NAND memory in [the context of the diagram].

[0035] Figure 10 This is a schematic diagram of the structure of another X-NAND memory provided in an embodiment of this application;

[0036] Figure 11 For application Figure 10 A data loading timing diagram of X-NAND memory in [the context of the diagram].

[0037] Figure 12 This is a schematic diagram of the structure of another X-NAND memory provided in an embodiment of this application;

[0038] Figure 13 For application Figure 12 A data loading timing diagram of X-NAND memory in [the context of the diagram].

[0039] Figure 14 This is a schematic diagram of the structure of another X-NAND memory provided in an embodiment of this application;

[0040] Figure 15 For application Figure 14 A data loading timing diagram of X-NAND memory in [the context of the diagram].

[0041] Figure 16 This is a schematic diagram of the structure of another X-NAND memory provided in an embodiment of this application;

[0042] Figure 17 For application Figure 16 A data loading timing diagram of X-NAND memory in [the context of the diagram].

[0043] Figure 18 This is a schematic diagram of the structure of another X-NAND memory provided in an embodiment of this application;

[0044] Figure 19 For application Figure 18 A data loading timing diagram of X-NAND memory in [the context of the diagram].

[0045] Figure 20 A flowchart illustrating an operation method of a memory provided in this application embodiment;

[0046] Figure 21 A structural block diagram of a memory system provided in an embodiment of this application;

[0047] Figure 22 This is a structural block diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0048] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0049] In the description of this disclosure, it should be understood that, unless the context requires otherwise, the term "comprising" is interpreted throughout the specification and claims as open-ended and encompassing, meaning "including, but not limited to." In the description, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example.

[0050] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0051] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0052] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0053] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0054] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0055] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0056] NAND flash memory arrays have multiple bit lines. Each bit line uses a page buffer for read / program operations, resulting in slow read / write speeds and a large number of page buffers. To improve read / write efficiency and reduce the number of page buffers per plane, the memory industry has proposed X-NAND memory. X-NAND memory uses a single page buffer to perform parallel read / program operations on multiple bit lines corresponding to a plane in the memory array.

[0057] like Figure 1 As shown, the X-NAND memory 100 includes a memory array 110 and peripheral circuitry 120 coupled to the memory array 110. The memory array 110 includes multiple planes, each plane including multiple bit lines (e.g., ...). Figure 1 BL0 to BL15) and multiple word lines (e.g. Figure 1 The peripheral circuit 120 includes a gating circuit 122 and multiple page buffers 121. The gating circuit 122 and the multiple page buffers 121 can be coupled to and controlled by the logic control circuit. In the X-NAND memory array 110, multiple bit lines of each plane are coupled to a page buffer 121 via the gating circuit 122, and multiple memory strings are coupled to each bit line. Each memory string has a top selective gate (TSG) at the top and a bottom selective gate (BSG) at the bottom. The gating circuit 122 includes multiple gating switches (e.g., ...). Figure 1 In the NAND memory (SG0 to SG15), each bit line is coupled to the corresponding page buffer 121 via a gating switch. Based on the read / program operation of NAND memory, X-NAND memory can realize the read / program operation of multiple bit lines by one page buffer through the control of the gating circuit, thereby improving the read / programming efficiency while reducing the number of page buffers.

[0058] Among them, such as Figure 2As shown, during programming, the X-NAND memory 100 needs to precharge multiple bit lines during the data loading phase. Then, during the programming period, a programming voltage (e.g., 20V) is applied to the selected word lines (BL0~BLn), and an on-state voltage (e.g., 10V) is applied to the unselected word lines. Simultaneously, the top select transistor (TSG) corresponding to the memory string containing the memory cell to be programmed is turned on, and the channel of that memory string is grounded (i.e., the voltage is 0V). The channels of the remaining unprogrammed memory strings are input with a higher bias voltage (e.g., 8V). Specifically, as... Figure 3 As shown, when a page buffer is used to precharge multiple bit lines, the gating switches (SG0~SGn) in the gating circuit are sequentially turned on from one end of each plane, thereby loading data (D0~Dn) onto each bit line sequentially. However, in this way, coupling problems will exist between two adjacent bit lines in the plane.

[0059] To resolve the coupling problem between two adjacent bit lines in a plane, one solution is to use a shielding circuit to address the coupling issue between them. Specifically, for example... Figure 4 As shown, in Figure 1 Based on the X-NAND memory, a shielding circuit 123 is added between each gating switch of the gating circuit 122 and its corresponding bit line. This shielding circuit 123 adds a shielding switch coupled to each bit line. Figure 4 The shielding switch consists of K0 to K15 in the diagram, and a power line Vss coupled to the shielding switch. The shielding switch corresponding to the nth bit line in each plane is controlled by a signal input via the first control line SH1; the shielding switch corresponding to the (n+1)th bit line in each plane is controlled by a signal input via the second control line SH2. Here, n is an odd number. During the data loading phase of the programming operation, the shielding switch corresponding to the nth bit line can be turned on first via the signal input via the first control line SH1, thereby providing a bias voltage Vss to the corresponding bit line, thus shielding the nth bit line and preventing it from being programmed. Then, the shielding switch corresponding to the (n+1)th bit line is turned on again via the signal input via the second control line SH2, thereby providing a bias voltage to the corresponding bit line, thus shielding the (n+1)th bit line and preventing it from being programmed. However, this method only allows half of the bit lines to be programmed at a time, which reduces programming efficiency.

[0060] Another solution proposes a method for synchronously reading / programming multiple bit lines in a plane using two page buffers. The first page buffer A1 is coupled to the nth bit line in the memory array via a gating circuit, and the second page buffer A2 is coupled to the (n+1)th bit line in the memory array via a gating circuit, where n is an odd number. Each bit line corresponds to a gating switch in the gating circuit. For example, ... Figure 5 As shown, taking a plane with 8 bit lines as an example. Assume page buffer A1 is coupled to the 1st bit line (BL0), 3rd bit line (BL2), 5th bit line (BL4), and 7th bit line (BL6) via the gating switches in gating circuit 122. Page buffer A2 is coupled to the 2nd bit line (BL1), 4th bit line (BL3), 6th bit line (BL5), and 8th bit line (BL7) via the gating switches in gating circuit 122. Bit lines BL0 to BL7 correspond one-to-one with gating switches SG0 to SG7. During the data loading phase of the programming operation, logic control circuit 121 can control the gating switches (SG0 to SG7) in gating circuit 122 to be turned on sequentially, thereby alternately pre-charging the 8 bit lines through page buffer A1 and page buffer A2. Specifically, as shown... Figure 6 As shown, when the selector switch of each bit line starts to conduct, the selector switch of the previous bit line remains on. For example, during the data loading phase, the corresponding selector switches can be sequentially activated from bit line BL0 to bit line BL7. Specifically, when SG1 starts to conduct, SG0 remains on. When SG2 starts to conduct, SG1 remains on, and so on. This method solves the coupling problem between adjacent bit lines in the same plane. However, X-NAND memory involves simultaneous programming of multiple planes. For example, during programming operations, each plane is programmed in the order from BL0 to BL7. If BL7 of a certain plane is pre-charged, the BL0 of the next adjacent plane, which has already been loaded with data, will be affected by the coupling problem. Therefore, this scheme cannot solve the coupling problem between adjacent bit lines of two adjacent planes.

[0061] To solve the above problems, such as Figure 7 As shown, this application embodiment provides a memory 700, which includes a memory array 710 and peripheral circuitry 720. The memory array is coupled to the peripheral circuitry 720. The memory array 710 includes multiple planes, each plane including multiple bit lines (e.g., ...). Figure 5(BL0 to BL15 in the original text). The peripheral circuit 720 includes a gating circuit 722 and multiple page buffers 721. The gating circuit 722 is coupled to the multiple page buffers 721, and the gating circuit 722 and the multiple page buffers 721 can be coupled to a logic control circuit and controlled by the logic control circuit. Of the aforementioned bit lines, the first bit line BL0, located at the first end of the plane, is coupled to the first page buffer B1 through the gating circuit 722. Bit lines other than the first bit line BL0 (e.g., ...) Figure 5 BL1 to BL15 are coupled to at least one of the multiple page buffers via a gating circuit 722, and at least two bit lines other than the first bit line are coupled to the same page buffer via the gating circuit. The gating circuit 722 may include multiple gating switches (e.g., ...). Figure 7 (SG0 to SG15 in the above). The above multiple gating switches (SG0 to SG15) can be controlled by logic control circuits, and each bit line in the multiple bit lines is coupled to the corresponding page buffer through a gating switch.

[0062] In one possible implementation, such as Figure 8 As shown, the at least one page buffer includes a second page buffer B2. Among the multiple bit lines, the second bit line BL15, located at the second end of the plane, is coupled to the second page buffer B2 via a gating circuit 722. Additionally, bit lines in the plane other than the first bit line BL0 and the second bit line BL15 can also be coupled to the second page buffer B2 via gating switches in the gating circuit 722. With this structure, during the data loading phase of the programming operation, while continuously pre-charging the first bit line located at the first end of the plane, the bit lines other than the first bit line BL0 can be pre-charged sequentially from the first bit line BL0 to the second bit line BL15 and from the second bit line BL15 to the first bit line BL0. The second bit line BL15 is the bit line located at the second end of the plane.

[0063] For example, such as Figure 9As shown, assume the plane includes 16 bit lines. The first bit line is BL0, and the second bit line is BL15. During the data loading phase of the programming operation, the gating switch SG0 corresponding to the first bit line BL0 can be continuously turned on, thereby continuously pre-charging the first bit line through the first page buffer. Then, the gating switches (SG1 to SG15) corresponding to the remaining bit lines (BL1 to BL15) can be turned on sequentially from the first bit line BL0 to the second bit line BL15, or sequentially from the second bit line BL15 to the first bit line BL0. Based on this, the first bit line BL0 can be continuously pre-charged during the data loading phase. At this time, even if a bit line adjacent to the first bit line BL0 in an adjacent plane is pre-charged, there will be no coupling problem between that bit line and the first bit line BL0.

[0064] In one possible implementation, such as Figure 10 As shown, the at least one page buffer includes a second page buffer B2 and a third page buffer B3. Among the multiple bit lines, the first bit line B0 at the first end of the plane is coupled to the first page buffer B1 via a gating circuit. The second bit line B15 at the second end of the plane is coupled to the second page buffer B2 via a gating circuit. All bit lines except the first bit line B0 and the second bit line B15 are coupled to the third page buffer B3 via gating circuits. With this structure, while continuously pre-charging the first bit line at the first end of the plane, the second bit line B15 at the second end of the plane can also be continuously pre-charged. Simultaneously, bit lines other than the first bit line B0 and the second bit line B15 can be pre-charged sequentially from the first bit line B0 to the second bit line B15. Alternatively, bit lines other than the first bit line B0 and the second bit line B15 can be pre-charged sequentially from the second bit line B15 to the first bit line B0.

[0065] For example, such as Figure 11As shown, assume the plane includes 16 bit lines. The first bit line is BL0, and the second bit line is BL15. During the data loading phase of the programming operation, the gating switch SG0 corresponding to the first bit line BL0 can be continuously turned on, thereby continuously pre-charging the first bit line B0 through the first page buffer B1. Simultaneously, the gating switch SG15 corresponding to the second bit line B15 can be continuously turned on, thereby continuously pre-charging the second bit line B15 through the second page buffer B2. Furthermore, each bit line in the plane except for the first bit line B0 and the second bit line B15 can be coupled to the third page buffer B3 through corresponding gating switches (SG1~SG14). During the data loading phase of the programming operation, the corresponding gating switches can be turned on sequentially from the first bit line BL0 to the second bit line BL15, or sequentially from the second bit line BL15 to the first bit line BL0. Based on this, the bit lines at both ends of the plane are continuously pre-charged during the data loading phase, ensuring that the bit lines at both ends of the plane do not couple with adjacent bit lines in adjacent planes.

[0066] In one possible implementation, the at least one page buffer includes a first page buffer B1, a second page buffer B2, and a third page buffer B3. Of the multiple bit lines, the first bit line BL0, located at the first end of the plane, is coupled to the first page buffer B1 via a gating circuit 722; the second bit line BL15, located at the second end of the plane, is coupled to the second page buffer B2 via the gating circuit 722. The bit lines other than the first bit line BL0 and the second bit line BL15 comprise a first portion and a second portion. The bit lines in the first portion are coupled to the second page buffer B2 via the gating circuit 722. The bit lines in the second portion are coupled to the third page buffer B3 via the gating circuit 722.

[0067] In one embodiment, the bit lines in the first part include the (n+1)th bit line from the second bit line BL15 to the first bit line direction BL0. The bit lines in the second part include the nth bit line from the second bit line BL15 to the first bit line BL0; where n is an odd number, and its specific value range is determined according to the total number of bit lines in the plane, which is not specifically limited in this embodiment.

[0068] For example, such as Figure 12As shown, assume a plane has 16 bit lines (BL0 to BL15). The first bit line is BL0, and the second bit line is BL15. The bit lines in the first part are the second bit line BL13, the fourth bit line BL11, the sixth bit line BL9, the eighth bit line BL7, the tenth bit line BL5, the twelfth bit line BL3, and the fourteenth bit line BL1, moving from the second bit line to the first bit line. The bit lines in the second part are the first bit line BL14, the third bit line BL12, the fifth bit line BL10, the seventh bit line BL8, the ninth bit line BL6, the eleventh bit line BL4, and the thirteenth bit line BL2, moving from the second bit line to the first bit line. In this way, during the data loading phase of the programming operation, the gating switch corresponding to the first bit line BL0 can be continuously turned on, thereby continuously pre-charging the first bit line BL0 through the first page buffer. Additionally, the corresponding selector switches can be sequentially activated in the order of BL1 to BL15 to precharge each bit line. For example, Figure 13 As shown, to address the coupling issue between adjacent bit lines in a plane, during the continuous pre-charging of the first bit line located at the first end of the plane, the pre-charging timing of adjacent bit lines (excluding the first bit line) partially overlaps. For example, when the gating switch corresponding to BL2 is on, the gating switch corresponding to BL1 remains on. When the gating switch corresponding to BL3 is on, the gating switch corresponding to BL2 remains on, and so on, until all bit lines in the plane have completed pre-charging. In this implementation, the gating switch corresponding to the first bit line BL0 can also be intermittently turned on during the data loading phase. For example, the gating switch corresponding to the first bit line BL0 can be turned on before the gating switch corresponding to bit line BL1 is turned on, and then turned off after a period of time. Then, the first bit line BL0 is turned on before the gating switch corresponding to the second bit line BL15 is turned off.

[0069] In another embodiment, the bit lines in the first part include the first to nth bit lines in the direction from the second bit line BL15 to the first bit line BL0. The bit lines in the second part include the (n+1)th to kth bit lines in the direction from the second bit line BL15 to the first bit line BL0. The maximum value of k is the total number of bit lines between the first bit line BL0 and the second bit line BL15, and its specific range is determined based on the total number of bit lines in the plane; this embodiment does not impose a specific limitation on this. The value of n ranges from 1 to k-1.

[0070] For example, such as Figure 14As shown, suppose a plane has 16 bit lines (BL0 to BL15). The first bit line is BL0, and the second bit line is BL15. The first part of the bit lines refers to the first bit line BL14 to the seventh bit line BL8 in the direction from the second bit line BL15 to the first bit line BL0. The second part of the bit lines refers to the eighth bit line BL7 to the fourteenth bit line BL1 in the direction from the second bit line BL15 to the first bit line BL0. In this way, as... Figure 15 As shown, during the data loading phase of the programming operation, the gating switch corresponding to the first bit line BL0 can be continuously turned on, thereby continuously pre-charging the first bit line BL0 through the first page buffer B1. Alternatively, the corresponding gating switches can be turned on sequentially in the order of BL1 to BL15 to pre-charge each bit line.

[0071] In one possible implementation, the at least one page buffer includes a first page buffer B1, a second page buffer B2, a third page buffer B3, and a fourth page buffer B4. The first bit line BL0, located at the first end of the plane, is coupled to the first page buffer B1 via a gating switch SG0 in the gating circuit 722. The second bit line BL15, located at the second end of the plane, is coupled to the second page buffer B2 via a gating switch SG15 in the gating circuit 722. Of the multiple bit lines, the bit lines other than the first bit line BL0 and the second bit line BL15 include a first portion and a second portion. The bit line of the first portion is coupled to the third page buffer B3 via the gating circuit 722. The bit line of the second portion is coupled to the fourth page buffer B4 via the gating circuit 722.

[0072] In one embodiment, the bit lines in the first part include the (n+1)th bit line in the direction from the second bit line BL15 to the first bit line BL0. The bit lines in the second part include the nth bit line in the direction from the second bit line BL15 to the first bit line BL0; where n is an odd number, and its specific value range is determined according to the total number of bit lines in the plane, which is not specifically limited in this embodiment.

[0073] For example, such as Figure 16As shown, assuming the plane includes 16 bit lines (BL0~BL15), where the first bit line is BL0 and the second bit line is BL15. The bit lines in the first part are the second bit line BL13, the fourth bit line BL11, the sixth bit line BL9, the eighth bit line BL7, the tenth bit line BL5, the twelfth bit line BL3, and the fourteenth bit line BL1, running from the second bit line BL15 to the first bit line BL0. The bit lines in the second part are the first bit line BL14, the third bit line BL12, the fifth bit line BL10, the seventh bit line BL8, the ninth bit line BL6, the eleventh bit line BL4, and the thirteenth bit line BL2, running from the second bit line BL15 to the first bit line BL0. During the data loading phase of the programming operation, the activation timing of the selector switches (SG0~SG15) corresponding to each bit line (BL0~BL15) is as follows: Figure 17 As shown. During the continuous pre-charging of the first bit line located at the first end of the plane, the second bit line located at the second end of the plane can be continuously pre-charged. Simultaneously, from the first bit line BL0 to the second bit line BL15, the bit lines other than the first bit line BL0 and the second bit line BL15 are pre-charged sequentially. Alternatively, from the second bit line BL15 to the first bit line BL0, the bit lines other than the first bit line BL0 and the second bit line BL15 are pre-charged sequentially. For example, the selector switches corresponding to the first bit line BL0 and the second bit line BL15 can be continuously turned on, thereby continuously pre-charging the first bit line BL0 through the first page buffer and continuously pre-charging the second bit line BL15 through the second page buffer. The bit lines of the first part and the bit lines of the second part can have their corresponding selector switches turned on sequentially in the order from BL1 to BL14, thereby pre-charging each bit line. Alternatively, the bit lines of the first part and the bit lines of the second part can have their corresponding selector switches turned on sequentially in the order from bit line BL14 to bit line BL1, thereby pre-charging each bit line. When the gating switch of a certain bit line is turned on, the gating switch of the previous bit line is still turned on, thus solving the coupling problem between two adjacent bit lines in the plane.

[0074] In the above implementation, the corresponding gating switches (SG0 to SG15) can also be turned on sequentially from bit line BL0 to bit line BL15. Except for the first bit line, the precharge timing of adjacent bit lines overlaps. For example, when the gating switch of bit line BL1 is turned on, the gating switch corresponding to bit line BL0 remains on; when the gating switch corresponding to bit line BL2 is turned on, the gating switch corresponding to BL1 remains on. This continues until the gating switch corresponding to bit line BL15 is turned on. Furthermore, considering that X-NAND memory often involves simultaneous programming operations across multiple planes, when the gating switch corresponding to bit line BL15 is turned on, the gating switch corresponding to bit line BL1 in the adjacent plane is also turned on.

[0075] In another embodiment, the bit lines in the first part include the first to nth bit lines from the second bit line BL15 in the direction of the first bit line BL0. The bit lines in the second part include the (n+1)th to kth bit lines from the second bit line BL15 in the direction of the first bit line BL0. The maximum value of k is the total number of bit lines between the first and second bit lines, and its specific range is determined based on the total number of bit lines in the plane; this embodiment does not impose specific limitations on this. The value of n ranges from 1 to k-1.

[0076] For example, such as Figure 18 As shown, assume the plane includes 16 bit lines (BL0~BL15). The first bit line is BL0, and the second bit line is BL15. The first part of the bit lines consists of the first bit line BL14 to the seventh bit line BL8 in the direction from the second bit line BL15 to the first bit line BL0. The second part of the bit lines consists of the eighth bit line BL7 to the fourteenth bit line BL1 in the direction from the second bit line BL15 to the first bit line BL0. During the data loading phase of the programming operation, the activation timing of the selector switches (SG0~SG15) corresponding to each bit line is as follows: Figure 19 As shown. The selector switches corresponding to the first bit line BL0 and the second bit line BL15 can be continuously turned on, thereby continuously pre-charging the first bit line BL0 through the first page buffer and continuously pre-charging the second bit line BL15 through the second page buffer B2. The bit lines in the first and second parts can have their corresponding selector switches turned on sequentially from BL1 to BL14, thereby pre-charging each bit line.

[0077] In the above-described implementation schemes, the number of bit lines in a plane is merely an example. In actual use, the number of bit lines in a plane is determined by the actual number of bit lines in each plane of the memory array 710. The bit line division method in the first part and the bit line division method in the second part described above is also merely an example and can be adjusted according to the actual number of bit lines. Furthermore, during the data loading phase of the programming operation, provided that the first bit line is continuously pre-charged through the first page buffer B1, the pre-charge timing of the remaining bit lines in the plane can be left unrestricted.

[0078] In one possible implementation, this application also provides a method for operating a memory, applied to a memory 700. The memory 700 includes a memory array 710 and peripheral circuitry 720. The memory array 710 is coupled to the peripheral circuitry 720. The memory array 710 includes multiple planes, each plane including multiple bit lines. The peripheral circuitry 720 includes a gating circuit 722 and multiple page buffers 721. Both the gating circuit 722 and the multiple page buffers 721 are coupled to logic control circuitry. Figure 20 As shown, this operation method can be executed by the logic control circuit in the peripheral circuit 720, and its specific execution process is as follows.

[0079] S201. Receive a first indication signal, which is used to indicate the conduction timing between each bit line in the plurality of bit lines and the corresponding page buffer in the plurality of page buffers.

[0080] When programming the memory array 710 is required, the logic control circuit can receive a first indication signal sent by an external device (e.g., a host). Based on the first indication signal, the conduction timing between each bit line and the corresponding page buffer among the multiple page buffers is determined, thereby determining the precharge timing of each bit line.

[0081] S202. In response to the first indication signal, the gate circuit is turned on according to the turn-on timing to precharge multiple bit lines, and the first bit line located at the first end of the plane is continuously precharged during the precharging process.

[0082] During the programming operation, the data to be programmed must first be loaded into the latches in each page buffer. The selection circuit 722 and multiple page buffers 721 are controlled by a logic control circuit to precharge the first bit line and other bit lines in the plane during the data loading phase. Specifically, the first bit line is continuously precharged during the data loading phase. Therefore, when precharging a bit line adjacent to the first bit line in another plane, coupling problems will not occur to the first bit line.

[0083] In one possible implementation, when precharging multiple bit lines according to the above-described turn-on timing selection circuit, the bit lines other than the first bit line can be precharged sequentially from the first bit line to the second bit line. The second bit line is the bit line located at the second end of the plane. This method solves the coupling problem between adjacent bit lines in two adjacent planes while reducing the number of page buffers used, thereby lowering costs.

[0084] In one possible implementation, when precharging multiple bit lines according to the above-described conduction timing gate circuit, the second bit line located at the second end of the plane can also be continuously precharged. In this way, the bit lines at both ends of the plane can be continuously precharged during the data loading phase, thereby better resolving the coupling problem between adjacent bit lines in two adjacent planes.

[0085] In one possible implementation, when precharging multiple bit lines according to the aforementioned conduction timing selection circuit, the bit lines other than the first bit line can be precharged sequentially from the first bit line to the second bit line and from the second bit line to the first bit line. The second bit line is the bit line located at the second end of the plane. In this way, bit lines at both ends of the plane can be precharged sequentially towards the middle bit line simultaneously, thereby improving the efficiency of data loading during the data loading stage.

[0086] In one possible implementation, when precharging multiple bit lines according to the above-described turn-on timing selection circuit, the precharging timing of two adjacent bit lines (excluding the first bit line) partially overlaps. In this way, the bit line with the later precharging timing among two adjacent bit lines can be precharged before the preceding bit line has finished precharging, thereby resolving the coupling problem between adjacent bit lines.

[0087] In one implementation scheme, such as Figure 21As shown, this application embodiment also provides a memory system 2100, which includes a memory controller 2110 and at least one memory 2120 coupled to the memory controller 2110. The memory system 2100 can be integrated into various types of storage devices, for example, included in the same package (e.g., universal flash storage (UFS) package or embedded multimedia card (eMMC) card). That is, the memory system 2100 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device having storage therein.

[0088] In some embodiments, the memory system 2100 includes a memory controller 2110 and a memory 2120. The memory system 2100 may be integrated into a memory card. The memory card may include any one of the following: PC card (PCMCIA, Personal Computer Memory Card International Association), compact flash (CF) card, smart media (SM) card, memory stick, multimedia card (MMC), secure digital memory card (SD) card, and UFS.

[0089] In other embodiments, the memory system 2100 includes a memory controller 2110 and a plurality of memories 2120. The memory system 2100 is integrated into a solid-state drive (SSD).

[0090] In some embodiments, the memory controller 2110 is configured to operate in a low duty cycle environment, such as an SD card, CF card, universal serial bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0091] In other embodiments, the memory controller 2110 is configured to operate in high duty cycle environments using SSDs or eMMCs, which are data storage devices for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays. In some embodiments, the memory controller 2110 may be configured to manage data stored in the memory 2120 and to communicate with external devices (e.g., host 2210). In some embodiments, the memory controller 2110 may also be configured to control operations of the memory 2120, such as read, erase, and program operations. In some embodiments, the memory controller 2110 may also be configured to manage various functions relating to data stored or to be stored in the memory 2120, including at least one of bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some embodiments, the memory controller 2110 is also configured to process error correction codes relating to data read from or written to the memory 2120.

[0092] Of course, the memory controller 2110 can also perform any other suitable functions, such as formatting the memory; for example, the memory controller 2110 can communicate with external devices (e.g., host 2210) through at least one of various interface protocols. It should be noted that the interface protocols include at least one of the following: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and Firewire protocol.

[0093] Some embodiments of this application also provide an electronic device 2200. For example... Figure 22 As shown, the electronic device 2200 may include the memory system 2100 described above and a host 2210 coupled to the memory system 2100. The host 2210 may include at least one of a central processing unit (CPU) and a cache. The electronic device 2200 may be any of a mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle equipment, wearable device (e.g., smartwatch, smart bracelet, smart glasses, etc.), power bank, game console, digital multimedia player, etc.

[0094] In one possible implementation, this application also provides a computer-readable storage medium. This computer-readable storage medium stores computer program instructions. When executed by a processor or logic control circuit, these computer program instructions implement the aforementioned memory operation method. The computer-readable storage medium can be any available medium accessible to a computer, or a data storage device such as a server or data center integrating one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a digital video disc (DVD); or it can be a semiconductor medium, such as a solid-state drive (SSD).

[0095] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A memory, characterized in that, It includes a memory array and peripheral circuitry; the memory array is coupled to the peripheral circuitry; the memory array includes multiple planes; each plane includes multiple bit lines; the peripheral circuitry includes gating circuitry and multiple page buffers; The gating circuit is coupled to the plurality of page buffers; Of the plurality of bit lines, the first bit line located at the first end of the plane is coupled to the first page buffer of the plurality of page buffers through the gating circuit; the bit lines other than the first bit line are coupled to at least one page buffer other than the first page buffer of the plurality of page buffers through the gating circuit, and at least two bit lines other than the first bit line are coupled to the same page buffer of the at least one page buffer through the gating circuit. During the data loading phase of the programming operation, when precharging the multiple bit lines, the first bit line is continuously precharged.

2. The memory according to claim 1, characterized in that, The at least one page buffer includes a second page buffer; Of the multiple bit lines, the second bit line located at the second end of the plane is coupled to the second page buffer through the gating circuit.

3. The memory according to claim 2, characterized in that, The at least one page buffer further includes a third page buffer; of the plurality of bit lines, all bit lines except the first bit line and the second bit line are coupled to the third page buffer through the gating circuit.

4. The memory according to claim 2, characterized in that, The at least one page buffer further includes a third page buffer; of the plurality of bit lines, the bit lines other than the first bit line and the second bit line include a first portion and a second portion; wherein... The bit lines in the first part are coupled to the second page buffer via the gating circuit; the bit lines in the second part are coupled to the third page buffer via the gating circuit.

5. The memory according to claim 2, characterized in that, The at least one page buffer further includes a third page buffer and a fourth page buffer; of the plurality of bit lines, the bit lines other than the first bit line and the second bit line include a first portion and a second portion; wherein... The bit lines of the first portion are coupled to the third page buffer via the gating circuit; the bit lines of the second portion are coupled to the fourth page buffer via the gating circuit.

6. The memory according to claim 4 or 5, characterized in that, The bit lines in the first part include the (n+1)th bit line in the direction from the second bit line to the first bit line; the bit lines in the second part include the nth bit line in the direction from the second bit line to the first bit line; where n is an odd number.

7. The memory according to claim 4 or 5, characterized in that, The bit lines in the first part include the first to nth bit lines in the direction from the second bit line to the first bit line; the bit lines in the second part include the (n+1)th to kth bit lines in the direction from the second bit line to the first bit line; wherein, the maximum value of k is the total number of bit lines between the first bit line and the second bit line.

8. The memory according to claim 1, characterized in that, The gating circuit includes multiple gating switches; each bit line in the multiple bit lines is coupled to the corresponding page buffer through a gating switch.

9. A method for operating a memory, characterized in that, The invention is applied to a memory, which includes a memory array and peripheral circuitry; the memory array is coupled to the peripheral circuitry; the memory array includes multiple planes; each plane includes multiple bit lines; The peripheral circuitry includes a gating circuit and multiple page buffers; The gating circuit is coupled to the plurality of page buffers; the method includes: Receive a first indication signal; the first indication signal is used to indicate the conduction timing between each bit line in the plurality of bit lines and the corresponding page buffer in the plurality of page buffers; In response to the first indication signal, the gating circuit is turned on according to the turn-on timing to precharge the multiple bit lines, and the first bit line located at the first end of the plane is continuously precharged during the precharging process.

10. The method according to claim 9, characterized in that, The method further includes: When the selection circuit is turned on according to the turn-on timing, and the multiple bit lines are pre-charged, the bit lines other than the first bit line are pre-charged sequentially from the first bit line to the second bit line; wherein, the second bit line is the bit line located at the second end of the plane.

11. The method according to claim 9, characterized in that, The method further includes: When the selection circuit is turned on according to the turn-on timing, and the multiple bit lines are pre-charged, the second bit line located at the second end of the plane is continuously pre-charged.

12. The method according to claim 11, characterized in that, The method further includes: When the selection circuit is turned on according to the turn-on timing, and the multiple bit lines are pre-charged, the bit lines other than the first bit line and the second bit line are pre-charged sequentially from the first bit line to the second bit line; or, the bit lines other than the first bit line and the second bit line are pre-charged sequentially from the second bit line to the first bit line.

13. The method according to claim 9, characterized in that, The method further includes: When the selection circuit is turned on according to the turn-on timing, the multiple bit lines are pre-charged in sequence from the first bit line to the second bit line and from the second bit line to the first bit line; wherein, the second bit line is the bit line located at the second end of the plane.

14. The method according to any one of claims 9-13, characterized in that, When the selection circuit is turned on according to the turn-on timing, and the multiple bit lines are precharged, the precharge timing of two adjacent bit lines, excluding the first bit line, partially overlaps.

15. A memory system, characterized in that, include: A memory controller and a memory coupled to the memory controller as described in any one of claims 1-8.

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