A memory operation method, a memory, a memory system, and an electronic system

Abstract

This application discloses an operation method for a memory, a memory, a memory system, and an electronic system. The memory includes a page buffer, which includes a first sensing circuit coupled to a sensing node and a dynamic storage circuit coupled to the first sensing circuit. The memory's storage cells are configured to store one of a plurality of programmed states. The operation method includes: storing first verification information to the first sensing circuit based on a first potential of the sensing node; transmitting initial verification information from the dynamic storage circuit to the sensing node; transmitting the first verification information from the first sensing circuit to the dynamic storage circuit and performing a clear operation on the first sensing circuit; and storing second verification information or initial verification information to the first sensing circuit based on a second potential of the sensing node.

Description

Technical Field

[0001] This application relates to the field of memory technology, and in particular to a memory operation method, a memory, a memory system, and an electronic system. Background Technology

[0002] Currently, 3D NAND flash memory typically uses Incremental Step Pulse Programming (ISPP) for programming. Specifically, multiple progressively increasing pulse programming voltages are used sequentially to program the memory cells. Each programming process can include a programming operation and a verification operation, where the verification operation is performed after the programming operation. That is, after each programming operation is performed on a memory cell, a verification voltage is used to verify these memory cells. Summary of the Invention

[0003] This application provides an operation method for a memory, a memory, a memory system, and an electronic system.

[0004] In a first aspect, embodiments of this application provide a method for operating a memory, the memory including a page buffer, the page buffer including a first sensing circuit coupled to a sensing node and a dynamic storage circuit coupled to the first sensing circuit; the memory includes storage cells configured to store one of a plurality of programming states; the operation method includes:

[0005] Based on the first potential of the sensing node, the first verification information is stored in the first sensing circuit;

[0006] The initial verification information in the dynamic storage circuit is transmitted to the sensing node; the initial verification information includes the verification information corresponding to the verified programming state among the plurality of programming states;

[0007] The first verification information is transmitted from the first sensing circuit to the dynamic storage circuit, and the first sensing circuit is cleared.

[0008] Based on the second potential of the sensing node, store the second verification information or the initial verification information into the first sensing circuit;

[0009] Wherein, the first potential of the sensing node corresponding to the first verification information is greater than the second potential of the sensing node corresponding to the second verification information.

[0010] Secondly, embodiments of this application also provide a method for operating a memory, the memory including a page buffer, the page buffer including a first sensing circuit coupled to a sensing node and a dynamic storage circuit coupled to the first sensing circuit; the memory includes storage cells configured to store one of a plurality of programming states; the operation method includes:

[0011] During the first sensing phase of the verification operation in the memory, first verification information is latched into the first sensing circuit.

[0012] The initial verification information in the dynamic storage circuit is transmitted to the sensing node; the initial verification information includes verification information corresponding to the verified programming state among the multiple programming states contained in the memory;

[0013] The transmission channel between the first sensing circuit and the dynamic storage circuit is opened, and the first verification information is transmitted to the dynamic storage circuit; and the first sensing circuit is cleared.

[0014] In the second sensing phase of the verification operation, the second verification information is latched into the first sensing circuit;

[0015] Wherein, the first potential of the sensing node corresponding to the first verification information is greater than the second potential of the sensing node corresponding to the second verification information.

[0016] Thirdly, embodiments of this application provide a memory, including:

[0017] A storage array; the storage array contains storage units configured to store one of a plurality of programmed states;

[0018] Multiple page buffers coupled to the memory array; each page buffer includes: a first sensing circuit coupled to a sensing node and a dynamic memory circuit coupled to the first sensing circuit;

[0019] and control logic circuitry coupled to the memory array and the plurality of page buffers; wherein,

[0020] The control logic circuit is configured to: store first verification information in the first sensing circuit according to the first potential of the sensing node; transmit initial verification information in the dynamic storage circuit to the sensing node; the initial verification information includes verification information corresponding to the verified programming state among the plurality of programming states; transmit the first verification information from the first sensing circuit to the dynamic storage circuit and perform a clear operation on the first sensing circuit; and store second verification information or the initial verification information in the first sensing circuit according to the second potential of the sensing node; wherein the first potential of the sensing node corresponding to the first verification information is greater than the second potential of the sensing node corresponding to the second verification information.

[0021] Fourthly, embodiments of this application also provide a memory system, including: one or more of the aforementioned memories and a memory controller coupled to the memories and used to control the memories.

[0022] Fifthly, embodiments of this application also provide an electronic system, including: the aforementioned memory system and a host coupled to the memory system.

[0023] This application provides an operation method for a memory, a memory, a memory system, and electronics. The memory includes a page buffer, which includes a first sensing circuit coupled to a sensing node and a dynamic storage circuit coupled to the first sensing circuit. The memory's storage cells are configured to store one of a plurality of programming states. The operation method includes: storing first verification information to the first sensing circuit based on a first potential of the sensing node; transmitting initial verification information from the dynamic storage circuit to the sensing node; the initial verification information including verification information corresponding to a verified programming state among the plurality of programming states; transmitting the first verification information from the first sensing circuit to the dynamic storage circuit and performing a clear operation on the first sensing circuit; and storing second verification information or the initial verification information to the first sensing circuit based on a second potential of the sensing node; wherein the first potential of the sensing node corresponding to the first verification information is greater than the second potential of the sensing node corresponding to the second verification information. The operation method provided in this application embodiment transmits the initial verification information in the dynamic storage circuit to the sensing node, and transmits the first verification information from the first sensing circuit to the dynamic storage circuit, and performs a clearing operation on the first sensing circuit, thereby enabling the first sensing circuit to sense the first verification information and the second verification information at different times. This allows the programming verification operation of the 4BL (bit line) scheme of the memory cell to be completed by performing only one complete sensing under the same verification voltage. Attached Figure Description

[0024] In accompanying drawings that are not necessarily drawn to scale, the same reference numerals can describe similar components in different views. The same numbers with different letter suffixes can represent different instances of similar components. The accompanying drawings generally illustrate the various embodiments discussed in this document by way of example, not limitation.

[0025] Figure 1 An exemplary system block diagram of an electronic device having a memory system according to some aspects of this application;

[0026] Figure 2 This is a schematic diagram of an exemplary memory card with memory provided according to some aspects of this application;

[0027] Figure 3 A schematic diagram of an exemplary SSD with memory provided according to some aspects of this application;

[0028] Figure 4 This is a schematic diagram of an exemplary memory including peripheral circuitry provided according to some aspects of this application;

[0029] Figure 5 A side view of a cross section of an exemplary memory array 401 including NAND memory strings 408, provided according to some aspects of this application;

[0030] Figure 6 A block diagram of an exemplary memory including a memory array and peripheral circuitry, provided according to some aspects of this application;

[0031] Figure 7 A set of exemplary programming voltages for the ISPP programming method provided according to some aspects of this application;

[0032] Figure 8 A set of exemplary verification voltages for verification operations provided according to some aspects of this application;

[0033] Figure 9 A schematic diagram of a 4BL BIAS programming method provided according to some aspects of this application;

[0034] Figure 10 A comparison diagram of one and two sensing operations provided according to some aspects of this application;

[0035] Figure 11 This is a flowchart illustrating a method of operating a memory according to some aspects of this application;

[0036] Figure 12 This is a schematic diagram illustrating the relationship between a memory-included page buffer group and a memory array according to some aspects of this application;

[0037] Figures 13 to 16 This is a schematic diagram showing the state of the sensing nodes corresponding to the first storage unit, the second storage unit, and the third storage unit before and after the initial verification information in the dynamic storage circuit is transmitted to the sensing node, according to some aspects of this application.

[0038] Figure 17 A schematic diagram of a circuit structure for a page buffer 121 provided according to some aspects of this application;

[0039] Figure 18 This is a flowchart illustrating the implementation of the 4BLBIAS programming method using the operation method provided in the embodiments of this application, according to some aspects of this application.

[0040] Figure 19 This is a flowchart illustrating a memory operation method described from a timing perspective, according to some aspects of this application.

[0041] Figure 20 For some aspects provided in accordance with this application Figure 19 A timing diagram describing the operation method;

[0042] Figure 21 This is a schematic diagram of the structure of a memory provided according to some aspects of this application. Detailed Implementation

[0043] The various embodiments of this application are described in more detail below with reference to the accompanying drawings. Other embodiments, which can be variations of any disclosed embodiment, can be formed by different configurations or arrangements of the elements and features in the embodiments of this application. Therefore, the embodiments of this application are not limited to the embodiments set forth herein. Rather, the described embodiments are provided so that the embodiments of this application are thorough and complete, and fully convey the scope of the embodiments of this application to those skilled in the art to which the embodiments of this application pertain. It should be noted that references to "embodiment," "another embodiment," etc., do not necessarily indicate only one embodiment, and different references to any such phrases do not necessarily refer to the same embodiment. It should be understood that although the terms "first," "second," "third," etc., may be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element having the same or similar name. Therefore, without departing from the spirit and scope of the embodiments of this application, a first element in one embodiment may also be referred to as a second or third element in another embodiment.

[0044] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale may be enlarged to clearly show the features of the embodiments. When an element is referred to as a connection or coupling to another element, it should be understood that the former may be directly connected to or coupled to the latter, or may be electrically connected to or coupled to the latter via one or more intermediate elements between the two. Furthermore, it should be understood that when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or there may be one or more intermediate elements.

[0045] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application. Singular forms as used herein are intended to include plural forms unless the context clearly indicates otherwise. Unless otherwise stated or clearly understood from the context, the articles “a” and / or “an” used in the embodiments of this application and the appended claims should be interpreted as meaning “one or more”. It should be further understood that the terms “comprising,” “including,” “containing,” and “comprising” as used in the embodiments of this application specify the presence of the stated element and do not exclude the presence or addition of one or more other elements. The term “and / or” as used in the embodiments of this application includes any and all combinations of one or more of the associated listed items. Unless otherwise defined, all terms used in the embodiments of this application, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains in light of the embodiments of this application. It should be further understood that unless explicitly defined in the embodiments of this application, terms such as “belong to” as defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the embodiments of this application and related technologies, and should not be interpreted in an idealized or overly formal manner.

[0046] In the following description, numerous specific details are set forth to provide a thorough understanding of this application, which can be practiced without some or all of these specific details. In other instances, well-known processing structures and / or processes have not been described in detail to avoid unnecessarily obscuring this application. It should also be understood that, in some cases, unless otherwise specifically apparent to those skilled in the art, a feature or element described with respect to one embodiment may be used alone or in combination with other features or elements of another embodiment. Various embodiments of this application are described in detail below with reference to the accompanying drawings. The following description focuses on details to facilitate understanding of embodiments of this application. Well-known technical details may have been omitted to avoid obscuring the features and aspects of the embodiments of this application.

[0047] This application relates to a memory operation method that enables the programming verification operation of the 4BL scheme of the memory cell to be completed with only one complete sensing under the same verification voltage.

[0048] The embodiments of this application will be further described in detail below with reference to the accompanying drawings and specific examples.

[0049] Figure 1 A block diagram of an exemplary system with memory according to some aspects of this application is shown. Figure 1 In this context, system 100 can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. For example... Figure 1 As shown, system 100 may include a host 108 and a memory system 102, wherein the memory system 102 has one or more memories 104 and a memory controller 106; the host 108 may be a processor of an electronic device, such as a central processing unit (CPU) or a system-on-a-chip (SoC), wherein the SoC may be, for example, an application processor (AP). The host 108 may be configured to send data to or receive data from the memory 104. Specifically, the memory 104 may be any memory disclosed in this application, such as phase-change random access memory (PCRAM), three-dimensional NAND flash memory, etc.

[0050] According to some embodiments, memory controller 106 is coupled to memory 104 and host 108, and is configured to control memory 104. Memory controller 106 can manage data stored in memory 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in a low duty cycle environment, such as on Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones in low duty cycle environments. In some embodiments, memory controller 106 is designed to operate in a high duty cycle environment, such as on solid-state drives (SSDs) or embedded multimedia cards (eMMCs), where SSDs or eMMCs are used as data storage for mobile devices in high duty cycle environments such as smartphones, tablets, and laptops, as well as enterprise storage arrays. Memory controller 106 can be configured to control the operation of memory 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECCs) relating to data read from or written to the memory 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 can communicate with external devices (e.g., host 108) according to specific communication protocols.For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0051] The memory controller 106 and one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2 In one example shown, the memory controller 106 and a single memory 104 can be integrated into the memory card 202. The memory card can include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card can also include a connector for the memory card to a host computer (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 3 In another example shown, the memory controller 106 and multiple memories 104 can be integrated into the SSD 302. The SSD may also include components for connecting the SSD to a host computer (e.g., Figure 1 The SSD connector 304 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD is greater than that of the memory card. Furthermore, the memory controller 106 can also be configured to control erase, read, and write operations of the memory 104.

[0052] Figure 4 A schematic diagram of an exemplary memory including peripheral circuitry is shown. Figure 4As shown, memory 104 may include a memory array 401 and peripheral circuitry 402 coupled to the memory array 401. The memory array 401 may be a NAND flash memory array, wherein memory cells 406 are provided in the form of an array of NAND memory strings 408, each NAND memory string 408 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 408 includes a plurality of memory cells 406 coupled in series and stacked vertically. Each memory cell 406 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the storage region of the memory cell 406. Each memory cell 406 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0053] In some embodiments, each memory cell 406 is a single-level cell (SLC) with two possible data states and thus capable of storing one bit of data. For example, a first data state "0" may correspond to a first voltage range, and a second data state "1" may correspond to a second voltage range. In some embodiments, the first and second voltage ranges may be referred to as the threshold voltage distribution of the memory cell. In some embodiments, each memory cell 406 may be a multi-level cell (MLC). For example, an MLC may store two bits per cell, three bits per cell (also known as a trinary level cell (TLC), or four bits per cell (also known as a quadruple level cell (QLC)). Regardless of the type of memory cell, the data states include an erase state and one or more programmable states. When a programming operation is performed on a memory cell, the memory cell in the erase state is programmed to a certain programmable state. Generally, the voltage value in the voltage range corresponding to the programmable state of the memory cell is relatively large.

[0054] like Figure 4As shown, each NAND memory string 408 may include a source select gate (SSG) 410 at its source end and a drain select gate (DSG) 412 at its drain end. SSG 410 and DSG 412 can be configured to activate the selected NAND memory string 408 (column of the array) during read and program (or write) operations. In some embodiments, the sources of NAND memory strings 408 in the same memory block 404 are coupled via the same source line (SL) 414 (e.g., common SL). In other words, according to some embodiments, all NAND memory strings 408 in the same memory block 404 have an array common source (ACS). According to some embodiments, the DSG 412 of each NAND memory string 408 is coupled to a corresponding bit line 416, from which data can be read and written via an output bus (not shown). In some embodiments, each NAND memory string 408 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having DSG412) or a deselection voltage (e.g., 0 volts (V)) to the corresponding DSG412 via one or more DSG lines 413 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having SSG410) or a deselection voltage (e.g., 0V) to the corresponding SSG410 via one or more SSG lines 415.

[0055] like Figure 4 As shown, NAND memory strings 408 can be organized into multiple memory blocks 404, each of which can have a common source line 414 (e.g., coupled to ground). In some embodiments, each memory block 404 is a basic data unit with an erase operation, i.e., all memory cells 406 on the same memory block 404 are erased simultaneously. To erase memory cells 406 in a selected memory block 404, a source line 414 biased to the selected memory block 404 and unselected memory blocks 404 on the same plane as the selected memory block 404 can be used. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at any suitable number of blocks or any suitable fraction of blocks. Memory cells 406 of adjacent NAND memory strings 408 can be coupled via word lines 418, which select which row of memory cells 406 receives read and program operations. In some embodiments, memory cells 406 coupled to the same word line 418 form a page 420.

[0056] Figure 5 A side view of a cross-section of an exemplary memory array 401 including NAND memory strings 408 is shown, according to some aspects of this application. Figure 5As shown, the NAND memory string 408 may extend vertically through the memory stack layer 502 above the substrate 501. The substrate 501 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0057] The memory stack layer 502 may include alternating gate conductive layers 503 and gate-to-gate dielectric layers 504. The number of pairs of gate conductive layers 503 and gate-to-gate dielectric layers 504 in the memory stack layer 502 determines the number of memory cells 406 in the memory array 401. The gate conductive layers 503 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. In some embodiments, each gate conductive layer 503 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 503 includes a doped polysilicon layer. Each gate conductive layer 503 may include a control gate surrounding the memory cell 406 and may extend laterally at the top of the memory stack layer 502 as a DSG line 413, at the bottom of the memory stack layer 502 as an SSG line 415, or between DSG lines 413 and SSG lines 415 as a word line 418.

[0058] like Figure 5 As shown, the NAND memory string 408 includes a channel structure 505 extending vertically through the memory stack layer 502. In some embodiments, the channel structure 505 includes channel holes filled with one or more semiconductor materials and one or more dielectric materials. In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure 505 may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0059] Return to reference Figure 4Peripheral circuitry 402 can be coupled to memory array 401 via bit line 416, word line 418, source line 414, SSG line 415, and DSG line 413. Peripheral circuitry 402 can include any suitable analog, digital, and mixed-signal circuitry to facilitate operation of memory array 401 by applying voltage and / or current signals to each target memory cell 406 via bit line 416, word line 418, source line 414, SSG line 415, and DSG line 413, and by sensing voltage and / or current signals from each target memory cell 406. Peripheral circuitry 402 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 6 Some exemplary peripheral circuitry is shown. Peripheral circuitry 402 includes a page buffer / sensor amplifier 604, a column decoder / bit line driver 606, a row decoder / word line driver 608, a voltage generator 610, a control logic unit 612, a register 614, an interface 616, and a data bus 618. It should be understood that in some examples, additional components may be included. Figure 6 Additional peripheral circuitry not shown.

[0060] Page buffer / sensor amplifier 604 can be configured to read data from memory array 401 and program (write) data to memory array 401 according to control signals from control logic unit 612. In one example, page buffer / sensor amplifier 604 can store a page of programming data (write data) to be programmed into a page 420 of memory array 401. In another example, page buffer / sensor amplifier 604 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 406 coupled to selected word line 418. In yet another example, page buffer / sensor amplifier 604 can also sense a low-power signal from bit line 416 representing a data bit stored in memory cell 406 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 606 can be configured to be controlled by control logic unit 612 and select one or more NAND memory strings 408 by applying a bit line voltage generated from voltage generator 610.

[0061] The row decoder / word line driver 608 can be configured to be controlled by the control logic unit 612 and to select / deselect memory blocks 404 of the memory array 401 and to select / deselect word lines 418 of memory blocks 404. The row decoder / word line driver 608 can also be configured to drive word lines 418 using word line voltages generated from the voltage generator 610. In some embodiments, the row decoder / word line driver 608 can also select / deselect and drive SSG lines 415 and DSG lines 413. As described in detail below, the row decoder / word line driver 608 is configured to perform an erase operation on memory cells 406 coupled to one or more selected word lines 418. The voltage generator 610 can be configured to be controlled by the control logic unit 612 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 401.

[0062] Control logic unit 612 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 614 can be coupled to control logic unit 612 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 616 can be coupled to control logic unit 612 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic unit 612, as well as to buffer status information received from control logic unit 612 and relay it to the host. Interface 616 can also be coupled to column decoder / bit line driver 606 via data bus 618 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 401.

[0063] Based on the memory and memory system described above, for a memory with multiple programming states, such as a 3D NAND flash memory, programming a memory cell includes programming and verification operations. The programming operation can employ the ISPP method, which involves progressively increasing the word line bias voltage while simultaneously programming the selected memory cell several times. The incremental step pulse V... pgm For reference Figure 7This verification operation can be used to determine whether a programmed memory cell has been programmed to the target programming state. Typically, the verification operation is performed between two programming voltages applied to the word line coupled to the memory cell; that is, programming and verification operations can be performed alternately. When verifying at least one memory cell in the same programming state, a corresponding verification voltage is applied to the word line coupled to that at least one memory cell, and the memory cell's verification is verified based on this verification voltage. Considering that memory cells coupled to the same word line may be in different programming states, corresponding to different reference threshold voltages, multiple verification processes are required. Therefore, the verification operation can include one or a set of verification voltage pulses, such as... Figure 8 As shown, Figure 8 In the diagram, 1001 and 1003 represent the step programming pulses V. pgm 1002 represents the verification voltage pulse. Each verification typically requires pre-charging the sensing node coupled to the memory cell to a higher potential (e.g., the preset initial voltage described later). Then, the sensing node undergoes at least one discharge operation. This allows the sensing circuit to sense the voltage at the sensing node (SO) corresponding to different discharge stages of the memory cell. Based on this sensing result, it is determined whether the verification of the memory cell is complete. The verification result can be stored in the page buffer to reflect the programming result of the memory cell.

[0064] In some embodiments, 4BL BIAS programming is typically used in the programming of 3D NAND flash memory to improve programming quality. Specifically, 4BL BIAS programming involves controlling the voltage applied to the bit lines of the memory cells to differ based on the programming state of the cell being programmed and its target programming state. This results in a differentiation in the voltages on the bit lines of memory cells in different programming states, leading to more precise programming of each cell and a better distribution of the threshold voltage (Vt) of the memory cells. To determine the voltages on the bit lines of memory cells in different programming states, such as... Figure 9 As shown, in the verification operation of the 4BL BIAS programming method, three sensing operations are required: 3BL sensing, 4BL sensing, and Pass sensing, to determine whether the threshold voltage of the verified memory cell has reached the 3BL range, 4BL range, or Pass range, respectively. It should be noted that the 3BL sensing process corresponds to... Figure 9 The 3BL verification (VFY) shown; the 4BL sensing process corresponds to Figure 9 The 4BL VFY shown corresponds to the Pass sensing process. Figure 9The Pass VFY shown. The 3BL interval can refer to... Figure 9 The area to the left of 3BL VFY; the 4BL range can refer to Figure 9 The overlapping area between the right side of the 3BL VFY and the left side of the 4BL VFY; the Pass interval can refer to Figure 9 The diagram shows the overlapping area between the right side of 4BL VFY and the left side of Pass VFY. When a memory cell in different intervals is programmed again, the bias voltage applied to the bit line is different to more accurately program the memory cell to the target programmed state. For example, when a memory cell in the 3BL interval is programmed, its corresponding bit line is applied with 0 volts (V); when a memory cell in the 4BL interval is programmed, its corresponding bit line is applied with voltage VBL3; and when a memory cell in the Pass interval is programmed, its corresponding bit line is applied with voltage VBL4.

[0065] In some embodiments, the verification operation of the 4BL BIAS programming method includes: 3BL sensing is performed separately, that is: first, the sensing node coupled to the memory cell to be verified is pre-charged to a higher voltage (e.g., a preset initial voltage), then the sensing node is discharged, and after a period of discharge, the potential of SO is sensed to determine whether the threshold voltage of the memory cell reaches the 3BL range; then 4BL sensing and Pass sensing can be performed in a dual-strobe sensing manner, that is, while the corresponding sensing node is pre-charged to a higher voltage (e.g., a preset initial voltage), 4BL sensing and Pass sensing are performed at different time points during the discharge process of the sensing node, thereby shortening the verification time and improving the performance of the memory. The advantage of using dual-strobe sensing for 4BL sensing and Pass sensing is that, Figure 10 As shown, in a single sensing operation, nodes 1 and 3 detect the SO potential to perform 4BL sensing and Pass sensing, respectively. Since precharging the corresponding SO to the preset initial voltage takes a relatively long time, performing 4BL sensing and Pass sensing at nodes 1 and 3 during a single SO precharging operation requires only one precharging process. This is faster than performing 4BL sensing and Pass sensing at nodes 1 and 2 separately using two independent precharging operations. Therefore, the memory using the dual-strobe sensing verification method performs better.

[0066] However, the verification operation of the above-mentioned 4BL BIAS programming method requires precharging the sensing node coupled to the memory cell to be verified to a higher voltage two or three times in order to complete 3BL sensing, 4BL sensing and Pass sensing. It is not possible to precharge the sensing node only once under the same verification voltage and then sense at three different time points during the discharge process of the sensing node to complete 3BL sensing, 4BL sensing and Pass sensing.

[0067] Based on this, such as Figure 11 As shown, this application provides a memory operation method that can solve the above-mentioned problems. The memory to which this operation method is applicable may include a page buffer, the page buffer including a first sensing circuit coupled to a sensing node and a dynamic storage circuit coupled to the first sensing circuit; the memory includes storage cells configured to store one of a plurality of programming states. Specifically, the operation method may include:

[0068] S1101: Store first verification information into the first sensing circuit according to the first potential of the sensing node;

[0069] S1102: Transmit the initial verification information in the dynamic storage circuit to the sensing node; the initial verification information includes the verification information corresponding to the verified programming state among the plurality of programming states;

[0070] S1103: Transmit the first verification information from the first sensing circuit to the dynamic storage circuit, and perform a clearing operation on the first sensing circuit;

[0071] S1104: Store the second verification information or the initial verification information into the first sensing circuit according to the second potential of the sensing node;

[0072] Wherein, the first potential of the sensing node corresponding to the first verification information is greater than the second potential of the sensing node corresponding to the second verification information.

[0073] It should be noted that the memory structure described above only describes the structure related to the operation method provided in this application. For other parts of the memory structure, please refer to the foregoing. Figures 1 to 6 The structure of the memory is shown. It should be noted that... Figures 1 to 6 The memory shown and its described structure are merely exemplary and not limiting. In other words, the operating methods provided in this application embodiment can be applied to any memory with the aforementioned technical problems.

[0074] For page buffers, such as Figure 12As shown, it illustrates a schematic diagram of the structure of the page buffer group contained in the memory. Figure 12 In this memory, the page buffer includes a page buffer / sensor amplifier 504 as described above. In a memory, each bit line is coupled to one page buffer; that is, in some embodiments, the memory may include a page buffer group 120. The page buffer group 120 may be coupled to the memory array 401 via multiple bit lines BL1 to BLK. The page buffer group 120 may include page buffer 1 (PB1) to page buffer K (PBK), each page buffer 121 being coupled to the memory array 401 via a bit line. For example, page buffers PB1 to PBK may be coupled to the memory array 401 via corresponding bit lines BL1 to BLK, respectively.

[0075] Here, the page buffer mentioned in this application refers to any one of the aforementioned page buffer groups, and its function is similar to that of the page buffer / sensor amplifier 604 described above. The page buffer may include a first sensing circuit coupled to the sensing node and a dynamic storage circuit coupled to the first sensing circuit. The first verification information may refer to the verification result obtained through 3BL sensing in the verification operation of the 4BL BIAS programming method. The second verification information may refer to the verification result obtained through 4BL sensing in the verification operation of the 4BL BIAS programming method.

[0076] In practical applications, in memory with a page buffer containing the aforementioned structure, due to the structural limitations of the dynamic storage circuit, the 3BL sensing and 4BL sensing in the verification operation of this type of memory using the 4BL BIAS programming method cannot be completed in the same sensing operation (the same sensing operation can refer to the same pre-charging of the sensing node to a preset initial voltage, with 3BL sensing and 4BL sensing completed at different times during the discharge process of the sensing node). In other words, due to the structural limitations of the dynamic storage circuit, the assistance of the sensing node and the first sensing circuit is required when caching data. Specifically, after the 3BL sensing in the verification operation of the 4BL BIAS programming method is completed, the first sensing circuit latches the first verification information; subsequently, if 4BL sensing is performed, since the first sensing circuit stores the first verification information and the potential on the sensing node contains the second verification information, that is, both the sensing node and the first sensing circuit are occupied at this time. The sensing node cannot help transfer the first verification information in the first sensing circuit to the dynamic storage circuit. Therefore, the second verification information on the sensing node cannot be correctly latched by the first sensing circuit, that is, the second verification information cannot be correctly stored. That is, in the verification operation of the 4BL BIAS programming method, 3BL sensing and 4BL sensing cannot be completed in the same sensing operation. To solve the above problem, the embodiment provided in this application first transmits the initial verification information in the dynamic storage circuit to the sensing node; then, the first verification information is transmitted from the first sensing circuit to the dynamic storage circuit, and a clearing operation is performed on the first sensing circuit. Based on this, the second verification information can be latched again after the data in the first sensing circuit is cleared.

[0077] In some embodiments, the page buffer further includes a second sensing circuit coupled to the sensing node; the operation method further includes:

[0078] Based on the third potential of the sensing node, the third verification information is stored in the second sensing circuit;

[0079] Wherein, the second potential of the sensing node corresponding to the second verification information is greater than the third potential of the sensing node corresponding to the third verification information.

[0080] It should be noted that the third verification information mentioned here may refer to the verification result obtained through pass sensing in the verification operation of the 4BL BIAS programming method.

[0081] That is, according to the operation method described above, in the verification operation of the 4BL BIAS programming method, after the first verification information is latched in the first sensing circuit, the initial verification information in the dynamic storage circuit is first transmitted to the sensing node; then, the first verification information is transmitted from the first sensing circuit to the dynamic storage circuit, and the first sensing circuit is cleared; then, the second verification information is latched into the first sensing circuit; and then, the third verification information is latched into the second sensing circuit. In this way, the verification operation of the 4BL BIAS programming method can precharge the sensing voltage only once under the same verification voltage, and then sense at three different time points during the discharge process to complete 3BL sensing, 4BL sensing and Pass sensing.

[0082] Here, the initial verification information described may include verification information corresponding to the verified programming states among the plurality of programming states. The programming state contained in the memory cell corresponding to the page buffer of the dynamic memory containing the initial verification information has been verified. In some embodiments, the initial verification information may include the verification result obtained via 4BL sensing corresponding to the verified programming state among the plurality of programming states.

[0083] In some embodiments, the dynamic storage circuit corresponding to the first storage unit in the unverified programming state or the second storage unit in the verified programming state that failed verification is in the initial state is in the initial state.

[0084] It should be noted that the first storage unit may include the storage unit corresponding to the programming state to be verified among the plurality of programming states, for example, the storage unit corresponding to the Pn programming state among the plurality of programming states. The second storage unit may include the storage unit that failed verification in the verified programming state adjacent to the programming state to be verified among the plurality of programming states, for example, the storage unit that failed verification in the Pn-1 programming state among the plurality of programming states. This describes the situation where the dynamic storage circuit contained in the page buffer corresponding to the first and second storage units is in an initial state and has not yet been operated; that is, the data stored in the dynamic storage circuit contained in the buffers of the first and second storage units can be initial default data. This initial default data can be used to characterize that the dynamic storage circuit is in a reset state and can be operated. In some embodiments, the initial default data can be 1.

[0085] In some embodiments, the page buffer further includes at least one data latch circuit; before storing the first verification information to the first sensing circuit according to the first potential of the sensing node, the operation method further includes:

[0086] The selection operation information is obtained based on the data information in the at least one data latch circuit and the initial verification information in the dynamic storage circuit; the selection operation information is used to select the first storage unit in the pending programming state or the second storage unit in the verified programming state that has failed verification.

[0087] The selected operation information is stored in the second sensing circuit;

[0088] According to the selected operation information, the sensing nodes corresponding to the first storage unit and the second storage unit are precharged to a preset initial voltage.

[0089] It should be noted that the at least one data latch circuit can be used to temporarily store data to be programmed into the memory array or to temporarily store data read from the memory array. In some embodiments, each page buffer may contain more than two data latch circuits.

[0090] For example, when the storage unit is a TLC type storage unit, it can store 3 bits of data: the lower page (LP) data, the middle page (MP) data, and the upper page (UP) data. Correspondingly, the page buffer can include three data latches: the LP lower page latch, the MP middle page latch, and the UP upper page latch. When the storage unit is a QLC storage unit, it can store 4 bits of data: the lower page (LP) data, the middle page (MP) data, the upper page (UP) data, and the extra page (XP) data. Correspondingly, the page buffer can include four data latches: the LP lower page latch, the MP middle page latch, the UP upper page latch, and the XP extra page latch.

[0091] It should be noted that the above example is merely an exemplary correspondence between the number of data latch circuits in a page buffer and the number of bits of data stored in a memory cell. In practical applications, the number of data latch circuits can also be less than the number of bits stored in a memory cell; for example, some data latch circuits can be designed as dynamic latch circuits.

[0092] This describes a process where, before sensing the aforementioned first, second, and third verification information, the sensing nodes coupled to the selected memory cell need to be pre-charged. The selected memory cell can refer to the aforementioned first and second memory cells. The pre-charging process for the sensing nodes coupled to the selected memory cell may include: firstly, obtaining selection operation information based on data information in at least one data latch circuit and initial verification information in the dynamic storage circuit to determine the selected memory cell; then, storing the selection operation information in the second sensing circuit so that, during operation, the second sensing circuit pre-charges the sensing nodes corresponding to the first and second memory cells to a preset initial voltage based on the selection operation information. This preset initial voltage can be determined by design. The data information described here can refer to data programmed into the storage array and encoded accordingly. For example, the encoding could be Gray code. For an understanding of this step, please refer to the following... Figure 17 and Figure 18 The detailed descriptions in the text are omitted here.

[0093] In some embodiments, step S1102 may include:

[0094] The sensing node corresponding to the third storage unit that has been successfully verified in the verified programming state among the plurality of programming states is charged according to the initial verification information, so as to transmit the initial verification information to the sensing node.

[0095] Here, the third storage unit may include a successfully verified storage unit in a verified programming state adjacent to the programming state to be verified among the plurality of programming states, for example, a successfully verified storage unit in the Pn-1 programming state among the plurality of programming states. The aforementioned process of transmitting the initial verification information in the dynamic storage circuit to the sensing node can be as follows: charging the sensing node corresponding to the third storage unit according to the initial verification information, so as to transmit the initial verification information to the sensing node. Here, step S1102 can also be referred to as: reading the initial verification information onto the sensing node.

[0096] The following example illustrates the specific implementation of step 1102 above, using the programming state to be verified as Pn and the verified programming state as Pn-1.

[0097] Specifically, such as Figures 13 to 16 And as shown in Tables 1 to 3, where, Figure 13 This is a schematic diagram of the state of the sensing node and the dynamic storage circuit in the page buffer corresponding to the first storage unit in the Pn programming state before transmitting the initial verification information in the dynamic storage circuit to the sensing node, according to some aspects of this application. Figure 14This application provides a schematic diagram of the state of the sensing node and the dynamic storage circuit in the page buffer corresponding to the third storage unit in the Pn-1 programming state before transmitting the initial verification information in the dynamic storage circuit to the sensing node. Figure 15 This is a schematic diagram showing the state of the sensing node and the dynamic storage circuit in the page buffer corresponding to the first storage unit in the Pn programming state after the initial verification information in the dynamic storage circuit is transmitted to the sensing node, according to some aspects of this application. Figure 16 This is a schematic diagram of the state of the sensing node and the dynamic storage circuit in the page buffer corresponding to the second storage unit of the Pn-1 programming state after the initial verification information in the dynamic storage circuit is transmitted to the sensing node, according to some aspects of this application. Table 1 shows the states of the sensing node, dynamic storage circuit, and first sensing circuit in the page buffers corresponding to the first storage unit in the Pn programming state, the second storage unit in the Pn-1 programming state, and the third storage unit in the Pn-1 programming state before transmitting the initial verification information from the dynamic storage circuit to the sensing node; Table 2 shows the states of the sensing node, dynamic storage circuit, and first sensing circuit in the page buffers corresponding to the first storage unit in the Pn programming state, the second storage unit in the Pn-1 programming state, and the third storage unit in the Pn-1 programming state after transmitting the initial verification information from the dynamic storage circuit to the sensing node; Table 3 shows the states of the sensing node, dynamic storage circuit, and first sensing circuit in the page buffers corresponding to the first storage unit in the Pn programming state, the second storage unit in the Pn-1 programming state, and the third storage unit in the Pn-1 programming state after the second SO discharge (4BL sensing) following the completion of 3BL sensing.

[0098] exist Figure 13 In this context, the ds latch can be an exemplary structure of the aforementioned second sensing circuit; the dl latch can be an exemplary structure of the aforementioned first sensing circuit; and the dm transistor, with its corresponding parasitic capacitance, can be an exemplary structure of the aforementioned dynamic storage circuit.

[0099] Figure 13The diagram shows the potential of the SO corresponding to the first memory cell in the Pn programming state before the initial verification information in the dynamic storage circuit included in the page buffer is transmitted to the sensing node. This SO has completed 3BL sensing and latching of 3BL verification data, and has also undergone another discharge (4BL sensing). This potential can be represented by SO = "sensing". In this embodiment, since the selected memory cells are the first memory cell in the Pn programming state and the second memory cell in the Pn-1 programming state that failed 4BL verification, the second memory cell also performs the same verification operation as the first memory cell, i.e., it also performs 3BL sensing and latching of 3BL verification data; and the SO has also undergone another discharge (4BL sensing). The potential of the SO corresponding to the second memory cell in the Pn-1 programming state before the initial verification information in the dynamic storage circuit included in the page buffer is transmitted to the sensing node can be found in [reference needed]. Figure 13 This needs to be understood. However, for the dynamic storage circuits corresponding to the first and second storage units, since the first storage unit has not performed 4BL sensing data latching, its dynamic storage circuit is in its initial state, for example, DM = "1". Since the second storage unit is a storage unit that has not passed 4BL verification, the dynamic storage circuit has already performed 4BL sensing data latching, so the data stored in its dynamic storage circuit is the 4BL sensing verification result (not passed 4BL verification). At this time, the dynamic storage circuit corresponding to the second storage unit has DM = "4BL'".

[0100] exist Figure 14 In the middle, the structure of the page buffer and Figure 13 The structure of the middle page buffer is the same, as detailed above, and will not be repeated here.

[0101] Figure 14The diagram shows that before transmitting the initial verification information from the dynamic storage circuit in the page buffer to the sensing node, the third storage cell corresponding to the Pn-1 programming state is an unselected storage cell. Its corresponding SO is not pre-charged to the preset initial voltage, nor is it subjected to at least one discharge operation. At this time, the potential of the SO corresponding to the third storage cell does not change and can be represented as SO = "0". Furthermore, the state of the dynamic sensing circuit corresponding to the third storage cell is DM = 4BL', where 4BL' is the verification result of the third storage cell via 4BL sensing (verified by 4BL). Here, although the dynamic storage circuits of both the second and third storage cells store 4BL', their specific states are different, and the stored values ​​are different. In some embodiments, the dynamic storage circuit DM = 4BL' = "1" for the second storage cell and DM = 4BL' = "0" for the third storage cell, representing opposite states.

[0102] Specifically, Figure 13 and Figure 14 The described state is the same as the state described in Table 1.

[0103] Table 1

[0104] Pn-1 Pn DM (or dm) 4BL 1 SO 0 sensing DS (or ds) ~4BL / 0 1

[0105] exist Figure 15 In the middle, the structure of the page buffer and Figure 13 , Figure 14 The structure of the middle page buffer is the same, as detailed above, and will not be repeated here. Specifically, Figure 15 This describes the potential of SO in the page buffer corresponding to the first memory cell in the Pn programming state after the initial verification information in the dynamic storage circuit is transmitted to the sensing node. Since no control signal en_4bl_b is applied to the page buffer in the Pn programming state, the page buffer corresponding to the first memory cell in the Pn programming state does not perform the operation of transmitting the initial verification information in the dynamic storage circuit to the sensing node, and the potential of SO remains at the potential during 4BL sensing. Therefore, it can still be represented as: SO = "sensing". Correspondingly, since the SO corresponding to the second memory cell undergoes the same operation as the first memory cell, the potential of SO corresponding to the second memory cell can also be represented as: SO = "sensing". According to the above understanding, the state of the dynamic storage circuit of the first and second memory cells is still DM = "1".

[0106] Similarly, in Figure 16 In the middle, the structure of the page buffer and Figure 13 , Figure 14 , Figure 15 The structure of the intermediate page buffer is the same, as detailed above, and will not be repeated here. Specifically, after transmitting the initial verification information in the dynamic storage circuit to the sensing node, the potential of the sensing node of the page buffer corresponding to the third storage unit in the Pn-1 programming state is adjusted. Since the control signal en_4bl_b is applied to the page buffer corresponding to the third storage unit, the potential of SO corresponding to the third storage unit in the Pn-1 programming state is pulled high. That is, the page buffer corresponding to the third storage unit has performed the operation of transmitting the initial verification information in the dynamic storage circuit to the sensing node. The potential of SO of the third storage unit can be represented as SO = "4BL'"; correspondingly, the state of the dynamic storage circuit corresponding to the third storage unit is DM = "4BL'".

[0107] Specifically, Figure 15 and Figure 16 The described state is the same as the state described in Table 2.

[0108] Table 2

[0109] Pn-1 Pn DM (or dm) 4BL 1 SO 4BL sensing DS (or ds) ~4BL / 0 1

[0110] based on Figures 13 to 16As can be seen from the description of the states of the devices related to the various technical solutions of this application in the page buffer, before the initial verification information in the dynamic storage circuit is transmitted to the sensing node, since the first and second storage units are the storage units to be verified, the sensing nodes corresponding to the first and second storage units are pre-charged to a preset initial voltage and then discharged to perform 3BL sensing and 4BL sensing. Therefore, the potential of the sensing node of the page buffer corresponding to the first storage unit in the Pn programming state and the sensing node of the page buffer corresponding to the second storage unit in the Pn-1 programming state can be expressed as SO = "sensing". The third storage unit is a storage unit that has been verified and successfully verified. Therefore, its corresponding sensing node is not pre-charged to the preset initial voltage. That is, before the initial verification information in the dynamic storage circuit is transmitted to the sensing node, the potential of the sensing node corresponding to the third storage unit can be expressed as SO = "0". After the initial verification information in the dynamic storage circuit is transmitted to the sensing node, since the current verified Pn programming state does not have 4BL data, and the 4BL data corresponding to the Pn-1 programming state that failed 4BL is unverified data, the page buffers corresponding to the first storage unit of the Pn programming state and the second storage unit of the Pn-1 programming state that failed 4BL will not be given the control signal en_4bl_b. Therefore, they will not perform the operation of transmitting (or reading) the initial verification information in the dynamic storage circuit to the corresponding SO. Thus, the SO will not be precharged, that is, the sensing on the SO is unaffected. However, the page buffer corresponding to the third storage unit is given the control signal en_4bl_b and its dynamic storage circuit stores the initial verification information (that is, the verification result of the successfully programmed 4BL sensing). Therefore, the page buffer corresponding to the third storage unit performs the operation of reading the initial verification information to the corresponding SO, thereby reading the initial verification information to the SO.

[0111] Here, Table 3 shows the status of the sensing nodes, dynamic storage circuit, and second sensing circuit of the first storage unit, the second storage unit, and the third storage unit after the first verification information is stored.

[0112] Table 3

[0113] Pn-1 Pn DM (or dm) 3BL 3BL SO 0 sensing DS (or ds) ~4BL / 0 1

[0114] In some embodiments, the step S1103, which involves transmitting the first verification information from the first sensing circuit to the dynamic storage circuit, may include:

[0115] The transmission channel between the first sensing circuit and the dynamic storage circuit is opened, so that the first verification information in the first sensing circuit is transmitted to the dynamic storage circuit.

[0116] It should be noted that the first sensing circuit and the dynamic storage circuit can transmit data, and there is a storage channel between them. Therefore, in order to store the first verification information from the first sensing circuit to the corresponding storage circuit, the transmission channel between them must first be opened, so that the first verification information in the first sensing circuit can be transmitted to the corresponding dynamic storage circuit.

[0117] In some embodiments, the clearing operation of the first sensing circuit in step 1103 may include:

[0118] The first sensing circuit is reset to its initial state.

[0119] It should be noted that in order to store the second verification information, the first sensing circuit needs to be cleared before storage. That is, the first sensing circuit needs to be reset to restore the first sensing circuit to its initial state, for example, restoring the first sensing circuit dl = "1".

[0120] In some embodiments, the operating method further includes:

[0121] The sensing node is discharged from the preset initial voltage. After a first preset time, the discharge to the sensing node is paused. The first potential of the sensing node is sensed, and the first verification information is stored in the first sensing circuit.

[0122] The sensing node is discharged from the first potential. After a second preset time, the discharge to the sensing node is paused. After the first sensing circuit is cleared, the second potential of the sensing node is sensed, and the second verification information is stored in the first sensing circuit.

[0123] The sensing node is discharged from the second potential. After a third preset time, the discharge to the sensing node is paused. The third potential of the sensing node is sensed, and the third verification information is stored in the second sensing circuit.

[0124] In some embodiments, the operating method further includes:

[0125] If the first potential is greater than or equal to the first preset voltage, the first verification information is used to indicate the first group of storage cells in the first storage cell and the second storage cell that have passed the verification of the first verification voltage.

[0126] If the second potential is greater than or equal to the second preset voltage, the second verification information is used to indicate the second group of storage cells in the first storage cell and the second storage cell that have passed the verification of the second verification voltage;

[0127] If the third potential is greater than or equal to the third preset voltage, the third verification information is used to indicate the third group of storage cells in the first storage cell and the second storage cell that have passed the verification of the third verification voltage.

[0128] Wherein, the first verification voltage is less than the second verification voltage; the second verification voltage is less than the third verification voltage.

[0129] It should be noted that the description here is that after the sensing node is precharged to a preset initial voltage, it undergoes three discharges to achieve the verification operation of the 4BL BIAS programming method. This allows the bit line to be precharged only once at the same verification voltage. Then, during the discharge process, sensing is performed at three different time points to complete 3BL sensing, 4BL sensing, and Passsensing.

[0130] Specifically, the sensing nodes corresponding to the aforementioned first and second storage units are pre-charged to a preset initial voltage. After discharging for a first preset duration, the first potential of the sensing node is lower than the predetermined initial voltage. The first potential of the corresponding sensing node is sensed, and first verification information is stored. Obtaining the first verification information may include comparing the first potential with a first preset voltage to obtain the first verification information and latching the first verification information. Then, based on the first potential, the sensing node is discharged for a second preset duration, and then the second potential of the sensing node is sensed. Based on the comparison of the second potential with a second preset voltage, second verification information is obtained and finally stored. Similarly, based on the second potential, the sensing node is discharged for a third preset duration, and then the third potential of the sensing node is sensed. Based on the comparison of the third potential with a third preset voltage, third verification information is obtained and finally stored. The first, second, and third preset durations may be different. In some embodiments, the first preset duration is less than the second preset duration; the second preset duration is less than the third preset duration.

[0131] The embodiments of this application charge the sensing node at the initial moment, and at least three verification operations are completed sequentially with only one charging operation, which reduces the number of times the sensing node needs to be charged during the sensing process and saves verification time.

[0132] In this embodiment, taking the ISPP programming scheme of a 3D NAND flash memory storage device as an example, in different programming stages of an ISPP programming process, in order to optimize the threshold voltage distribution and make the threshold voltage of the memory cell more concentrated in the threshold voltage region of the corresponding data state, different bit line voltages are biased on the bit lines of memory cells of different bit lines, that is, bit line forcing operation is implemented. In this way, even if the programming voltage Vpgm of the gate (applied through the word line) of the memory cells of different bit lines is the same, the programming effect will be different. The threshold voltage difference of memory cells with large current threshold voltage differences will be reduced after programming and will be relatively closer to the threshold voltage region of the corresponding data.

[0133] In some embodiments, the operating method may further include:

[0134] Different bit line voltages are applied to the bit lines coupled to the first memory cell based on the first verification information, the second verification information, and the third verification information.

[0135] Specifically, a first bit line voltage is applied to the first bit line connected to the first forced unit; a second bit line voltage is applied to the second bit line connected to the second forced unit; and a programmable disable bit line voltage is applied to the third bit line connected to the third group of memory cells. The first forced unit is a memory cell in the first group of memory cells other than the second group of memory cells and the third group of memory cells. The second forced unit is a memory cell in the second group of memory cells other than the third group of memory cells.

[0136] It should be noted that, in the embodiments of this application, based on the first verification information, the second verification information and the third verification information, two bit line forced operation programming methods can be used for different memory cells in one programming process. In this way, the memory cells can be prevented from being overprogrammed, thereby reducing the width of the threshold voltage distribution of multiple memory cells and improving the accuracy of programming operations.

[0137] Specifically, the control logic circuit of the memory is configured to: apply a first bit line voltage to the first bit line connected to the first forced unit, apply a second bit line voltage to the second bit line connected to the second forced unit, apply a programmable inhibit bit line voltage to the third bit line connected to the third group of memory cells, and apply a programming voltage to the selected word line, based on the first verification information, the second verification information, and the third verification information; wherein, the first bit line voltage is greater than the ground voltage and less than the programmable inhibit bit line voltage, and the second bit line voltage is greater than the first bit line voltage. Here, the first forced unit refers to the memory cells in the first group of memory cells other than the second group of memory cells and the third group of memory cells; the second forced unit refers to the memory cells in the second group of memory cells other than the third group of memory cells; wherein, the first group of memory cells may refer to the first group of memory cells, which includes memory cells in the first and second groups of memory cells that have passed the verification of the first verification voltage; the second group of memory cells may refer to the second group of memory cells, which includes memory cells in the first and second groups of memory cells that have passed the second verification voltage; the third group of memory cells may be memory cells in the first and second groups of memory cells that have passed the third verification voltage.

[0138] In some embodiments, the control logic circuit is further configured to apply a normal programming bit line voltage Vprog (e.g., ground voltage Vgnd) to the memory cell performing normal programming operations based on first verification information, second verification information, and third verification information. Here, the programmable bit line voltage Vinh can be the power supply voltage Vdd, the first bit line voltage is greater than the ground voltage (normal programming bit line voltage Vprog) and less than the programmable bit line voltage Vinh, and the second bit line voltage is greater than the first bit line voltage and less than the programmable bit line voltage Vinh.

[0139] In programming processes such as ISPP, when applying the same programming voltage Vpgm to a selected row of memory cells for programming operations, the sensing circuit can use the first verification information DL, the second verification information DM, and the third verification information DS to apply corresponding bit line voltages to the corresponding memory cells, thereby allowing the memory cells to be differentiated for bit line forced operations. In other words, in the embodiments of this application, different memory cells are classified for programming control, and the memory cells can be divided into normal programming cells, first forced cells that will undergo a first bit line forced operation, second forced cells that will undergo a second bit line forced operation, and third memory cells that will undergo a prohibited programming operation. Different bit line voltages are used to classify and program these four types of memory cells. During the programming operation, in addition to using two bit line voltages—the disable programming bit line voltage Vinh (e.g., Vdd) and the normal programming bit line voltage Vprog (e.g., ground voltage Vgnd)—if only one forced bit line voltage (greater than the normal programming bit line voltage Vprog and less than the disable programming bit line voltage Vinh) is added to perform programming operations on multiple forced cells, although programming operations with a certain degree of differentiation can be achieved, the threshold voltage distribution of multiple memory cells after programming may not be narrow enough. Therefore, in the programming operation of this embodiment, in addition to using the disable programming bit line voltage Vinh (e.g., VDD) and the normal programming bit line voltage Vprog (e.g., ground voltage Vgnd), a first bit line voltage and a second bit line voltage (both greater than the normal programming bit line voltage Vprog and less than the disable programming bit line voltage Vinh) are also used to perform programming operations with finer differentiation on multiple memory cells.

[0140] In some embodiments, the operating method further includes:

[0141] After applying different bit line voltages to the bit line coupled to the first memory cell, it is determined whether the programming state to be verified is the last programming state among the plurality of programming states;

[0142] If it is determined that the programming state to be verified is not the last programming state, an exchange operation is performed on the first sensing circuit and the dynamic storage circuit, so that the second verification information is stored in the dynamic storage circuit and the first verification information is stored in the first sensing circuit.

[0143] It should be noted that, as described above, the memory provided in this application embodiment includes multiple programming states. After applying different bit line voltages to the first memory cell according to the first verification information, second verification information, and third verification information corresponding to the programming state to be verified, the verification of the programming state to be verified has been completed, and the information obtained from the verification guides the next programming. It is necessary to determine whether the programming state to be verified is the last programming state. If it is not the last programming state, the first sensing circuit and the dynamic storage circuit need to perform an exchange operation, so that the second verification information is stored in the dynamic storage circuit and the first verification information is stored in the first sensing circuit. That is, the data of the first sensing circuit and the dynamic storage circuit are transmitted bidirectionally to realize the exchange of data, thereby preparing for the verification of the next programming state. If the programming state to be verified is the last programming state, the verification ends.

[0144] In some embodiments, programming the memory includes at least one programming cycle; the programming cycle includes programming operations and verification operations; the operation method may further include:

[0145] Before the verification operation, the first sensing circuit and the dynamic storage circuit are cleared.

[0146] It should be noted that, as mentioned above, the verification operation performed between two programming operations includes verification of each of the multiple programming states. Therefore, the term "before the verification operation" here can refer to the period before the verification operation of the first programming state among the multiple programming states contained in the memory. In other words, before the verification operation, a clearing operation is performed on the first sensing circuit and the dynamic storage circuit; or, before the current verification operation, the data stored in the first sensing circuit and the dynamic storage circuit by the previous verification or programming operation is cleared, i.e., the first sensing circuit and the dynamic storage circuit are reset and restored to their initial state for later use.

[0147] To understand the operation method provided in the embodiments of this application, please refer to... Figures 17 to 18 As shown, where, Figure 17 A schematic diagram of a circuit structure for a page buffer is shown. Figure 18 This diagram illustrates a complete BLBIAS programming method for verification operations using the operation method provided in the embodiments of this application.

[0148] It should be noted that, in Figure 17 The page buffer shown includes at least: a precharge circuit, a discharge circuit, a first sensing circuit dl, a second sensing circuit ds, a dynamic sensing circuit dm, and a data latch circuit (d1, d2, d3, dc), wherein;

[0149] The pre-charge circuit is coupled to the corresponding bit line through the sensing node SO and is configured to receive a power supply voltage (e.g., VDD). During SO pre-charging, it provides a preset initial voltage to SO. It includes a transmission gate composed of transistors P1 and P2 connected in parallel and transistor P3. Each transistor responds to the signal generated by the third verification information stored in the second sensing circuit, the Prech_all signal, and the Prech_sel signal, respectively, to pre-charge SO to the preset initial voltage. The discharge circuit includes transistors T3 and T4 connected in series and is configured to discharge SO in response to the discharge signal sodisch and the signal generated by the third verification information stored in the second sensing circuit, respectively. In addition, the page buffer also includes: a first transistor T1 and a second transistor T2 connected in series, wherein one end of the first transistor is connected to the positive terminal of the power supply (e.g., VDD); one end of the second transistor is connected to the sensing node, and the second transistor is controlled by a first transmission signal; and the first transistor is controlled by initial verification information. Under the action of the first transmission signal and the initial verification information, the first transistor and the second transistor are turned on to charge the sensing node corresponding to the third memory cell that has been successfully verified in the multiple programming states, so as to transmit the initial verification information to the sensing node.

[0150] Combination Figure 17 The page buffer is described, and without loss of generality, it is assumed that a single (verification) verify sequence contains programming states Pn-1, Pn, and Pn+1. Since the selection of a programming state is based on 0 data in D1 / D2 / D3 / DC (d1, d2, d3, and dc), selecting a programming state may involve selecting a state lower than that programming state. Therefore, it is assumed that the selection of state Pn may simultaneously select Pn-1. Using this as an example, the steps of the memory programming verification method provided in this application embodiment are described, where 3BL data (i.e., the first verification information) is represented by 0 to represent reaching 3BL, and 4BL data (and the second verification information) is represented by 0 to represent reaching 4BL. See [link / reference] Figure 18 The process shown specifically includes:

[0151] ① Begin verification; this step combines Figure 17 The circuit is described as follows: When entering verify from program pulse, the 3BL data in DL is cleared (DL=1), and the 4BL data in DM is cleared (DM=1), thus entering the verification operation.

[0152] ② Select the Pn programming state; here, the selection process has been described in detail above, and the selected memory cells to be verified also include those memory cells in the Pn-1 programming state that failed programming verification, that is: the selected memory cells include the aforementioned first and second memory cells. This step combines... Figure 17The circuit description is as follows: The Pn-1 state verify is similar to the Pn state. Assuming that the Pn-1 verify is completed, the verify Pn state is entered. The selected programming state operation DS = DM & P* is performed. P* selects the Pn programming state based on the data in D1 / D2 / D3 / DC. DM contains the 4BL data of the Pn-1 programming state. Therefore, the selection operation will select all Pn state cells and cells in the Pn-1 state that have not passed 4BL.

[0153] ③ 3BL sensing; Here, before 3BL sensing, the SO corresponding to the first and second memory cells is pre-charged and pre-charged to a preset initial voltage. During 3BL sensing, the first verification information is latched into the first sensing circuit DL. This step is combined with... Figure 17 The circuit description is as follows: SO is precharged using data from DS (i.e., the aforementioned selected operation information). Then, SO continuously develops and discharges. After the development time of t_sodev_3bl, soblk and sodisch are turned off to stop development. Then, rst_l is turned on to sense the 3BL data into DL (DL = DL & ~ SO). Here, the symbol & represents logical AND; the symbol ~ represents logical NOT.

[0154] ④ Read 4BL; here, reading 4BL means transmitting the initial verification information in the dynamic storage circuit corresponding to the third storage unit to the corresponding sensing node. The specific process has been explained in detail above and will not be repeated here. This step is combined with Figure 17 The circuit description is as follows: Soblk and Sodisch are turned on. After the develop time of t_sodev_4bl, Soblk and Sodisch are turned off to stop the develop process. Then, en_4bl_b is turned on to read the 4BL' data from state Pn-1 onto SO (SO = SO|~DM). In this step, since the currently verified Pn state does not have 4BL data, the SO in the Pn state will not be precharged, and SOsensing is unaffected. Here, the symbol | represents a logical OR, and both expressions on both sides of the symbol are evaluated, followed by a truth / false judgment.

[0155] ⑤, Transmit / Clear DL; that is: DM = DL; DL = "1". Here, it corresponds to the aforementioned clearing operation of the first sensing circuit, the specific operation of which has been described in detail above and will not be repeated here.

[0156] ⑥, 4BL sensing; that is: DL = ~SO. Here, based on 3BL sensing, SO is discharged for a period of time (e.g., the second preset duration), and then the second verification information is latched into the first sensing circuit DL.

[0157] The two steps are combined Figure 17 The circuit description is as follows: Pass_l is opened to transfer 3BL data to DM; DL data is cleared to prepare for 4BL sensing (DL=1); rst_l is opened to sense 4BL data into DL (DL=~SO). The symbol = indicates assignment.

[0158] ⑦ Pass sensing; Here, based on 4BL sensing, SO is further discharged for a period of time (e.g., a third preset duration), and then the third verification information is latched into the second sensing circuit DS. This step combines... Figure 17 The circuit is described as follows: turn on soblk and sodisch, and after the develop time of t_sodev_Pass, turn off soblk and sodisch to stop develop; clear the DS data to prepare for Pass sensing (DS=1); turn on rst_s to sense the Pass data into DS (DS=~SO); during the develop process, because sodisch is turned on, the 4BL' data on SO will be cleared by DS.

[0159] ⑧. The Pass memory cell is disabled from programming; this means that, based on the first verification information, the second verification information, and the third verification information, different bit line voltages are applied to the bit lines coupled to the first memory cell, and the memory cells that have passed verification are disabled from programming (the disable programming bit line voltage is applied to the third bit line connected to the third group of memory cells). This step is combined with... Figure 17 The circuit description is as follows: The Pass data in DS is used to inhibit the data of D1 / D2 / D3 / DC in Pn state, i.e., write it as 1. That is: D* = `DS&P*.

[0160] 9. Determine if this is the last programmed state;

[0161] ⑩ If not, exchange the second verification information in DL with the first verification information in DM. This step combines... Figure 17 The circuit is described as follows: Data in DL and DM are swapped. After the swap, DL contains 3BL data and DM contains 4BL data. Then, the Pn+1 state verify operation is performed, similar to the above.

[0162] If so, end the verification process. Pn+1 is the last verify programming state, so after it ends, it directly enters verify recovery, ending the verify sequence.

[0163] This application provides a memory operation method. By transmitting initial verification information from the dynamic storage circuit to the sensing node, and transmitting the first verification information from the first sensing circuit to the dynamic storage circuit, and clearing the first sensing circuit, the first sensing circuit can sense the first and second verification information at different times. This allows for the completion of 4BL (bit line) programming verification of the memory cell using only one complete sensing operation under the same verification voltage. Specifically, in the page buffer structure based on a dynamic latch, the 4BL programming verification uses triple-strobe, detecting SO data at three time points during a complete SO sensing discharge to obtain 3BL / 4BL / Pass data (first verification information, second verification information, and third verification information). This scheme effectively reduces programming time and improves programming performance.

[0164] Based on the same inventive concept, this application also provides another memory operation method. This embodiment is described from a timing perspective to illustrate how the operation method provided by this application enables the verification operation of the 4BL BIAS programming mode to precharge the bit line only once under the same verification voltage, and then sense at three different time points during the discharge process to complete 3BL sensing, 4BL sensing, and Pass sensing. It should be noted that the memory to which this operation method is applicable also includes a page buffer, which includes a first sensing circuit coupled to the sensing node and a dynamic storage circuit coupled to the first sensing circuit; the memory contains storage cells configured to store one of a plurality of programming states.

[0165] Specifically, such as Figure 19 As shown, the operation method may include:

[0166] S1901: In the first sensing phase of the verification operation of the memory, the first verification information is latched into the first sensing circuit.

[0167] S1902: Transmit the initial verification information in the dynamic storage circuit to the sensing node; the initial verification information includes verification information corresponding to the verified programming state among the multiple programming states contained in the memory;

[0168] S1903: Open the transmission channel between the first sensing circuit and the dynamic storage circuit, transmit the first verification information to the dynamic storage circuit, and perform a clearing operation on the first sensing circuit;

[0169] S1904: In the second sensing phase of the verification operation, the second verification information is latched into the first sensing circuit;

[0170] Wherein, the first potential of the sensing node corresponding to the first verification information is greater than the second potential of the sensing node corresponding to the second verification information.

[0171] In some embodiments, the page buffer further includes: a second sensing circuit coupled to the sensing node; the operation method further includes:

[0172] In the third sensing phase of the verification operation, third verification information is latched into the second sensing circuit, wherein the second potential of the sensing node corresponding to the second verification information is greater than the third potential of the sensing node corresponding to the third verification information.

[0173] In some embodiments, the page buffer further includes at least one data latch circuit; prior to the first sensing phase of the verification operation of the memory, the operation method further includes: a pre-charge phase and a first discharge phase, wherein;

[0174] During the pre-charging phase, the selected operation information is latched into the second sensing circuit; the sensing node is pre-charged to a preset initial voltage based on the selected operation information.

[0175] In the first discharge phase, the sensing node is discharged from the preset initial voltage, and after a first preset time, the discharge to the sensing node is paused.

[0176] The selected operation information is obtained based on the data information in the at least one data latch circuit and the initial verification information in the dynamic storage circuit, and is used to select the first storage unit in the pending programming state or the second storage unit in the verified programming state that has failed verification.

[0177] In some embodiments, latching the first verification information to the first sensing circuit includes:

[0178] After the sensing node stops discharging, the first sensing circuit responds to the first latch signal and latches the first verification information into the first sensing circuit.

[0179] In some embodiments, before the second sensing phase of the verification operation of the memory, the operation method further includes: a second discharge phase; wherein, in the second discharge phase, the sensing node is discharged from the first potential, and after a second preset time, the discharge of the sensing node is paused.

[0180] After the second sensing phase of the verification operation of the memory, the operation method further includes a third discharge phase; wherein, in the third discharge phase, the sensing node is discharged from the second potential, and after a third preset time, the discharge of the sensing node is paused.

[0181] In some embodiments, the operating method further includes:

[0182] After the second discharge phase, the first sensing circuit is made to respond to the second latch signal and latch the second verification information to the first sensing circuit.

[0183] After the third discharge phase, the second sensing circuit is caused to latch the third verification information to the second sensing circuit in response to the third latch signal.

[0184] In some embodiments, after the third sensing phase of the verification operation, the operation method further includes:

[0185] Different bit line voltages are applied to the bit lines coupled to the first memory cell in the programming state to be verified in the plurality of programming states, based on the first verification information, the second verification information, and the third verification information.

[0186] Specifically, a first bit line voltage is applied to the first bit line connected to the first forced unit; a second bit line voltage is applied to the second bit line connected to the second forced unit; and a programmable disable bit line voltage is applied to the third bit line connected to the third group of memory cells. The first forced unit is a memory cell in the first group of memory cells other than the second group of memory cells and the third group of memory cells. The second forced unit is a memory cell in the second group of memory cells other than the third group of memory cells.

[0187] In some embodiments,

[0188] The first group of storage cells includes the storage cells that have passed the verification of the first verification voltage.

[0189] The second group of storage cells includes the storage cells in the first storage cell that have passed the verification of the second verification voltage;

[0190] The third group of storage units includes the storage units in the first storage unit that have passed the verification of the third verification voltage;

[0191] Wherein, if the first potential is greater than or equal to the first preset voltage, the first verification information is used to indicate the first group of storage cells in the first storage cell and the second storage cell that have passed the verification of the first verification voltage.

[0192] If the second potential is greater than or equal to the second preset voltage, the second verification information is used to indicate the second group of storage cells in the first storage cell and the second storage cell that have passed the verification of the second verification voltage;

[0193] If the third potential is greater than or equal to the third preset voltage, the third verification information is used to indicate the third group of storage cells in the first storage cell and the second storage cell that have passed the verification of the third verification voltage.

[0194] The first verification voltage is less than the second verification voltage; the second verification voltage is less than the third verification voltage.

[0195] In some embodiments, after the third sensing phase of the verification operation, the operation method further includes:

[0196] After applying different bit line voltages to the bit line coupled to the first memory cell, it is determined whether the programming state to be verified is the last programming state among the plurality of programming states;

[0197] If it is determined that the programming state to be verified is not the last programming state, an exchange operation is performed on the first sensing circuit and the dynamic storage circuit, so that the second verification information is stored in the dynamic storage circuit and the first verification information is stored in the first sensing circuit.

[0198] In some embodiments, programming the memory includes at least one programming cycle; the programming cycle includes a programming operation and a verification operation; before the verification operation, the operation method further includes a clearing operation on the first sensing circuit and the dynamic storage circuit.

[0199] In some embodiments, the page cache further includes a first transistor and a second transistor connected in series; wherein one end of the first transistor is connected to the positive terminal of a power supply; one end of the second transistor is connected to the sensing node; the step of transmitting the initial verification information in the dynamic storage circuit to the sensing node includes:

[0200] The second transistor is controlled by the first transmission signal; and the first transistor is controlled by the initial verification information;

[0201] Under the action of the first transmission signal and the initial verification information, the first transistor and the second transistor are turned on to charge the sensing node corresponding to the third memory cell that has been successfully verified in the multiple programming states, so as to transmit the initial verification information to the sensing node.

[0202] It should be noted that the memory operation method described above from a timing perspective is conceptually the same as the memory operation method described above. The implementation of the technical features and the interpretation of the terms mentioned therein have been clearly described above and will not be repeated here.

[0203] To understand the operation method described above from a timing perspective, such as Figure 20 As shown, the verification operation of the 4BL BIAS programming method implemented by the operation method provided in the embodiments of this application can precharge the bit line only once under the same verification voltage, and then sense at three different time points during the discharge process to complete 3BL sensing, 4BL sensing and Pass sensing.

[0204] like Figure 20 As shown, the verification operation of the aforementioned 4BL BIAS programming scheme includes three stages: 3BL sensing, 4BL sensing, and Pass sensing. Therefore, the operation method described from a time-series perspective is also described around these three stages. The first sensing stage is also known as 3BL sensing; the second sensing stage is also known as 4BL sensing; and the third sensing stage is also known as Pass sensing.

[0205] Therefore, in terms of the timing sequence, the specific process of this operation method can be as follows: Before the first sensing stage, a pre-charging stage and a first discharging stage are performed. Specifically, in the pre-charging stage, in response to the control of the pre-charging signal prech_sel, the corresponding SO is pre-charged to a preset initial voltage; in the first discharging stage, in response to the discharging signals vsoblk and vsodsch, the SO is discharged from the preset initial voltage for a period of time (e.g., a first preset duration), and the discharge of the SO is paused; then, the first sensing stage begins; in this stage, in response to the control of the first latch signal rst_l, the first verification information is latched into the first sensing circuit (3bl). After the SO is discharged for a period of time (e.g., a second preset time), the discharge of the SO is paused. Then, in response to the first transmission signal en_4bl_b, the initial verification information is read onto the corresponding SO. In response to the second transmission signal pass_l, the first verification information is transmitted to the dynamic storage circuit, and in response to the clear signals rst_sa_latch and set_l, the first verification information in the first sensing circuit is cleared. Then, the second sensing stage begins. In this stage, in response to the second latch signal rst_l' (generated with a timing different from the first latch signal), the second verification information is latched onto the first sensing circuit (4BL strobe). Then, after the SO is discharged for a period of time (e.g., a third preset time), the discharge of the SO is paused. Then, the third sensing stage begins. In this stage, in response to the third latch signal rst_s, the third verification information is latched onto the second sensing circuit (fine strobe). Thus, with one pre-charge of the SO, the verification operation of the 4BL BIAS programming scheme, including 3BL sensing and 4BL, is completed through three sensing at different time points. Sensing and Pass sensing.

[0206] Based on the same inventive concept, such as Figure 21 As shown, this application embodiment provides a memory 210, including:

[0207] Storage array 2101; the storage array includes storage units configured to store one of a plurality of programmed states;

[0208] A page buffer group 2102 coupled to the storage array, wherein the page buffer group 2102 includes a plurality of page buffers; each page buffer includes: a first sensing circuit coupled to a sensing node and a dynamic storage circuit coupled to the first sensing circuit;

[0209] and control logic circuitry 2103 coupled to the memory array and the plurality of page buffers; wherein,

[0210] The control logic circuit is configured to: store first verification information in the first sensing circuit according to the first potential of the sensing node; transmit initial verification information in the dynamic storage circuit to the sensing node; the initial verification information includes verification information corresponding to the verified programming state among the plurality of programming states; transmit the first verification information from the first sensing circuit to the dynamic storage circuit and perform a clear operation on the first sensing circuit; and store second verification information or the initial verification information in the first sensing circuit according to the second potential of the sensing node; wherein the first potential of the sensing node corresponding to the first verification information is greater than the second potential of the sensing node corresponding to the second verification information.

[0211] In some embodiments, the page buffer further includes: a second sensing circuit coupled to the sensing node;

[0212] The control logic circuit is further configured to: store third verification information into the second sensing circuit based on the third potential of the sensing node; wherein the second potential of the sensing node corresponding to the second verification information is greater than the third potential of the sensing node corresponding to the third verification information.

[0213] In some embodiments, the page buffer further includes at least one data latch circuit; the control logic circuit is further configured to: obtain selection operation information based on data information in the at least one data latch circuit and the initial verification information in the dynamic storage circuit; the selection operation information is used to select a first storage unit in the pending programming state or a second storage unit in the verified programming state that has failed verification; store the selection operation information in the second sensing circuit; and precharge the sensing nodes corresponding to the first storage unit and the second storage unit to a preset initial voltage based on the selection operation information.

[0214] In some embodiments, the page cache further includes a first transistor and a second transistor connected in series;

[0215] Wherein, the other end of the first transistor is connected to the positive terminal of the power supply; the other end of the second transistor is connected to the sensing node; the first transistor is controlled by the initial verification information; the second transistor is controlled by the first transmission signal; under the action of the first transmission signal and the initial verification information, the first transistor and the second transistor are turned on to charge the sensing node corresponding to the third memory cell that has been successfully verified in the multiple programming states, so as to transmit the initial verification information to the sensing node.

[0216] In some embodiments, the page buffer further includes a transmission switch; the transmission switch is configured to transmit the first verification information from the first sensing circuit to the dynamic storage circuit in response to a second transmission signal sent by the control logic circuit.

[0217] In some embodiments, the page buffer further includes a precharge circuit; the control logic circuit is further configured to: obtain selected operation information based on data information in the at least one data latch circuit and initial verification information stored in the dynamic storage circuit; latch the selected operation information to the second sensing circuit; and generate a precharge signal;

[0218] The pre-charging circuit is configured to: in response to the pre-charging signal, pre-charge the sensing nodes corresponding to the first storage unit and the second storage unit to the preset initial voltage based on the selected operation information.

[0219] In some embodiments, the page buffer further includes a discharge circuit;

[0220] The control logic circuit is further configured to generate a first discharge signal, a second discharge signal, and a third discharge signal.

[0221] The discharge circuit is configured to: in response to the first discharge signal, cause the sensing node to start discharging from the preset initial voltage, and after a first preset time, pause the discharge to the sensing node;

[0222] In response to the second discharge signal, the sensing node is caused to discharge from the first potential, and after a second preset time, the discharge to the sensing node is paused.

[0223] In response to the third discharge signal, the sensing node is made to discharge from the second potential, and after a third preset time, the discharge to the sensing node is paused.

[0224] Here, the first discharge signal, the second discharge signal, and the third discharge signal are used to correspond to the discharge of SO in the first discharge stage, the discharge of SO in the second discharge stage, and the discharge of SO in the third discharge stage, respectively.

[0225] In some embodiments, the first sensing circuit includes a first latch for storing first verification information; the second sensing circuit includes a second latch for storing third verification information; and the dynamic storage circuit includes a dynamic latch for storing second verification information.

[0226] In some embodiments, the control logic circuit is further configured to: after applying different bit line voltages to the bit line coupled to the first memory cell based on the first verification information, the second verification information, and the third verification information, determine whether the programming state to be verified is the last programming state among the plurality of programming states; if it is determined that the programming state to be verified is not the last programming state, control the first sensing circuit and the dynamic storage circuit to perform an exchange operation, so that the second verification information is stored in the dynamic storage circuit and the first verification information is stored in the first sensing circuit.

[0227] In some embodiments, after the first verification information is transmitted from the first sensing circuit to the dynamic storage circuit, the first sensing circuit is further configured to: reset the first sensing circuit in response to a clear signal sent by the control logic circuit, so that the first sensing circuit returns to its initial state.

[0228] It should be noted that the memory provided in this application embodiment is a hardware structure for implementing the operation method provided in the aforementioned application embodiment. The operation steps provided in this application embodiment involved here have been described in detail above. Therefore, the terms appearing in the operation steps in the memory described here can be understood with reference to the aforementioned description of the operation method, and will not be repeated here.

[0229] Based on the same inventive concept, embodiments of this application also provide a memory system, including: one or more of the aforementioned memory and a memory controller coupled to the memory and used to control the memory.

[0230] This application also provides an electronic system, including: the aforementioned memory system and a host coupled to the memory system.

[0231] It should be noted that the memory system and electronic system provided in the embodiments of this application include the aforementioned memory, and the two have the same technical features. The structure of the memory and the terms appearing in the technical solutions related to this application have been described in detail above. Therefore, the terms appearing here can be understood according to the meanings described above, and will not be repeated here.

[0232] The above description is intended to be illustrative and not restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used, such as those applicable to a person skilled in the art upon reading the above description. It should be understood that it is not intended to interpret or limit the scope or meaning of the claims. Furthermore, in the above detailed description, various features may be combined to simplify the application. This should not be construed as meaning that any unclaimed disclosed feature is essential to any claim. Rather, the subject matter of the disclosure may lie in fewer than all features of a particular disclosed embodiment. Therefore, the appended claims are thus incorporated into the detailed description, wherein each claim is an independent, separate embodiment, and these embodiments are contemplated to be combined with each other in various combinations or substitutions. The scope of this application should be determined by reference to the appended claims and the full scope of their equivalents.

Claims

1. A method for operating a memory, characterized in that, The memory includes a page buffer, which includes a first sensing circuit coupled to a sensing node and a dynamic storage circuit coupled to the first sensing circuit. The memory contains storage units configured to store one of a plurality of programming states; The operation method includes: Based on the first potential of the sensing node, the first verification information is stored in the first sensing circuit; The initial verification information in the dynamic storage circuit is transmitted to the sensing node; the initial verification information includes the verification information corresponding to the verified programming state among the plurality of programming states; The first verification information is transmitted from the first sensing circuit to the dynamic storage circuit, and the first sensing circuit is cleared. Based on the second potential of the sensing node, store the second verification information or the initial verification information into the first sensing circuit; Wherein, the first potential of the sensing node corresponding to the first verification information is greater than the second potential of the sensing node corresponding to the second verification information.

2. The operating method according to claim 1, characterized in that, The page buffer further includes a second sensing circuit coupled to the sensing node; the operation method further includes: Based on the third potential of the sensing node, the third verification information is stored in the second sensing circuit; Wherein, the second potential of the sensing node corresponding to the second verification information is greater than the third potential of the sensing node corresponding to the third verification information.

3. The operating method according to claim 1, characterized in that, The dynamic storage circuit corresponding to the first storage unit in the unverified programming state or the second storage unit in the verified programming state that failed verification is in the initial state among the multiple programming states is in the initial state.

4. The operating method according to claim 3, characterized in that, The step of transmitting the initial verification information in the dynamic storage circuit to the sensing node includes: The sensing node corresponding to the third storage unit that has been successfully verified in the verified programming state among the plurality of programming states is charged according to the initial verification information, so as to transmit the initial verification information to the sensing node.

5. The operating method according to claim 1, characterized in that, The step of transmitting the first verification information from the first sensing circuit to the dynamic storage circuit includes: The transmission channel between the first sensing circuit and the dynamic storage circuit is opened, so that the first verification information in the first sensing circuit is transmitted to the dynamic storage circuit.

6. The operating method according to claim 1, characterized in that, The clearing operation on the first sensing circuit includes: The first sensing circuit is reset to its initial state.

7. The operating method according to claim 2, characterized in that, The page buffer also includes at least one data latch circuit; Before storing the first verification information into the first sensing circuit based on the first potential of the sensing node, the operation method further includes: The selection operation information is obtained based on the data information in the at least one data latch circuit and the initial verification information in the dynamic storage circuit; the selection operation information is used to select the first storage unit in the pending programming state or the second storage unit in the verified programming state that has failed verification. The selected operation information is stored in the second sensing circuit; According to the selected operation information, the sensing nodes corresponding to the first storage unit and the second storage unit are precharged to a preset initial voltage.

8. The operating method according to claim 7, characterized in that, The operation method further includes: The sensing node is discharged from the preset initial voltage. After a first preset time, the discharge to the sensing node is paused. The first potential of the sensing node is sensed, and the first verification information is stored in the first sensing circuit. The sensing node is discharged from the first potential. After a second preset time, the discharge to the sensing node is paused. After the first sensing circuit is cleared, the second potential of the sensing node is sensed, and the second verification information is stored in the first sensing circuit. The sensing node is discharged from the second potential. After a third preset time, the discharge to the sensing node is paused. The third potential of the sensing node is sensed, and the third verification information is stored in the second sensing circuit.

9. The operating method according to claim 8, characterized in that, The operation method further includes: If the first potential is greater than or equal to the first preset voltage, the first verification information is used to indicate the first group of storage cells in the first storage cell and the second storage cell that have passed the verification of the first verification voltage. If the second potential is greater than or equal to the second preset voltage, the second verification information is used to indicate the second group of storage cells in the first storage cell and the second storage cell that have passed the verification of the second verification voltage; If the third potential is greater than or equal to the third preset voltage, the third verification information is used to indicate the third group of storage cells in the first storage cell and the second storage cell that have passed the verification of the third verification voltage. Wherein, the first verification voltage is less than the second verification voltage; the second verification voltage is less than the third verification voltage.

10. The operating method according to claim 9, characterized in that, The operation method further includes: Different bit line voltages are applied to the bit lines coupled to the first memory cell based on the first verification information, the second verification information, and the third verification information. Specifically, a first bit line voltage is applied to the first bit line connected to the first forced unit; a second bit line voltage is applied to the second bit line connected to the second forced unit; and a programmable disable bit line voltage is applied to the third bit line connected to the third group of memory cells. The first forced unit is a memory cell in the first group of memory cells other than the second group of memory cells and the third group of memory cells. The second forced unit is a memory cell in the second group of memory cells other than the third group of memory cells.

11. The operating method according to claim 10, characterized in that, The operation method further includes: After applying different bit line voltages to the bit line coupled to the first memory cell, it is determined whether the programming state to be verified is the last programming state among the plurality of programming states; If it is determined that the programming state to be verified is not the last programming state, an exchange operation is performed on the first sensing circuit and the dynamic storage circuit, so that the second verification information is stored in the dynamic storage circuit and the first verification information is stored in the first sensing circuit.

12. The operating method according to claim 2, characterized in that, The programming of the memory includes at least one programming cycle; The programming loop includes: programming operations and verification operations; the operation method further includes: Before the verification operation, the first sensing circuit and the dynamic storage circuit are cleared.

13. A method for operating a memory, characterized in that, The memory includes a page buffer, which includes a first sensing circuit coupled to a sensing node and a dynamic storage circuit coupled to the first sensing circuit. The memory includes storage units configured to store one of a plurality of programming states; the operation method includes: During the first sensing phase of the verification operation in the memory, first verification information is latched into the first sensing circuit. The initial verification information in the dynamic storage circuit is transmitted to the sensing node; the initial verification information includes verification information corresponding to the verified programming state among the multiple programming states contained in the memory; The transmission channel between the first sensing circuit and the dynamic storage circuit is opened, and the first verification information is transmitted to the dynamic storage circuit; and the first sensing circuit is cleared. In the second sensing phase of the verification operation, the second verification information is latched into the first sensing circuit; Wherein, the first potential of the sensing node corresponding to the first verification information is greater than the second potential of the sensing node corresponding to the second verification information.

14. The operating method according to claim 13, characterized in that, The page buffer further includes: a second sensing circuit coupled to the sensing node; the operation method further includes: In the third sensing phase of the verification operation, third verification information is latched into the second sensing circuit, wherein the second potential of the sensing node corresponding to the second verification information is greater than the third potential of the sensing node corresponding to the third verification information.

15. The operating method according to claim 14, characterized in that, The page buffer further includes at least one data latch circuit; prior to the first sensing phase of the verification operation of the memory, the operation method further includes: a pre-charge phase and a first discharge phase, wherein; During the pre-charging phase, the selected operation information is latched into the second sensing circuit; the sensing node is pre-charged to a preset initial voltage based on the selected operation information. In the first discharge phase, the sensing node is discharged from the preset initial voltage, and after a first preset time, the discharge to the sensing node is paused. The selected operation information is obtained based on the data information in the at least one data latch circuit and the initial verification information in the dynamic storage circuit, and is used to select the first storage unit in the pending programming state or the second storage unit in the verified programming state that has failed verification.

16. The operating method according to claim 15, characterized in that, The latching of the first verification information to the first sensing circuit includes: After the sensing node stops discharging, the first sensing circuit responds to the first latch signal and latches the first verification information into the first sensing circuit.

17. The operating method according to claim 16, characterized in that, Before the second sensing phase of the verification operation of the memory, the operation method further includes: a second discharge phase; wherein, in the second discharge phase, the sensing node is discharged from the first potential, and after a second preset time, the discharge of the sensing node is paused. After the second sensing phase of the verification operation of the memory, the operation method further includes a third discharge phase; wherein, in the third discharge phase, the sensing node is discharged from the second potential, and after a third preset time, the discharge of the sensing node is paused.

18. The operating method according to claim 17, characterized in that, The operation method further includes: After the second discharge phase, the first sensing circuit is made to respond to the second latch signal and latch the second verification information to the first sensing circuit. After the third discharge phase, the second sensing circuit is caused to latch the third verification information to the second sensing circuit in response to the third latch signal.

19. The operating method according to claim 15, characterized in that, After the third sensing phase of the verification operation, the operation method further includes: Different bit line voltages are applied to the bit lines coupled to the first memory cell in the programming state to be verified in the plurality of programming states, based on the first verification information, the second verification information, and the third verification information. Specifically, a first bit line voltage is applied to the first bit line connected to the first forced unit; a second bit line voltage is applied to the second bit line connected to the second forced unit; and a programmable disable bit line voltage is applied to the third bit line connected to the third group of memory cells. The first forced unit is a memory cell in the first group of memory cells other than the second group of memory cells and the third group of memory cells. The second forced unit is a memory cell in the second group of memory cells other than the third group of memory cells.

20. The operating method according to claim 19, characterized in that, The first group of storage cells includes the storage cells that have passed the verification of the first verification voltage. The second group of storage cells includes the storage cells in the first storage cell that have passed the verification of the second verification voltage; The third group of storage units includes the storage units in the first storage unit that have passed the verification of the third verification voltage; Wherein, if the first potential is greater than or equal to the first preset voltage, the first verification information is used to indicate the first group of storage cells in the first storage cell and the second storage cell that have passed the verification of the first verification voltage. If the second potential is greater than or equal to the second preset voltage, the second verification information is used to indicate the second group of storage cells in the first storage cell and the second storage cell that have passed the verification of the second verification voltage; If the third potential is greater than or equal to the third preset voltage, the third verification information is used to indicate the third group of storage cells in the first storage cell and the second storage cell that have passed the verification of the third verification voltage. The first verification voltage is less than the second verification voltage; the second verification voltage is less than the third verification voltage.

21. The operating method according to claim 19, characterized in that, After the third sensing phase of the verification operation, the operation method further includes: After applying different bit line voltages to the bit line coupled to the first memory cell, it is determined whether the programming state to be verified is the last programming state among the plurality of programming states; If it is determined that the programming state to be verified is not the last programming state, an exchange operation is performed on the first sensing circuit and the dynamic storage circuit, so that the second verification information is stored in the dynamic storage circuit and the first verification information is stored in the first sensing circuit.

22. The operating method according to claim 14, characterized in that, The programming of the memory includes at least one programming cycle; The programming loop includes a programming operation and a verification operation; before the verification operation, the operation method further includes a clearing operation on the first sensing circuit and the dynamic storage circuit.

23. The operating method according to claim 15, characterized in that, The page cache further includes a first transistor and a second transistor connected in series; wherein one end of the first transistor is connected to the positive terminal of the power supply; one end of the second transistor is connected to the sensing node; the step of transmitting the initial verification information in the dynamic storage circuit to the sensing node includes: The second transistor is controlled by the first transmission signal; and the first transistor is controlled by the initial verification information; Under the action of the first transmission signal and the initial verification information, the first transistor and the second transistor are turned on to charge the sensing node corresponding to the third memory cell that has been successfully verified in the multiple programming states, so as to transmit the initial verification information to the sensing node.

24. A memory, characterized in that, include: Storage array; The storage array contains storage units configured to store one of a plurality of programmed states; Multiple page buffers coupled to the storage array; Each page buffer includes: a first sensing circuit coupled to a sensing node and a dynamic storage circuit coupled to the first sensing circuit; and control logic circuitry coupled to the memory array and the plurality of page buffers; wherein, The control logic circuit is configured to: store first verification information in the first sensing circuit according to the first potential of the sensing node; transmit initial verification information in the dynamic storage circuit to the sensing node; the initial verification information includes verification information corresponding to the verified programming state among the plurality of programming states; transmit the first verification information from the first sensing circuit to the dynamic storage circuit and perform a clear operation on the first sensing circuit; and store second verification information or the initial verification information in the first sensing circuit according to the second potential of the sensing node; wherein the first potential of the sensing node corresponding to the first verification information is greater than the second potential of the sensing node corresponding to the second verification information.

25. The memory according to claim 24, characterized in that, The page buffer further includes: a second sensing circuit coupled to the sensing node; The control logic circuit is further configured to: store third verification information into the second sensing circuit based on the third potential of the sensing node; wherein the second potential of the sensing node corresponding to the second verification information is greater than the third potential of the sensing node corresponding to the third verification information.

26. The memory according to claim 25, characterized in that, The page buffer further includes at least one data latch circuit; the control logic circuit is further configured to: obtain selection operation information based on data information in the at least one data latch circuit and initial verification information in the dynamic storage circuit; the selection operation information is used to select a first storage unit in the pending programming state or a second storage unit in the verified programming state that has failed verification; store the selection operation information in the second sensing circuit; and precharge the sensing nodes corresponding to the first storage unit and the second storage unit to a preset initial voltage based on the selection operation information.

27. The memory according to claim 26, characterized in that, The page cache also includes a first transistor and a second transistor connected in series; Wherein, the other end of the first transistor is connected to the positive terminal of the power supply; the other end of the second transistor is connected to the sensing node; the first transistor is controlled by the initial verification information; the second transistor is controlled by the first transmission signal; under the action of the first transmission signal and the initial verification information, the first transistor and the second transistor are turned on to charge the sensing node corresponding to the third memory cell that has been successfully verified in the multiple programming states, so as to transmit the initial verification information to the sensing node.

28. The memory according to claim 27, characterized in that, The page buffer further includes a transmission switch; the transmission switch is configured to transmit the first verification information from the first sensing circuit to the dynamic storage circuit in response to a second transmission signal sent by the control logic circuit.

29. The memory according to claim 28, characterized in that, The page buffer further includes a pre-charge circuit; the control logic circuit is further configured to: obtain selected operation information based on data information in the at least one data latch circuit and initial verification information stored in the dynamic storage circuit; and latch the selected operation information to the second sensing circuit; Generate a precharge signal; The pre-charging circuit is configured to: in response to the pre-charging signal, pre-charge the sensing nodes corresponding to the first storage unit and the second storage unit to the preset initial voltage based on the selected operation information.

30. The memory according to claim 29, characterized in that, The page buffer also includes: a discharge circuit; The control logic circuit is further configured to generate a first discharge signal, a second discharge signal, and a third discharge signal. The discharge circuit is configured to: in response to the first discharge signal, cause the sensing node to start discharging from the preset initial voltage, and after a first preset time, pause the discharge to the sensing node; In response to the second discharge signal, the sensing node is caused to discharge from the first potential, and after a second preset time, the discharge to the sensing node is paused. In response to the third discharge signal, the sensing node is made to discharge from the second potential, and after a third preset time, the discharge to the sensing node is paused.

31. The memory according to claim 25, characterized in that, The first sensing circuit includes a first latch for storing first verification information; the second sensing circuit includes a second latch for storing third verification information; and the dynamic storage circuit includes a dynamic latch for storing second verification information.

32. The memory according to claim 26, characterized in that, The control logic circuit is further configured to: after applying different bit line voltages to the bit line coupled to the first memory cell based on the first verification information, the second verification information, and the third verification information, determine whether the programming state to be verified is the last programming state among the plurality of programming states; if it is determined that the programming state to be verified is not the last programming state, control the first sensing circuit and the dynamic storage circuit to perform an exchange operation, so that the second verification information is stored in the dynamic storage circuit and the first verification information is stored in the first sensing circuit.

33. The memory according to claim 25, characterized in that, After the first verification information is transmitted from the first sensing circuit to the dynamic storage circuit, the first sensing circuit is further configured to: in response to a clear signal sent by the control logic circuit, reset the first sensing circuit to restore the first sensing circuit to its initial state.

34. A memory system, characterized in that, include: One or more of the memory according to any one of claims 24 to 33 and a memory controller coupled to the memory and used for controlling the memory.

35. An electronic system, characterized in that, include: The memory system of claim 34 and the host computer coupled to the memory system.

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