Memory, operation method and system of memory and storage medium

Abstract

The invention provides a memory, an operation method and system of the memory and a storage medium, and relates to the technical field of storage. The memory comprises a peripheral circuit and a memory cell array, the peripheral circuit comprises a plurality of page buffers and a logic control circuit; the page buffer comprises a first bit line connection point, a second bit line connection point, a first switching device and a second switching device; the first bit line connection point and the second bit line connection point are used for connecting bit lines in the memory cell array; the first bit line connection point and the second bit line connection point are respectively connected to a power supply end through independent pre-charging circuits, and the first bit line connection point and the second bit line connection point are respectively connected to a latch in the page buffer; the pre-charging circuit is a circuit for pre-charging a bit line by the page buffer; the first switching device is connected with the first bit line connection point and the second bit line connection point; and the second switching device is located on the pre-charging circuit corresponding to the second bit line connection point.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a memory, a method for operating a memory, a system and a storage medium. Background Art

[0002] In memory products such as NAND flash, page buffer is an important circuit for realizing data sensing and storage.

[0003] In the related art, a page buffer is connected to a bit line in a memory cell array of a memory, senses storage data by sensing / amplifying a signal from the bit line, and writes data by controlling a voltage of the bit line. Summary of the invention

[0004] The present application provides a memory, a memory operation method, a system and a storage medium, which can reduce the overall size of a page buffer in the memory while keeping the number of bit lines in the memory unchanged, and increase the number of bit lines in the memory while keeping the die size of the memory unchanged. The technical solution is as follows:

[0005] In one aspect, a memory is provided, the memory comprising a peripheral circuit and a memory cell array; the peripheral circuit comprises a plurality of page buffers, and a logic control circuit coupled to the plurality of page buffers and configured to control the plurality of page buffers; the page buffer comprises a first bit line connection point, a second bit line connection point, a first switch device, and a second switch device;

[0006] The first bit line connection point and the second bit line connection point are used to connect the bit lines in the memory cell array; the first bit line connection point and the second bit line connection point are respectively connected to the power supply terminal through independent precharging circuits, and the first bit line connection point and the second bit line connection point are respectively connected to the latch in the page buffer; the precharging circuit is a circuit for the page buffer to precharge the bit lines; the first switching device connects the first bit line connection point and the second bit line connection point; the second switching device is located on the precharging circuit corresponding to the second bit line connection point.

[0007] In an optional embodiment, the control logic circuit is configured to disconnect the first switching device and connect the second switching device when a programming operation is performed through the page buffer; the control logic circuit is configured to connect the first switching device and disconnect the second switching device when a read operation is performed through the page buffer.

[0008] In an optional embodiment, a third switch device is provided between the first bit line connection point and the sensing latch in the page buffer, and the third switch device is located outside the precharge circuit corresponding to the first bit line connection point.

[0009] In an optional embodiment, the control logic circuit is configured to turn off the third switch device when a programming operation is performed through the page buffer; the control logic circuit is configured to turn on the third switch device when a read operation is performed through the page buffer.

[0010] In an optional embodiment, the first bit line connection point is connected to N bit lines among the 2×N bit lines included in the memory cell array, and the second bit line connection point is connected to another N bit lines among the 2×N bit lines, where N is an integer greater than or equal to 2; the 2×N bit lines are adjacent to each other in sequence, and the bit lines respectively connected to the first bit line connection point and the second bit line connection point are arranged alternately in sequence.

[0011] In an optional embodiment, the control logic circuit is configured to apply a bias voltage to the second bit line during a programming operation on a memory cell coupled to the first bit line through the page buffer; wherein the first bit line and the second bit line are two adjacent bit lines among the 2×N bit lines.

[0012] In an optional embodiment, the control logic circuit is configured to apply programming pulse voltages to the 2×N bit lines in sequence through the first bit line connection point and the second bit line connection point in the order of arrangement of the 2×N bit lines when performing a programming operation on the memory cells coupled to the 2×N bit lines through the page buffer; wherein, among the 2×N bit lines, there is an overlapping part in the time interval for applying the programming pulse voltage to two adjacent bit lines, so as to achieve the application of bias voltages to adjacent bit lines of the bit lines during the programming operation on the memory cells coupled to one bit line.

[0013] In an optional embodiment, for the 4×N bit lines in the memory cell array that are adjacent to the two page buffer vectors, the order in which the programming pulse voltages are applied sequentially to the first 2×N bit lines of the 4×N bit lines is opposite to the order in which the programming pulse voltages are applied sequentially to the last 2×N bit lines of the 4×N bit lines.

[0014] On the other hand, a method for operating a memory is provided, the method being executed by a control logic circuit in a peripheral logic circuit of the memory, the memory being a memory as shown in any of the above embodiments, the method comprising: when performing a programming operation through the page buffer, turning off the first switching device and turning on the second switching device; when performing a read operation through the page buffer, turning on the first switching device and turning off the second switching device.

[0015] In an optional embodiment, a third switch device is provided between the first bit line connection point and the sensing latch in the page buffer, and the third switch device is located outside the precharge circuit corresponding to the first bit line connection point.

[0016] In an optional embodiment, the method further includes: turning off the third switch device when performing a programming operation through the page buffer; and turning on the third switch device when performing a read operation through the page buffer.

[0017] In an optional embodiment, the first bit line connection point is connected to N bit lines among the 2×N bit lines included in the memory cell array, and the second bit line connection point is connected to another N bit lines among the 2×N bit lines, where N is an integer greater than or equal to 2; the 2×N bit lines are adjacent to each other in sequence, and the bit lines respectively connected to the first bit line connection point and the second bit line connection point are arranged alternately in sequence.

[0018] In an optional embodiment, the method further includes: applying a bias voltage to a second bit line during a programming operation on a memory cell coupled to the first bit line through the page buffer; wherein the first bit line and the second bit line are two adjacent bit lines among the 2×N bit lines.

[0019] In an optional embodiment, the process of applying a bias voltage to the second bit line during the programming operation on the memory cell coupled to the first bit line through the page buffer includes: when the programming operation is performed on the memory cells coupled to the 2×N bit lines through the page buffer, the programming pulse voltage is applied to the 2×N bit lines in sequence through the first bit line connection point and the second bit line connection point in the order of arrangement of the 2×N bit lines; wherein, among the 2×N bit lines, there is an overlapping part in the time interval for applying the programming pulse voltage to two adjacent bit lines, so as to achieve the application of bias voltage to adjacent bit lines of the bit line during the programming operation on the memory cell coupled to one bit line.

[0020] In an optional embodiment, for the 4×N bit lines in the memory cell array that are adjacent to the two page buffer vectors, the order in which the programming pulse voltages are applied sequentially to the first 2×N bit lines of the 4×N bit lines is opposite to the order in which the programming pulse voltages are applied sequentially to the last 2×N bit lines of the 4×N bit lines.

[0021] On the other hand, a storage system is provided, comprising: one or more memories as described in any one of the above embodiments, and a controller coupled to the memories and configured to control the memories.

[0022] On the other hand, a computer system is provided, comprising: a host; one or more memories as described in any one of the above embodiments; and a controller coupled to the memories and configured to control the memories.

[0023] On the other hand, a computer-readable storage medium is provided, in which instructions are stored. When the instructions are executed on a control logic unit, the memory operation method described in any of the above embodiments is implemented.

[0024] The technical solution provided by this application may have the following beneficial effects:

[0025] For multiple page buffers in the peripheral circuit of the memory, each page buffer includes two bit line connection points each having an independent pre-charging circuit, and the two bit line connection points are respectively connected to the bit line in the memory cell array and the latch in the page buffer, and at the same time, the two bit line connection points are also connected through a first switching device, and a second switching device is also provided on the pre-charging circuit of one of the bit line connection points; in the above scheme, when the two bit line connection points in the page buffer respectively implement pre-charging of the bit line during the programming process, part of the circuit structure in the page buffer can be shared, specifically for example, in the pre-charging stage of the programming process, the first switching device is disconnected, and the second switching device is connected, so that the two bit line connection points are respectively connected. The bit lines are precharged through their respective precharging circuits, and during the reading process, the second switching device is disconnected, and the first switching device is connected to realize the reading of the storage unit coupled to any one of the two bit lines, so that the two bit line connection points share the circuit structure of the sensing part; through the above scheme, two or more bit line connection points can be integrated into a page buffer, and part of the circuit structure in the page buffer is shared, and there is no need to set a page buffer for each bit line connection point, so that the overall size of the page buffer in the memory can be reduced while the number of bit lines in the memory remains unchanged, and the number of bit lines in the memory can be increased while the mold size of the memory remains unchanged, thereby improving the storage capacity and performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 is a schematic diagram of a computer system provided by an embodiment of the present application;

[0028] Figure 2 It is a structural schematic diagram of a memory card involved in the present application;

[0029] Figure 3 is a structural schematic diagram of a solid-state drive involved in the present application;

[0030] Figure 4 is a block diagram of a memory shown in an exemplary embodiment of the present application;

[0031] Figure 5 is a schematic circuit diagram of a memory shown in an exemplary embodiment of the present application;

[0032] Figure 6 is a perspective view of a portion of a three-dimensional storage array structure shown in an exemplary embodiment of the present application;

[0033] Figure 7 It is a schematic diagram of the connection between a NAND flash memory cell array and a page buffer;

[0034] Figure 8 It is a connection diagram of another NAND flash memory cell array and page buffer;

[0035] Fig. 9 is a framework diagram of a memory provided by an exemplary embodiment of the present application;

[0036] Fig.10 is a schematic diagram of the structure of a page buffer involved in an embodiment of the present application;

[0037] Fig.11 is a schematic diagram of the structure of another page buffer involved in an embodiment of the present application;

[0038] Fig.12 is a schematic diagram of the structure of another page buffer involved in an embodiment of the present application;

[0039] Fig.13 is a structural diagram of another page buffer involved in an embodiment of the present application;

[0040] Fig.14 is a structural diagram of another page buffer involved in an embodiment of the present application;

[0041] Fig.15 is a structural diagram of another page buffer involved in an embodiment of the present application;

[0042] Fig.16 is a circuit structure diagram of a page buffer involved in an exemplary embodiment of the present application;

[0043] Fig.17 is a schematic diagram of a connection between a page buffer and a bit line involved in an embodiment of the present application;

[0044] Fig.18 is an execution timing diagram of a programming operation involved in an embodiment of the present application;

[0045] Fig.19 is a schematic diagram of a connection between a page buffer and a bit line involved in an embodiment of the present application;

[0046] Fig. 20 is an execution timing diagram of another programming operation involved in an embodiment of the present application;

[0047] Fig.21 is a flow chart of a method for operating a memory provided by an exemplary embodiment of the present application;

[0048] Fig. 22 It is a structural block diagram of a storage system provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0049] The implementation methods of the present application are further described in detail below in conjunction with the accompanying drawings.

[0050] The computer system provided in the embodiment of the present application may include a host and a storage system. The storage system may include a 3D memory, for example, a 3D NAND flash memory.

[0051] Figure 1 Schematic diagram of a computer system provided by an embodiment of the present application. Figure 1 As shown, the computer system 10 includes: one or more memories 100, and a controller 200 coupled to the memories 100 and configured to control the memories 100. The controller 200 may also be referred to as a memory controller.

[0052] The controller 200 may be configured to control operations performed by the memory 100. Such as read, erase and program operations. The controller 200 may also be configured to manage various functions regarding data stored or to be stored in the memory 100, including but not limited to bad block management, garbage collection, conversion of logical addresses to physical addresses, wear leveling, etc. Optionally, the controller 200 may also be configured to process error correction codes (ECC) regarding data read from or written to the memory 100. The controller 200 may also perform any other suitable functions. For example, formatting the memory 100.

[0053] The controller 200 can also communicate with the external device according to a specific communication protocol. For example, the controller 200 can communicate with the external device through at least one of various interface protocols. The interface protocol can be a universal serial bus USB protocol, a multimedia card (Multi-Media Card, MMC) protocol, a peripheral component interconnect (Peripheral Component Interconnect, PCI) protocol, a PCI high-speed (PCI-E) protocol, an advanced technology attachment (Advanced Technology Attachment, ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer interface (Small Computer System Interface, SCSI) protocol, an enhanced small disk interface (Enhanced Small Drive Interface, ESDI) protocol, an integrated drive electronics (Integrated Development Environment, IDE) protocol, a Firewire (Fire wire) protocol, etc.

[0054] In an optional embodiment, the controller 200 and one or more memories 100 may be integrated into various types of electronic devices. The electronic device may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. In this scenario, Figure 1 As shown, the computer system 10 further includes a host 300. The controller 200 is coupled to the host 300. The controller 200 can manage data stored in the memory 100 and communicate with the host 300 to implement the functions of the aforementioned electronic device.

[0055] In other embodiments, the controller 200 and one or more memories 100 may be integrated into various types of storage devices.

[0056] As an example, Figure 2 Schematic diagram of the structure of a memory card involved in this application. Figure 2 As shown, the controller 200 and the single memory 100 may be integrated into the memory card 40. The memory card 40 may include a Personal Computer Memory Card International Association (PCMCIA, PC) card, a Compact Flash (CF) card, a Smart Media (SM) card, a memory stick, a Multi-Media Card (MMC), a RS-MMC, a micro-MMC, a Secure Digital (SD) card, a Universal Flash Storage (UFS), etc. Figure 2 As shown, the memory card 40 may further include a connector 410 for coupling the memory card 40 with a host.

[0057] As another example, Figure 3 Schematic diagram of a solid state drive involved in this application. Figure 3 As shown, the controller 200 and the plurality of memories 100 may be integrated into a solid state drive (SSD) 50. The solid state drive 50 may further include a connector 510 for coupling the solid state drive 50 with a host. The storage capacity and / or operating speed of the solid state drive 50 is greater than the storage capacity and / or operating speed of the memory card 40.

[0058] also, Figures 1 to 3 The memory 100 in the embodiment may be any memory involved in the embodiment of the present application. For example, it may be a 3D NAND (NAND gate) memory. The structure of the memory 100 is explained below.

[0059] Figure 4 is a block diagram of a memory according to an exemplary embodiment of the present application. Figure 4 , the memory 400 may include a memory cell array 401, a page buffer 404, a column decoder 406, a row decoder 408, a voltage generator 410, a control logic unit 412, a register 414, and a data input / output circuit 416. It should be understood that in some examples, the memory 400 may also include Figure 4 Additional peripheral circuits not shown.

[0060] The page buffer 404 may be configured to read data from the memory cell array 401 and program (write) data to the memory cell array 401 according to a control signal from the control logic unit 412. In one example, the page buffer 404 may store data (write data) to be programmed into a selected page of the memory cell array 401. In another example, the page buffer 404 may output the read data in a program verification operation to ensure that the data has been correctly programmed into the corresponding memory cell of the selected word line coupled to the memory cell array 401. The column decoder 406 may operate in response to a control signal provided by the control logic unit to select one or more NAND memory strings in the memory cell array 401. The row decoder may operate in response to a control signal provided by the control logic unit and select / deselect a selected row of the memory cell array 401. The row decoder may also be configured to supply a voltage generated from the voltage generator 410 to a selected word line and an unselected word line of the memory cell array 401. As described in detail below, the row decoder / word line driver 408 is configured to perform an erase operation on a memory cell coupled to one or more selected word lines in the memory cell array 401. The voltage generator 410 may use an external power supply voltage or an internal power supply voltage to generate various voltages required by the memory, such as a program voltage, a read voltage, a pass voltage, a verification voltage, a bit line voltage, etc., and combinations thereof.

[0061] The control logic unit 412 may be coupled to the voltage generator 410, the page buffer 404, the column decoder 406, the row decoder 408, and the data input / output circuit 416, etc., and is configured to control the operation of each peripheral circuit. The control logic unit may generate an operation signal in response to a command or control signal from the storage controller. The register 414 may be coupled to the control logic unit 412, and includes a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The data input / output circuit 416 may be coupled to the control logic unit 412, and act as a control buffer to buffer a control command received from a host (not shown) and relay it to the control logic unit 412, and to buffer status information received from the control logic unit 412 and relay it to the host. The data input / output circuit 416 may also be coupled to the column decoder, and act as a data input / output interface and a data buffer to buffer data and relay it to the memory cell array 401 or relay or buffer data from the memory cell array 401.

[0062] Figure 5 FIG. 1 is a schematic circuit diagram of a memory device according to an exemplary embodiment of the present application. Figure 5As shown, the memory 500 may include a memory cell array device 501 and a peripheral circuit 502 coupled to the memory cell array device 501. The memory cell array device 501 may be a NAND flash memory cell array, wherein the memory cell 506 is provided in the form of an array of NAND memory strings 508, each NAND memory string 508 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 508 includes a plurality of memory cells 506 coupled in series and stacked vertically. Each memory cell 506 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor. In some embodiments, each memory cell 506 is a single-level cell (SLC) having two possible memory states that can store one bit of data. For example, the first memory state "0" may correspond to a first voltage range, and the second memory state "1" may correspond to a second voltage range. In some embodiments, each memory cell 506 is a multi-level cell capable of storing more than a single bit of data in more than two memory states. For example, two bits can be stored per cell (i.e., Multi-Level Cell (MLC)), three bits can be stored per cell (i.e., Triple-Level Cell (TLC)), or four bits can be stored per cell (i.e., Quad-Level Cell (QLC)).

[0063] like Figure 5 As shown in , each NAND memory string 508 may include at least one source selection transistor 510 at its source terminal and at least one drain selection transistor 512 at its drain terminal. The source selection transistor 510 and the drain selection transistor 512 may be configured to activate the selected NAND memory string 508 during read and program operations. In some embodiments, the sources of the NAND memory strings 508 in the same block 504 are coupled through the same source line (Source Line, SL). According to some embodiments, the drain selection transistor 512 of each NAND memory string 508 is coupled to a corresponding bit line 516. In some embodiments, each NAND memory string 508 is configured to be selected or deselected by applying a selection voltage or a deselection voltage (e.g., 0V) to the corresponding drain selection transistor 512 via one or more drain selection lines 515 and / or by applying a selection voltage or a deselection voltage (e.g., 0V) to the corresponding source selection transistor 510 via one or more source selection lines 515.

[0064] like Figure 5As shown in , the memory cell array may include a plurality of blocks. In some embodiments, each block 504 is a basic data unit for an erase operation, that is, all memory cells 506 on the same block 504 are erased at the same time.

[0065] Figure 6 6 is a perspective view of a portion of a three-dimensional memory array structure shown in an exemplary embodiment of the present application. The memory cell array structure 600 includes a substrate 630 and a stacked structure above the substrate 630. The stacked structure includes alternately stacked gate conductive layers and interlayer dielectric layers. The substrate 630 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material. The gate conductive layer may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer includes a doped polysilicon layer. The gate conductive layer may include a plurality of word lines 633, at least one source select line 632, and at least one drain select line 634.

[0066] like Figure 6 As shown, the memory cell array 600 includes a plurality of channel structures 612 extending vertically through a memory stack structure 635. In some embodiments, the channel structure 612 includes a memory film 637 and a channel 638. Figure 6 As shown, according to some embodiments, a well 644 (eg, a P-well and / or an N-well) is formed in the substrate 630, and the source terminal of the memory cell array is in contact with the well 644. It should be understood that although Figure 6 Not shown, but additional features of the memory cell array 600 may be formed, including but not limited to gate line slits / source contacts, local contacts, interconnect layers, etc.

[0067] For technical details not disclosed in the above memory-related hardware embodiments, please refer to the description of the computer system embodiments and method embodiments of the present application for understanding.

[0068] Please refer to Figure 7 , which shows a schematic diagram of the connection between a NAND flash memory cell array and a page buffer. Figure 7 As shown, the memory cell array 71 includes several bit lines, namely BL 0 to BL K. Correspondingly, the page buffer 72 includes K+1 page buffers, namely page buffer 720 to page buffer 72K, wherein each bit line is connected to an independent page buffer.

[0069] Please refer to Figure 8, which shows a connection diagram of another NAND flash memory cell array and page buffer. Figure 8 As shown, the memory cell array 81 includes a number of bit lines, namely BL 0 to BL K, and the page buffer 82 includes k+1 page buffers, namely page buffer 820 to page buffer 82k, where the value of k is smaller than the value of K; Figure 8 In the structure shown, the bit lines BL[0-K] are connected to the page buffer through the switch device 83. Figure 7 Compared with the architecture shown in FIG. 1 , the number of page buffers can be reduced. For example, two or more bit lines can be connected to the same page buffer, which reduces the number of page buffers used. Figure 8 The NAND shown may also be referred to as X-NAND.

[0070] exist Figure 7 or Figure 8 In the NAND flash memory shown, each page buffer has only one bit line connection point. Conversely, for multiple bit line connection points, a page buffer needs to be set up respectively. However, due to the large circuit size of the page buffer, it usually occupies about 20% to 40% of the die size. Therefore, the number of page buffers in the NAND flash memory is usually limited, which affects the capacity and performance of the NAND flash. For example, when the number of page buffers is limited, the number of bit lines connected to the page buffers will be limited, which in turn limits the storage capacity of the NAND flash memory; in addition, when the number of page buffers is limited, the concurrency of the programming process will be limited, thereby limiting the write speed of the NAND flash.

[0071] In this regard, the solution shown in the subsequent embodiments of the present application provides a new circuit structure of a page buffer and an operating method based on the circuit structure, which can reduce the overall size of the page buffer in the memory while keeping the number of bit lines in the memory unchanged, and increase the number of bit lines in the memory while keeping the mold size of the memory unchanged.

[0072] Please refer to Fig. 9 , which is a framework diagram of a memory provided by an exemplary embodiment of the present application. The memory may be as follows Figure 1 The memory 100 in the system 10 shown, or, alternatively, may be Figure 4 or Figure 5 The memory 400 or the memory 500 shown. Fig. 9 As shown, the memory includes a peripheral circuit 910 and a memory cell array 920 .

[0073] like Fig. 9As shown, the peripheral circuit 910 includes a plurality of page buffers 912 , and a logic control circuit 914 coupled to the plurality of page buffers 912 and configured to control the plurality of page buffers 912 .

[0074] like Fig. 9 As shown, the page buffer 912 includes a first bit line connection point 912a, a second bit line connection point 912b, a first switching device 912c, and a second switching device 912d.

[0075] The bit line connection point refers to the point where the page buffer 192 is connected to the bit line BL.

[0076] The first switch device 912c and the second switch device 912d may be metal oxide semiconductor field effect transistors (MOSFET), which may be referred to as MOS tubes for short.

[0077] like Fig. 9 As shown, the first bit line connection point 912a and the second bit line connection point 912b are used to connect the bit lines in the memory cell array 920; the first bit line connection point 912a and the second bit line connection point 912b are respectively connected to the power supply terminal 912f through independent pre-charging circuits 912e, and the first bit line connection point 912a and the second bit line connection point 912b are respectively connected to the latch 912g in the page buffer 912; the pre-charging circuit 912e is a circuit for the page buffer 912 to pre-charge the bit lines.

[0078] like Fig. 9 As shown, the first switch device 912c is connected to the first bit line connection point 912a and the second bit line connection point 912b; the second switch device 912d is located on the precharge circuit 912e corresponding to the second bit line connection point 912b.

[0079] In summary, the scheme shown in the embodiment of the present application is that for multiple page buffers in the peripheral circuit of the memory, each page buffer includes two bit line connection points each having an independent pre-charging circuit, and the two bit line connection points are respectively connected to the bit line in the memory cell array and the latch in the page buffer, and at the same time, the two bit line connection points are also connected through a first switching device, and a second switching device is also provided on the pre-charging circuit of one of the bit line connection points; in the above scheme, when the two bit line connection points in the page buffer respectively implement pre-charging of the bit line during the programming process, part of the circuit structure in the page buffer can be shared. Specifically, for example, in the pre-charging stage of the programming process, the first switching device is disconnected, and the second switching device is connected, so that the two The bit line connection points precharge the bit lines through their respective precharging circuits, and during the reading process, the second switch device is disconnected, and the first switch device is connected to realize the reading of the storage unit coupled to any one of the two bit lines, so that the two bit line connection points share the circuit structure of the sensing part; through the above scheme, two or more bit line connection points can be integrated into a page buffer, and part of the circuit structure in the page buffer can be shared, and there is no need to set a page buffer for each bit line connection point, so that the overall size of the page buffer in the memory can be reduced while the number of bit lines in the memory remains unchanged, and the number of bit lines in the memory can be increased while the mold size of the memory remains unchanged, thereby improving the storage capacity and performance.

[0080] Among them, Fig. 9 In the circuit structure shown, a page buffer 912 includes two bit line connection points, optionally, one based on Fig. 9 In the circuit structure shown, a page buffer 912 may also include more than two bit line connection points. For example, a page buffer 912 may include a first bit line connection point 912a and two or more second bit line connection points 912b.

[0081] For example, based on Fig. 9 The circuit structure shown in FIG. 1 is a circuit structure in which a page buffer 912 includes a first bit line connection point 912a and two second bit line connection points 912b. Fig.10 , which shows a schematic diagram of the structure of a page buffer involved in an embodiment of the present application. Fig.10As shown, a page buffer 912 includes a first bit line connection point 912a, and two second bit line connection points 912b, and the two second bit line connection points 912b are respectively connected to the first bit line connection point 912a through a first switch device 912c (that is, there are two first switch devices 912c), the two second bit line connection points 912b and the first bit line connection point 912a respectively have independent pre-charging circuits (that is, there are three independent pre-charging circuits), and the pre-charging circuits 912e corresponding to the two second bit line connection points 912b respectively have second switch components 912d (that is, there are two second switch components 912d).

[0082] in, Fig.10 The following description only takes an example in which a page buffer includes a first bit line connection point 912a and two second bit line connection points 912b. Optionally, the page buffer may also include three or more second bit line connection points 912b.

[0083] In one possible implementation, based on Fig. 9 or Fig.10 In the circuit architecture shown, the control logic circuit 914 can ensure accurate execution of the programming operation and the reading operation by controlling the on and off states of the first switching device 912c and the second switching device 912d during the programming operation and the reading operation.

[0084] Specifically, the control logic circuit 914 is configured to turn off the first switch device 912c and turn on the second switch device 912d when performing a programming operation through the page buffer 912;

[0085] The control logic circuit 914 is configured to turn on the first switching device 912 c and turn off the second switching device 912 d when a read operation is performed through the page buffer 912 .

[0086] For example, in Fig. 9 In the circuit structure shown, when the first switch device 912c is disconnected and the second switch device 912d is connected, the independent pre-charging circuits of the first bit line connection point 912a and the second bit line connection point 912b can be in a conducting state. At the same time, the independent pre-charging circuits of the first bit line connection point 912a and the second bit line connection point 912b can not interfere with each other. At this time, programming operations are performed through the page buffer 912, and the bit lines in the memory cell array 920 can be pre-charged at the same time through the two bit line connection points, thereby realizing concurrent programming operations on the memory cells coupled to different bit lines in the memory cell array 920.

[0087] For example, in Fig. 9In the circuit structure shown, when the first switch device 912c is turned on and the second switch device 912d is turned off, the pre-charging circuit of the second bit line connection point 912b is turned off, while the pre-charging circuit of the first bit line connection point 912a can be in the on state. At the same time, since the first switch device 912c between the first bit line connection point 912a and the second bit line connection point 912b is turned on, the above two bit line connection points can share a pre-charging circuit (that is, the pre-charging circuit of the first bit line connection point 912a). At this time, if the circuits between the two bit line connection points and the bit lines in the memory cell array 920 are turned on in sequence, the different bit lines in the memory cell array 920 can be pre-charged in sequence through the pre-charging circuit of the first bit line connection point 912a, and then the memory cells coupled to the bit lines of the memory cell array 920 can be sensed / read in sequence through the two bit line connection points.

[0088] Among them, the above-mentioned precharging circuit through the first bit line connection point 912a precharges different bit lines in the memory cell array 920, and then can sense / read the memory cells coupled to the bit lines of the memory cell array 920 through two bit line connection points in sequence. This process can be achieved by connecting the connections between the two bit line connection points and the bit lines in sequence.

[0089] For example, based on Fig. 9 For the scheme shown, please refer to Fig.11 , which shows a schematic diagram of the structure of another page buffer involved in an embodiment of the present application. Fig.11As shown in FIG. 1 , the page buffer further includes a fourth switch device 912h and a fifth switch device 912i, wherein the fourth switch device 912h is located in the circuit between the first bit line connection point 912a and the first switch device 912c, and in the circuit between the first bit line connection point 912a and the power supply terminal 912f, and is located outside the circuit between the first switch device 912c and the power supply terminal 912f; correspondingly, the fifth switch device 912i is located in the circuit between the second bit line connection point 912b and the first switch device 912c, and in the circuit between the second bit line connection point 912b and the first switch device 912c. The first switching device 912a is connected to the circuit between the first connection point 912b and the power supply terminal 912f, and is located outside the circuit between the first switching device 912c and the power supply terminal 912f; during the read operation, the control logic circuit 914 first connects the first switching device 912c and disconnects the second switching device 912d; when reading through the first bit line connection point 912a, the fourth switching device 912h is connected and the fifth switching device 912i is disconnected. At this time, the first bit line connection point 912a can be connected to the pre-charge circuit corresponding to the first bit line connection point 912a. After the precharging is completed, the memory cell coupled to the bit line connected to the first bit line connection point 912a can be sensed / read through the sensing amplifier circuit in the page buffer and the sensing latch in the latch 912g; accordingly, when reading through the second bit line connection point 912b, the fourth switch device 912h is disconnected and the fifth switch device 912i is connected. At this time, the precharging circuit corresponding to the first bit line connection point 912a can sense / read the second bit line connection point 912b through the first switching device 912c and the second bit line connection point 912b. The bit line connected to the bit line connection point 912b is precharged, and after the precharging is completed, the storage unit coupled to the bit line connected to the second bit line connection point 912b can be sensed / read through the sensing amplifier circuit in the page buffer and the sensing latch in the latch 912g; that is, in the read operation, the first bit line connection point and the second bit line connection point can share a precharge circuit, and accordingly, also share the circuits corresponding to the sensing amplifier circuit and the sensing latch, so that the two bit line connection points can share a circuit for sensing / reading in the page buffer.

[0090] Among them, the above Fig.11 The structure of the page buffer shown is only described by taking an example in which a page buffer includes a first bit line connection point 912a and a second bit line connection point 912b. Optionally, the above-mentioned page buffer may also include two or more second bit line connection points 912b.

[0091] For example, a page buffer includes a first bit line connection point 912a and two second bit line connection points 912b. Fig.12 , which shows a schematic diagram of the structure of another page buffer involved in an embodiment of the present application. Fig.12 As shown, for two second bit line connection points 912b in the page buffer, each second bit line connection point 912b corresponds to a fifth switch device 912i, and each fifth switch device 912i is located in the circuit between the corresponding second bit line connection point 912b and the first switch device 912c, and in the circuit between the corresponding second bit line connection point 912b and the power supply terminal 912f, and is located outside the circuit between the first switch device 912c and the power supply terminal 912f; during the read operation, the control logic circuit 914 first connects all the first switch devices 912c and disconnects all the second switch devices 912d; when reading through the first bit line connection point 912a, the fourth switch device 912h is connected. connected, and all the fifth switch devices 912i are disconnected; when reading through a certain second bit line connection point 912b, the fourth switch device 912h is disconnected, the fifth switch device 912i corresponding to the current second bit line connection point 912b is connected, and the fifth switch device 912i corresponding to another second bit line connection point 912b is disconnected. At this time, the bit line connected to the current second bit line connection point 912b can be precharged through the precharge circuit corresponding to the first bit line connection point 912a. After the precharge is completed, the storage unit coupled to the bit line connected to the current second bit line connection point 912b can be sensed / read through the sensing amplifier circuit in the page buffer and the sensing latch in the latch 912g.

[0092] Similarly, in Fig.12 Based on the circuit structure shown, if the above-mentioned page buffer contains three or more second bit line connection points 912b, when reading is performed through one of the second bit line connection points 912b, the fifth switch device 912i corresponding to the current second bit line connection point 912b is connected, and the fourth switch device 912h and the fifth switch devices 912i corresponding to the other second bit line connection points 912b are disconnected.

[0093] In a possible implementation of the present application, a third switch device 912j is provided between the first bit line connection point and the sensing latch in the page buffer, and the third switch device is located outside the precharge circuit corresponding to the first bit line connection point.

[0094] In an embodiment of the present application, during a read operation, since two or more bit line connection points share the pre-charging circuit corresponding to the first bit line connection point for pre-charging, that is, a circuit between the first bit line connection point and the sensing latch is required in the page buffer, and during the programming process, the circuit between the first bit line connection point and the sensing latch needs to be disconnected. In this regard, in an embodiment of the present application, a third switching device 912j can be set between the first bit line connection point and the sensing latch in the page buffer.

[0095] It should be noted that the third switch device 912j is also located in the circuit of the sensing latch->first switch device 912c->second bit line connection point 912b.

[0096] Meanwhile, the third switch device 912j is also located between the first bit line connection point and other circuit elements for sensing / reading in the page buffer.

[0097] In a possible implementation of the present application, the control logic circuit 914 is configured to disconnect the third switch device 912j when a programming operation is performed through the page buffer 912; the control logic circuit 914 is configured to connect the third switch device 912j when a read operation is performed through the page buffer 912.

[0098] In an embodiment of the present application, during a programming operation, the control logic circuit 914 can control the third switch device 912j to be disconnected, thereby preventing the programming process from affecting the sensing latch and other circuit elements used for sensing / reading; correspondingly, during a read operation, the control logic circuit 914 can control the third switch device 912j to be turned on, so that the sensing latch and other circuit elements used for sensing / reading can correctly perform a read operation on the storage cell coupled to the currently connected bit line.

[0099] For example, in Fig.11 Based on Fig.13 , which shows a schematic diagram of the structure of another page buffer involved in the embodiment of the present application. Fig.13 As shown, the latch 912g of the page buffer 912 includes a sense latch 912k and other latches (for example, an LVT latch), and corresponding to the sense latch, it also includes a grounded capacitor element 912m; when the fourth switch device 912h is turned on, the sense latch 912k and the capacitor element 912m can be connected to the first bit line connection point 912a, and when the first switch device 912c is turned on, the sense latch 912k and the capacitor element 912m can also be connected to the corresponding second bit line connection point 912b; in order to avoid the read operation from affecting the sense latch 912k and the capacitor element 912m, Fig.13 In the embodiment, a third switch device 912j is provided between the sensing latch 912k / capacitor element 912m and the two bit line connection points. During the programming process, the third switch device 912j is disconnected to prevent the programming operation from affecting the sensing latch 912k and the capacitor element 912m; during the reading operation, the third switch device 912j is turned on, and at this time, the reading operation can be implemented through the sensing latch 912k and the capacitor element 912m.

[0100] In the above Fig.13 In the embodiment, the capacitor element 912m is a grounded capacitor. Optionally, the capacitor element 912m may not be grounded. For example, the capacitor element 912m may be connected to any fixed potential. In addition, the capacitor element 912m may be a designed capacitor device, or the capacitor element may be a parasitic capacitor.

[0101] Among them, the above Fig.13 The page buffer structure shown in FIG. 1 is still applicable to the case where a page buffer includes two or more second bit line connection points 912 b. For example, please refer to Fig.14 , which shows a schematic diagram of the structure of another page buffer involved in the embodiment of the present application. Fig.14 As shown, when the fourth switch device 912h is turned on, the sensing latch 912k and the capacitor element 912m can be connected to the first bit line connection point 912a, and when a first switch device 912c is turned on, the sensing latch 912k and the capacitor element 912m can also be connected to the second bit line connection point 912b corresponding to the first switch device 912c; in order to avoid the reading operation affecting the sensing latch 912k and the capacitor element 912m, Fig.14 In the embodiment, a third switch device 912j is provided between the sense latch 912k / capacitive element 912m and the three bit line connection points.

[0102] In a possible implementation of the present application, a sixth switch device 912p and a seventh switch device 912q are further provided between the second switch device 912d and the power supply terminal 912f on the precharge circuit corresponding to the second bit line connection point 912b, wherein the sixth switch device 912p is controlled to be turned on or off by the register 912g. For example, when the register 912g has sufficient voltage output, the sixth switch device 912p is turned on. Specifically, for example, at least during the programming process, the register 912g will control the sixth switch device 912p to be turned on; the seventh switch device 912q can be controlled by the control logic circuit 914. For example, outside the programming process, when the register 912g has sufficient voltage output, the sixth switch device 912p will be turned on. If the control logic circuit 914 is controlling the page buffer to perform a read operation at this time, the power supply terminal 912f will affect the capacitor element 912m. In this regard, the control logic circuit 914 can control the seventh switch device 912q to be turned off to ensure the correct execution of the read operation; and in the programming process, when the bit line connected to the second bit line connection point 912b needs to be pre-charged, the control logic circuit 914 can control the seventh switch device 912q to be turned on to ensure successful pre-charging.

[0103] For example, please refer to Fig.15, which shows a schematic diagram of the structure of another page buffer involved in the embodiment of the present application. Fig.15 As shown in FIG. 1 , on the precharge circuit corresponding to the second bit line connection point 912b, a sixth switch device 912p and a seventh switch device 912q are sequentially arranged near the power supply terminal 912f, and the on or off state of the sixth switch device 912p is controlled by a register 912g. In addition, the seventh switch device 912q is controlled by a control logic circuit 914. During the programming operation, at the stage of precharging the bit line through the second bit line connection point 912b, the register 912g has a voltage output to control the sixth switch device 912p to be turned on. At the same time, the control logic circuit 914 controls The seventh switch device 912q, the second switch device 912d and the fifth switch device 912i corresponding to the second bit line connection point 912b are turned on. At this time, the pre-charging circuit from the power supply terminal 912f to the second bit line connection point 912b is turned on, and pre-charging can be achieved; and in the read operation, the register 912g may have a voltage output, that is, the sixth switch device 912p may be in the on state. At this time, the control logic circuit 914 needs to control the seventh switch device 912q to be disconnected to prevent the voltage output from the power supply terminal 912f from being applied to the capacitor element 912m.

[0104] Among them, the pre-charging circuit corresponding to the first bit line connection point 912a has two switch devices with the same functions and connection methods as the sixth switch device 912p and the seventh switch device 912q, which will not be described in detail here.

[0105] In addition, the sixth switch device 912p and the seventh switch device 912q are also applicable to the circuit structure of multiple second bit line connection points 912b. That is, when the page buffer 912 includes two or more second bit line connection points 912b, the pre-charging circuit corresponding to each second bit line connection point 912b includes the sixth switch device 912p and the seventh switch device 912q respectively.

[0106] Based on the above Figures 9 to 15 For the scheme shown, please refer to Fig.16 , which shows a circuit structure diagram of a page buffer involved in an exemplary embodiment of the present application. Taking a page buffer including two bit line connection points as an example, the positions of the first bit line connection point 912a, the second bit line connection point 912b, the first switch device 912c, the second switch device 912d, the precharge circuit 912e, the power supply terminal 912f, the fourth switch device 912h, the fifth switch device 912i, the third switch device 912j, the sensing latch 912k, the capacitor element 912m, the sixth switch device 912p, and the seventh switch device 912q are as shown in FIG. Fig.16 shown.

[0107] exist Fig.16 In the embodiment, the first switch device 912c can be turned on by the SW1 signal control, the second switch device 912d can be turned on by the VSOBLK_1 signal control, the third switch device 912j can be turned on by the VSOBLK_0 signal control, the fourth switch device 912h can be turned on by the VPASS_HV0 signal control, the fifth switch device 912i can be turned on by the VPASS_HV1 signal control, and the seventh switch device 912q can be turned on by the EN_4BL_B signal control.

[0108] Among them, for the first bit line connection point 912a, the switching device corresponding to the sixth switching device 912p is the eighth switching device 912s, and the switching device corresponding to the seventh switching device 912q is the ninth switching device 912t, and the ninth switching device 912t can be turned on by VBLCLAMP signal control.

[0109] Based on the above Figures 5 to 16 In any of the solutions shown, in the memory involved, two bit line connection points can be connected to a plurality of bit lines respectively.

[0110] In a possible implementation of the present application, a first bit line connection point is connected to N bit lines among 2×N bit lines included in a memory cell array, and a second bit line connection point is connected to another N bit lines among the 2×N bit lines, where N is an integer greater than or equal to 2; the 2×N bit lines are adjacent in sequence, and the bit lines to which the first bit line connection point and the second bit line connection point are respectively connected are arranged alternately in sequence.

[0111] Please refer to Fig.17 , which shows a schematic diagram of the connection between a page buffer and a bit line involved in an embodiment of the present application. Fig.17 As shown, the memory cell array includes at least 2×N bit lines that are adjacent to each other in sequence, and are numbered BL 0 to BL 2N-1, respectively, wherein the first bit line connection point 912a and the second bit line connection point 912b are respectively connected to the N bit lines through the switch device 922, and the bit lines respectively connected to the first bit line connection point and the second bit line connection point are arranged alternately in sequence, that is, in the above 2×N bit lines, of every two adjacent bit lines, one bit line is connected to the first bit line connection point 912a through the switch device 922, and the other bit line is connected to the second bit line connection point 912b through the switch device 922; specifically, for example, in Fig.17 In the embodiment, the first bit line connection point 912a is connected to BL 0, BL 2, ..., BL 2N-2 respectively through the switch device 922, and the second bit line connection point 912b is connected to BL 1, ..., BL 2N-3, BL 2N-1 respectively through the switch device 922.

[0112] The switch device 922 can be used to connect a bit line connection point to one of the corresponding N bit lines at the same time point, and disconnect the bit line connection point from the other N-1 bit lines of the corresponding N bit lines. Different bit line connection points can be connected to their corresponding bit lines at the same time.

[0113] In a possible implementation of the present application, the control logic circuit 914 is configured to apply a bias voltage to the second bit line during a programming operation on a memory cell coupled to the first bit line through the page buffer 912; wherein the first bit line and the second bit line are two adjacent bit lines among the 2×N bit lines.

[0114] The page buffer involved in the solution shown in the above embodiment of the present application, and the connection relationship between the two bit line connection points in the page buffer and the bit lines in the memory cell array can be used to remove the BL to BL coupling during the programming operation.

[0115] Specifically, parasitic capacitance is an unavoidable and usually unwanted capacitance that exists between parts of electronic components or circuits simply because they are close to each other. When two conductors with different voltages are close together, the electric field between them causes charge to be stored on the two conductors. This effect is capacitance. For high-density memory cell arrays, the bit lines may be very long and the spacing between the bit lines may be very close. When the distance between the bit lines is close, mutual capacitance will occur between the two bit lines. This mutual capacitance is like parasitic between the wiring, so it can be called parasitic capacitance, also known as stray capacitance. Due to the existence of parasitic capacitance between bit lines, when the page buffer programs multiple bit lines in succession, it may cause coupling problems between bit lines. For example, in the above example, Fig.17 For example, at time 1, the page buffer performs a programming operation on BL 0. At time 2 after the programming operation on BL 0 is completed, the page buffer performs a programming operation on BL 1. Since BL 0 and BL 1 are two adjacent bit lines and the distance between them is relatively close, there will be a parasitic capacitance between them. When the page buffer performs a programming operation on BL 1, coupling will occur between BL 1 and BL 0, resulting in a change in the data already stored in the storage unit in BL 0, thereby causing a data error. Similarly, at time 3 after the programming operation on BL 1 is completed, the page buffer performs a programming operation on BL 2. Since BL 1 and BL 2 are two adjacent bit lines and the distance between them is relatively close, there will be a parasitic capacitance. When the page buffer performs a programming operation on BL 2, coupling will occur between BL 1 and BL 2, resulting in a change in the data already stored in the storage unit in BL 1, thereby causing a data error.

[0116] For the above problems, based on the above application Fig.17 The connection method between the bit line connection point and the bit line shown is that since two adjacent bit lines are connected to different bit line connection points in a page buffer, and different bit line connection points have their own independent pre-charging circuits, therefore, for two adjacent bit lines, when the page buffer performs a programming operation on the storage unit coupled to the first bit line through a bit line connection point, since the adjacent second bit line is connected to another bit line connection point, at this time, the page buffer can apply a bias voltage to the second bit line through the pre-charging circuit corresponding to the other bit line connection point, thereby suppressing the coupling between the first bit line and the second bit line.

[0117] For example, in Fig.17 In the embodiment, at time 1, the page buffer starts to perform a programming operation on BL 0 through the first bit line connection point. During the programming operation, the page buffer can apply a bias voltage to BL 1 through the second bit line connection point, thereby suppressing the coupling between BL 0 and BL 1. Similarly, at time 2, the page buffer starts to perform a programming operation on BL1 through the second bit line connection point. During the programming operation, the page buffer can apply a bias voltage to BL 0 through the first bit line connection point, thereby suppressing the coupling between BL 0 and BL 1.

[0118] In a possible implementation of the present application, the control logic circuit is configured to apply programming pulse voltages to the 2×N bit lines in sequence through the first bit line connection point and the second bit line connection point in the order in which the 2×N bit lines are arranged when a programming operation is performed on the memory cells coupled to the 2×N bit lines through a page buffer; wherein, among the 2×N bit lines, there is an overlapping part in the time interval for applying the programming pulse voltage to two adjacent bit lines, so as to achieve the application of bias voltages to adjacent bit lines of the bit lines during the programming operation of the memory cells coupled to one bit line.

[0119] In the above embodiment, the page buffer starts to perform a programming operation on BL 0 through the first bit line connection point. During the programming operation, the page buffer applies a bias voltage to BL 1 through the second bit line connection point. If the bias voltage applied by the page buffer to BL 1 through the second bit line connection point is only used to eliminate the coupling between BL 0 and BL 1, the page buffer will be unable to perform a programming operation through the second bit line connection point, which will affect the concurrency performance of the programming operation, resulting in a too long programming time, thereby affecting the data write rate.

[0120] In this regard, the solution shown in the embodiment of the present application provides a timing design for performing programming operations on memory cells coupled to adjacent bit lines respectively through two bit line connection points. Specifically, for example, when the page buffer performs a programming operation on the memory cell coupled to the first bit line through the first bit line connection point, after the programming operation starts and before the programming operation ends, the page buffer starts to perform a programming operation on the memory cell coupled to the second bit line adjacent to the first bit line through the second bit line connection point. Since the programming operation on the memory cell coupled to the first bit line has not yet ended at this time, a programming pulse voltage is still being applied to the first bit line through the first bit line connection point. Therefore, the programming pulse voltage (i.e., the above-mentioned bias voltage) applied by the page buffer to the second bit line through the second bit line connection point will not cause coupling between the first bit line and the second bit line. Accordingly, when the page buffer finishes programming the storage unit coupled to the first bit line through the first bit line connection point, it can start programming the storage unit coupled to the next adjacent third bit line of the second bit line through the first bit line connection point. At this time, the programming operation of the storage unit coupled to the second bit line has not yet ended, and the programming pulse voltage is still being applied to the second bit line through the second bit line connection point. Therefore, the programming pulse voltage (i.e., the above-mentioned bias voltage) applied by the page buffer to the third bit line through the first bit line connection point will not cause coupling between the second bit line and the third bit line, and so on. Through the execution timing of the above-mentioned programming operation, the scheme shown in the present application can suppress the coupling between adjacent bit lines without affecting the concurrent performance of performing programming operations separately through two bit line access points.

[0121] Among them, please refer to Fig.18 , which shows an execution timing diagram of a programming operation involved in an embodiment of the present application. Fig.18 As shown, the first bit line connection point and the second bit line connection point in the page buffer are arranged in accordance with Fig.17 As shown in the connection mode, each of which is connected to four bit lines as an example, it is assumed that the first bit line connection point is connected to BL 0, BL 2, BL 4 and BL 6 respectively through switch device 0, switch device 2, switch device 4 and switch device 6, and the second bit line connection point is connected to BL 1, BL 3, BL 5 and BL 7 respectively through switch device 1, switch device 3, switch device 5 and switch device 6; wherein, the data to be programmed corresponding to BL 0 to BL 7 are D 0 to D 7 respectively; as shown in FIG. Fig.18 As shown, the time intervals corresponding to the switch devices 0 to 7 are the time when the switch devices 0 to 7 are respectively turned on, and the time intervals corresponding to D 0 to D 7 are the time when D 0 to D 7 are respectively loaded; Fig.18It can be seen that in the order from BL 0 to BL 7, the turn-on times of the switch devices corresponding to two adjacent bit lines intersect with each other, thereby ensuring that when programming of one bit line begins, the programming operation of the adjacent previous bit line has not yet been completed, thereby suppressing the coupling between the two bit lines.

[0122] pass Fig.17 The bit line connections shown and Fig.18 The programming operation timing shown can ensure the suppression of coupling between the eight bit lines BL 0 to BL7. Then, when there are adjacent bit lines after BL 7 (such as BL 8), since BL8 is the bit line corresponding to other page buffers, when other page buffers start to perform programming operations on storage cells coupled to BL 8, if no programming operation is being performed in BL 7 at this time, the programming operation of BL 8 will cause BL 8 to couple to BL 7. If BL 7 has completed the programming operation at this time, the data in BL 7 will be changed, thereby causing data errors. In this regard, the scheme shown in the embodiment of the present application can coordinate the programming operations of the two page buffers through the control logic circuit, so that the time when different page buffers perform programming operations on the storage cells coupled to BL 7 and BL 8 respectively is the same or there is overlap.

[0123] In one possible implementation of the present application, for the 4×N bit lines in the memory cell array that are adjacent to two page buffer vectors, the order in which the programming pulse voltages are applied sequentially to the first 2×N bit lines of the 4×N bit lines is opposite to the order in which the programming pulse voltages are applied sequentially to the last 2×N bit lines of the 4×N bit lines.

[0124] Specifically, for 4×N bit lines that are adjacent to each other, the front and rear parts of the 4×N bit lines are connected to different page buffers, for example, please refer to Fig.19 , which shows a schematic diagram of the connection between a page buffer and a bit line involved in an embodiment of the present application. Fig.19 As shown, the memory cell array includes at least 4×N bit lines that are adjacent to each other in sequence, and are numbered BL 0 to BL 4N-1, respectively. The first bit line connection point 912a and the second bit line connection point 912b of the page buffer 1 are respectively connected to N bit lines of the first 2×N bit lines through a switch device 922, and the bit lines connected to the first bit line connection point and the second bit line connection point are arranged alternately in sequence. Specifically, for example, Fig.19In the embodiment, the first bit line connection point 912a of the page buffer 1 is connected to BL 0, BL 2, ... BL 2N-2 respectively through the switch device 922, and the second bit line connection point 912b of the page buffer 1 is connected to BL 1, ..., BL 2N-3, BL 2N-1 respectively through the switch device 922; correspondingly, the first bit line connection point 912a and the second bit line connection point 912b of the page buffer 2 are respectively connected to N bit lines of the last 2×N bit lines through the switch device 922, and the bit lines respectively connected to the first bit line connection point and the second bit line connection point are arranged alternately in sequence. Specifically, for example, in Fig.19 In the embodiment, the first bit line connection point 912a of the page buffer 2 is connected to BL 2N, BL 2N+2, ... BL 4N-2 respectively through the switch device 922, and the second bit line connection point 912b of the page buffer 2 is connected to BL 2N+1, ..., BL 4N-3, BL4N-1 respectively through the switch device 922.

[0125] Among them, combined Fig.19 , please refer to Fig. 20 , which shows another execution timing diagram of a programming operation involved in an embodiment of the present application. Fig. 20 As shown, the first bit line connection point and the second bit line connection point in the page buffer 1 and the page buffer 2 are arranged according to Fig.19 As shown in the connection mode, each of which connects 4 bit lines as an example, it is assumed that the first bit line connection point in the page buffer 1 is connected to BL 0, BL 2, BL 4 and BL 6 respectively through the switch device 0, the switch device 2, the switch device 4 and the switch device 6, the second bit line connection point in the page buffer 1 is connected to BL 1, BL 3, BL 5 and BL 7 respectively through the switch device 1, the switch device 3, the switch device 5 and the switch device 6, the first bit line connection point in the page buffer 2 is connected to BL 8, BL 10, BL 12 and BL 14 respectively through the switch device 8, the switch device 10, the switch device 12 and the switch device 14, the second bit line connection point in the page buffer 2 is connected to BL 9, BL 11, BL 13 and BL 15 respectively through the switch device 9, the switch device 11, the switch device 13 and the switch device 15; wherein, the to-be-programmed data corresponding to BL 0 to BL 15 are D 0 to D 15 respectively; as shown in FIG. Fig. 20 As shown, the time intervals corresponding to the switch devices 0 to 15 are the time when the switch devices 0 to 15 are respectively turned on, and the time intervals corresponding to D 0 to D 15 are the time when D 0 to D 15 are respectively loaded; Fig. 20It can be seen that, in the order from BL 0 to BL 7, the turn-on times of the switch devices corresponding to two adjacent bit lines intersect with each other, and in the order from BL 15 to BL 8, the turn-on times of the switch devices corresponding to two adjacent bit lines intersect with each other, thereby ensuring that when programming of one bit line begins, the programming operation of the adjacent previous bit line has not yet been completed. At the same time, the two page buffers can perform programming operations synchronously, and the programming operation time of BL 7 and BL 8 is the same, thereby suppressing the coupling between each two adjacent bit lines in each bit line corresponding to the two page buffers.

[0126] Fig.21 is a flow chart of a memory operation method provided by an exemplary embodiment of the present application, the method is applied to the memory and is executed by a control logic circuit in a peripheral logic circuit of the memory; wherein the memory may be as follows Fig. 9 , Fig.17 or Fig.19 The memory shown; Fig.21 As shown, the method includes the following.

[0127] Step 2101, when performing a programming operation through a page buffer, turning off a first switching device and turning on a second switching device.

[0128] Step 2102, when performing a read operation through the page buffer, turning on the first switch device and turning off the second switch device.

[0129] In a possible implementation of the present application, a third switch device is provided between the first bit line connection point and the latch in the page buffer, and the third switch device is located outside the precharge circuit corresponding to the first bit line connection point.

[0130] In a possible implementation of the present application, the method further includes: when performing a programming operation through the page buffer, turning off the third switch device; when performing a read operation through the page buffer, turning on the third switch device.

[0131] In a possible implementation of the present application, a first bit line connection point is connected to N bit lines among 2×N bit lines included in a memory cell array, and a second bit line connection point is connected to another N bit lines among the 2×N bit lines, where N is an integer greater than or equal to 2; the 2×N bit lines are adjacent in sequence, and the bit lines to which the first bit line connection point and the second bit line connection point are respectively connected are arranged alternately in sequence.

[0132] In a possible implementation of the present application, the method further includes: applying a bias voltage to the second bit line during a programming operation on a storage unit coupled to the first bit line through a page buffer; wherein the first bit line and the second bit line are two adjacent bit lines among the 2×N bit lines.

[0133] In a possible implementation of the present application, during a programming operation on a memory cell coupled to a first bit line through a page buffer, a bias voltage is applied to a second bit line, including: during a programming operation on memory cells coupled to 2×N bit lines through a page buffer, a programming pulse voltage is sequentially applied to the 2×N bit lines through a first bit line connection point and a second bit line connection point in the order in which the 2×N bit lines are arranged; wherein, among the 2×N bit lines, there is an overlapping portion in the time interval for applying the programming pulse voltage to two adjacent bit lines, so as to achieve the application of a bias voltage to adjacent bit lines of the bit lines during a programming operation on a memory cell coupled to one bit line.

[0134] In one possible implementation of the present application, for the 4×N bit lines in the memory cell array that are adjacent to two page buffer vectors, the order in which the programming pulse voltages are applied sequentially to the first 2×N bit lines of the 4×N bit lines is opposite to the order in which the programming pulse voltages are applied sequentially to the last 2×N bit lines of the 4×N bit lines.

[0135] Fig. 22 is a structural block diagram of a storage system provided by an exemplary embodiment of the present application, such as Fig. 22 As shown, the storage system 2200 includes: one or more memories 2210, and,

[0136] A controller 2220 is coupled to the memory 2210 and configured to control the memory 2210 .

[0137] Storage system 2200 may be all or part of a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0138] Optionally, the storage system 2200 may include a host and a storage subsystem, the storage subsystem having one or more memories 2210 and a controller 2220. The host may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host may be configured to send data to the memory 2210. Alternatively, the host may be configured to receive data from the memory 2210.

[0139] According to some embodiments, the controller 2220 is also coupled to a host. The controller 2220 may manage data stored in the memory 2210 and communicate with the host.

[0140] In some embodiments, the controller 2220 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0141] In some embodiments, the controller 2220 is designed to operate in a high duty cycle environment solid state drive (SSD) or embedded Multi Media Card (eMMC), which is used as data storage for mobile devices such as smart phones, tablet computers, laptops, etc., as well as enterprise storage arrays.

[0142] The controller 2220 may be configured to control operations of the memory 2210, such as read, erase, and program operations. The controller 2220 may also be configured to manage various functions regarding data stored or to be stored in the memory 2210, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the controller 2220 is also configured to process error correction codes (ECC) regarding data read from or written to the memory 2210.

[0143] Controller 2220 may also perform any other suitable functions, such as formatting memory 2210. Controller 2220 may communicate with an external device according to a specific communication protocol.

[0144] The controller 2220 and one or more memories 2210 can be integrated into various types of storage devices, for example, included in the same package (eg, a universal flash storage (UFS) package or an eMMC package). That is, the memory system 2200 can be implemented and packaged into different types of terminal electronic products.

[0145] Illustratively, the controller 2220 and the single memory 2210 may be integrated into a memory card. The memory card may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card may also include a memory card connector for coupling the memory card to a host.

[0146] Illustratively, the controller 2220 and the plurality of memories 2210 may be integrated into a solid state drive (SSD). In some implementations, the storage capacity and / or operating speed of the solid state drive is greater than the storage capacity and / or operating speed of the memory card.

[0147] The memory 2210 may be implemented as follows: Fig. 9 , Fig.17 or Fig.19 Memory shown.

[0148] It is understood that the control logic circuit in the memory 2210 can execute the above Fig.21 All or part of the steps in the scheme shown.

[0149] The present application embodiment provides a computer system, which includes: a host; one or more Fig. 9 , Fig.17 or Fig.19 The memory shown; and, a controller coupled to the memory and configured to control the memory.

[0150] The embodiment of the present application provides a computer-readable storage medium, which stores instructions, which, when executed on a control logic circuit of a controller, implement the following Fig.21 The embodiment shown in the figure provides a method for operating a memory. Optionally, the memory may be as follows: Fig. 9 , Fig.17 or Fig.19 Any of the memories shown.

[0151] In the present application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "at least one" means one or more, and the term "plurality" means two or more, unless otherwise clearly defined.

[0152] The term "and / or" in this application is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0153] The above description is only an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A memory, characterized in that: The memory includes a peripheral circuit and a memory cell array; The peripheral circuit includes a plurality of page buffers, and a logic control circuit coupled to the plurality of page buffers and configured to control the plurality of page buffers; The page buffer comprises a first bit line connection point, a second bit line connection point, a first switch device and a second switch device; The first bit line connection point and the second bit line connection point are used to connect the bit lines in the memory cell array; the first bit line connection point and the second bit line connection point are respectively connected to the power supply terminal through independent precharging circuits, and the first bit line connection point and the second bit line connection point are respectively connected to the latch in the page buffer; the precharging circuit is a circuit for the page buffer to precharge the bit lines; The first switch device connects the first bit line connection point and the second bit line connection point; The second switch device is located on a precharge circuit corresponding to the second bit line connection point.

2. The memory according to claim 1, characterized in that: The control logic circuit is configured to turn off the first switching device and turn on the second switching device when a programming operation is performed through the page buffer; The control logic circuit is configured to turn on the first switching device and turn off the second switching device when a read operation is performed through the page buffer.

3. The memory according to claim 2, characterized in that: A third switch device is provided between the first bit line connection point and the sensing latch in the page buffer, and the third switch device is located outside the precharge circuit corresponding to the first bit line connection point.

4. The memory according to claim 3, characterized in that: The control logic circuit is configured to turn off the third switch device when a programming operation is performed through the page buffer; The control logic circuit is configured to turn on the third switch device when a read operation is performed through the page buffer.

5. The memory according to any one of claims 1 to 4, characterized in that: The first bit line connection point is connected to N bit lines among the 2×N bit lines included in the memory cell array, and the second bit line connection point is connected to another N bit lines among the 2×N bit lines, where N is an integer greater than or equal to 2; The 2×N bit lines are adjacent to each other in sequence, and the bit lines respectively connected to the first bit line connection point and the second bit line connection point are arranged alternately in sequence.

6. The memory according to claim 5, characterized in that: The control logic circuit is configured to apply a bias voltage to the second bit line during a programming operation of a memory cell coupled to the first bit line through the page buffer; The first bit line and the second bit line are two adjacent bit lines among the 2×N bit lines.

7. The memory according to claim 6, characterized in that: The control logic circuit is configured to, when performing a programming operation on the memory cells coupled to the 2×N bit lines through the page buffer, Applying programming pulse voltages to the 2×N bit lines in sequence according to the arrangement order of the 2×N bit lines through the first bit line connection point and the second bit line connection point; Among the 2×N bit lines, there is an overlapped portion in the time intervals of applying programming pulse voltages to two adjacent bit lines, so as to implement application of bias voltages to adjacent bit lines of the bit line during the programming operation of a storage unit coupled to a bit line.

8. The memory according to claim 7, characterized in that: For the 4×N bit lines in the memory cell array that are adjacent to the two page buffer vectors, the order in which the programming pulse voltages are applied sequentially to the first 2×N bit lines among the 4×N bit lines is opposite to the order in which the programming pulse voltages are applied sequentially to the last 2×N bit lines among the 4×N bit lines.

9. A method for operating a memory, characterized in that: The method is executed by a control logic circuit in a peripheral logic circuit of a memory, the memory is a memory as shown in claim 1, and the method comprises: When performing a programming operation through the page buffer, turning off the first switching device and turning on the second switching device; When a read operation is performed through the page buffer, the first switching device is turned on, and the second switching device is turned off.

10. The method according to claim 9, characterized in that A third switch device is provided between the first bit line connection point and the sensing latch in the page buffer, and the third switch device is located outside the precharge circuit corresponding to the first bit line connection point.

11. The method according to claim 10, characterized in that The method further comprises: When performing a programming operation through the page buffer, turning off the third switching device; The third switching device is turned on when a read operation is performed through the page buffer.

12. The method according to any one of claims 9 to 11, characterized in that: The first bit line connection point is connected to N bit lines among the 2×N bit lines included in the memory cell array, and the second bit line connection point is connected to another N bit lines among the 2×N bit lines, where N is an integer greater than or equal to 2; The 2×N bit lines are adjacent to each other in sequence, and the bit lines respectively connected to the first bit line connection point and the second bit line connection point are arranged alternately in sequence.

13. The method according to claim 12, characterized in that The method further comprises: applying a bias voltage to the second bit line during a programming operation of a memory cell coupled to the first bit line through the page buffer; The first bit line and the second bit line are two adjacent bit lines among the 2×N bit lines.

14. The method according to claim 13, characterized in that The step of applying a bias voltage to a second bit line during a program operation on a memory cell coupled to the first bit line through the page buffer comprises: When performing a programming operation on the memory cells coupled to the 2×N bit lines through the page buffer, sequentially applying programming pulse voltages to the 2×N bit lines through the first bit line connection point and the second bit line connection point according to the arrangement order of the 2×N bit lines; Among the 2×N bit lines, there is an overlapped portion in the time intervals of applying programming pulse voltages to two adjacent bit lines, so as to implement application of bias voltages to adjacent bit lines of the bit line during the programming operation of a storage unit coupled to a bit line.

15. The method according to claim 14, characterized in that For the 4×N bit lines in the memory cell array that are adjacent to the two page buffer vectors, the order in which the programming pulse voltages are applied sequentially to the first 2×N bit lines among the 4×N bit lines is opposite to the order in which the programming pulse voltages are applied sequentially to the last 2×N bit lines among the 4×N bit lines.

16. A storage system, characterized in that: The storage system comprises: One or more memories according to any one of claims 1 to 8, and, A controller is coupled to the memory and configured to control the memory.

17. A computer system, characterized in that: The computer system comprises: Host; One or more memories as claimed in any one of claims 1 to 8; and, A controller is coupled to the memory and configured to control the memory.

18. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores instructions, and when the instructions are executed on the control logic circuit, the memory operation method according to any one of claims 9 to 15 is implemented.

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