Operation method of memory, memory, memory system and electronic system

Abstract

The embodiment of the invention discloses an operation method of a memory, the memory, a memory system and an electronic system. Wherein the memory comprises a page buffer, the page buffer comprises a first sensing circuit coupled with a sensing node and a dynamic storage circuit coupled with the first sensing circuit; a memory cell included in the memory is configured to store one of a plurality of programming states; the operation method comprises the following steps: storing first verification information to the first sensing circuit according to a first potential of the sensing node; transmitting the initial verification information in the dynamic storage circuit to a sensing node; transmitting the first verification information from the first sensing circuit to the dynamic storage circuit, and performing a clearing operation on the first sensing circuit; second verification information or initial verification information is stored to the first sensing circuit according to a second potential of the sensing node.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to a memory operation method, a memory, a memory system and an electronic system. Background Art

[0002] At present, three-dimensional NAND flash memory is usually programmed by incremental step pulse programming (ISPP). Specifically, multiple gradually increasing pulse programming voltages are used in sequence to program the memory cells of the memory, and each programming process may include a programming operation and a verification operation, wherein the verification operation is performed after the programming operation, that is, the verification voltage is used to verify the memory cells after each programming operation is performed on the memory cells. Summary of the invention

[0003] Embodiments of the present application provide a memory operating method, a memory, a memory system, and an electronic system.

[0004] In a first aspect, an embodiment of the present application provides an operating method of a memory, wherein the memory includes a page buffer, the page buffer includes a first sensing circuit coupled to a sensing node and a dynamic storage circuit coupled to the first sensing circuit; the memory includes a storage unit configured to store one of a plurality of programming states; the operating method includes:

[0005] storing first verification information in the first sensing circuit according to a first potential of the sensing node;

[0006] transmitting initial verification information in the dynamic storage circuit to the sensing node; the initial verification information includes verification information corresponding to a verified programming state among the multiple programming states;

[0007] transmitting the first verification information from the first sensing circuit to the dynamic storage circuit, and performing a clearing operation on the first sensing circuit;

[0008] storing second verification information or the initial verification information in the first sensing circuit according to a second potential of the sensing node;

[0009] The first potential of the sensing node corresponding to the first verification information is greater than the second potential of the sensing node corresponding to the second verification information.

[0010] In a second aspect, an embodiment of the present application further provides an operating method of a memory, wherein the memory includes a page buffer, the page buffer includes a first sensing circuit coupled to a sensing node and a dynamic storage circuit coupled to the first sensing circuit; the memory includes a storage unit configured to store one of a plurality of programming states; the operating method includes:

[0011] In a first sensing phase of a verification operation of the memory, latching first verification information into the first sensing circuit;

[0012] transmitting initial verification information in the dynamic storage circuit to the sensing node; the initial verification information includes verification information corresponding to a verified programming state among a plurality of programming states contained in the memory;

[0013] Opening a transmission channel between the first sensing circuit and the dynamic storage circuit to transmit the first verification information to the dynamic storage circuit; and performing a clearing operation on the first sensing circuit;

[0014] During a second sensing phase of the verification operation, latching second verification information into the first sensing circuit;

[0015] The first potential of the sensing node corresponding to the first verification information is greater than the second potential of the sensing node corresponding to the second verification information.

[0016] In a third aspect, an embodiment of the present application provides a memory, including:

[0017] A memory array; the memory cells included in the memory array are configured to store one of a plurality of programming states;

[0018] A plurality of page buffers coupled to the memory array; each page buffer comprising: a first sensing circuit coupled to a sensing node and a dynamic storage circuit coupled to the first sensing circuit;

[0019] and a control logic circuit coupled to the storage array and the plurality of page buffers; wherein,

[0020] The control logic circuit is configured to: store first verification information in the first sensing circuit according to the first potential of the sensing node; transmit initial verification information in the dynamic storage circuit to the sensing node; the initial verification information includes verification information corresponding to a verified programming state among the multiple programming states; transmit the first verification information from the first sensing circuit to the dynamic storage circuit, and perform a clear operation on the first sensing circuit; store second verification information or the initial verification information in the first sensing circuit according to the second potential of the sensing node; wherein the first potential of the sensing node corresponding to the first verification information is greater than the second potential of the sensing node corresponding to the second verification information.

[0021] In a fourth aspect, an embodiment of the present application further provides a memory system, comprising: one or more of the aforementioned memories and a memory controller coupled to the memories and used to control the memories.

[0022] In a fifth aspect, an embodiment of the present application further provides an electronic system, comprising: the aforementioned memory system and a host coupled to the memory system.

[0023] The embodiment of the present application provides a method for operating a memory, a memory, a memory system and an electronic device. The memory includes a page buffer, the page buffer includes a first sensing circuit coupled to a sensing node and a dynamic storage circuit coupled to the first sensing circuit; the storage unit included in the memory is configured to store one of a plurality of programming states; the operation method includes: storing first verification information to the first sensing circuit according to the first potential of the sensing node; transmitting initial verification information in the dynamic storage circuit to the sensing node; the initial verification information includes verification information corresponding to a verified programming state in the plurality of programming states; transmitting the first verification information from the first sensing circuit to the dynamic storage circuit, and performing a clearing operation on the first sensing circuit; storing second verification information or the initial verification information to the first sensing circuit according to the second potential of the sensing node; wherein the first potential of the sensing node corresponding to the first verification information is greater than the second potential of the sensing node corresponding to the second verification information. The operating method provided in the embodiment of the present application transmits the initial verification information in the dynamic storage circuit to the sensing node, transmits the first verification information from the first sensing circuit to the dynamic storage circuit, and performs a clearing operation on the first sensing circuit, thereby enabling the first sensing circuit to sense the first verification information and the second verification information at different times, thereby achieving the programming verification operation of the 4BL (bit line) scheme of the storage cell of the memory by performing only one complete sensing under the same verification voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In the drawings, which are not necessarily drawn to scale, the same reference numerals may describe similar components in different views. The same numerals with different letter suffixes may represent different instances of similar components. The drawings generally illustrate various embodiments discussed in this document by way of example and not limitation.

[0025] Figure 1 An exemplary system block diagram of an electronic device having a memory system according to some aspects of the present application;

[0026] Figure 2 A schematic diagram of an exemplary memory card having a memory provided according to some aspects of the present application;

[0027] Figure 3 A schematic diagram of an exemplary SSD having a memory according to some aspects of the present application;

[0028] Figure 4 A schematic diagram of an exemplary memory including a peripheral circuit according to some aspects of the present application;

[0029] Figure 5 is a side view of a cross section of an exemplary memory array 401 including NAND memory strings 408 provided in accordance with some aspects of the present application;

[0030] Figure 6 A block diagram of an exemplary memory including a memory array and peripheral circuits provided according to some aspects of the present application;

[0031] Figure 7 A set of exemplary programming voltages for the ISPP programming method provided according to some aspects of the present application;

[0032] Figure 8 A set of exemplary verification voltages for verification operations provided according to some aspects of the present application;

[0033] Fig. 9 A schematic diagram of a 4BL BIAS programming method provided according to some aspects of the present application;

[0034] Fig.10 A comparison diagram of single sensing and double sensing provided according to some aspects of the present application;

[0035] Fig.11 A schematic flow chart of a memory operation method provided according to some aspects of the present application;

[0036] Fig.12 A schematic diagram of the relationship between a page buffer group and a storage array included in a memory provided according to some aspects of the present application;

[0037] Figures 13 to 16 A schematic diagram of states of sensing nodes corresponding to the first storage unit, the second storage unit and the third storage unit before and after the initial verification information in the dynamic storage circuit is transmitted to the sensing node according to some aspects of the present application;

[0038] Fig.17 A schematic diagram of a circuit structure of a page buffer 121 provided according to some aspects of the present application;

[0039] Fig.18 A flowchart of implementing a 4BLBIAS programming mode using an operation method provided in an embodiment of the present application according to some aspects of the present application;

[0040] Fig.19 A flowchart of a method for operating a memory described from a timing perspective according to some aspects of the present application;

[0041] Fig. 20 According to some aspects of the present application, Fig.19 A timing diagram of the described method of operation;

[0042] Fig.21 A schematic diagram of the structure of a memory provided according to some aspects of the present application. DETAILED DESCRIPTION

[0043] The following describes the various embodiments of the present application in more detail with reference to the accompanying drawings. Other embodiments that can be used as variations of any disclosed embodiment can be formed by configuring or arranging the elements and features in the embodiments of the present application in different ways. Therefore, the embodiments of the present application are not limited to the embodiments set forth herein. On the contrary, the described embodiments are provided so that the embodiments of the present application are thorough and complete, and the scope of the embodiments of the present application is fully conveyed to the technicians in the technical field to which the embodiments of the present application belong. It should be noted that references to "embodiment", "another embodiment" and the like do not necessarily represent only one embodiment, and different references to any such phrases are not necessarily for the same embodiment. It should be understood that, although the terms "first", "second", "third" and the like can be used in this article to identify various elements, these elements are not limited by these terms. These terms are used to distinguish an element from another element with the same or similar name. Therefore, without departing from the spirit and scope of the embodiments of the present application, the first element in one embodiment may also be referred to as the second or third element in another embodiment.

[0044] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale may be enlarged to clearly illustrate the features of the embodiments. When an element is referred to as being connected or coupled to another element, it should be understood that the former may be directly connected or coupled to the latter, or may be electrically connected or coupled to the latter via one or more intermediate elements therebetween. In addition, it should also be understood that when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or one or more intermediate elements may also be present.

[0045] The terms used in this article are only for the purpose of describing a specific embodiment, and are not intended to limit the present application. As used herein, the singular form is intended to include the plural form, unless the context clearly indicates otherwise. Unless otherwise specified or can be clearly understood from the context as a singular form, otherwise the articles "one" and / or "one" used in the present application embodiment and the appended claims should be collectively interpreted as indicating "one or more". It should be further understood that the terms "including", "including", "including" and "including" used in the present application embodiment specify the presence of the element and do not exclude the presence or addition of one or more other elements. The term "and / or" used in the present application embodiment includes any and all combinations of one or more associated listed items. Unless otherwise defined, all terms including technology and scientific technology used in the present application embodiment have the same meaning as those of ordinary skill in the field of the present application in view of the present application embodiment. It should be further understood that unless the present application embodiment is clearly defined, such as defined in a common dictionary, it should be interpreted as having a meaning consistent with its meaning in the environment of the present application embodiment and the related technology, and should not be interpreted in an idealized or overly formalized manner.

[0046] In the following description, many specific details are set forth to provide a thorough understanding of the present application, and the present application can be practiced without some or all of these specific details. In other cases, well-known processing structures and / or processing are not described in detail, so as not to unnecessarily obscure the present application. It should also be understood that, in some cases, unless otherwise special, it is obvious to those skilled in the relevant art that the features or elements described about one embodiment can be used alone or in combination with other features or elements of another embodiment. Hereinafter, various embodiments of the present application are described in detail with reference to the accompanying drawings. The following description focuses on details to facilitate understanding of the embodiments of the present application. Well-known technical details may be omitted, so as not to obscure the features and aspects of the embodiments of the present application.

[0047] An embodiment of the present application relates to a method for operating a memory, which can complete a programming verification operation of a 4BL scheme on a storage cell of the memory by performing only one complete sensing under the same verification voltage.

[0048] The embodiments of the present application are further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0049] Figure 1 A block diagram of an exemplary system with a memory provided according to some aspects of the present application is shown. Figure 1 In the embodiment, the system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 1 As shown, the system 100 may include a host 108 and a memory system 102, wherein the memory system 102 has one or more memories 104 and a memory controller 106; the host 108 may be a processor of an electronic device, such as a central processing unit (CPU) or a system on a chip (SoC), wherein the system on a chip may be, for example, an application processor (AP). The host 108 may be configured to send data to the memory 104 or receive data from the memory 104. Specifically, the memory 104 may be any memory disclosed in the present application. For example, a phase change random access memory (PCRAM), a three-dimensional NAND flash memory, and the like.

[0050] According to some embodiments, the memory controller 106 is coupled to the memory 104 and the host 108. And is configured to control the memory 104. The memory controller 106 can manage the data stored in the memory 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices with low duty cycle environments such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment, such as a solid state drive (SSD) or an embedded multimedia card (eMMC), where the SSD or eMMC is used as a data storage device for mobile devices with high duty cycle environments such as smart phones, tablet computers, laptop computers, and enterprise storage arrays. The memory controller 106 can be configured to control the operation of the memory 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 may communicate with an external device (e.g., the host 108) according to a specific communication protocol.For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnection (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.

[0051] The memory controller 106 and the one or more memories 104 may be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 102 may be implemented and packaged into different types of terminal electronic products. Figure 2 In one example shown, the memory controller 106 and the single memory 104 may be integrated into a memory card 202. The memory card may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card may also include a processor that connects the memory card to a host (e.g., Figure 1 The memory card connector 204 is coupled to the host 108 in the embodiment. Figure 3 In another example shown, the memory controller 106 and the plurality of memories 104 may be integrated into the SSD 302. The SSD may also include a processor that interfaces the SSD with a host (e.g., Figure 1 The memory controller 106 may be configured to control the erase, read, and write operations of the memory 104.

[0052] Figure 4 A schematic diagram of an exemplary memory including peripheral circuits is shown. Figure 4As shown, the memory 104 may include a memory array 401 and a peripheral circuit 402 coupled to the memory array 401, wherein the memory array 401 may be a NAND flash memory array, wherein memory cells 406 are provided in the form of an array of NAND memory strings 408, each NAND memory string 408 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 408 includes a plurality of memory cells 406 coupled in series and stacked vertically. Each memory cell 406 may hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the storage region of the memory cell 406. Each memory cell 406 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0053] In some embodiments, each memory cell 406 is a single level cell (SLC) having two possible data states and thus can store one bit of data, for example, the first data state "0" can correspond to a first voltage range, and the second data state "1" can correspond to a second voltage range. In some embodiments, the first voltage range and the second voltage range can be referred to as the threshold voltage distribution of the memory cell. In some embodiments, each memory cell 406 can be a multi-level cell (MLC), for example, MLC can store two bits per cell, three bits per cell (also known as a tri-level cell (TLC), or four bits per cell (also known as a quadruple level cell (QLC). Wherein, the data state of any type of memory cell includes an erased state and (one or more) programmed states. When a programming operation is performed on a memory cell, a memory cell in an erased state is programmed to a certain programmed state. Generally speaking, the voltage value in the voltage range corresponding to the programmed state of the memory cell is relatively large.

[0054] like Figure 4As shown, each NAND memory string 408 may include a source select gate (SSG) 410 at its source end and a drain select gate (DSG) 412 at its drain end. The SSG 410 and the DSG 412 may be configured to activate the selected NAND memory string 408 (column of the array) during read and program (or write) operations. In some embodiments, the sources of the NAND memory strings 408 in the same memory block 404 are coupled by the same source line (SL) 414 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 408 in the same memory block 404 have an array common source (ACS). According to some embodiments, the DSG 412 of each NAND memory string 408 is coupled to a corresponding bit line 416, and data can be read and written from the bit line 416 via an output bus (not shown). In some embodiments, each NAND memory string 408 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of a transistor having DSG412) or a deselect voltage (e.g., 0 volts (V)) to a corresponding DSG412 via one or more DSG lines 413 and / or applying a select voltage (e.g., higher than the threshold voltage of a transistor having SSG410) or a deselect voltage (e.g., 0 V) ​​to a corresponding SSG410 via one or more SSG lines 415.

[0055] like Figure 4 As shown, the NAND memory string 408 can be organized into a plurality of memory blocks 404, each of which can have a common source line 414 (e.g., coupled to ground). In some embodiments, each memory block 404 is a basic data unit with an erase operation, that is, all memory cells 406 on the same memory block 404 are erased at the same time. In order to erase the memory cells 406 in the selected memory block 404, the source lines 414 coupled to the selected memory block 404 and the unselected memory blocks 404 in the same plane (Plane) as the selected memory block 404 can be biased with an erase voltage (Vers) (e.g., a high positive voltage of 20V or higher). It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at any suitable number of blocks or any suitable fraction of blocks. The memory cells 406 of adjacent NAND memory strings 408 can be coupled by word lines 418, which select which row of memory cells 406 receives read and program operations. In some embodiments, memory cells 406 coupled to the same word line 418 form a page 420 .

[0056] Figure 5 4 shows a side view of a cross section of an exemplary memory array 401 including NAND memory strings 408 according to some aspects of the present application. Figure 5As shown in FIG, NAND memory string 408 can extend vertically through memory stack layer 502 above substrate 501. Substrate 501 can include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0057] The memory stack 502 may include alternating gate conductive layers 503 and gate-to-gate dielectric layers 504. The number of pairs of gate conductive layers 503 and gate-to-gate dielectric layers 504 in the memory stack 502 may determine the number of memory cells 406 in the memory array 401. The gate conductive layers 503 may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 503 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 503 includes a doped polysilicon layer. Each gate conductive layer 503 may include a control gate surrounding the memory cell 406 and may extend laterally at the top of the memory stack 502 as a DSG line 413, at the bottom of the memory stack 502 as an SSG line 415, or between the DSG line 413 and the SSG line 415 as a word line 418.

[0058] like Figure 5 As shown in , the NAND memory string 408 includes a channel structure 505 extending vertically through the memory stack layer 502. In some embodiments, the channel structure 505 includes a channel hole filled with (one or more) semiconductor materials and (one or more) dielectric materials. In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure 505 may have a cylindrical shape (e.g., a column shape). According to some embodiments, the semiconductor channel, the tunneling layer, the storage layer, and the barrier layer are arranged radially from the center of the column toward the outer surface of the column in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0059] Return to reference Figure 4, the peripheral circuit 402 may be coupled to the memory array 401 via the bit line 416, the word line 418, the source line 414, the SSG line 415, and the DSG line 413. The peripheral circuit 402 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory array 401 by applying a voltage signal and / or a current signal to each target memory cell 406 and sensing a voltage signal and / or a current signal from each target memory cell 406 via the bit line 416, the word line 418, the source line 414, the SSG line 415, and the DSG line 413. The peripheral circuit 402 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 6 Some exemplary peripheral circuits are shown, and the peripheral circuit 402 includes a page buffer / sense amplifier 604, a column decoder / bit line driver 606, a row decoder / word line driver 608, a voltage generator 610, a control logic unit 612, a register 614, an interface 616, and a data bus 618. It should be understood that in some examples, it may also include Figure 6 Additional peripheral circuits not shown.

[0060] The page buffer / sense amplifier 604 may be configured to read data from the memory array 401 and program (write) data to the memory array 401 according to a control signal from the control logic unit 612. In one example, the page buffer / sense amplifier 604 may store a page of programming data (write data) to be programmed into one page 420 of the memory array 401. In another example, the page buffer / sense amplifier 604 may perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 406 coupled to the selected word line 418. In yet another example, the page buffer / sense amplifier 604 may also sense a low-power signal from the bit line 416 representing a data bit stored in the memory cell 406 and amplify a small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 606 may be configured to be controlled by the control logic unit 612 and select one or more NAND memory strings 408 by applying a bit line voltage generated from the voltage generator 610.

[0061] The row decoder / word line driver 608 may be configured to be controlled by the control logic unit 612 and select / deselect the memory block 404 of the memory array 401 and select / deselect the word line 418 of the memory block 404. The row decoder / word line driver 608 may also be configured to drive the word line 418 using the word line voltage generated from the voltage generator 610. In some embodiments, the row decoder / word line driver 608 may also select / deselect and drive the SSG line 415 and the DSG line 413. As described in detail below, the row decoder / word line driver 608 is configured to perform an erase operation on the memory cell 406 coupled to the selected word line(s) 418. The voltage generator 610 may be configured to be controlled by the control logic unit 612 and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a local voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory array 401.

[0062] The control logic unit 612 may be coupled to each peripheral circuit described above, and is configured to control the operation of each peripheral circuit. The register 614 may be coupled to the control logic unit 612, and includes a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The interface 616 may be coupled to the control logic unit 612, and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic unit 612, and to buffer status information received from the control logic unit 612 and relay them to the host. The interface 616 may also be coupled to the column decoder / bit line driver 606 via a data bus 618, and act as a data I / O interface and a data buffer to buffer data and relay them to the storage array 401 or relay or buffer data from the storage array 401.

[0063] Based on the memory and memory system described above, for a memory with multiple programming states, such as a 3D NAND flash memory, when programming the memory cell of the NAND flash memory, it includes a programming operation and a verification operation, wherein the programming operation can adopt an ISPP method, and the ISPP scheme can be based on a step voltage to gradually increase the word line bias voltage while programming the selected memory cell several times, wherein the incremental step pulse V pgm For reference Figure 7. The verification operation may be an operation for understanding whether the programmed memory cell is programmed to the target programming state. Usually, the verification operation is performed between applying two programming voltages to the word line coupled to the memory cell, that is, the programming operation and the verification operation may be performed alternately. When at least one memory cell in the same programming state is to be verified, a corresponding verification voltage is applied to the word line coupled to the at least one memory cell, and whether the memory cell passes the verification is verified based on the verification voltage. Considering that the memory cells coupled to the same word line may be in different programming states, corresponding to different reference threshold voltages, multiple verification processes are required, that is, the verification operation may include one or a group of verification voltage pulses, and the verification voltage pulses such as Figure 8 As shown, Figure 8 1001 and 1003 are step programming pulses V pgm 1002 is a verification voltage pulse. For each verification, it is usually necessary to precharge the sensing node coupled to the storage cell to a higher potential (for example, a preset initial voltage described later), and then the sensing node performs at least one discharge operation, so as to sense the voltage at the sensing node (SO, Sensing Node) corresponding to the storage cell at different discharge stages through the sensing circuit, so as to determine whether the verification of the storage cell is completed according to the sensing result. The verification result can be stored in the page buffer to reflect the programming result of the storage cell.

[0064] In some embodiments, in the programming of 3D NAND flash memory, in order to improve the programming quality, 4BL BIAS programming is usually used for programming. Specifically, the 4BL BIAS programming method can refer to controlling the voltage applied to the bit line of the memory cell by the difference between the programming state of the memory cell being programmed and the respective target programming state, so that the voltage on the bit line of the memory cell currently in different programming states has a certain difference, so as to have more accurate programming of each memory cell, thereby obtaining a better distribution of the threshold voltage (Vt) of the memory cell. In order to determine the voltage on the bit line of the memory cell in different programming states, such as Fig. 9 As shown in the figure, in the verification operation of the 4BL BIAS programming method, three sensing operations are required, namely 3BL sensing, 4BL sensing and Pass sensing, to determine whether the threshold voltage of the verified memory cell reaches the 3BL interval, 4BL interval or Pass interval respectively. It should be noted that the 3BL sensing process corresponds to Fig. 9 The 3BL verification (VFY) shown in the figure; the 4BL sensing process corresponds to Fig. 9 4BL VFY shown in the figure; the Pass sensing process corresponds to Fig. 9The Pass VFY shown in . The 3BL interval can refer to Fig. 9 The area to the left of the 3BL VFY; the 4BL range can refer to Fig. 9 The overlapping area between the right side of 3BL VFY and the left side of 4BL VFY; the Pass interval can refer to Fig. 9 The overlapped area between the right side of 4BL VFY and the left side of Pass VFY shown in FIG. When the memory cells in different intervals perform programming operations again, the bias voltages applied to the bit lines are different, so as to more accurately program the memory cells to the target programming state. For example, when the memory cells in the 3BL interval perform programming operations, 0 volts (V) are applied to the corresponding bit lines; when the memory cells in the 4BL interval perform programming operations, the corresponding bit lines are applied with voltage VBL3; when the memory cells in the Pass interval perform programming operations, the corresponding bit lines are applied with voltage VBL4.

[0065] In some embodiments, the implementation of the verification operation of the 4BL BIAS programming method includes: 3BL sensing is performed separately, that is: first pre-charge the sensing node coupled to the memory cell to be verified to a higher voltage (for example, a preset initial voltage), and then discharge the sensing node. After a period of discharge, sense the potential of SO to determine whether the threshold voltage of the memory cell reaches the 3BL interval; then 4BL sensing and Pass sensing can be performed in a dual-strobe sensing manner, that is, pre-charge the corresponding sensing node to a higher voltage (for example, a preset initial voltage) at the same time, and perform 4BL sensing and Pass sensing at different time points during the discharge process of the sensing node, thereby shortening the verification time and improving the performance of the memory. The advantages of using dual-strobe sensing for 4BL sensing and Pass sensing are that, Fig.10 As shown, in one sensing, nodes 1 and 3 detect the SO potential respectively to perform 4BL sensing and Pass sensing respectively. Because it takes a long time to precharge the corresponding SO to the preset initial voltage, 4BL sensing and Pass sensing are performed at nodes 1 and 3 respectively during one SO precharge. Since only one precharge process is required, it takes less time than two independent precharges to perform 4BL sensing and Pass sensing at nodes 1 and 2 respectively. Therefore, the memory using dual-strobe sensing verification has better performance.

[0066] However, the verification operation of the above-mentioned 4BL BIAS programming method requires precharging the sensing node coupled to the memory cell to be verified to a higher voltage twice or three times to complete 3BL sensing, 4BL sensing and Pass sensing. It is not possible to precharge the sensing node only once at the same verification voltage and then sense at three different time points during the discharge process of the sensing node to complete 3BL sensing, 4BL sensing and Pass sensing.

[0067] Based on this, Fig.11 As shown, an embodiment of the present application provides an operating method of a memory, which can solve the above problems. The memory to which the operating method is applicable may include a page buffer, the page buffer including a first sensing circuit coupled to a sensing node and a dynamic storage circuit coupled to the first sensing circuit; the memory includes a storage unit configured to store one of a plurality of programming states. Specifically, the operating method may include:

[0068] S1101: storing first verification information in the first sensing circuit according to a first potential of the sensing node;

[0069] S1102: transmitting initial verification information in the dynamic storage circuit to the sensing node; the initial verification information includes verification information corresponding to a verified programming state among the multiple programming states;

[0070] S1103: transmitting the first verification information from the first sensing circuit to the dynamic storage circuit, and performing a clearing operation on the first sensing circuit;

[0071] S1104: storing second verification information or the initial verification information in the first sensing circuit according to the second potential of the sensing node;

[0072] The first potential of the sensing node corresponding to the first verification information is greater than the second potential of the sensing node corresponding to the second verification information.

[0073] It should be noted that the above-described memory structure only describes the structure related to the operation method provided by the present application. For other parts of the memory structure, please refer to the above Figures 1 to 6 The memory structure shown in FIG. Figures 1 to 6 The memory shown and the structure described are only exemplary and not limiting. That is to say, the operation method provided in the embodiment of the present application can be applied to any memory having the above technical problems.

[0074] For page buffers, such as Fig.12As shown, it shows a schematic diagram of the structure of the page buffer group included in the memory. Fig.12 In the embodiment, the page buffer includes a page buffer / sense amplifier 504 as described above, wherein each bit line in a memory is coupled to a page buffer, that is, in some embodiments, the memory may include a page buffer group 120. The page buffer group 120 may be coupled to the memory array 401 via a plurality of bit lines BL1 to BLK. The page buffer group 120 may include a page buffer 1 (PB1) to a page buffer K (PBK), each of which is coupled to the memory array 401 via a bit line, for example, the page buffers PB1 to PBK may be coupled to the memory array 401 via corresponding bit lines BL1 to BLK, respectively.

[0075] Here, the page buffer mentioned in the present application is any one of the aforementioned page buffer groups, and its function is such as the function of the page buffer / sense amplifier 604 described above. The page buffer may include a first sensing circuit coupled to a sensing node and a dynamic storage circuit coupled to the first sensing circuit. The first verification information may refer to the verification result obtained by 3BL sensing in the verification operation of the 4BL BIAS programming method. The second verification information may refer to the verification result obtained by 4BL sensing in the verification operation of the 4BLBIAS programming method.

[0076] In actual application, in a memory including a page buffer of the aforementioned structure, due to the structural limitation of the dynamic storage circuit, the 4BL BIAS programming method is used in this type of memory, and the 3BL sensing and 4BL sensing in the verification operation included therein cannot be completed in the same sensing (the same sensing can refer to the same precharging of the sensing node to a preset initial voltage, and the 3BL sensing and 4BL sensing are completed at different times during the discharge of the sensing node). In other words, due to the structural limitation of the dynamic storage circuit, the assistance of the sensing node and the first sensing circuit is required when caching data. Specifically, after the 3BL sensing in the verification operation of the 4BL BIAS programming method is completed, the first sensing circuit latches the first verification information; thereafter, if the 4BL sensing is performed again, since the first sensing circuit stores the first verification information and the potential on the sensing node contains the second verification information, that is, at this time, the sensing node and the first sensing circuit are both occupied, and the sensing node cannot help transfer the first verification information in the first sensing circuit to the dynamic storage circuit. Then, the second verification information on the sensing node cannot be correctly latched by the first sensing circuit, that is, the second verification information cannot be correctly stored. That is, the 3BL sensing and 4BL sensing in the verification operation of the 4BL BIAS programming method cannot be completed in the same sensing. In order to solve the above problem, the embodiment provided by the present application first transmits the initial verification information in the dynamic storage circuit to the sensing node; then, the first verification information is transmitted from the first sensing circuit to the dynamic storage circuit, and the first sensing circuit is cleared. Based on this, the second verification information can be latched again after the data in the first sensing circuit is cleared.

[0077] In some embodiments, the page buffer further includes a second sensing circuit coupled to the sensing node; and the operating method further includes:

[0078] storing third verification information in the second sensing circuit according to a third potential of the sensing node;

[0079] The second potential of the sensing node corresponding to the second verification information is greater than the third potential of the sensing node corresponding to the third verification information.

[0080] It should be noted that the third verification information mentioned here may refer to the verification result obtained through Pass sensing in the verification operation of the 4BL BIAS programming method.

[0081] That is, according to the operating method described above, in the verification operation of the 4BL BIAS programming method, after the first sensing circuit latches the first verification information, the initial verification information in the dynamic storage circuit is first transmitted to the sensing node; then, the first verification information is transmitted from the first sensing circuit to the dynamic storage circuit, and the first sensing circuit is cleared, and then the second verification information is latched into the first sensing circuit; thereafter, the third verification information is latched into the second sensing circuit, thereby realizing the verification operation of the 4BL BIAS programming method, which can pre-charge the sensing voltage only once at the same verification voltage, and then sense at three different time points during the discharge process to complete 3BL sensing, 4BL sensing and Pass sensing.

[0082] Here, the described initial verification information may include verification information corresponding to a verified programming state among the multiple programming states. The programming state included in the storage unit corresponding to the page buffer of the dynamic memory containing the initial verification information has been verified. In some embodiments, the initial verification information may include a verification result obtained via 4BL sensing corresponding to the verified programming state among the multiple programming states.

[0083] In some embodiments, the dynamic storage circuit corresponding to a first storage cell in a to-be-verified programming state among the multiple programming states or a second storage cell in a verified programming state that fails verification is in an initial state.

[0084] It should be noted that the first storage unit may include a storage unit corresponding to a programming state to be verified among the multiple programming states, for example, a storage unit corresponding to a Pn programming state among the multiple programming states. The second storage unit may include a storage unit that has failed verification in a verified programming state adjacent to the programming state to be verified among the multiple programming states, for example, a storage unit that has failed verification in a Pn-1 programming state among the multiple programming states. What is described here is that the dynamic storage circuit included in the page buffer corresponding to the first storage unit and the second storage unit is in an initial state and has not been operated, that is, the data stored in the dynamic storage circuit included in the buffer of the first storage unit and the second storage unit may be initial default data. The initial default data may be used to characterize that the dynamic storage circuit is in a reset state and can be operated. In some embodiments, the initial default data may be 1.

[0085] In some embodiments, the page buffer further includes at least one data latch circuit; before storing the first verification information in the first sensing circuit according to the first potential of the sensing node, the operating method further includes:

[0086] Obtaining selected operation information according to the data information in the at least one data latch circuit and the initial verification information in the dynamic storage circuit; the selected operation information is used to select a first storage unit in a programming state to be verified among the multiple programming states or a second storage unit in a verified programming state that fails verification;

[0087] storing the selected operation information in the second sensing circuit;

[0088] The sensing nodes corresponding to the first storage unit and the second storage unit are precharged to a preset initial voltage according to the selection operation information.

[0089] It should be noted that the at least one data latch circuit can be used to temporarily store data to be programmed into the memory array or temporarily store data read from the memory array. In some embodiments, each page buffer can include more than two data latch circuits.

[0090] For example, when the memory cell is a TLC type memory cell, the memory cell can store 3 bits of data, namely, lower page (LP, Low Page) data, middle page (MP, Middle Page) data and upper page (Up Page) data, and correspondingly, the page buffer can include three data latches, including: LP lower page latch, MP middle page latch and UP upper page latch. When the memory cell is a QLC memory cell, the memory cell can store 4 bits of data, namely: lower page LP data, middle page MP data, upper page UP data and extra page (Extra Page, XP) data, and correspondingly, the page buffer can include four data latches: LP lower page latch, MP middle page latch, UP upper page latch and XP extra page latch.

[0091] It should be noted that the above example is only an exemplary correspondence between the number of data latch circuits in a page buffer and the number of data bits stored in a memory cell. In actual applications, the number of data latch circuits may be less than the number of bits stored in a memory cell. For example, some data latch circuits may be designed as dynamic latch circuits.

[0092] What is described here is that before performing the sensing of the aforementioned first verification information, the second verification information and the third verification information, the sensing node coupled to the selected storage unit needs to be precharged. The selected storage unit described here may refer to the aforementioned first storage unit and the second storage unit. The process of precharging the sensing node coupled to the selected storage unit may include: first obtaining the selected operation information according to the data information in at least one data latch circuit and the initial verification information in the dynamic storage circuit to determine the selected storage unit, and then storing the selected operation information in the second sensing circuit so that the second sensing circuit precharges the sensing nodes corresponding to the first storage unit and the second storage unit to a preset initial voltage according to the selected operation information when working. Among them, the preset initial voltage can be determined according to the design. What is described here is that the data information may refer to the data programmed into the storage array after the data is set and encoded. Among them, for example, the set encoding may be Gray encoding. For understanding of this step, please refer to the following Fig.17 and Fig.18 The detailed description in will not be repeated here.

[0093] In some embodiments, step S1102 may include:

[0094] The sensing node corresponding to the third storage unit successfully verified in the verified programming state among the multiple programming states is charged according to the initial verification information, so as to transmit the initial verification information to the sensing node.

[0095] Here, the third storage unit may include a storage unit that has been successfully verified in a verified programming state adjacent to the programming state to be verified in the multiple programming states, for example, a storage unit that has been successfully verified in the Pn-1 programming state in the multiple programming states. The aforementioned process of transmitting the initial verification information in the dynamic storage circuit to the sensing node may be as follows: charging the sensing node corresponding to the third storage unit according to the initial verification information to transmit the initial verification information to the sensing node. Here, step S1102 may also be referred to as: reading the initial verification information to the sensing node.

[0096] The specific implementation of the above step 1102 is described below by taking the to-be-verified programming state as the Pn programming state and the verified programming state as the Pn-1 programming state as an example.

[0097] Specifically, Figures 13 to 16 As shown in Tables 1 to 3, Fig.13 A schematic diagram of states of a sensing node and a dynamic storage circuit in a page buffer corresponding to a first storage unit corresponding to a Pn programming state before transmitting initial verification information in the dynamic storage circuit to the sensing node according to some aspects of the present application; Fig.14A schematic diagram of states of a sensing node and a dynamic storage circuit in a page buffer corresponding to a third storage unit corresponding to a Pn-1 programming state before transmitting initial verification information in the dynamic storage circuit to the sensing node according to some aspects of the present application; Fig.15 A schematic diagram of states of a sensing node and a dynamic storage circuit in a page buffer corresponding to a first storage unit corresponding to a Pn programming state after initial verification information in the dynamic storage circuit is transmitted to the sensing node according to some aspects of the present application; Fig.16 A schematic diagram of states of a sensing node and a dynamic storage circuit in a page buffer corresponding to a second storage unit corresponding to a Pn-1 programming state after initial verification information in the dynamic storage circuit is transmitted to the sensing node according to some aspects of the present application. Table 1 shows the states of the page buffer corresponding to the first storage unit corresponding to the Pn programming state, the page buffer corresponding to the second storage unit corresponding to the Pn-1 programming state, and the sensing node, the dynamic storage circuit, and the first sensing circuit in the page buffer corresponding to the third storage unit corresponding to the Pn-1 programming state before the initial verification information in the dynamic storage circuit is transmitted to the sensing node; Table 2 shows the states of the page buffer corresponding to the first storage unit corresponding to the Pn programming state, the page buffer corresponding to the second storage unit corresponding to the Pn-1 programming state, and the sensing node, the dynamic storage circuit, and the first sensing circuit in the page buffer corresponding to the first storage unit corresponding to the Pn programming state, the page buffer corresponding to the second storage unit corresponding to the Pn-1 programming state, and the page buffer corresponding to the third storage unit corresponding to the Pn-1 programming state after the initial verification information in the dynamic storage circuit is transmitted to the sensing node; Table 3 shows the states of the page buffer corresponding to the first storage unit corresponding to the Pn programming state, the page buffer corresponding to the second storage unit corresponding to the Pn-1 programming state, and the sensing node, the dynamic storage circuit, and the first sensing circuit in the page buffer corresponding to the first storage unit corresponding to the Pn programming state, the page buffer corresponding to the second storage unit corresponding to the Pn-1 programming state, and the page buffer corresponding to the third storage unit corresponding to the Pn-1 programming state after the SO discharge (4BLsensing) is completed.

[0098] exist Fig.13 In the embodiment, the DS latch can be an exemplary structure of the aforementioned second sensing circuit; the DL latch can be an exemplary structure of the aforementioned first sensing circuit; and the DM transistor with its corresponding parasitic capacitance can be an exemplary structure of the aforementioned dynamic storage circuit.

[0099] Fig.13It is shown that before the initial verification information in the dynamic storage circuit included in the page buffer is transmitted to the sensing node, the SO corresponding to the first storage unit corresponding to the Pn programming state has completed 3BL sensing and latching of the 3BL verification data; and when the SO is discharged again (4BL sensing), the potential corresponding to the SO can be represented by SO = "sensing". In the embodiment of the present application, since the selected storage unit is the first storage unit in the Pn programming state and the second storage unit in the Pn-1 programming state that has not passed the 4BL verification during the selection operation, at this time, the second storage unit also performs the same verification operation as the first storage unit, that is, 3BL sensing and latching of the 3BL verification data are also performed; and the SO is discharged again (4BL sensing), at this time, the potential of the SO corresponding to the second storage unit can also be represented by SO = "sensing". For the potential of the SO corresponding to the second storage unit in the Pn-1 programming state before the initial verification information in the dynamic storage circuit included in the page buffer is transmitted to the sensing node, please refer to Fig.13 Understand. However, for the dynamic storage circuit corresponding to the first storage unit and the second storage unit, since the first storage unit has not performed data latching of 4BL sensing, its dynamic storage circuit is in an initial state, for example, DM = "1". Since the second storage unit is a storage unit that has not passed the 4BL verification, the dynamic storage circuit has performed data latching of 4BL sensing, so the data stored in its dynamic storage circuit is the verification result of 4BL sensing (failed to pass 4BL verification). At this time, the dynamic storage circuit corresponding to the second storage unit DM = "4BL'".

[0100] exist Fig.14 In the structure of the page buffer Fig.13 The structure of the middle page buffer is the same, which has been described in detail above and will not be repeated here.

[0101] Fig.14It is shown that before the initial verification information in the dynamic storage circuit in the page buffer is transmitted to the sensing node, the third storage unit corresponding to the Pn-1 programming state is an unselected storage unit, and its corresponding SO is not precharged to the preset initial voltage, and it will not perform at least one discharge operation. At this time, the potential of the SO corresponding to the third storage unit will not change, and it can be represented by SO = "0". In addition, the state of the dynamic sensing circuit corresponding to the third storage unit is DM = 4BL', where 4BL' is the verification result of the third storage unit through 4BL sensing (verified by 4BL). Here, although the dynamic storage circuit storage of the second storage unit and the third storage unit is 4BL', the specific states should be understood to be different, and the specific values ​​stored are different. In some embodiments, the dynamic storage circuit corresponding to the second storage unit DM = 4BL' = "1"; the dynamic storage circuit corresponding to the third storage unit DM = 4BL' = "0", and the two represent opposite states.

[0102] Specifically, Fig.13 and Fig.14 The described status is the same as the status described in Table 1.

[0103] Table 1

[0104] Pn-1 Pn DM (or dm) 4BL 1 SO 0 sensing DS (or ds) ~4BL / 0 1

[0105] exist Fig.15 In the structure of the page buffer Fig.13 , Fig.14 The structure of the page buffer is the same as that of the middle page buffer, which has been described in detail above and will not be repeated here. Fig.15 What is described is the potential of SO in the page buffer corresponding to the first storage unit corresponding to the Pn programming state after the initial verification information in the dynamic storage circuit is transmitted to the sensing node. Since the control signal en_4bl_b is not applied to the page buffer in the Pn programming state, the page buffer corresponding to the first storage unit corresponding to the Pn programming state does not perform the operation of transmitting the initial verification information in the dynamic storage circuit to the sensing node, and the potential of SO remains at the potential during 4BL sensing, so it can still be expressed as: SO = "sensing"; correspondingly, since the SO corresponding to the second storage unit is the same operation as the first storage unit, the potential of SO corresponding to the second storage unit can also be expressed as: SO = "sensing". According to the above understanding, the state of the dynamic storage circuit of the first storage unit and the second storage unit is still DM = "1".

[0106] Similarly, in Fig.16 In the structure of the page buffer Fig.13 , Fig.14 , Fig.15 The structure of the page buffer in the same manner has been described in detail above and will not be repeated here. Specifically, after the initial verification information in the dynamic storage circuit is transmitted to the sensing node, the potential of the sensing node of the page buffer corresponding to the third storage unit corresponding to the Pn-1 programming state is, because the control signal en_4bl_b is applied to the page buffer corresponding to the third storage unit, therefore, the potential of SO corresponding to the third storage unit corresponding to the Pn-1 programming state is pulled up, that is, the page buffer corresponding to the third storage unit performs the operation of transmitting the initial verification information in the dynamic storage circuit to the sensing node, and the potential of SO of the third storage unit can be expressed as SO = "4BL'"; correspondingly, the state of the dynamic storage circuit corresponding to the third storage unit is DM = "4BL'".

[0107] Specifically, Fig.15 and Fig.16 The described status is the same as the status described in Table 2.

[0108] Table 2

[0109] Pn-1 Pn DM (or dm) 4BL 1 SO 4BL sensing DS (or ds) ~4BL / 0 1

[0110] based on Figures 13 to 16From the description of the states of the devices related to the technical solution of the present application in the page buffer shown, it can be known that before the initial verification information in the dynamic storage circuit is transmitted to the sensing node, since the first storage unit and the second storage unit are the storage units to be verified, the sensing nodes corresponding to the first storage unit and the second storage unit will be precharged to a preset initial voltage, and then discharged to perform 3BL sensing and 4BL sensing, so that the potential of the sensing node of the page buffer corresponding to the first storage unit corresponding to the Pn programming state and the sensing node of the page buffer corresponding to the second storage unit corresponding to the Pn-1 programming state can be expressed as SO = "sensing". The third storage unit is a storage unit that has been verified and successfully verified, so its corresponding sensing node is not precharged to the preset initial voltage, that is, before the initial verification information in the dynamic storage circuit is transmitted to the sensing node, the potential of the sensing node corresponding to the third storage unit can be expressed as SO = "0". After the initial verification information in the dynamic storage circuit is transmitted to the sensing node, since the current verified Pn programming state does not have 4BL data; and the 4BL data corresponding to the Pn-1 programming state that has not passed 4BL is data that has not been verified, the page buffer corresponding to the first storage unit corresponding to the Pn programming state and the second storage unit corresponding to the Pn-1 programming state that has not passed 4BL will not be applied with the control signal en_4bl_b, so it will not perform the operation of transmitting (or reading) the initial verification information in the dynamic storage circuit to the corresponding SO, so SO will not be charged (precharge), that is, the sensing on SO is not affected. The page buffer corresponding to the third storage unit is applied with the control signal en_4bl_b and the initial verification information (that is, the verification result of the 4BL sensing of successful programming verification) is stored in its dynamic storage circuit, so the page buffer corresponding to the third storage unit performs the operation of reading the initial verification information to the corresponding SO, thereby reading the initial verification information to SO.

[0111] Here, Table 3 shows the states of the sensing nodes, the dynamic storage circuit, and the second sensing circuit of the first storage unit, the second storage unit, and the third storage unit after the first verification information is stored.

[0112] Table 3

[0113] Pn-1 Pn DM (or dm) 3BL 3BL SO 0 sensing DS (or ds) ~4BL / 0 1

[0114] In some embodiments, the step S1103 of transmitting the first verification information from the first sensing circuit to the dynamic storage circuit may include:

[0115] A transmission channel between the first sensing circuit and the dynamic storage circuit is opened, so that the first verification information in the first sensing circuit is transmitted to the dynamic storage circuit.

[0116] It should be noted that data can be transmitted between the first sensing circuit and the dynamic storage circuit, and there is a storage channel between the two. Therefore, in order to store the first verification information from the first sensing circuit to the corresponding storage circuit, it is necessary to first open the transmission channel between the two, so that the first verification information in the first sensing circuit is transmitted to the corresponding dynamic storage circuit.

[0117] In some embodiments, the clearing operation on the first sensing circuit in step 1103 may include:

[0118] The first sensing circuit is reset to restore the first sensing circuit to an initial state.

[0119] It should be noted that in order to store the second verification information, the first sensing circuit needs to be cleared before storage, that is, the first sensing circuit is reset to restore the first sensing circuit to an initial state, for example, restoring the first sensing circuit dl="1".

[0120] In some embodiments, the operating method further includes:

[0121] Discharging the sensing node from the preset initial voltage, pausing the discharging of the sensing node after a first preset time, sensing the first potential of the sensing node, and storing the first verification information in the first sensing circuit;

[0122] causing the sensing node to discharge from the first potential, pausing the discharge of the sensing node after a second preset time, sensing the second potential of the sensing node after the first sensing circuit is cleared, and storing the second verification information in the first sensing circuit;

[0123] The sensing node is made to discharge from the second potential, and after a third preset time, the discharging of the sensing node is suspended, the third potential of the sensing node is sensed, and the third verification information is stored in the second sensing circuit.

[0124] In some embodiments, the operating method further includes:

[0125] If the first potential is greater than or equal to a first preset voltage, the first verification information is used to indicate a first group of storage cells in the first storage unit and the second storage unit that have passed the verification of the first verification voltage;

[0126] If the second potential is greater than or equal to a second preset voltage, the second verification information is used to indicate a second group of storage cells in the first storage cell and the second storage cell that have passed the verification of the second verification voltage;

[0127] If the third potential is greater than or equal to a third preset voltage, the third verification information is used to indicate a third group of storage units in the first storage unit and the second storage unit that have passed the verification of the third verification voltage;

[0128] Among them, the first verification voltage is lower than the second verification voltage; the second verification voltage is lower than the third verification voltage.

[0129] It should be noted that what is described here is that after the sensing node is pre-charged to a preset initial voltage, it is discharged three times to implement the verification operation of the 4BL BIAS programming method. The bit line can be pre-charged only once at the same verification voltage, and then it is sensed at three different time points during the discharge process to complete 3BL sensing, 4BL sensing and Passsensing.

[0130] Specifically, the sensing nodes corresponding to the aforementioned first storage unit and the second storage unit are precharged to a preset initial voltage, and after a discharge of a first preset time, the first potential of the sensing node is lower than the predetermined initial voltage, the first potential of the corresponding sensing node is sensed, and the first verification information is stored, wherein the acquisition of the first verification information may include: comparing the first potential with the first preset voltage to obtain the first verification information, and latching the first verification information. Afterwards, the sensing node is discharged for a second preset time based on the first potential, and then senses the second potential of the sensing node, and obtains the second verification information based on the comparison of the second potential with the second preset voltage, and finally stores the second verification information; similarly, the sensing node is discharged for a third preset time based on the second potential, and then senses the third potential of the sensing node, and obtains the third verification information based on the comparison of the third potential with the third preset voltage, and finally stores the third verification information. Among them, the first preset time, the second preset time and the third preset time may be different. In some embodiments, the first preset time is less than the second preset time; the second preset time is less than the third preset time.

[0131] The embodiment of the present application charges the sensing node at the initial moment, and only requires one charging operation to complete at least three verification operations in sequence, thereby reducing the number of times the sensing node is charged during the sensing process and saving verification time.

[0132] In this embodiment, taking the ISPP programming scheme of a 3D NAND flash memory storage device as an example, in different programming stages of an ISPP programming process, in order to optimize the threshold voltage distribution and distribute the threshold voltage of the storage cell more concentratedly in the threshold voltage region of the corresponding data state, different bit line voltages are biased on the bit lines of the storage cells of different bit lines, that is, a bit line forcing operation is implemented. In this way, even if the programming voltages Vpgm of the gates of the storage cells of different bit lines (applied through the word lines) are the same, the programming effects will be different, and the threshold voltage differences of the storage cells with large current threshold voltage differences will be reduced after being programmed and will be relatively close to the ideal threshold voltage region of the corresponding data.

[0133] In some embodiments, the operation method may further include:

[0134] applying different bit line voltages to a bit line coupled to the first memory cell based on the first verification information, the second verification information, and the third verification information;

[0135] Among them, a first bit line voltage is applied to a first bit line connected to a first forcing unit; a second bit line voltage is applied to a second bit line connected to a second forcing unit; a programming inhibit bit line voltage is applied to a third bit line connected to the third group of memory cells; the first forcing unit is a memory cell in the first group of memory cells except the second group of memory cells and the third group of memory cells; the second forcing unit is a memory cell in the second group of memory cells except the third group of memory cells.

[0136] It should be noted that in the embodiment of the present application, based on the first verification information, the second verification information and the third verification information, it is possible to implement a programming method in which two bit line forced operations are used for different memory cells in a single programming process. In this way, the memory cells can be prevented from being over-programmed, thereby reducing the width of the threshold voltage distribution of multiple memory cells and improving the accuracy of the programming operation.

[0137] Specifically, the control logic circuit of the memory is configured to: according to the first verification information, the second verification information and the third verification information, apply the first bit line voltage to the first bit line connected to the first forcing unit, apply the second bit line voltage to the second bit line connected to the second forcing unit, apply the programming prohibition bit line voltage to the third bit line connected to the third group of storage cells, and apply the programming voltage to the selected word line; wherein the first bit line voltage is greater than the ground voltage and less than the programming prohibition bit line voltage, and the second bit line voltage is greater than the first bit line voltage. Here, the first forcing unit is the storage unit in the first group of storage cells except the second group of storage cells and the third group of storage cells; the second forcing unit is the storage unit in the second group of storage cells except the third group of storage cells; wherein the first group of storage cells may refer to the first group of storage cells, and the first group of storage cells includes the storage cells in the first storage cells and the second storage cells that have passed the verification of the first verification voltage; the second group of storage cells may refer to the second group of storage cells, and the second group of storage cells includes the storage cells in the first storage cells and the second storage cells that have passed the second verification voltage; the third group of storage cells may be the storage cells in the first storage cells and the second storage cells that have passed the third verification voltage.

[0138] In some embodiments, the control logic circuit is further configured to: apply a normal programming bit line voltage Vprog (e.g., a ground voltage Vgnd) to a memory cell that performs a normal programming operation according to the first verification information, the second verification information, and the third verification information. Here, the inhibit programming bit line voltage Vinh may be a power supply voltage Vdd, the first bit line voltage is greater than the ground voltage (the normal programming bit line voltage Vprog) and less than the inhibit programming bit line voltage Vinh, and the second bit line voltage is greater than the first bit line voltage and less than the inhibit programming bit line voltage Vinh.

[0139] In the programming process of ISPP, for example, when applying the same programming voltage Vpgm to the memory cells of a selected row for programming operation, the sensing circuit can use the first verification information DL, the second verification information DM and the third verification information DS to apply the corresponding bit line voltage to the corresponding memory cells, so that the memory cells can be distinguished to perform the bit line forced operation. In other words, in the embodiment of the present application, different memory cells are classified for programming control, and the memory cells can be divided into normal programming cells, first forced cells to perform the first bit line forced operation, second forced cells to perform the second bit line forced operation and third memory cells to perform the forbidden programming operation, and different bit line voltages are used to classify the programming control of these four types of memory cells. In the programming operation, in addition to using two bit line voltages, the programming inhibit bit line voltage Vinh (e.g., Vdd) and the normal programming bit line voltage Vprog (e.g., ground voltage Vgnd), if only one forced bit line voltage (which is greater than the normal programming bit line voltage Vprog and less than the programming inhibit bit line voltage Vinh) is added to perform programming operations on multiple forced cells, although a programming operation with a certain degree of differentiation in programming degrees can be achieved, the threshold voltage distribution of multiple memory cells after being programmed may not be narrow enough. Therefore, in the programming operation of this embodiment, in addition to using two bit line voltages, the programming inhibit bit line voltage Vinh (e.g., VDD) and the normal programming bit line voltage Vprog (e.g., ground voltage Vgnd), the first bit line voltage and the second bit line voltage (which are both greater than the normal programming bit line voltage Vprog and less than the programming inhibit bit line voltage Vinh) are also used, so as to perform a programming operation with a finer degree of differentiation in programming degrees on multiple memory cells.

[0140] In some embodiments, the operating method further includes:

[0141] After applying different bit line voltages to the bit line coupled to the first memory cell, determining whether the programming state to be verified is the last programming state among the plurality of programming states;

[0142] If it is determined that the programming state to be verified is not the last programming state, a swap operation is performed on the first sensing circuit and the dynamic storage circuit so that the second verification information is stored in the dynamic storage circuit and the first verification information is stored in the first sensing circuit.

[0143] It should be noted that, as described above, the memory provided in the embodiment of the present application includes multiple programming states. After applying different bit line voltages to the first storage unit according to the first verification information, the second verification information and the third verification information corresponding to the programming state to be verified, the verification of the programming state to be verified has been completed, and the next programming is guided according to the information obtained by the verification. It is necessary to determine whether the programming state to be verified is the last programming state. If it is not the last programming state, the first sensing circuit and the dynamic storage circuit need to perform an exchange operation so that the second verification information is stored in the dynamic storage circuit and the first verification information is stored in the first sensing circuit. That is, the data of the first sensing circuit and the dynamic storage circuit are bidirectionally transmitted to realize data exchange, thereby preparing for the verification of the next programming state. If the programming state to be verified is the last programming state, the verification is terminated.

[0144] In some embodiments, the programming of the memory includes at least one round of programming loop; the programming loop includes: a programming operation and a verification operation; the operation method may also include:

[0145] Before the verification operation, a clearing operation is performed on the first sensing circuit and the dynamic storage circuit.

[0146] It should be noted that, as mentioned above, the verification operation performed between two programming operations includes verification of each of the multiple programming states, and therefore, the "before verification operation" mentioned here may refer to before the verification operation of the first programming state among the multiple programming states contained in the memory. The operation here means that before the verification operation, the first sensing circuit and the dynamic storage circuit are cleared, or, before the current verification operation, the data stored in the first sensing circuit and the dynamic storage circuit in the previous verification operation or programming operation are cleared, that is, the first sensing circuit and the dynamic storage circuit are reset and restored to the initial state for later use.

[0147] To understand the operation method provided by the embodiments of the present application, see Figure 17 to Figure 18 As shown, Fig.17 A schematic diagram showing a circuit structure of a page buffer is shown; Fig.18 A schematic flow chart of a verification operation of a complete BLBIAS programming mode using the operation method provided in an embodiment of the present application is shown.

[0148] It should be noted that in Fig.17 The page buffer shown at least includes: a precharge circuit, a discharge circuit, a first sensing circuit d1, a second sensing circuit ds, a dynamic sensing circuit dm and a data latch circuit (d1, d2, d3, dc), wherein;

[0149] The precharge circuit is coupled to the corresponding bit line through a sensing node SO, and is configured to access a power supply voltage (such as VDD), and provide a preset initial voltage for the SO when the SO is precharged, and includes: a transmission gate composed of a transistor P1 and a transistor P2 connected in parallel and a transistor P3, and each transistor precharges the SO to a preset initial voltage in response to a signal generated by the third verification information stored in the second sensing circuit, a Prech_all signal, and a Prech_sel signal; the discharge circuit includes series-connected transistors T3 and T4, and is configured to discharge the SO in response to a discharge signal sodisch and a signal generated by the third verification information stored in the second sensing circuit. In addition, the page buffer also includes: a first transistor T1 and a second transistor T2 connected in series, and one end of the first transistor is connected to the positive end of the power supply (such as VDD); one end of the second transistor is connected to the sensing node, and the second transistor is controlled by a first transmission signal; and the first transistor is controlled by initial verification information. Under the action of the first transmission signal and the initial verification information, the first transistor and the second transistor are turned on to charge the sensing node corresponding to the third storage unit that has been successfully verified in the verified programming state among multiple programming states, so as to transmit the initial verification information to the sensing node.

[0150] Combination Fig.17 The page buffer is described, and without loss of generality it is assumed that a (verification) verify sequence includes programming states Pn-1, Pn, Pn+1. Since the selected programming state is based on the 0 data in D1 / D2 / D3 / DC (d1, d2, d3 and dc), selecting a programming state may select a state lower than the programming state. Therefore, it is assumed that the selection of the Pn state may simultaneously select Pn-1. Taking this as an example, the steps of the programming verification method of the memory provided in an embodiment of the present application are introduced, wherein the 3BL data (that is, the first verification information) represents reaching 3BL with 0, and the 4BL data (and the second verification information) represents reaching 4BL with 0. See. Fig.18 The process shown, specifically, includes:

[0151] ①, start verification; this step is combined with Fig.17 The circuit is described as follows: when entering verify from program pulse, the 3BL data in DL is cleared (DL=1), and the 4BL data in DM is cleared (DM=1), thereby entering the verification operation.

[0152] ②, select the Pn programming state; here, how to select has been described in detail above, and the selected storage cells to be verified also include the storage cells that have not passed the programming verification in the Pn-1 programming state, that is, the selected storage cells include the first storage cell and the second storage cell mentioned above. This step is combined with Fig.17The circuit description is as follows: Pn-1 state verify is similar to Pn state. Assume that after Pn-1 verify is completed, enter verify Pn state, select programming state operation DS=DM&P*, where P* selects Pn programming state according to the data in D1 / D2 / D3 / DC. DM contains 4BL data of Pn-1 programming state. Therefore, all Pn state cells and cells in Pn-1 state that have not passed 4BL will be selected in the selection operation.

[0153] ③, 3BL sensing; Here, before 3BL sensing, the SO corresponding to the first storage unit and the second storage unit is precharged, and the SO is precharged to a preset initial voltage. During 3BL sensing, the first verification information is latched into the first sensing circuit DL. This step is combined with Fig.17 The circuit in is described as follows: Use the data of DS (that is, the selected operation information mentioned above) to precharge SO, then SO continues to develop and discharge, after the development time of t_sodev_3bl, close soblk and sodisch to stop development, then open rst_l to sense the 3BL data into DL (DL=DL&~SO). The symbol & represents logical AND, and the symbol ~ represents logical NOT.

[0154] ④, read 4BL; here, reading 4BL means transmitting the initial verification information in the dynamic storage circuit corresponding to the third storage unit to the corresponding sensing node. The specific process has been described in detail above and will not be repeated here. This step is combined with Fig.17 The circuit in is described as follows: turn on soblk and sodisch, after the development time of t_sodev_4bl, turn off soblk and sodisch to stop development, then turn on en_4bl_b to read the 4BL' data of Pn-1 state to SO (SO=SO|~DM); in this step, since the current verified Pn state has no 4BL data, the SO of Pn state will not be precharged, and SOsensing will not be affected. Among them, the symbol | is a logical OR, and the expressions on both sides of the symbol will be calculated, and then the true or false judgment will be made.

[0155] ⑤, transmit / clear DL; that is, DM=DL; DL=“1”. Here, it corresponds to the aforementioned clearing operation of the first sensing circuit, and the specific operation has been described in detail above and will not be repeated here.

[0156] ⑥, 4BL sensing; that is, DL=~SO. Here, based on 3BL sensing, SO continues to be discharged for a period of time (such as a second preset time length), and then the second verification information is latched into the first sensing circuit DL.

[0157] The two steps are combined Fig.17 The circuit in is described as follows: Open Pass_l to transfer 3BL to DM; clear DL data to prepare for 4BL sensing (DL=1); open rst_l to sense 4BL data into DL (DL=~SO). The symbol = indicates assignment.

[0158] ⑦, Pass sensing; here, based on 4BL sensing, SO continues to discharge for a period of time (such as a third preset time), and then latches the third verification information into the second sensing circuit DS. This step is combined with Fig.17 The circuit description is as follows: turn on soblk and sodisch, and after the development time of t_sodev_Pass, turn off soblk and sodisch to stop development; clear the DS data to prepare for Pass sensing (DS=1); turn on rst_s to sense the Pass data into DS (DS=~SO); during the development process, because sodisch is turned on, the 4BL' data on SO will be cleared by DS.

[0159] ⑧, the Pass storage unit is prohibited from programming; here, that is, according to the first verification information, the second verification information and the third verification information, the bit line voltage of the bit line coupled to the first storage unit is different, wherein the storage unit that has passed the verification is prohibited from programming (the programming prohibition bit line voltage is applied to the third bit line connected to the third group of storage units). This step is combined with Fig.17 The circuit in is described as follows: Use the Pass data in DS to inhibit the data of D1 / D2 / D3 / DC in the Pn state, that is, write it as 1. That is: D*=`DS&P*.

[0160] ⑨, determine whether it is the last programming state;

[0161] ⑩, if not, exchange the second verification information in DL with the first verification information in DM. This step combines Fig.17 The circuit description is as follows: the data in DL / DM is exchanged, and after the exchange, DL contains 3BL data and DM contains 4BL data. After that, the Pn+1 state verify operation is entered, which is similar to the above.

[0162] If yes, the verification ends. Pn+1 is the last verify programming state, so after the end, it directly enters the verify recovery and ends the verify sequence.

[0163] The embodiment of the present application provides a method for operating a memory, by transmitting the initial verification information in the dynamic storage circuit to the sensing node, and transmitting the first verification information from the first sensing circuit to the dynamic storage circuit, and performing a clearing operation on the first sensing circuit, so that the first sensing circuit can sense the first verification information and the second verification information at different times, so that only one complete sensing under the same verification voltage can complete the programming verification operation of the 4BL (bit line) scheme of the storage unit of the memory. That is: in the page buffer structure based on the dynamic latch circuit (dynamic latch), triple storage (triple-strobe) is used in the verify of 4BL programming, that is, SO data is detected at three time points of a complete SO sensing discharge, and 3BL / 4BL / Pass data (first verification information, second verification information and third verification information) are obtained respectively. This scheme can effectively reduce the programming time and improve the programming performance.

[0164] Based on the same inventive concept, the embodiment of the present application also provides another method for operating a memory, which is described from the perspective of timing to illustrate how the operation method provided by the present application implements the verification operation of the 4BL BIAS programming method, which can precharge the bit line only once at the same verification voltage, and then sense it at three different time points during the discharge process to complete 3BL sensing, 4BL sensing, and Pass sensing. It should be noted that the memory to which the operation method is applicable also includes a page buffer, and the page buffer includes a first sensing circuit coupled to a sensing node and a dynamic storage circuit coupled to the first sensing circuit; the memory includes a storage cell configured to store one of a plurality of programming states.

[0165] Specifically, Fig.19 As shown, the operation method may include:

[0166] S1901: In a first sensing phase of a verification operation of the memory, latching first verification information into the first sensing circuit;

[0167] S1902: transmitting initial verification information in the dynamic storage circuit to the sensing node; the initial verification information includes verification information corresponding to a verified programming state among a plurality of programming states contained in the memory;

[0168] S1903: Opening a transmission channel between the first sensing circuit and the dynamic storage circuit, transmitting the first verification information to the dynamic storage circuit; and performing a clearing operation on the first sensing circuit;

[0169] S1904: In the second sensing phase of the verification operation, latching second verification information into the first sensing circuit;

[0170] The first potential of the sensing node corresponding to the first verification information is greater than the second potential of the sensing node corresponding to the second verification information.

[0171] In some embodiments, the page buffer further includes: a second sensing circuit coupled to the sensing node; and the operating method further includes:

[0172] In the third sensing phase of the verification operation, third verification information is latched into the second sensing circuit, wherein the second potential of the sensing node corresponding to the second verification information is greater than the third potential of the sensing node corresponding to the third verification information.

[0173] In some embodiments, the page buffer further comprises at least one data latch circuit; before the first sensing phase of the verification operation of the memory, the operation method further comprises: a pre-charging phase and a first discharging phase, wherein;

[0174] In the pre-charging stage, latching the selected operation information into the second sensing circuit; pre-charging the sensing node to a preset initial voltage based on the selected operation information;

[0175] In the first discharge phase, the sensing node is discharged from the preset initial voltage, and after a first preset time, the discharge of the sensing node is suspended;

[0176] Among them, the selected operation information is obtained based on the data information in the at least one data latch circuit and the initial verification information in the dynamic storage circuit, and is used to select the first storage unit in the multiple programming states that is in the programming state to be verified or the second storage unit that fails verification in the verified programming state.

[0177] In some embodiments, latching the first verification information to the first sensing circuit includes:

[0178] After the sensing node stops discharging, the first sensing circuit is enabled to latch the first verification information into the first sensing circuit in response to a first latch signal.

[0179] In some embodiments, before the second sensing phase of the verification operation of the memory, the operation method further includes: a second discharge phase; wherein, in the second discharge phase, the sensing node is discharged from the first potential, and after a second preset time, the discharge of the sensing node is suspended;

[0180] After the second sensing phase of the verification operation of the memory, the operation method further includes: a third discharge phase; wherein, in the third discharge phase, the sensing node is discharged from the second potential, and after a third preset time, the discharge of the sensing node is suspended.

[0181] In some embodiments, the operating method further includes:

[0182] After the second discharge phase, causing the first sensing circuit to respond to a second latch signal to latch the second verification information into the first sensing circuit;

[0183] After the third discharge phase, the second sensing circuit is enabled to latch third verification information into the second sensing circuit in response to a third latch signal.

[0184] In some embodiments, after the third sensing phase of the verification operation, the operation method further includes:

[0185] applying different bit line voltages to a bit line coupled to the first memory cell in a programming state to be verified among the plurality of programming states according to the first verification information, the second verification information, and the third verification information;

[0186] Among them, a first bit line voltage is applied to a first bit line connected to a first forcing unit; a second bit line voltage is applied to a second bit line connected to a second forcing unit; a programming inhibit bit line voltage is applied to a third bit line connected to a third group of memory cells; the first forcing unit is a memory cell in the first group of memory cells except for the second group of memory cells and the third group of memory cells; the second forcing unit is a memory cell in the second group of memory cells except for the third group of memory cells.

[0187] In some embodiments,

[0188] The first group of memory cells includes memory cells in the first memory cells that have passed verification of a first verification voltage;

[0189] The second group of memory cells includes memory cells in the first memory cells that have passed verification of a second verification voltage;

[0190] The third group of memory cells includes memory cells in the first memory cells that have passed verification of a third verification voltage;

[0191] If the first potential is greater than or equal to a first preset voltage, the first verification information is used to indicate a first group of storage units in the first storage unit and the second storage unit that have passed the verification of the first verification voltage;

[0192] If the second potential is greater than or equal to a second preset voltage, the second verification information is used to indicate a second group of storage cells in the first storage cell and the second storage cell that have passed the verification of the second verification voltage;

[0193] If the third potential is greater than or equal to a third preset voltage, the third verification information is used to indicate a third group of storage units in the first storage unit and the second storage unit that have passed the verification of the third verification voltage;

[0194] The first verification voltage is lower than the second verification voltage; and the second verification voltage is lower than the third verification voltage.

[0195] In some embodiments, after the third sensing phase of the verification operation, the operation method further includes:

[0196] After applying different bit line voltages to the bit line coupled to the first memory cell, determining whether the programming state to be verified is the last programming state among the plurality of programming states;

[0197] If it is determined that the programming state to be verified is not the last programming state, a swap operation is performed on the first sensing circuit and the dynamic storage circuit so that the second verification information is stored in the dynamic storage circuit and the first verification information is stored in the first sensing circuit.

[0198] In some embodiments, programming of the memory includes at least one programming loop; the programming loop includes: a programming operation and a verification operation; before the verification operation, the operating method further includes: performing a clearing operation on the first sensing circuit and the dynamic storage circuit.

[0199] In some embodiments, the page buffer further includes a first transistor and a second transistor connected in series; wherein one end of the first transistor is connected to a positive power supply terminal; one end of the second transistor is connected to the sensing node; and the initial verification information in the dynamic storage circuit is transmitted to the sensing node, comprising:

[0200] causing the second transistor to be controlled by a first transmission signal; and causing the first transistor to be controlled by the initial verification information;

[0201] Under the action of the first transmission signal and the initial verification information, the first transistor and the second transistor are turned on, and the sensing node corresponding to the third storage unit that has been successfully verified in the verified programming state among the multiple programming states is charged to transmit the initial verification information to the sensing node.

[0202] It should be noted that the operating method of the memory described above from a timing perspective is conceptually the same as the operating method of the memory described above, and the implementation methods of the technical features and the interpretation methods of the terms appearing therein have been clearly described above and will not be repeated here.

[0203] In order to understand the above operation method described from the timing perspective, Fig. 20 As shown, it shows that the verification operation of the 4BL BIAS programming method implemented by the operation method provided in the embodiment of the present application can pre-charge the bit line only once at the same verification voltage, and then sense it at three different time points during the discharge process to complete 3BL sensing, 4BL sensing and Pass sensing.

[0204] like Fig. 20 As shown, the verification operation of the aforementioned 4BL BIAS programming scheme includes three stages: 3BL sensing, 4BL sensing, and Pass sensing. Therefore, the operation method described from a timing perspective is also explained around these three stages, among which the first sensing stage is also 3BL sensing; the second sensing node is also 4BL sensing; and the third sensing stage is also Pass sensing.

[0205] Therefore, in terms of the sequence of timing, the specific process of the operation method can be as follows: before the first sensing stage, a pre-charging stage and a first discharging stage are first performed. Specifically, in the pre-charging stage, in response to the control of the pre-charging signal prech_sel, the corresponding SO is pre-charged to a preset initial voltage; in the first discharging stage, in response to the discharge signals vsoblk and vsodosch, the SO is discharged from the preset initial voltage for a period of time (for example, a first preset time length), and the discharge of the SO is suspended; thereafter, the first sensing stage is entered; in this stage, in response to the control of the first latch signal rst_l, the first verification information is latched into the first sensing circuit (3bl strobe); then, while continuing to discharge the SO for a period of time (for example, a second preset time), the discharge of the SO is suspended; then, in response to the first transmission signal en_4bl_b, the initial verification information is read to the corresponding SO; in response to the second transmission signal pass_l, the first verification information is transmitted to the dynamic storage circuit, and in response to the clearing signals rst_sa_latch and set_l, the first verification information in the first sensing circuit is cleared; then, the second sensing phase is entered, in this phase, in response to the second latching signal rst_l' (generated at a timing different from the first latching signal), the second verification information is latched to the first sensing circuit (4bl strobe); then, while continuing to discharge the SO for a period of time (for example, a third preset time), the discharge of the SO is suspended; then, the third sensing phase is entered; in this phase, in response to the third latching signal rst_s, the third verification information is latched to the second sensing circuit (fine strobe), so far, in the case of precharging the SO once, the verification operation of the 4BL BIAS programming scheme including 3BL sensing, 4BL sensing and Pass sensing.

[0206] Based on the same inventive concept, Fig.21 As shown, the embodiment of the present application provides a memory 210, including:

[0207] Storage array 2101; the storage cells included in the storage array are configured to store one of a plurality of programming states;

[0208] A page buffer group 2102 coupled to the memory array, wherein the page buffer group 2102 includes a plurality of page buffers; each page buffer includes: a first sensing circuit coupled to a sensing node and a dynamic storage circuit coupled to the first sensing circuit;

[0209] and a control logic circuit 2103 coupled to the storage array and the plurality of page buffers; wherein,

[0210] The control logic circuit is configured to: store first verification information in the first sensing circuit according to the first potential of the sensing node; transmit initial verification information in the dynamic storage circuit to the sensing node; the initial verification information includes verification information corresponding to a verified programming state among the multiple programming states; transmit the first verification information from the first sensing circuit to the dynamic storage circuit, and perform a clear operation on the first sensing circuit; store second verification information or the initial verification information in the first sensing circuit according to the second potential of the sensing node; wherein the first potential of the sensing node corresponding to the first verification information is greater than the second potential of the sensing node corresponding to the second verification information.

[0211] In some embodiments, the page buffer further includes: a second sensing circuit coupled to the sensing node;

[0212] The control logic circuit is further configured to: store third verification information to the second sensing circuit according to the third potential of the sensing node; wherein the second potential of the sensing node corresponding to the second verification information is greater than the third potential of the sensing node corresponding to the third verification information.

[0213] In some embodiments, the page buffer also includes at least one data latch circuit; the control logic circuit is further configured to: obtain selected operation information based on data information in the at least one data latch circuit and the initial verification information in the dynamic storage circuit; the selected operation information is used to select a first storage unit in a programming state to be verified among the multiple programming states or a second storage unit in a verified programming state that fails verification; store the selected operation information in the second sensing circuit; and precharge the sensing nodes corresponding to the first storage unit and the second storage unit to a preset initial voltage based on the selected operation information.

[0214] In some embodiments, the page buffer further includes a first transistor and a second transistor connected in series;

[0215] Among them, the other end of the first transistor is connected to the positive end of the power supply; the other end of the second transistor is connected to the sensing node; the first transistor is controlled by the initial verification information; the second transistor is controlled by the first transmission signal; under the action of the first transmission signal and the initial verification information, the first transistor and the second transistor are turned on to charge the sensing node corresponding to the third storage unit that has been successfully verified in the verified programming state among the multiple programming states, so as to transmit the initial verification information to the sensing node.

[0216] In some embodiments, the page buffer further includes: a transmission switch; the transmission switch is configured to: transmit the first verification information from the first sensing circuit to the dynamic storage circuit in response to a second transmission signal sent by the control logic circuit.

[0217] In some embodiments, the page buffer further comprises a precharge circuit; the control logic circuit is further configured to: obtain selected operation information according to the data information in the at least one data latch circuit and the initial verification information stored in the dynamic storage circuit; latch the selected operation information to the second sensing circuit; generate a precharge signal;

[0218] The precharge circuit is configured to: in response to the precharge signal, precharge the sensing nodes corresponding to the first storage unit and the second storage unit to the preset initial voltage based on the selected operation information.

[0219] In some embodiments, the page buffer further comprises: a discharge circuit;

[0220] The control logic circuit is further configured to: generate a first discharge signal, a second discharge signal and a third discharge signal;

[0221] The discharge circuit is configured to: in response to the first discharge signal, discharge the sensing node from the preset initial voltage, and suspend the discharge of the sensing node after a first preset time period;

[0222] In response to the second discharge signal, the sensing node starts to discharge from the first potential, and after a second preset time, the discharge of the sensing node is suspended;

[0223] In response to the third discharge signal, the sensing node is discharged from the second potential, and the discharge of the sensing node is suspended after a third preset time period.

[0224] Here, the first discharge signal, the second discharge signal, and the third discharge signal are used for discharge corresponding to the first discharge stage SO, the second discharge stage SO, and the third discharge stage SO, respectively.

[0225] In some embodiments, the first sensing circuit includes a first latch for storing first verification information; the second sensing circuit includes a second latch for storing third verification information; and the dynamic storage circuit includes a dynamic latch for storing second verification information.

[0226] In some embodiments, the control logic circuit is further configured to: after applying different bit line voltages to the bit line coupled to the first storage unit based on the first verification information, the second verification information and the third verification information, determine whether the programming state to be verified is the last programming state among the multiple programming states; if it is determined that the programming state to be verified is not the last programming state, control the first sensing circuit and the dynamic storage circuit to perform an exchange operation so that the second verification information is stored in the dynamic storage circuit and the first verification information is stored in the first sensing circuit.

[0227] In some embodiments, after transmitting the first verification information from the first sensing circuit to the dynamic storage circuit, the first sensing circuit is further configured to: in response to a clear signal sent by the control logic circuit, reset the first sensing circuit to restore the first sensing circuit to an initial state.

[0228] It should be noted that the memory provided in the embodiment of the present application is a hardware structure implemented by the operating method provided in the aforementioned embodiment of the present application. The operating steps provided in the embodiment of the present application involved here have been described in detail in the aforementioned description. Therefore, the nouns appearing in the operating steps in the memory described here can be understood by referring to the aforementioned description of the operating method and will not be repeated here.

[0229] Based on the same inventive concept, an embodiment of the present application further provides a memory system, comprising: one or more of the aforementioned memories and a memory controller coupled to the memories and used to control the memories.

[0230] An embodiment of the present application further provides an electronic system, comprising: the aforementioned memory system and a host coupled to the memory system.

[0231] It should be noted that the memory system and electronic system provided in the embodiments of the present application include the aforementioned memory, and the two have the same technical features. The aforementioned has already described in detail the structure of the memory and the nouns appearing in the technical solution of the present application. Therefore, the nouns appearing here can be understood according to the meaning of the aforementioned description and will not be repeated here.

[0232] The above description is intended to be illustrative, not restrictive. For example, the above examples (or one or more aspects thereof) can be used in combination with each other. Other embodiments can be used, such as those available to those skilled in the art when reading the above description. It should be understood that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the above detailed description, various features can be combined together to simplify the application. This should not be interpreted as meaning that the disclosed features that are not claimed for protection are essential to any claim. On the contrary, the disclosed subject matter may be less than all the features of a specific disclosed embodiment. Therefore, the attached claims are thus incorporated into the detailed description, wherein each claim is independently used as a separate embodiment, and it is expected that these embodiments can be combined with each other in various combinations or permutations. The scope of the present application should be determined with reference to the attached claims and the full scope of the equivalents given by these claims.

Claims

1. A method for operating a memory, characterized in that: The memory includes a page buffer, the page buffer includes a first sensing circuit coupled to a sensing node and a dynamic storage circuit coupled to the first sensing circuit; The memory comprises a storage unit configured to store one of a plurality of programming states; The operation method comprises: storing first verification information in the first sensing circuit according to a first potential of the sensing node; transmitting initial verification information in the dynamic storage circuit to the sensing node; the initial verification information includes verification information corresponding to a verified programming state among the multiple programming states; transmitting the first verification information from the first sensing circuit to the dynamic storage circuit, and performing a clearing operation on the first sensing circuit; storing second verification information or the initial verification information in the first sensing circuit according to a second potential of the sensing node; The first potential of the sensing node corresponding to the first verification information is greater than the second potential of the sensing node corresponding to the second verification information.

2. The operating method according to claim 1, characterized in that: The page buffer further includes a second sensing circuit coupled to the sensing node; the operating method further includes: storing third verification information in the second sensing circuit according to a third potential of the sensing node; The second potential of the sensing node corresponding to the second verification information is greater than the third potential of the sensing node corresponding to the third verification information.

3. The operating method according to claim 1, characterized in that: The dynamic storage circuit corresponding to the first storage cell in the to-be-verified programming state among the multiple programming states or the second storage cell in the verified programming state that fails verification is in an initial state.

4. The operating method according to claim 3, characterized in that: The transmitting the initial verification information in the dynamic storage circuit to the sensing node comprises: The sensing node corresponding to the third storage unit successfully verified in the verified programming state among the multiple programming states is charged according to the initial verification information, so as to transmit the initial verification information to the sensing node.

5. The operating method according to claim 1, characterized in that: The transmitting the first verification information from the first sensing circuit to the dynamic storage circuit comprises: A transmission channel between the first sensing circuit and the dynamic storage circuit is opened, so that the first verification information in the first sensing circuit is transmitted to the dynamic storage circuit.

6. The operating method according to claim 1, characterized in that: The clearing operation on the first sensing circuit includes: The first sensing circuit is reset to restore the first sensing circuit to an initial state.

7. The operating method according to claim 2, characterized in that: The page buffer further includes at least one data latch circuit; Before storing the first verification information in the first sensing circuit according to the first potential of the sensing node, the operating method further includes: Obtaining selected operation information according to the data information in the at least one data latch circuit and the initial verification information in the dynamic storage circuit; the selected operation information is used to select a first storage unit in a programming state to be verified among the multiple programming states or a second storage unit in a verified programming state that fails verification; storing the selected operation information in the second sensing circuit; The sensing nodes corresponding to the first storage unit and the second storage unit are precharged to a preset initial voltage according to the selection operation information.

8. The operating method according to claim 7, characterized in that: The operation method also includes: Discharging the sensing node from the preset initial voltage, pausing the discharging of the sensing node after a first preset time, sensing the first potential of the sensing node, and storing the first verification information in the first sensing circuit; causing the sensing node to discharge from the first potential, pausing the discharge of the sensing node after a second preset time, sensing the second potential of the sensing node after the first sensing circuit is cleared, and storing the second verification information in the first sensing circuit; The sensing node is made to discharge from the second potential, and after a third preset time, the discharging of the sensing node is suspended, the third potential of the sensing node is sensed, and the third verification information is stored in the second sensing circuit.

9. The operating method according to claim 8, characterized in that: The operation method also includes: If the first potential is greater than or equal to a first preset voltage, the first verification information is used to indicate a first group of storage cells in the first storage unit and the second storage unit that have passed the verification of the first verification voltage; If the second potential is greater than or equal to a second preset voltage, the second verification information is used to indicate a second group of storage cells in the first storage cell and the second storage cell that have passed the verification of the second verification voltage; If the third potential is greater than or equal to a third preset voltage, the third verification information is used to indicate a third group of storage units in the first storage unit and the second storage unit that have passed the verification of the third verification voltage; Among them, the first verification voltage is lower than the second verification voltage; the second verification voltage is lower than the third verification voltage.

10. The operating method according to claim 9, characterized in that: The operation method also includes: applying different bit line voltages to a bit line coupled to the first memory cell based on the first verification information, the second verification information, and the third verification information; Among them, a first bit line voltage is applied to a first bit line connected to a first forcing unit; a second bit line voltage is applied to a second bit line connected to a second forcing unit; a programming inhibit bit line voltage is applied to a third bit line connected to the third group of memory cells; the first forcing unit is a memory cell in the first group of memory cells except the second group of memory cells and the third group of memory cells; the second forcing unit is a memory cell in the second group of memory cells except the third group of memory cells.

11. The operating method according to claim 10, characterized in that: The operation method also includes: After applying different bit line voltages to the bit line coupled to the first memory cell, determining whether the programming state to be verified is the last programming state among the plurality of programming states; If it is determined that the programming state to be verified is not the last programming state, a swap operation is performed on the first sensing circuit and the dynamic storage circuit so that the second verification information is stored in the dynamic storage circuit and the first verification information is stored in the first sensing circuit.

12. The operating method according to claim 2, characterized in that: The programming of the memory includes at least one programming cycle; The programming cycle includes: a programming operation and a verification operation; the operation method also includes: Before the verification operation, a clearing operation is performed on the first sensing circuit and the dynamic storage circuit.

13. A method for operating a memory, characterized in that: The memory includes a page buffer, the page buffer includes a first sensing circuit coupled to a sensing node and a dynamic storage circuit coupled to the first sensing circuit; The memory comprises a storage unit configured to store one of a plurality of programming states; the operation method comprises: In a first sensing phase of a verification operation of the memory, latching first verification information into the first sensing circuit; transmitting initial verification information in the dynamic storage circuit to the sensing node; the initial verification information includes verification information corresponding to a verified programming state among a plurality of programming states contained in the memory; Opening a transmission channel between the first sensing circuit and the dynamic storage circuit to transmit the first verification information to the dynamic storage circuit; and performing a clearing operation on the first sensing circuit; During a second sensing phase of the verification operation, latching second verification information into the first sensing circuit; The first potential of the sensing node corresponding to the first verification information is greater than the second potential of the sensing node corresponding to the second verification information.

14. The operating method according to claim 13, characterized in that: The page buffer further includes: a second sensing circuit coupled to the sensing node; and the operating method further includes: In the third sensing phase of the verification operation, third verification information is latched into the second sensing circuit, wherein the second potential of the sensing node corresponding to the second verification information is greater than the third potential of the sensing node corresponding to the third verification information.

15. The operating method according to claim 14, characterized in that: The page buffer further comprises at least one data latch circuit; before the first sensing phase of the verification operation of the memory, the operation method further comprises: a pre-charging phase and a first discharging phase, wherein; In the pre-charging stage, latching the selected operation information into the second sensing circuit; pre-charging the sensing node to a preset initial voltage based on the selected operation information; In the first discharge phase, the sensing node is discharged from the preset initial voltage, and after a first preset time, the discharge of the sensing node is suspended; Among them, the selected operation information is obtained based on the data information in the at least one data latch circuit and the initial verification information in the dynamic storage circuit, and is used to select the first storage unit in the multiple programming states that is in the programming state to be verified or the second storage unit that fails verification in the verified programming state.

16. The operating method according to claim 15, characterized in that: The latching of the first verification information into the first sensing circuit comprises: After the sensing node stops discharging, the first sensing circuit is enabled to latch the first verification information into the first sensing circuit in response to a first latch signal.

17. The operating method according to claim 16, characterized in that: Before the second sensing phase of the verification operation of the memory, the operation method further includes: a second discharge phase; wherein, in the second discharge phase, the sensing node is discharged from the first potential, and after a second preset time, the discharge of the sensing node is suspended; After the second sensing phase of the verification operation of the memory, the operation method further includes: a third discharge phase; wherein, in the third discharge phase, the sensing node is discharged from the second potential, and after a third preset time, the discharge of the sensing node is suspended.

18. The operating method according to claim 17, characterized in that: The operation method also includes: After the second discharge phase, causing the first sensing circuit to respond to a second latch signal to latch the second verification information into the first sensing circuit; After the third discharge phase, the second sensing circuit is enabled to latch third verification information into the second sensing circuit in response to a third latch signal.

19. The operating method according to claim 15, characterized in that: After the third sensing phase of the verification operation, the operation method further includes: applying different bit line voltages to a bit line coupled to the first memory cell in a programming state to be verified among the plurality of programming states according to the first verification information, the second verification information, and the third verification information; Among them, a first bit line voltage is applied to a first bit line connected to a first forcing unit; a second bit line voltage is applied to a second bit line connected to a second forcing unit; a programming inhibit bit line voltage is applied to a third bit line connected to a third group of memory cells; the first forcing unit is a memory cell in the first group of memory cells except for the second group of memory cells and the third group of memory cells; the second forcing unit is a memory cell in the second group of memory cells except for the third group of memory cells.

20. The operating method according to claim 19, characterized in that: The first group of memory cells includes memory cells in the first memory cells that have passed verification of a first verification voltage; The second group of memory cells includes memory cells in the first memory cells that have passed verification of a second verification voltage; The third group of memory cells includes memory cells in the first memory cells that have passed the verification of the third verification voltage; If the first potential is greater than or equal to a first preset voltage, the first verification information is used to indicate a first group of storage units in the first storage unit and the second storage unit that have passed the verification of the first verification voltage; If the second potential is greater than or equal to a second preset voltage, the second verification information is used to indicate a second group of storage cells in the first storage cell and the second storage cell that have passed the verification of the second verification voltage; If the third potential is greater than or equal to a third preset voltage, the third verification information is used to indicate a third group of storage units in the first storage unit and the second storage unit that have passed the verification of the third verification voltage; The first verification voltage is lower than the second verification voltage; and the second verification voltage is lower than the third verification voltage.

21. The operating method according to claim 19, characterized in that: After the third sensing phase of the verification operation, the operation method further includes: After applying different bit line voltages to the bit line coupled to the first memory cell, determining whether the programming state to be verified is the last programming state among the plurality of programming states; If it is determined that the programming state to be verified is not the last programming state, a swap operation is performed on the first sensing circuit and the dynamic storage circuit so that the second verification information is stored in the dynamic storage circuit and the first verification information is stored in the first sensing circuit.

22. The operating method according to claim 14, characterized in that: The programming of the memory includes at least one programming cycle; The programming cycle includes: a programming operation and a verification operation; before the verification operation, the operation method further includes: performing a clearing operation on the first sensing circuit and the dynamic storage circuit.

23. The operating method according to claim 15, characterized in that: The page buffer further includes a first transistor and a second transistor connected in series; wherein one end of the first transistor is connected to a positive end of a power supply; one end of the second transistor is connected to the sensing node; and the initial verification information in the dynamic storage circuit is transmitted to the sensing node, comprising: The second transistor is controlled by a first transmission signal; and the first transistor is controlled by the initial verification information; Under the action of the first transmission signal and the initial verification information, the first transistor and the second transistor are turned on, and the sensing node corresponding to the third storage unit that has been successfully verified in the verified programming state among the multiple programming states is charged to transmit the initial verification information to the sensing node.

24. A memory, characterized in that: include: Storage arrays; The memory array includes memory cells configured to store one of a plurality of programming states; a plurality of page buffers coupled to the memory array; Each page buffer includes: a first sensing circuit coupled to a sensing node and a dynamic storage circuit coupled to the first sensing circuit; and a control logic circuit coupled to the storage array and the plurality of page buffers; wherein, The control logic circuit is configured to: store first verification information in the first sensing circuit according to the first potential of the sensing node; transmit initial verification information in the dynamic storage circuit to the sensing node; the initial verification information includes verification information corresponding to a verified programming state among the multiple programming states; transmit the first verification information from the first sensing circuit to the dynamic storage circuit, and perform a clear operation on the first sensing circuit; store second verification information or the initial verification information in the first sensing circuit according to the second potential of the sensing node; wherein the first potential of the sensing node corresponding to the first verification information is greater than the second potential of the sensing node corresponding to the second verification information.

25. The memory according to claim 24, characterized in that The page buffer further includes: a second sensing circuit coupled to the sensing node; The control logic circuit is further configured to: store third verification information to the second sensing circuit according to the third potential of the sensing node; wherein the second potential of the sensing node corresponding to the second verification information is greater than the third potential of the sensing node corresponding to the third verification information.

26. The memory according to claim 25, characterized in that The page buffer also includes at least one data latch circuit; the control logic circuit is further configured to: obtain selected operation information based on data information in the at least one data latch circuit and the initial verification information in the dynamic storage circuit; the selected operation information is used to select a first storage unit in a programming state to be verified among the multiple programming states or a second storage unit in a verified programming state that fails verification; store the selected operation information in the second sensing circuit; and precharge the sensing nodes corresponding to the first storage unit and the second storage unit to a preset initial voltage based on the selected operation information.

27. The memory according to claim 26, characterized in that The page buffer also includes a first transistor and a second transistor connected in series; Among them, the other end of the first transistor is connected to the positive end of the power supply; the other end of the second transistor is connected to the sensing node; the first transistor is controlled by the initial verification information; the second transistor is controlled by the first transmission signal; under the action of the first transmission signal and the initial verification information, the first transistor and the second transistor are turned on to charge the sensing node corresponding to the third storage unit that has been successfully verified in the verified programming state among the multiple programming states, so as to transmit the initial verification information to the sensing node.

28. The memory according to claim 27, characterized in that The page buffer further includes a transmission switch, and the transmission switch is configured to transmit the first verification information from the first sensing circuit to the dynamic storage circuit in response to a second transmission signal sent by the control logic circuit.

29. The memory according to claim 28, characterized in that The page buffer further includes a precharge circuit; the control logic circuit is further configured to: obtain selected operation information according to the data information in the at least one data latch circuit and the initial verification information stored in the dynamic storage circuit; latch the selected operation information to the second sensing circuit; generating a precharge signal; The precharge circuit is configured to precharge the sensing nodes corresponding to the first storage unit and the second storage unit to the preset initial voltage based on the selected operation information in response to the precharge signal.

30. The memory according to claim 29, characterized in that The page buffer further includes: a discharge circuit; The control logic circuit is further configured to: generate a first discharge signal, a second discharge signal and a third discharge signal; The discharge circuit is configured to: in response to the first discharge signal, discharge the sensing node from the preset initial voltage, and suspend the discharge of the sensing node after a first preset time period; In response to the second discharge signal, the sensing node starts to discharge from the first potential, and after a second preset time, the discharge of the sensing node is suspended; In response to the third discharge signal, the sensing node is discharged from the second potential, and the discharge of the sensing node is suspended after a third preset time period.

31. The memory according to claim 25, characterized in that The first sensing circuit includes a first latch for storing first verification information; the second sensing circuit includes a second latch for storing third verification information; and the dynamic storage circuit includes a dynamic latch for storing second verification information.

32. The memory according to claim 26, characterized in that The control logic circuit is further configured to: after applying different bit line voltages to the bit line coupled to the first storage unit based on the first verification information, the second verification information and the third verification information, determine whether the programming state to be verified is the last programming state among the multiple programming states; if it is determined that the programming state to be verified is not the last programming state, control the first sensing circuit and the dynamic storage circuit to perform an exchange operation so that the second verification information is stored in the dynamic storage circuit and the first verification information is stored in the first sensing circuit.

33. The memory according to claim 25, characterized in that After transmitting the first verification information from the first sensing circuit to the dynamic storage circuit, the first sensing circuit is further configured to: in response to a clear signal sent by the control logic circuit, reset the first sensing circuit to restore the first sensing circuit to an initial state.

34. A memory system, characterized in that: include: A memory as claimed in any one of one or more claims 24 to 33 and a memory controller coupled to the memory and used to control the memory.

35. An electronic system, characterized in that: include: The memory system of claim 34 and a host coupled to the memory system.

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