Current mode multiplexing type transmitting final stage and data transmitting method
By integrating the function of the current mode multiplexer to the transmission end stage in a half-rate data transmitter, the problem of high power consumption of the current mode data buffer link in traditional technology is solved, and a lower overall power consumption management is achieved.
Patent Information
- Application Number
- CN202411329480.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-23
- Publication Date
- 2025-04-18
Smart Images
Figure CN119853713A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of automobile technology, and in particular to a current mode multiplexing type transmitting final stage, a data transmitting method, a half-rate data transmitter, a communication system and a vehicle. Background Art
[0002] A half-rate data transmitter is a device or circuit used to convert digital data signals into analog or digital signals suitable for transmission. It is one of the key components of a data communication system, used to convert data to be transmitted into signals for transmission in a communication channel. In a half-rate data transmitter, a current mode multiplexer is usually required to convert two orthogonal half-rate data channels into one full-rate data channel to achieve the final data output.
[0003] Traditional half-rate data transmitters usually set the current mode multiplexer in the front stage, which means that a corresponding current mode data buffer link needs to be set in the back stage of the current mode multiplexer for driving and amplifying, so that data can be output through the corresponding transmission final stage. However, the power consumption of the current mode data buffer link is high, which makes the overall power consumption management of the half-rate data transmitter difficult. Summary of the invention
[0004] The embodiments of the present application provide a current mode multiplexing type transmitting final stage, a data transmission method, a half-rate data transmitter, a communication system and a vehicle, which can reduce the overall power consumption of the half-rate data transmitter to at least partially solve the above-mentioned technical problems.
[0005] In order to achieve the above-mentioned object, according to a first aspect of the present application, a current mode multiplexing type transmitting final stage is provided, the current mode multiplexing type transmitting final stage comprising a first input terminal for electrically connecting to an output terminal of a first data buffer link, a second input terminal for electrically connecting to an output terminal of a second data buffer link, a third input terminal for electrically connecting to a first output terminal of a clock buffer link, and an output terminal for outputting target data;
[0006] The current mode multiplexing type transmission final stage is used to integrate the half-rate first processed data output by the first data buffer link and the half-rate second processed data output by the second data buffer link according to the clock signal output by the clock buffer link, to obtain the full-rate target data, and transmit the target data.
[0007] Optionally, the current mode multiplexing type transmitting final stage includes a current mode multiplexer and a current mode transmitting final stage;
[0008] The current mode multiplexer includes a first input terminal for electrically connecting to an output terminal of the first data buffer link, a second input terminal for electrically connecting to an output terminal of the second data buffer link, a third input terminal for electrically connecting to a first output terminal of the clock buffer link, and an output terminal electrically connected to an input terminal of the current mode transmitting final stage;
[0009] The current mode transmission final stage also includes an output terminal for outputting target data.
[0010] Optionally, the current mode multiplexer includes a first data switch tube group, a second data switch tube group, a clock switch tube group and a current adjustment unit;
[0011] The first data switch tube group includes a driving end electrically connected to the output end of the first data buffer link, a first access end electrically connected to the input end of the current mode transmitter final stage, and a second access end electrically connected to the first access end of the clock switch tube group;
[0012] The second data switch tube group includes a driving end electrically connected to the output end of the second data buffer link, a first access end electrically connected to the input end of the current mode transmitter final stage, and a second access end electrically connected to the first access end of the clock switch tube group;
[0013] The current adjustment unit includes a first access terminal electrically connected to the second access terminal of the clock switch tube group and a second access terminal for grounding;
[0014] The clock switch tube group also includes a driving end for electrically connecting to the first output end of the clock buffer link.
[0015] Optionally, the current mode multiplexer further includes an isolation inductor;
[0016] The isolation inductor comprises a first access terminal electrically connected to the second access terminal of the clock switch tube group and a second access terminal electrically connected to the first access terminal of the current adjustment unit.
[0017] Optionally, the current adjustment unit includes an adjustable resistance unit and a calibration logic unit;
[0018] The adjustable resistance unit includes a first access terminal electrically connected to the second access terminal of the isolation inductor, a second access terminal for grounding, and a control terminal electrically connected to the output terminal of the calibration logic unit.
[0019] Optionally, the adjustable resistance unit includes a plurality of shunt resistors connected in parallel and a control switch tube corresponding to each shunt resistor;
[0020] Each shunt resistor includes a first access end electrically connected to the second access end of the isolation inductor and a second access end electrically connected to the first access end of the corresponding control switch tube. Each control switch tube also includes a second access end for grounding and a driving end electrically connected to the corresponding output end of the calibration logic unit.
[0021] Optionally, the current adjustment unit further includes a comparator;
[0022] The comparator includes a first input terminal electrically connected to the first access terminal of the first data switch tube group, the first access terminal of the second data switch tube group and the input terminal of the current mode emission final stage respectively, a second access terminal for accessing a first reference voltage and an output terminal electrically connected to the input terminal of the calibration logic unit.
[0023] Optionally, the current mode multiplexer further includes a first feedthrough compensation switch tube group and a second feedthrough compensation switch tube group;
[0024] The first feedthrough compensation switch tube group includes a driving end electrically connected to the output end of the first data buffer link and a first access end electrically connected to the input end of the current-mode emission final stage, and the second feedthrough compensation switch tube group includes a driving end electrically connected to the output end of the second data buffer link and a first access end electrically connected to the input end of the current-mode emission final stage.
[0025] Optionally, the current mode multiplexer further includes a common-gate switch tube group;
[0026] The common-gate switch tube group includes a first access terminal electrically connected to the input terminal of the current-mode emission final stage, a second access terminal electrically connected to the first access terminal of the first data switch tube group and the first access terminal of the second data switch tube group respectively, and a driving terminal for accessing a working voltage.
[0027] According to a second aspect of the present application, a data transmission method is provided. The data transmission method is applied to the current mode multiplexing type transmission final stage in any of the above embodiments. The data transmission method includes the following steps performed by the current mode multiplexing type transmission final stage:
[0028] Acquire a clock signal output by a clock buffer link, first processed data at half the rate output by a first data buffer link, and second processed data at half the rate output by a second data buffer link;
[0029] Integrate the first processed data and the second processed data according to the clock signal to obtain full-rate target data;
[0030] Transmit the target data.
[0031] According to a third aspect of the present application, a half-rate data transmitter is provided, comprising a first data buffer link, a second data buffer link, a clock buffer link, and a current-mode multiplexing type transmitting final stage in any one of the above embodiments.
[0032] Optionally, the half-rate data transmitter further comprises a clock buffer final stage;
[0033] The clock buffer final stage comprises an input terminal for electrically connecting to the first output terminal of the clock buffer link and an output terminal electrically connecting to the third input terminal of the current mode multiplexing type transmitting final stage;
[0034] The clock buffer final stage is used to reduce the swing of the clock signal input to the clock buffer link, and then output the clock signal with the reduced swing to the current mode multiplexing type transmitting final stage.
[0035] Optionally, the clock buffer final stage includes a clock buffer and a voltage regulator;
[0036] The clock buffer includes an input terminal electrically connected to the first output terminal of the clock buffer link, an output terminal electrically connected to the third input terminal of the current mode multiplexing type transmitting final stage, and a ground terminal electrically connected to the first access terminal of the regulator, and the regulator also includes a second access terminal for grounding.
[0037] Optionally, the voltage regulator includes a front-stage operational amplifier and a current adjustment switch tube;
[0038] The front-stage operational amplifier includes a first input terminal electrically connected to the ground terminal of the clock buffer and the first access terminal of the current adjustment switch tube respectively, a second input terminal for accessing a second reference voltage, and an output terminal electrically connected to the driving end of the current adjustment switch tube, and the current adjustment switch tube also includes a second access terminal for grounding.
[0039] Optionally, the voltage regulator further includes a phase compensation resistor and a phase compensation capacitor;
[0040] The phase compensation resistor includes a first access end electrically connected to the output end of the previous operational amplifier and the driving end of the current adjustment switch tube respectively, and a second access end electrically connected to the first access end of the phase compensation capacitor. The phase compensation capacitor also includes a second access end for grounding.
[0041] Optionally, the voltage regulator also includes a ripple suppression capacitor;
[0042] The ripple suppression capacitor comprises a first access terminal electrically connected to the first input terminal of the pre-stage operational amplifier, the ground terminal of the clock buffer and the first access terminal of the current adjustment switch tube respectively, and a second access terminal for grounding.
[0043] Optionally, the clock buffer final stage further includes an adjustable current source;
[0044] The adjustable current source comprises a first access terminal electrically connected to the output terminal of the clock buffer and the third input terminal of the current mode multiplexing type transmitting final stage respectively, and a second access terminal for grounding.
[0045] Optionally, the clock buffer final stage further includes a drain switch tube and a drain resistor;
[0046] The drainage switch tube includes a first access terminal electrically connected to the power supply terminal of the clock buffer, a second access terminal electrically connected to the first access terminal of the drainage resistor, and a driving terminal for accessing the drainage control signal. The drainage resistor also includes a second access terminal electrically connected to the ground terminal of the clock buffer and the first access terminal of the regulator respectively.
[0047] Optionally, the half-rate data transmitter further comprises a data serializer;
[0048] The data serializer includes a first input terminal for accessing initial data, a second input terminal electrically connected to the second output terminal of the clock buffer link, a first output terminal electrically connected to the input terminal of the first data buffer link, and a second output terminal electrically connected to the input terminal of the second data buffer link.
[0049] According to a fourth aspect of the present application, a communication system is provided, the communication system comprising the half-rate data transmitter in any one of the above embodiments.
[0050] According to a fifth aspect of the present application, a vehicle is provided, the vehicle comprising the communication system in any one of the above embodiments.
[0051] In the current-mode multiplexing transmitting final stage of the embodiment of the present application, the function of the current-mode multiplexer is integrated into the transmitting final stage, and the first input terminal and the second input terminal of the current-mode multiplexing transmitting final stage are respectively used to electrically connect to the output terminal of the first data buffer link and the output terminal of the second data buffer link, so that the current-mode multiplexing transmitting final stage serves as the latter stage of the data buffer link. For the data buffer link serving as the former stage, there is no need to adopt the current-mode type, thereby reducing the power consumption corresponding to the data buffer link, and further reducing the difficulty of overall power consumption management of the half-rate data transmitter.
[0052] Other features and advantages of the present application will be described in detail in the subsequent specific implementation section. BRIEF DESCRIPTION OF THE DRAWINGS
[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.
[0054] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same figure numbers represent the same parts in the following description.
[0055] Figure 1 is a schematic structural diagram of a half-rate data transmitter provided in an exemplary embodiment disclosed in the present application;
[0056] Figure 2 It is a structural schematic diagram of a half-rate data transmitter provided in an exemplary embodiment disclosed in the present application, wherein the current mode multiplexing type transmission final stage includes a current mode multiplexer and a current mode transmission final stage;
[0057] Figure 3 It is a schematic diagram of the specific structure of the current mode multiplexing type transmitting final stage provided in the exemplary embodiment disclosed in this application;
[0058] Figures 4a to 4c is a schematic diagram of the operation analysis of the current mode multiplexer in the exemplary embodiment disclosed in the present application;
[0059] Figure 5 is a schematic diagram of small signal analysis from a common mode perspective after adding an isolation inductor in an exemplary embodiment disclosed in the present application;
[0060] Figure 6 It is a specific structural schematic diagram of a current mode multiplexing type transmitting final stage with an adjustable resistance unit and a calibration logic unit added in an exemplary embodiment disclosed in the present application;
[0061] Figure 7 is a schematic diagram of a specific structure of an adjustable resistance unit in an exemplary embodiment disclosed in the present application;
[0062] Figure 8 is a schematic diagram of a circuit principle of a calibration logic unit in an exemplary embodiment disclosed in the present application;
[0063] Fig. 9 is a schematic structural diagram of a half-rate data transmitter with a clock buffer final stage added in an exemplary embodiment disclosed in the present application;
[0064] Fig.10 is a structural schematic diagram of a half-rate data transmitter including a clock buffer and a voltage regulator at the final stage of the clock buffer in an exemplary embodiment disclosed in the present application;
[0065] Fig.11 is a schematic diagram of a specific structure of a clock buffer and a voltage regulator in an exemplary embodiment disclosed in the present application;
[0066] Fig.12 is a specific circuit diagram of an adjustable current source in an exemplary embodiment disclosed in the present application;
[0067] Fig.13 FIG. 4 is a systematic diagram of a half-rate data transmitter in an exemplary embodiment disclosed in the present application.
[0068] Description of reference numerals:
[0069] R_term, pull-up resistor; MN0-MN12, switch tube; MN20-MN23, switch tube; MP0-MP3, switch tube; L, isolation inductor; R_currentset, adjustable resistance unit; cmp, comparator; amp, pre-stage operational amplifier; MN_power, current adjustment switch tube; MP_lowfreq, current diversion switch tube; R_lowfreq, current diversion resistor; prog_current, adjustable current source; R1, phase compensation resistor; C1, phase compensation capacitor; C2, ripple suppression capacitor.
[0070] I1, current mode multiplexing type transmitting final stage; I2, CMOS logic clock buffer final stage; I3, first CMOS logic data buffer link; I4, second CMOS logic data buffer link; I5, multi-bit to two-bit data serializer; I6, CMOS logic clock buffer link. DETAILED DESCRIPTION
[0071] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.
[0072] According to the first aspect of the present application, a current mode multiplexing type transmitting final stage is provided, such as Figure 1 As shown, the current-mode multiplexing type transmitting final stage includes a first input terminal for electrically connecting to the output terminal of the first data buffer link, a second input terminal for electrically connecting to the output terminal of the second data buffer link, a third input terminal for electrically connecting to the first output terminal of the clock buffer link, and an output terminal for outputting the target data TX_out.
[0073] Among them, the current mode multiplexing type transmission final stage is used to integrate the half-rate first processed data output by the first data buffer link and the half-rate second processed data output by the second data buffer link according to the clock signal output by the clock buffer link, so as to output the full-rate target data TX_out.
[0074] Among them, Figure 1In the embodiment, the input end of the first data buffer link is used to be electrically connected to the first output end of the data serializer, the input end of the second data buffer link is used to be electrically connected to the second output end of the data serializer, the first input end of the data serializer is used to access the initial data parallel data to be processed, the second output end of the clock buffer link is also used to be electrically connected to the second input end of the data serializer, and the input end of the clock buffer link is used to access the unprocessed clock signal clk.
[0075] The clock buffer link is used to drive and amplify the connected clock signal clk to obtain a processed clock signal, and then output the processed clock signal to the data serializer and the current mode multiplexing type transmission final stage respectively.
[0076] The data serializer performs a timing logic operation on the received initial data parallel data according to the clock signal output by the clock buffer link, thereby converting the initial data parallel data into two paths of odd and even half-rate data, the phases of the two paths of data are in an orthogonal relationship, and the two paths of half-rate data include first half-rate data output to the first data buffer link and second half-rate data output to the second data buffer link.
[0077] The first data buffer link drives and amplifies the first half-rate data received, obtains the processed first processed data, and then outputs the first processed data to the current mode multiplexing type transmitting final stage. The second data buffer link drives and amplifies the second half-rate data received, obtains the processed second processed data, and then outputs the second processed data to the current mode multiplexing type transmitting final stage.
[0078] To summarize, the data serializer, the clock buffer link, the first data buffer link, the second data buffer link and the current-mode multiplexing type transmitting final stage constitute a half-rate data transmitter, which realizes the function of initial data access to the target data output. In the half-rate data transmitter, due to the existence of the current-mode multiplexing type transmitting final stage, the current-mode circuit is set in the final stage, and the first data buffer link and the second data buffer link of the previous stage do not need to adopt the current-mode method.
[0079] In the current-mode multiplexing transmitting final stage of the embodiment of the present application, the function of the current-mode multiplexer is integrated into the transmitting final stage, and the first input terminal and the second input terminal of the current-mode multiplexing transmitting final stage are respectively used to electrically connect to the output terminal of the first data buffer link and the output terminal of the second data buffer link, so that the current-mode multiplexing transmitting final stage serves as the latter stage of the data buffer link. For the data buffer link serving as the former stage, there is no need to adopt the current-mode type, thereby reducing the power consumption corresponding to the data buffer link, and further reducing the difficulty of overall power consumption management of the half-rate data transmitter.
[0080] Optional, such as Figure 2 As shown, the current mode multiplexing type transmitting final stage includes a current mode multiplexer and a current mode transmitting final stage.
[0081] Among them, Figure 2 In the embodiment, the current mode multiplexer includes a first input terminal electrically connected to the output terminal of the first data buffer link, a second input terminal electrically connected to the output terminal of the second data buffer link, a third input terminal electrically connected to the first output terminal of the clock buffer link, and an output terminal electrically connected to the input terminal of the current mode transmitting final stage, and the current mode transmitting final stage also includes an output terminal for outputting the target data TX_out.
[0082] Among them, the current mode multiplexer and the current mode transmitter final stage can both adopt the traditional circuit structure. The current mode multiplexer is used to realize the integration of the first processing data of half rate and the second processing data of half rate to obtain the target data of full rate, and the current mode transmitter final stage is used to realize the impedance matching of the transmission line and shield the high frequency capacitance to ensure the transmission bandwidth.
[0083] Optional, such as Figure 3 As shown, the current mode multiplexer includes a first data switch tube group (including switch tube MN3 and switch tube MN4), a second data switch tube group (including switch tube MN5 and switch tube MN6), a clock switch tube group (including switch tube MN1 and switch tube MN2) and a current adjustment unit (in Figure 3 In the example, it may be a switch tube MN0).
[0084] Among them, Figure 3 In the embodiment, the first data switch tube group includes a driving end for electrically connecting to the output end of the first data buffer link (including the gate of the switch tube MN3 for connecting to the first component dataop in the first processed data and the gate of the switch tube MN4 for connecting to the second component dataon in the first processed data), a first access end electrically connected to the input end of the current mode emission final stage (including the first source and drain electrically connected between the switch tube MN3 and the pull-up resistor R_term and the first source and drain electrically connected between the switch tube MN4 and the pull-up resistor R_term), and a second access end electrically connected to the first access end of the clock switch tube group (including the second source and drain electrically connected between the switch tube MN3 and the switch tube MN1 or the second source and drain electrically connected between the switch tube MN4 and the switch tube MN1).
[0085] Among them, Figure 3In the embodiment, the second data switch tube group includes a driving end for electrically connecting to the output end of the second data buffer link (including the gate of the switch tube MN5 for connecting to the first component dataep in the second processed data and the gate of the switch tube MN6 for connecting to the second component dataen in the second processed data), a first access end electrically connected to the input end of the current mode emission final stage (including the first source and drain electrically connected to the pull-up resistor R_term of the switch tube MN5 and the first source and drain electrically connected to the pull-up resistor R_term of the switch tube MN6), and a second access end electrically connected to the first access end of the clock switch tube group (including the second source and drain electrically connected to the switch tube MN5 and the switch tube MN2 or the second source and drain electrically connected to the switch tube MN6 and the switch tube MN2).
[0086] Among them, Figure 3 In the embodiment, the clock switch tube group also includes a driving end for electrically connecting to the first output end of the clock buffer link (including a gate of the switch tube MN1 for accessing the first component ckp in the clock signal and a gate of the switch tube MN2 for accessing the second component ckn in the clock signal).
[0087] Among them, Figure 3 In the embodiment, the current adjustment unit includes a first access terminal electrically connected to the second access terminal of the clock switch tube group (including a first source and drain of the switch tube MN0 electrically connected to the second source and drain of the switch tube MN1 and the second source and drain of the switch tube MN2 respectively) and a second access terminal for grounding (including a second source and drain of the switch tube MN0 for grounding), and the gate of the switch tube MN0 is used to access the current adjustment signal nb1.
[0088] Among them, the switch tube MN0 is the bottom current source tube, the switch tube MN1 and the switch tube MN2 constitute a clock-controlled switch tube, the switch tube MN3, the switch tube MN4, the switch tube MN5, and the switch tube MN6 are data input tubes, and the above seven tubes can constitute a conventional current mode multiplexer circuit.
[0089] Optional, such as Figure 3 As shown, the current mode multiplexer also includes an isolation inductor L.
[0090] Among them, Figure 3 In the embodiment, the isolation inductor L includes a first access end electrically connected to the second access end of the clock switch tube group (including a first access end electrically connected to the second source and drain of the switch tube MN1 and the second source and drain of the switch tube MN2 respectively) and a second access end electrically connected to the first access end of the current adjustment unit (including a second access end electrically connected to the first source and drain of the switch tube MN0).
[0091] Among them, Figures 4a to 4cAs shown in the figure, switch tube MN1 and switch tube MN2 will switch alternately under the half-rate clock signal. Due to the nonlinear relationship between gate voltage and conduction current, there will be two stages of additional equivalent common-mode input in the switching process of the two clock-controlled switches. First, there is a stage where one switch tube is turned on and the other switch tube is turned off ( Figures 4a to 4c In step 1 and step 3), the input differential clock signal will only affect the output current on the on side. Second, there is a stage where both switches are on ( Figures 4a to 4c In step 2), due to the nonlinearity of the device voltage and current, the voltage at the source of the switch tube needs to change if the constant current relationship is to be satisfied. The above two nonlinear clock-controlled switch conversion processes can be equivalent to a linear voltage-current model. The switch tube inputs common-mode noise in addition to the differential-mode input signal. Since there are two edges in a clock cycle and the input clock edge is faster, the clock switching is equivalent to the clock-controlled tube inputting common-mode regular noise with a data rate that is multiple multiples of the fundamental frequency. To reduce glitches, the transmitter clock-controlled switch tube should reduce its gain at high frequencies for the equivalent input common-mode signal. Since the switch tube MN0 has a small output impedance ( Figures 4a to 4c Rs in the drain junction capacitance and additional parasitic capacitance ( Figures 4a to 4c Cs in the circuit), its drain terminal is difficult to become a high impedance node at a higher frequency, and the drain terminal will consume a large amount of current during the fast switching process of the clock-controlled switch. Since the voltage at the drain terminal of the switch tube MN0 cannot instantaneously track the common-mode voltage change of the equivalent input, the traditional current-mode multiplexer will generate a large overshoot current through the transconductance gain of the switch tube. If the clock switch switches slowly, due to the limited output impedance of the current source, the output common-mode current noise will still have a large amplitude at the data rate baseband.
[0092] Among them, when the isolation inductor L is added, it forms a shielding effect between the total capacitance of the drain of the switch tube MN0 and the source of the input switch, thereby increasing the data rate frequency band and the equivalent impedance from the source end of the clock control tube downward, which is much higher than the data frequency.
[0093] Among them, Figure 5 As shown, gm is the transconductance of the input tube, C gs is the gate-source junction capacitance of the input tube, C s is the total capacitance of the drain of the switch tube MN0, R s is the output impedance of the switch tube MN0, L is the inductive reactance of the added isolation inductor, ω is the angular frequency of the input data, and j is an imaginary number.
[0094] The common-mode current gain without adding the current source series isolation inductor L is:
[0095]
[0096] Since the transmitter device is biased at a higher characteristic frequency, it can be ignored to a certain extent. Therefore, we are mainly concerned about the common-mode noise current gain caused by the lower output impedance of the switch tube MN0 and the high-frequency admittance of the drain node capacitance, which can be simplified as:
[0097]
[0098] After adding the isolation inductor L, the common-mode noise current gain amplitude in the frequency band of interest is dominated by the admittance of the isolation inductor L:
[0099]
[0100] From the analysis, it can be seen that in order to achieve a certain isolation effect, the self-resonant frequency of the isolation inductor L must be much higher than the data rate. The parasitic capacitance introduced by the isolation inductor L itself should not deteriorate the equivalent common-mode noise current gain. For this reason, the isolation inductor L can be selected by connecting multiple metal coil inductors with small parasitic capacitances in series.
[0101] Optional, such as Figure 6 As shown, the current adjustment unit includes an adjustable resistance unit R_currentset and a calibration logic unit.
[0102] Among them, Figure 6 In the embodiment, the adjustable resistance unit R_currentset includes a first access terminal electrically connected to the second access terminal of the clock switch tube group (such as the second source and drain of the switch tube MN1 and the second source and drain of the switch tube MN2), a second access terminal for grounding, and a control terminal electrically connected to the output terminal of the calibration logic unit to access the control signal varify_ctrl.
[0103] Among them, the calibration logic unit is used to implement power on vod calibration, which specifically refers to the process of calibrating VOD when the device is powered on. VOD calibration can be used to adjust the amplitude, waveform and stability of the output voltage to ensure that the device can work normally after power-on and meet performance and reliability requirements.
[0104] The control signal varify_ctrl output by the calibration logic unit can control the resistance value of the corresponding loop connected to the adjustable resistance unit R_currentset, so as to meet the actual demand.
[0105] Among them, when applied to a low-voltage power supply scenario, the current adjustment unit in the form of a switch tube will not work properly, while the current adjustment unit in the form of a resistor can be suitable for low-voltage power supply scenarios. In addition, since the isolation inductor L provides a higher impedance at high frequencies, the switch tube MN0 in the above embodiment can be completely replaced by an adjustable resistance unit R_currentset. Compared with using a current mirror tube to provide current, the adjustable resistance unit R_currentset can provide a larger voltage margin. In addition, it introduces a lower port capacitance, which is more conducive to reducing glitches. However, it should be noted that compared with the conventional current mirror solution, the adjustable resistance unit R_currentset will introduce a larger error after replacement, so a digital automatic correction mechanism is required, that is, calibration is performed through the control signal varify_ctrl output by the calibration logic unit, so that the resistance of the adjustable resistance unit R_currentset connected to the corresponding loop is calibrated and meets the requirements.
[0106] Optional, such as Figure 6 and Figure 7 As shown, the adjustable resistance unit R_currentset includes a plurality of parallel shunt resistors and a control switch tube corresponding to each shunt resistor.
[0107] Among them, Figure 6 and Figure 7 In the embodiment, each shunt resistor includes a first access terminal electrically connected to the second access terminal of the isolation inductor L and a second access terminal electrically connected to the first access terminal of the corresponding control switch tube, and each control switch tube also includes a second access terminal for grounding and a driving terminal electrically connected to the corresponding output terminal of the calibration logic unit, so as to respectively access the corresponding switch signal varify_ctrl <0> , switch signal varify_ctrl <1> , switch signal varify_ctrl <2> , switch signal varify_ctrl <3> , switch signal varify_ctrl <4> , switch signal varify_ctrl <5> , the switch signal varify_const, and finally determines the resistance Rp connected to the corresponding circuit.
[0108] Among them, the adjustable resistance unit R_currentset uses binary code to directly control the parallel amount of the shunt resistor, which can obtain a smaller control step size compared to the adjustment scheme of the short-circuit series resistor. Among them, varify_const is a normally open control, and varify_ctrl<5:0> is a digital calibration control. Using external combinational logic, all resistors can be directly controlled to close, thereby obtaining the power-off control of the final stage of the transmitter.
[0109] Optional, such as Figure 6 As shown, the current adjustment unit further includes a comparator cmp.
[0110] Among them, Figure 6 In the embodiment, the comparator cmp includes a first input terminal electrically connected to the first access terminal of the first data switch tube group (such as the first source and drain of the switch tube MN3 and the first source and drain of the switch tube MN4), the first access terminal of the second data switch tube group (such as the first source and drain of the switch tube MN5 and the first source and drain of the switch tube MN6) and the input terminal of the current-mode emission final stage (such as the pull-up resistor R_term), a second access terminal for accessing the first reference voltage vref_vol, and an output terminal electrically connected to the input terminal of the calibration logic unit.
[0111] Among them, Figure 8 As shown, the calibration logic unit consists of a counter that can count up and down and a digital code zero-crossing detection circuit. After power-on, the start signal and the correction end signal will jointly control the gate clock of the up-down counter. The up-down counter will change the correction code step by step according to the judgment result signal of the comparator cmp. When the correction code reaches the minimum error, it will jump between two adjacent values. The zero-crossing detection circuit will track the judgment result signal of the comparator cmp. When it is detected that the output of the comparator cmp flips within a certain period, that is, the correction voltage difference crosses zero, the end signal of the zero-crossing detection will be set to "1" for a long time, and the up-down counter will stop counting and lock the correction result.
[0112] Optional, such as Figure 3 As shown, the current mode multiplexer also includes a first feedthrough compensation switch tube group (including switch tube MN7 and switch tube MN8) and a second feedthrough compensation switch tube group (including switch tube MN9 and switch tube MN10).
[0113] Among them, Figure 3 In the embodiment, the first feedthrough compensation switch tube group includes a driving end electrically connected to the output end of the first data buffer link (including a gate of the switch tube MN7 for accessing the first component dataep in the second processed data and a gate of the switch tube MN8 for accessing the second component dataen in the second processed data) and a first access end electrically connected to the input end of the current-mode emission final stage (including a first source and drain electrically connected to the pull-up resistor R_term by the switch tube MN7 and a first source and drain electrically connected to the pull-up resistor R_term by the switch tube MN8).
[0114] Among them, Figure 3In the embodiment, the second feedthrough compensation switch tube group includes a driving end electrically connected to the output end of the second data buffer link (including a gate of the switch tube MN9 for accessing the first component dataep in the second processed data and a gate of the switch tube MN10 for accessing the second component dataen in the second processed data) and a first access end electrically connected to the input end of the current-mode emission final stage (including a first source and drain electrically connected to the pull-up resistor R_term by the switch tube MN9 and a first source and drain electrically connected to the pull-up resistor R_term by the switch tube MN10).
[0115] in, Figure 3 The switch tubes MN7, MN8, MN9 and MN10 added in the embodiment offset the feedthrough effect of the two half-rate data input tubes.
[0116] Optional, such as Figure 3 As shown, the current mode multiplexer further includes a common-gate switch tube group (including a switch tube MN11 and a switch tube MN12).
[0117] Among them, Figure 3 In the embodiment, the common-gate switch tube group includes a first access terminal electrically connected to the input terminal of the current-mode emission final stage (including a first source and drain electrically connected to the pull-up resistor R_term of the switch tube MN11 and a first source and drain electrically connected to the pull-up resistor R_term of the switch tube MN12), a second access terminal electrically connected to the first access terminal of the first data switch tube group and the first access terminal of the second data switch tube group respectively (including a second source and drain electrically connected to the first source and drain of the switch tube MN11 and the first source and drain of the switch tube MN3 and the first source and drain of the switch tube MN5 respectively, and a second source and drain electrically connected to the first source and drain of the switch tube MN4 and the first source and drain of the switch tube MN6 respectively), and a driving terminal for connecting to the working voltage (including a gate of the switch tube MN11 and a gate of the switch tube MN12).
[0118] The switch tubes MN11 and MN12 acting as common-gate tubes can further reduce the noise caused by data feedthrough and improve the equivalent impedance of the transmitter end looking toward the ground, ensuring that the impedance matching of the output stage is only related to the termination resistor network.
[0119] According to a second aspect of the present application, a data transmission method is provided. The data transmission method is applied to the current mode multiplexing type transmission final stage in any of the above embodiments. The data transmission method includes the following steps performed by the current mode multiplexing type transmission final stage:
[0120] Acquire a clock signal output by a clock buffer link, first processed data at half the rate output by a first data buffer link, and second processed data at half the rate output by a second data buffer link;
[0121] Integrate the first processed data and the second processed data according to the clock signal to obtain full-rate target data;
[0122] Transmit the target data.
[0123] According to the third aspect of this application, Figure 1 As shown, a half-rate data transmitter is provided, and the half-rate data transmitter includes the current mode multiplexing type transmitting final stage in any one of the above embodiments.
[0124] In the half-rate data transmitter of the embodiment of the present application, the function of the current mode multiplexer is integrated into the transmitting final stage, and the first input terminal and the second input terminal of the current mode multiplexing transmitting final stage are respectively used to electrically connect to the output terminal of the first data buffer link and the output terminal of the second data buffer link, so that the current mode multiplexing transmitting final stage serves as the latter stage of the data buffer link. For the data buffer link as the former stage, there is no need to adopt the current mode type, thereby reducing the power consumption corresponding to the data buffer link, and further reducing the difficulty of the overall power consumption management of the half-rate data transmitter.
[0125] Optional, such as Fig. 9 As shown, the half rate data transmitter also includes a clock buffer final stage.
[0126] Among them, Fig. 9 In the embodiment, the clock buffer final stage comprises an input terminal electrically connected to a first output terminal of the clock buffer link and an output terminal electrically connected to a third input terminal of the current mode multiplexing type transmitting final stage.
[0127] The clock buffer final stage is used to reduce the swing of the clock signal input to the clock buffer link, and then output the clock signal with the reduced swing to the current mode multiplexing type transmitting final stage.
[0128] Among them, Figure 1 In the corresponding embodiment, the first output end of the clock buffer link is directly electrically connected to the third input end of the current mode multiplexing type transmitting final stage. However, the swing of the clock signal directly output by the clock buffer link has not been processed and adjusted, and it is easy to generate burrs. Therefore, in this embodiment, a clock buffer final stage dedicated to reducing the swing of the clock signal is added, so that the first output end of the clock buffer link is electrically connected to the third input end of the current mode multiplexing type transmitting final stage through the clock buffer final stage, thereby solving the burr problem to a certain extent.
[0129] Specifically, the clock buffer final stage directly converts the full-swing differential clock signal of the clock buffer link input into a clock signal with a lower swing, which helps to reduce the invalid input swing of the clock-controlled switch tube in the current-mode multiplexing transmitting final stage when only one side is turned on during the switching process. However, it should be noted that the voltage swing of the low-swing clock signal still needs to be greater than the threshold voltage of the clock-controlled switch tube.
[0130] Optional, such as Fig.10 As shown, the clock buffer final stage includes a clock buffer and a voltage regulator.
[0131] Among them, Fig.10 In the embodiment, the clock buffer includes an input terminal electrically connected to a first output terminal of a clock buffer link, an output terminal electrically connected to a third input terminal of a current mode multiplexing type transmitting final stage, and a ground terminal electrically connected to a first access terminal of a voltage regulator, and the voltage regulator also includes a second access terminal for grounding.
[0132] Optional, such as Fig.11 As shown, the voltage regulator includes a front-stage operational amplifier amp and a current adjustment switch tube MN_power, and the clock buffer includes switch tubes MP0, MP1, MP2, MP3, MN20, MN21, MN22, and MN23.
[0133] Among them, Fig.11 In the figure, the front-stage operational amplifier amp includes a first input terminal electrically connected to the ground terminal of the clock buffer (such as the second source and drain of the switch tube MN20, the second source and drain of the switch tube MN21, the second source and drain of the switch tube MN22, and the second source and drain of the switch tube MN23) and the first source and drain of the current adjustment switch tube MN_power, a second input terminal for accessing the second reference voltage vref_vssl, and an output terminal electrically connected to the gate of the current adjustment switch tube MN_power, and the current adjustment switch tube MN_power also includes a second source and drain for grounding.
[0134] The clock buffer final stage is used to reduce the swing of the full-swing clock signals ckn_in and ckp_in input by the clock buffer link, thereby outputting lower-swing clock signals ckn_out and ckp_out to the current-mode multiplexing type transmitting final stage.
[0135] Optional, such as Fig.11 As shown, the voltage regulator further includes a phase compensation resistor R1 and a phase compensation capacitor C1.
[0136] Among them, Fig.11In the embodiment, the phase compensation resistor R1 includes a first access terminal electrically connected to the output terminal of the previous operational amplifier amp and the gate of the current adjustment switch tube MN_power respectively, and a second access terminal electrically connected to the first access terminal of the phase compensation capacitor C1, and the phase compensation capacitor C1 also includes a second access terminal for grounding.
[0137] Among them, the phase compensation resistor R1 and the phase compensation capacitor C1 will constitute a phase boost compensation, and the additional left half plane zeros introduced will be beneficial to the stability of the voltage stabilization loop.
[0138] Optional, such as Fig.11 As shown, the voltage regulator further includes a ripple suppression capacitor C2.
[0139] Among them, Fig.11 In the figure, the ripple suppression capacitor C2 includes a first access end electrically connected to the first input end of the previous operational amplifier amp, the ground end of the clock buffer (such as the second source and drain of the switch tube MN20, the second source and drain of the switch tube MN21, the second source and drain of the switch tube MN22, and the second source and drain of the switch tube MN23), and the first source and drain of the current adjustment switch tube MN_power, and a second access end for grounding.
[0140] The ripple suppression capacitor C2 is helpful to reduce the ripple of the ground potential and avoid introducing additional clock jitter.
[0141] Optional, such as Fig.11 As shown, the clock buffer final stage further includes an adjustable current source prog_current.
[0142] Among them, Fig.11 The adjustable current source prog_current includes a first access terminal electrically connected to the output terminal of the clock buffer and the third input terminal of the current mode multiplexing type transmitting final stage respectively, so as to output clock signals ckn_out and ckp_out with lower swing amplitude. The adjustable current source prog_current also includes a second access terminal for grounding.
[0143] in, Fig.12 The circuit diagram of the adjustable current source prog_current adopts the source switch solution for current size control, which adjusts the rising and falling edge speeds of the clock at the final stage of the clock buffer, thereby changing the overlap point of the output differential clock signal. An appropriate number of clock high overlap points can offset the equivalent common-mode noise input when the clock-controlled switch tube in the current-mode multiplexing transmitter final stage switches, while an excessive number of clock high overlap points will cause the data edge speed to slow down and introduce additional data edge distortion, so the overlap point needs to be adjusted reasonably.
[0144] Optional, such as Fig.11As shown, the final stage of the clock buffer further includes a drain switch MP_lowfreq and a drain resistor R_lowfreq.
[0145] Among them, Fig.11 In the embodiment, the drainage switch tube MP_lowfreq includes a first source and drain electrically connected to the power supply end of the clock buffer, a second source and drain electrically connected to the first access end of the drainage resistor R_lowfreq, and a gate for accessing the drainage control signal. The drainage resistor R_lowfreq also includes a second access end electrically connected to the ground end of the clock buffer (such as the second source and drain of the switch tube MN20, the second source and drain of the switch tube MN21, the second source and drain of the switch tube MN22, and the second source and drain of the switch tube MN23) and the first access end of the regulator (including the first input end of the pre-stage operational amplifier amp and the first source and drain of the current adjustment switch tube MN_power).
[0146] Among them, at a lower operating frequency, the drain switch tube MP_lowfreq can be selected to be turned on, so that the static current introduced by the drain resistor R_lowfreq ensures the current lower limit of the power tube, which is beneficial to the stability of the voltage stabilization loop.
[0147] Optional, such as Fig.13 As shown, the half-rate data transmitter includes a multi-bit to two-bit data serializer I5, a first CMOS logic data buffer link I3, a second CMOS logic data buffer link I4, a current mode multiplexing type transmission final stage I1, a CMOS logic clock buffer link I6 and a CMOS logic clock buffer final stage I2.
[0148] in, Fig.13 The key to reducing power consumption of the new half-rate data transmitter solution shown is to directly use the current-mode multiplexer front-stage circuit required by the traditional half-rate data transmitter as the transmitter final-stage circuit, and eliminate the original large number of current-mode data buffer links with high static power consumption. Only the last stage of the entire system is a current-mode circuit, and the replaced CMOS logic data buffer link and CMOS logic clock buffer final stage have lower power consumption.
[0149] According to a fourth aspect of the present application, a communication system is provided, the communication system comprising the half-rate data transmitter in any one of the above embodiments.
[0150] In the communication system of the embodiment of the present application, the function of the current mode multiplexer is integrated into the transmitting final stage, and the first input terminal and the second input terminal of the current mode multiplexing transmitting final stage are respectively used to electrically connect to the output terminal of the first data buffer link and the output terminal of the second data buffer link, so that the current mode multiplexing transmitting final stage serves as the latter stage of the data buffer link. For the data buffer link serving as the former stage, there is no need to adopt the current mode type, thereby reducing the power consumption corresponding to the data buffer link, and further reducing the difficulty of overall power consumption management of the half-rate data transmitter.
[0151] According to a fifth aspect of the present application, a vehicle is provided, the vehicle comprising the communication system in any one of the above embodiments.
[0152] In the vehicle of the embodiment of the present application, the function of the current mode multiplexer is integrated into the transmitting final stage, and the first input terminal and the second input terminal of the current mode multiplexing transmitting final stage are respectively used to electrically connect to the output terminal of the first data buffer link and the output terminal of the second data buffer link, so that the current mode multiplexing transmitting final stage serves as the latter stage of the data buffer link. For the data buffer link as the former stage, there is no need to adopt the current mode type, thereby reducing the power consumption corresponding to the data buffer link, and further reducing the difficulty of the overall power consumption management of the half-rate data transmitter.
[0153] The vehicle can be a pure fuel vehicle, or a pure electric vehicle, a plug-in hybrid vehicle, an extended-range hybrid vehicle or other new energy vehicle, and this application does not make any specific limitations on this.
[0154] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.
[0155] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.
[0156] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.
[0157] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. In the embodiments of the present application, the description of each embodiment has its own focus. For the parts not described in detail in a certain embodiment, please refer to the relevant contents of other embodiments. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.
Claims
1. A current mode multiplexing type transmitting final stage, characterized in that: The current mode multiplexing type transmitting final stage comprises a first input terminal for electrically connecting to the output terminal of the first data buffer link, a second input terminal for electrically connecting to the output terminal of the second data buffer link, a third input terminal for electrically connecting to the first output terminal of the clock buffer link, and an output terminal for outputting target data; The current-mode multiplexing type transmission final stage is used to integrate the half-rate first processed data output by the first data buffer link and the half-rate second processed data output by the second data buffer link according to the clock signal output by the clock buffer link, to obtain full-rate target data, and transmit the target data.
2. The current mode multiplexing type transmitting final stage according to claim 1, characterized in that: The current mode multiplexing type transmitting final stage comprises a current mode multiplexer and a current mode transmitting final stage; The current mode multiplexer includes a first input terminal for electrically connecting to an output terminal of the first data buffer link, a second input terminal for electrically connecting to an output terminal of the second data buffer link, a third input terminal for electrically connecting to a first output terminal of the clock buffer link, and an output terminal electrically connecting to an input terminal of the current mode transmitting final stage; The current-mode transmission final stage also includes an output terminal for outputting the target data.
3. The current mode multiplexing type transmitting final stage according to claim 2, characterized in that: The current mode multiplexer comprises a first data switch tube group, a second data switch tube group, a clock switch tube group and a current adjustment unit; The first data switch tube group includes a driving end electrically connected to the output end of the first data buffer link, a first access end electrically connected to the input end of the current mode transmitter final stage, and a second access end electrically connected to the first access end of the clock switch tube group; The second data switch tube group includes a driving end electrically connected to the output end of the second data buffer link, a first access end electrically connected to the input end of the current mode transmitter final stage, and a second access end electrically connected to the first access end of the clock switch tube group; The current adjustment unit comprises a first access terminal electrically connected to the second access terminal of the clock switch tube group and a second access terminal for grounding; The clock switch tube group also includes a driving end for electrically connecting to the first output end of the clock buffer link.
4. The current mode multiplexing type transmitting final stage according to claim 3, characterized in that: The current mode multiplexer also includes an isolation inductor; The isolation inductor includes a first access terminal electrically connected to the second access terminal of the clock switch tube group and a second access terminal electrically connected to the first access terminal of the current adjustment unit.
5. The current mode multiplexing type transmitting final stage according to claim 4, characterized in that: The current adjustment unit includes an adjustable resistance unit and a calibration logic unit; The adjustable resistance unit includes a first access terminal electrically connected to the second access terminal of the isolation inductor, a second access terminal for grounding, and a control terminal electrically connected to the output terminal of the calibration logic unit.
6. The current mode multiplexing type transmitting final stage according to claim 5, characterized in that: The adjustable resistance unit includes a plurality of shunt resistors connected in parallel and a control switch tube corresponding to each of the shunt resistors; Each of the shunt resistors includes a first access end electrically connected to the second access end of the isolation inductor and a second access end electrically connected to the first access end of the corresponding control switch tube. Each of the control switch tubes also includes a second access end for grounding and a driving end electrically connected to the corresponding output end of the calibration logic unit.
7. The current mode multiplexing type transmitting final stage according to claim 5, characterized in that: The current adjustment unit also includes a comparator; The comparator includes a first input terminal electrically connected to the first access terminal of the first data switch tube group, the first access terminal of the second data switch tube group and the input terminal of the current-mode emission final stage respectively, a second access terminal for accessing a first reference voltage, and an output terminal electrically connected to the input terminal of the calibration logic unit.
8. The current mode multiplexing type transmitting final stage according to any one of claims 3 to 7, characterized in that: The current mode multiplexer also includes a first feedthrough compensation switch tube group and a second feedthrough compensation switch tube group; The first feedthrough cancellation switch tube group includes a driving end electrically connected to the output end of the first data buffer link and a first access end electrically connected to the input end of the current mode transmitting final stage; The second feedthrough cancellation switch tube group includes a driving end electrically connected to the output end of the second data buffer link and a first access end electrically connected to the input end of the current-mode transmitting final stage.
9. The current mode multiplexing type transmitting final stage according to any one of claims 3 to 7, characterized in that: The current mode multiplexer also includes a common-gate switch tube group; The common-gate switch tube group includes a first access terminal electrically connected to the input terminal of the current-mode emission final stage, a second access terminal electrically connected to the first access terminal of the first data switch tube group and the first access terminal of the second data switch tube group respectively, and a driving terminal for accessing a working voltage.
10. A data transmission method, characterized in that: The data transmission method is applied to the current mode multiplexing type transmission final stage according to any one of claims 1 to 9; the data transmission method comprises the following steps performed by the current mode multiplexing type transmission final stage: Acquire a clock signal output by a clock buffer link, first processed data at half the rate output by a first data buffer link, and second processed data at half the rate output by a second data buffer link; Integrating the first processed data and the second processed data according to the clock signal to obtain full-rate target data; Data transmission is performed on the target data.
11. A half-rate data transmitter, characterized in that: The half-rate data transmitter comprises a first data buffer link, a second data buffer link, a clock buffer link, and a current mode multiplexing type transmitting final stage as claimed in any one of claims 1 to 9.
12. The half-rate data transmitter according to claim 11, characterized in that The half-rate data transmitter also includes a clock buffer final stage; The clock buffer final stage comprises an input terminal for electrically connecting to a first output terminal of the clock buffer link and an output terminal electrically connecting to a third input terminal of the current mode multiplexing type transmitting final stage; The clock buffer final stage is used to reduce the swing of the clock signal input by the clock buffer link, and then output the clock signal with the reduced swing to the current mode multiplexing type transmitting final stage.
13. The half-rate data transmitter according to claim 12, characterized in that The clock buffer final stage includes a clock buffer and a voltage regulator; The clock buffer includes an input terminal electrically connected to the first output terminal of the clock buffer link, an output terminal electrically connected to the third input terminal of the current-mode multiplexing type transmitting final stage, and a ground terminal electrically connected to the first access terminal of the regulator, and the regulator also includes a second access terminal for grounding.
14. The half-rate data transmitter according to claim 13, characterized in that The voltage stabilizer includes a front-stage operational amplifier and a current adjustment switch tube; The front-stage operational amplifier includes a first input terminal electrically connected to the ground terminal of the clock buffer and the first access terminal of the current adjustment switch tube respectively, a second input terminal for accessing a second reference voltage, and an output terminal electrically connected to the driving end of the current adjustment switch tube, and the current adjustment switch tube also includes a second access terminal for grounding.
15. The half-rate data transmitter according to claim 14, characterized in that The voltage stabilizer also includes a phase compensation resistor and a phase compensation capacitor; The phase compensation resistor includes a first access end electrically connected to the output end of the previous operational amplifier and the driving end of the current adjustment switch tube respectively, and a second access end electrically connected to the first access end of the phase compensation capacitor, and the phase compensation capacitor also includes a second access end for grounding.
16. The half-rate data transmitter according to claim 14, characterized in that The voltage stabilizer also includes a ripple suppression capacitor; The ripple suppression capacitor comprises a first access terminal electrically connected to the first input terminal of the pre-stage operational amplifier, the ground terminal of the clock buffer and the first access terminal of the current adjustment switch tube respectively, and a second access terminal for grounding.
17. The half-rate data transmitter according to claim 13, characterized in that The clock buffer final stage also includes an adjustable current source; The adjustable current source comprises a first access terminal electrically connected to the output terminal of the clock buffer and the third input terminal of the current mode multiplexing type transmitting final stage respectively, and a second access terminal for grounding.
18. The half-rate data transmitter according to claim 13, characterized in that The clock buffer final stage also includes a drain switch tube and a drain resistor; The drain switch tube includes a first access terminal electrically connected to the power supply terminal of the clock buffer, a second access terminal electrically connected to the first access terminal of the drain resistor, and a driving terminal for accessing a drain control signal. The drain resistor also includes a second access terminal electrically connected to the ground terminal of the clock buffer and the first access terminal of the regulator respectively.
19. The half-rate data transmitter according to any one of claims 11 to 18, characterized in that: The half-rate data transmitter also includes a data serializer; The data serializer includes a first input terminal for accessing initial data, a second input terminal electrically connected to the second output terminal of the clock buffer link, a first output terminal electrically connected to the input terminal of the first data buffer link, and a second output terminal electrically connected to the input terminal of the second data buffer link.
20. A communication system, characterized in that: The communication system comprises the half-rate data transmitter according to any one of claims 11 to 19.
21. A vehicle, characterized in that: The vehicle comprises the communication system of claim 20.