Time slot boundary processing method, device and system, storage medium and program product
By receiving and converting GNSS timing information in the FPGA component of the communication system, and writing time slot boundary information into the memory of other modules using the PCIe bus, the problems of module redundancy and time-consuming in the prior art are solved, and more efficient time synchronization is achieved.
Patent Information
- Application Number
- CN202411143574.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-20
- Publication Date
- 2025-04-18
AI Technical Summary
In the time synchronization scheme of existing communication systems, there are many modules, redundant modules, and time-consuming problems.
By receiving GNSS timing information in the FPGA component of the communication system, it is converted into time slot boundary information, and writing this information into the memory of the first module other than the FPGA component with the time slot as a period.
It realizes the reduction of the number of modules used for time synchronization in the communication system, shortens the time consumption during the time synchronization process, and improves the efficiency and stability of the system.
Smart Images
Figure CN119853838A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of communication technology, and in particular to a time slot boundary processing method, device, system, storage medium and program product. Background Art
[0002] The synchronization of the communication system is to obtain timing information from the Global Navigation Satellite System (GNSS) timing system, convert the timing information into the required frame number, time slot number, etc. through different software or hardware, and distribute it to each module, so that the frame number and time slot number between each module of the system are consistent.
[0003] At present, the time slot boundary information technology scheme from timing system information to frame number and time slot number includes GNSS sending timing information to the driver, and the driver's software module converts the pulse per second (PPS) and current time (ToD) in the timing information into the frame number and time slot number required by the system and sends it to the erasable programmable logic device (EPLD), which is distributed to various software and hardware system modules through EPLD; or GNSS sends timing information to the central processing unit (CPU), and the CPU converts the PPS and ToD in the timing information into the frame number and time slot number required by the system, and sends the time slot boundary information to each module. The calculated frame number and time slot number can be transmitted to each module through a network card or other means, and each module performs subsequent calculations after receiving the time information. The above two schemes have the problems of requiring many modules, module redundancy, and long time consumption. Summary of the invention
[0004] The embodiments of the present application provide a time slot boundary processing method, device, system, storage medium and program product, which solve the problems of requiring multiple modules, module redundancy and long time consumption in existing time synchronization solutions.
[0005] In a first aspect, in order to achieve the above-mentioned purpose, an embodiment of the present application provides a time slot boundary processing method, which is applied to a field programmable gate array FPGA component of a communication system, and the method includes:
[0006] Receive timing information sent by the Global Navigation Satellite System (GNSS) timing system;
[0007] Converting the timing information into time slot boundary information;
[0008] The time slot boundary information is written into the memory of the first module of the communication system, where the first module is a module other than the FPGA component.
[0009] Optionally, the first module includes: one or more of: a physical layer, a media access control MAC layer, a driver module and an operation management OM module.
[0010] Optionally, writing the time slot boundary information into a memory of a first module of the communication system includes:
[0011] Taking the time slot as a cycle, the time slot boundary information obtained by the current conversion is written into the memory of the first module by using the high-speed serial computer bus PCIe.
[0012] Optionally, taking the time slot as a period and using the high-speed serial computer bus PCIe, writing the time slot boundary information obtained by the current conversion into the memory of the first module includes:
[0013] Writing the time slot boundary information obtained by the current conversion into PCIe, so that the PCIe writes the time slot boundary information into the memory of the first module;
[0014] Receiving a write completion signal fed back by the PCIe;
[0015] After receiving the write completion signal, a first value representing a flag bit being in a set state is written into the PCIe, so that the PCIe writes the first value into a memory storing the state of the flag bit in the first module, wherein the state of the flag bit is related to the writing status of the time slot boundary information in the memory.
[0016] Optionally, the method further comprises:
[0017] During the system initialization phase of the communication system, a memory address is read from a register, where the memory address is an address of a memory in the memory of the first module for storing the time slot boundary information.
[0018] In a second aspect, in order to achieve the above-mentioned object, an embodiment of the present application provides a time slot boundary processing method, which is applied to a first module of a communication system, and the method includes:
[0019] Checking the time slot boundary information in the memory of the first module; the time slot boundary information in the memory of the first module is written by the FPGA component;
[0020] When the time slot boundary information is checked and passed, the target operation is executed, and the target operation includes: sending the time slot boundary information to a second module, and / or performing data processing based on the time slot boundary information; wherein the second module is a module in the communication system other than the FPGA component and the first module.
[0021] Optionally, the first module includes: one or more of: a physical layer, a MAC layer, a driver module and an OM module.
[0022] Optionally, the method further comprises:
[0023] Writing the time slot boundary information transmitted by the FPGA component using PCIe into a memory storing the time slot boundary information; wherein the time slot boundary information is obtained by converting the timing information currently received by the FPGA component;
[0024] The first value transmitted by the FPGA component using the PCIe is written into the memory storing the status of the flag bit in the first module, wherein the status of the flag bit is related to the writing status of the time slot boundary information in the memory.
[0025] Optionally, checking the time slot boundary information in the memory of the first module includes:
[0026] When it is detected through polling that the time slot boundary information in the memory changes and the flag bit is set, the time slot boundary information in the memory of the first module is checked.
[0027] Optionally, checking the time slot boundary information in the memory of the first module includes:
[0028] Check whether the time slot boundary information detected in this polling differs from the time slot boundary information detected in the previous polling by 1 time slot;
[0029] Check whether the difference between the first time and the second time is within a preset range, wherein the first time is the time when the time slot boundary information is detected in this polling, the second time is the time when the time slot boundary information is detected in the last polling, and the preset range is related to the duration of 1 time slot;
[0030] Among them, the time slot boundary information detected in this polling differs from the time slot boundary information detected in the previous polling by 1 time slot, and the difference between the first time and the second time is within the preset range, determining that the time slot boundary information check has passed.
[0031] In a third aspect, in order to achieve the above-mentioned purpose, an embodiment of the present application provides a time slot boundary processing device, which is applied to a field programmable gate array FPGA component of a communication system, and the device includes:
[0032] A receiving module is used to receive timing information sent by the global navigation satellite system GNSS timing system;
[0033] A conversion module, used for converting the timing information into time slot boundary information;
[0034] A writing module is used to write the time slot boundary information into the memory of the first module of the communication system, and the first module is a module other than the FPGA component.
[0035] In a fourth aspect, in order to achieve the above-mentioned purpose, an embodiment of the present application provides a time slot boundary processing device, which is applied to a first module of a communication system, and the device includes:
[0036] A checking module, used for checking the time slot boundary information in the memory of the first module; the time slot boundary information in the memory of the first module is written by the FPGA component;
[0037] An execution module is used to execute a target operation when the time slot boundary information is checked and passed, and the target operation includes: sending the time slot boundary information to a second module, and / or performing data processing based on the time slot boundary information; wherein the second module is a module in the communication system other than the FPGA component and the first module.
[0038] In the fifth aspect, in order to achieve the above-mentioned purpose, an embodiment of the present application provides a communication system, including a transceiver, a processor, a memory, and a program stored in the memory and executable on the processor; when the processor executes the program, it implements the time slot boundary processing method as described in the first aspect, or implements the time slot boundary processing method as described in the second aspect.
[0039] In the sixth aspect, in order to achieve the above-mentioned purpose, an embodiment of the present application provides a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by the processor, the time slot boundary processing method as described in the first aspect is implemented, or the time slot boundary processing method as described in the second aspect is implemented.
[0040] In the seventh aspect, in order to achieve the above-mentioned purpose, an embodiment of the present application provides a computer program product, including computer instructions, which, when executed by a processor, implement the time slot boundary processing method as described by the first party Amin, or implement the time slot boundary processing method as described in the second aspect.
[0041] The beneficial effects of the above technical solution of the present application are as follows:
[0042] In the time slot boundary processing method of the embodiment of the present application, first, the FPGA component receives the timing information sent by the global navigation satellite system GNSS timing system; secondly, the FPGA component converts the timing information into time slot boundary information; finally, the FPGA component writes the time slot boundary information into the memory of the first module of the communication system, and the first module is a module other than the FPGA component. In this way, the timing information is converted into time slot boundary information by the FPGA component and sent to the first module that needs the time slot boundary information, so that the time synchronization process of the communication system requires fewer modules and takes less time. BRIEF DESCRIPTION OF THE DRAWINGS
[0043] Figure 1 This is one of the flowcharts of the time slot boundary processing method according to an embodiment of the present application;
[0044] Figure 2 A schematic diagram of generating time slot boundaries for an FPGA component in an embodiment of the present application;
[0045] Figure 3 A schematic diagram of writing time slot boundary information into a memory in an embodiment of the present application;
[0046] Figure 4 A schematic diagram of processing time slot boundaries by the first module in an embodiment of the present application;
[0047] Figure 5 This is a second flow chart of the time slot boundary processing method according to an embodiment of the present application;
[0048] Figure 6 The third flowchart of the time slot boundary processing method according to the embodiment of the present application;
[0049] Figure 7 This is one of the structural schematic diagrams of the time slot boundary processing device according to an embodiment of the present application;
[0050] Figure 8 This is a second structural diagram of the time slot boundary processing device according to an embodiment of the present application;
[0051] Fig. 9 A schematic diagram of the structure of a communication system according to an embodiment of the present application. DETAILED DESCRIPTION
[0052] In order to make the technical problems, technical solutions and advantages to be solved by the present application clearer, a detailed description will be given below with reference to the accompanying drawings and specific embodiments.
[0053] It should be understood that the references to "one embodiment" or "an embodiment" throughout the specification mean that the specific features, structures, or characteristics associated with the embodiment are included in at least one embodiment of the present application. Therefore, the references to "in one embodiment" or "in an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
[0054] In the various embodiments of the present application, it should be understood that the size of the serial numbers of the following processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.
[0055] Additionally, the terms "system" and "network" are often used interchangeably herein.
[0056] In the embodiments provided in the present application, it should be understood that "B corresponding to A" means that B is associated with A, and B can be determined according to A. However, it should also be understood that determining B according to A does not mean determining B only according to A, and B can also be determined according to A and / or other information.
[0057] The embodiment of the present application provides a time slot boundary processing method, which is applied to a field programmable gate array (FPGA) component of a communication system, such as Figure 1 As shown, the method includes:
[0058] Step 101, receiving timing information sent by a global navigation satellite system GNSS timing system; here, the timing information includes, for example, PPS and ToD;
[0059] Step 102, converting the timing information into time slot boundary information; here, the time slot boundary information includes, for example, a frame number and a time slot number required by the communication system; specifically, in this step, the FPGA component can convert the timing information into the time slot boundary information based on the communication system configuration;
[0060] Step 103, writing the time slot boundary information into the memory of the first module of the communication system, the first module being a module other than the FPGA component. Here, this step can also be described as: transmitting the time slot boundary information to the memory of the first module of the communication system; in addition, the first module in this step can be any module in the communication system that needs the time slot boundary information to perform an operation. In addition, the first module can also be called a first node or a first component, etc.
[0061] In the time slot boundary processing method of the embodiment of the present application, first, the FPGA component receives the timing information sent by the global navigation satellite system GNSS timing system; secondly, the FPGA component converts the timing information into time slot boundary information; finally, the FPGA component writes the time slot boundary information into the memory of the first module of the communication system, and the first module is a module other than the FPGA component. In this way, the timing information is converted into time slot boundary information through the FPGA component and sent to the first module that needs the time slot boundary information, so that the time synchronization process of the communication system requires fewer modules and takes less time.
[0062] Next, combine Figure 2 , the implementation process of the above step 102 of the present application is explained.
[0063] Here, it should be noted that the GNSS timing information is sent at a frequency of 1s, and the duration of the time slot may be 1ms, 500us, 250us, 125us, 62.5us, etc. according to different protocol parameters (numerologies). Obviously, this interval (the duration of 1slot) is smaller than the 1s interval of the GNSS timing system; therefore, the clock timing system of the FPGA component generates a frame number and a time slot number (time slot boundary) corresponding to the slot duration based on the GNSS timing information (such as second pulses). Among them, the time slot boundary diagram generated by the FPGA component in the horizontal time is as follows: Figure 2 As shown, the dotted box represents the generated time slot boundary information, which is not a real module.
[0064] As a specific implementation, the first module includes: one or more of a physical layer, a media access control (MAC) layer, a driver module, and an operation management (OM) module. As a preferred example, the first module is a physical layer.
[0065] As an optional implementation, step 103 includes:
[0066] Writing the time slot boundary information into the memory of the first module of the communication system includes:
[0067] The time slot boundary information obtained by the current conversion is written into the memory of the first module using a high-speed serial computer bus (peripheral component interconnect express, PCIe) with the time slot as a cycle.
[0068] Here, it should be noted that PCIe is a high-speed serial computer expansion bus, which belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission. In this optional implementation, the FPGA component writes the time slot boundary information into the memory of the first module through PCIe, which shortens the transmission path and reduces the transmission delay compared to transmitting the time slot boundary information through a network card, thereby reducing the probability of data loss.
[0069] As a specific implementation method, taking the time slot as a cycle and using the high-speed serial computer bus PCIe, the time slot boundary information obtained by the current conversion is written into the memory of the first module, including:
[0070] The time slot boundary information obtained by the current conversion is written into PCIe, so that the PCIe writes the time slot boundary information into the memory of the first module; Here, this step can also be described as: the FPGA component transmits the time slot boundary information obtained by the current conversion to PCIe, so that it is continuously written into the memory of the first module with the time slot as a period through the interface of the PCIe;
[0071] Receive the write completion signal fed back by the PCIe; here, Figure 3 As shown, after PCIe writes the time slot boundary information into the memory of the first module, it will feedback a write completion signal to the FPGA component ( Figure 3 (3) in step 3);
[0072] After receiving the write completion signal, a first value representing a flag bit in a set state is written into the PCIe, so that the PCIe writes the first value into a memory storing the state of the flag bit in the first module, wherein the state of the flag bit is related to the writing status of the time slot boundary information in the memory; for example, when the time slot boundary information is written to completion, the flag bit is set, and further, for example, after the first module detects that the flag bit is set, the first module can reset the flag bit so that after the time slot boundary information of the next cycle is successfully written into the memory of the first module, the FPGA component sets the flag bit again.
[0073] Here, it should be noted that in the embodiment of the present application, the memory storing time slot boundary information needs to be matched with the memory storing flag bits, for example: memory 1 is used to store time slot boundary information, memory 2 is used to store flag bits, and the memory address of memory 1 is associated with the memory address of memory 2.
[0074] Furthermore, as an optional implementation, the method further includes:
[0075] During the system initialization phase of the communication system, a memory address is read from a register, where the memory address is an address of a memory in the memory of the first module for storing the time slot boundary information.
[0076] That is, in this optional implementation, the first module needs to inform the FPGA component of the address of the memory used to store the time slot boundary information, such as Figure 3 As shown, the address can be notified to the FPGA component by writing to the register; in addition, the FPGA component reads the address from the register during the system initialization phase of the communication system, so that the process of the FPGA component reading the address has relatively little impact on the real-time task processing.
[0077] Below, taking the first module as the physical layer as an example, combined with Figure 3 The implementation process of the above two implementation methods (the process of the FPGA component writing the time slot boundary information into the first module) is illustrated by examples.
[0078] First, the physical layer writes the memory address used to store the time slot boundary information into a (fixed) register by writing a register, so that the FPGA component reads the memory address through the register during the system initialization phase; secondly, the FPGA component continuously writes the generated time slot boundary information into the memory through the PCIe interface with a time slot as a cycle. Specifically, Figure 3 As shown in the figure, the dotted line part represents the execution once when the system is initialized, when the frame number and time slot number are written into the memory ( Figure 3 After steps (1) and (2) in the above example, the FPGA component waits for the PCIe write completion signal ( Figure 3 After step (3) in the above, set the corresponding flag bit ( Figure 3 That is, the process of the FPGA component writing the time slot boundary information into the memory of the first module can be performed according to Figure 3 Execute steps (1) to (5) in .
[0079] The embodiment of the present application provides a time slot processing method, which is applied to a first module, such as Figure 4 As shown, the method includes:
[0080] Step 401, checking the time slot boundary information in the memory of the first module; the time slot boundary information in the memory of the first module is written by the FPGA component; here, the FPGA component can specifically write the time slot boundary information into the memory of the first module through PCIe;
[0081] The check in the above step may specifically be a continuity check and / or a timeout check of the time slot boundary information; this step can reduce the phenomenon of system freezing due to errors in the time slot boundary by checking the time slot boundary information;
[0082] Step 402, when the time slot boundary information is checked and passed, executing a target operation, the target operation includes: sending the time slot boundary information to a second module, and / or performing data processing based on the time slot boundary information; wherein the second module is a module in the communication system other than the FPGA component and the first module;
[0083] Here, performing data processing based on the time slot boundary information includes, for example: receiving uplink data based on the time slot boundary information; processing downlink data starting from the time slot boundary; or, when the first module is a physical layer, receiving signaling sent by the MAC layer;
[0084] The above steps execute the target operation after the check of the time slot boundary information is passed, so that it can be ensured that the communication system has a strictly identical timeline, thereby ensuring that subsequent tasks can be processed normally.
[0085] In the time slot processing method of the embodiment of the present application, first, the time slot boundary information in the memory of the first module is checked; the time slot boundary information in the memory of the first module is written by the FPGA component; secondly, if the time slot boundary information is checked and passed, the target operation is executed, and the target operation includes: sending the time slot boundary information to the second module, and / or, performing data processing based on the time slot boundary information; wherein, the second module is a module in the communication system other than the FPGA component and the first module; in this way, it is possible to prevent time interval anomalies such as false alarms, multiple alarms, and missed alarms of the time slot boundary information from the FPGA component to the first module, so as to ensure that the first module can obtain a strictly stable time slot boundary, while ensuring that other modules of the communication system can have a strictly identical time line, thereby ensuring that the timing of the system is stable and normal.
[0086] As a specific implementation, the first module includes: one or more of a physical layer, a MAC layer, a driver module, and an OM module. As a preferred example, the first module is a physical layer; wherein, when the first module is a physical layer, the second module is, for example, a MAC layer, a driver module, or an OM module; that is, as a preferred example, the FPGA component can transmit the time slot boundary information to the physical layer, so that the physical layer sends the time slot boundary information to other modules of the communication system.
[0087] As an optional implementation, the method further includes:
[0088] Writing the time slot boundary information transmitted by the FPGA component using PCIe into a memory storing the time slot boundary information; wherein the time slot boundary information is obtained by converting the timing information currently received by the FPGA component;
[0089] The first value transmitted by the FPGA component using the PCIe is written into the memory storing the status of the flag bit in the first module, wherein the status of the flag bit is related to the writing status of the time slot boundary information in the memory; for example, when the time slot boundary information is written, the flag bit is set, and further, for example, after the first module detects that the flag bit is set, the first module can reset the flag bit so that after the time slot boundary information of the next cycle is successfully written into the memory of the first module, the FPGA component will set the flag bit again.
[0090] As an optional implementation, step 401 includes:
[0091] When it is detected through polling that the time slot boundary information in the memory changes and the flag bit is set, the time slot boundary information in the memory of the first module is checked.
[0092] In this optional implementation, the first module not only detects changes in the flag bit, but also detects changes in the memory content corresponding to the flag bit. Only when both change at the same time, the first module determines that a new time slot boundary is written into the memory, thereby checking the new time slot boundary information, avoiding inaccurate inspection results due to misjudgment by the first module.
[0093] As a specific implementation manner, checking the time slot boundary information in the memory of the first module includes:
[0094] Check whether the time slot boundary information detected in this polling is different from the time slot boundary information detected in the previous polling by 1 time slot (slot); this step specifically checks the continuity of the time slot boundary information, and specifically the newly written time slot boundary information can be checked in the following manner:
[0095] oldFrame*numOfSlotInOneFrame+oldSlot+1;
[0096] newFrame*numOfSlotInOneFrame+newSlot;
[0097] Among them, numOfSlotInOneFrame indicates the number of time slots contained in one frame, oldSlot indicates the time slot number in the memory detected by the previous polling, newSlot indicates the time slot number in the memory detected by this polling, oldFrame indicates the frame number in the memory detected by the previous polling, and newFrame indicates the frame number in the memory detected by this polling. Normally, the calculation results of the above two formulas are the same. At this time, the subsequent timeout check process can be directly entered. Otherwise, it represents an abnormal situation, and the current processing is exited to enter the next time slot boundary processing waiting process;
[0098] Check whether the difference between the first time and the second time is within a preset range, wherein the first time is the time when the time slot boundary information is detected in this polling, the second time is the time when the time slot boundary information is detected in the previous polling, and the preset range is related to the duration of 1 time slot; this step specifically performs a timeout check on the time slot boundary information; here, the upper limit of the preset range is the sum of the duration of 1 slot and the first deviation value, and the lower limit of the preset range is the difference between the duration of 1 slot and the first deviation value;
[0099] That is to say, in the above steps, after passing the continuity check, a timeout check is performed. A time information can be maintained locally. When a new time slot boundary is detected, a time information is obtained. The time difference between the two times is obtained by taking the difference with the previous local time information. The difference is compared with a corresponding time range obtained based on the duration of 1slot. When the difference is within the range, it indicates normal and subsequent processing is performed. Otherwise, it indicates abnormality, and the current processing is exited to wait for the next time slot boundary processing.
[0100] Among them, the time slot boundary information detected in this polling differs from the time slot boundary information detected in the previous polling by 1 time slot, and the difference between the first time and the second time is within the preset range, determining that the time slot boundary information check has passed.
[0101] In the above optional implementation, when the physical layer polling detects that the data in the memory where the frame number and time slot number are located has changed and the flag is set, it means that a new time slot boundary has arrived, and the physical layer time slot boundary processing will be performed at this time. The physical layer checks the received new time slot boundary, mainly including continuity check and timeout check, to prevent time interval anomalies and time slot discontinuity, and reduce the phenomenon of system jamming caused by time slot boundary errors.
[0102] Next, combine Figure 5 , the process of checking the time slot boundary information by the first module is described:
[0103] Step 501, obtaining new time slot boundary information;
[0104] Step 502, continuity check, if the check passes, execute step 503, if the check fails, end the current check process and enter the next time slot boundary processing waiting process; wherein, the continuity check is used to check whether the time information newly polled this time increases by 1 compared with the previous time, if so, the check passes, if not, the check fails;
[0105] Step 503, timeout check, if the check passes, execute step 504, if the check fails, end the current check process and enter the next time slot boundary processing waiting process; wherein, the timeout check is used to check whether the time difference between two adjacent timeslot boundary information acquisitions is within a preset range related to the duration length of 1slot, if yes, the check passes, if not, the check fails;
[0106] Step 504, executing subsequent processes.
[0107] It should be noted here that in the communication system, the transmission and processing of data is carried out in units of time slots. Only when each module, especially the physical layer, processes data strictly in accordance with the timing of slots can the normal and stable operation of the communication system be guaranteed. Therefore, it is particularly important to obtain a correct and stable time slot boundary. Based on this, the embodiment of the present application provides a time slot boundary processing method, and specifically provides a physical layer time slot boundary processing mechanism based on the architecture of the existing large-scale antenna system, based on GNSS and FPGA components, to ensure that the physical layer can obtain strict and stable time slot boundaries, while ensuring that other modules of the communication system, such as FPGA components and MAC, have strictly the same timeline. Taking the first module as the physical layer and the second module as the MAC layer as an example, combined with Figure 6 , the implementation process of the embodiment of the present application is explained: the GNSS timing FPGA component every 1s, the FPGA component takes this as a benchmark, and uses the clock timing module to convert the timing information into time slot boundary information (frame number, time slot number) in units of time slots according to the communication system configuration. The FPGA component writes the generated time slot boundary information into the physical layer memory corresponding to the memory address informed by the physical layer (an example of the first module) of the FPGA component when the system is initialized. After the physical layer detects changes in the flag bit and the content in the memory, it performs continuity checks and timeout checks. Only after the check is completed, the physical layer performs subsequent processing as required (such as informing the MAC layer of the time slot boundary information).
[0108] In the time slot boundary processing method of the embodiment of the present application, first, the FPGA component is used to receive the GNSS timing information, and the FPGA component directly converts the timing information and generates the corresponding time slot boundary information, and forwards it to each software and hardware node (such as the first module mentioned above), which is simple to implement, reduces the modules required in the time slot boundary information transmission process, and avoids module redundancy. Second, through the PCIe interface, the FPGA component puts the time slot boundary information into the memory of the first module, passes through fewer nodes, has a low error rate, and improves real-time performance. And the FPGA group will not write the flag bit and the time slot boundary information at the same time, but waits to receive the feedback signal of the completion of the PCIe writing the time slot boundary information before writing the flag bit. And the above memory address is allocated to the FPGA component only in the system initialization stage, so as to have little impact on the real-time task processing. Third, the first module not only detects the change of the flag bit, but also detects the change of the corresponding time slot boundary memory content. Only when both change at the same time, it is determined that a new time slot boundary has arrived. Avoid system freezes due to incorrect time slot boundary information; fourthly, the physical layer will perform continuity checks and timeout checks when it receives new time slot boundaries to prevent time interval anomalies and time slot discontinuities, reduce system freezes due to time slot boundary errors, and ensure normal processing of subsequent tasks.
[0109] That is to say, the time slot boundary processing method of the embodiment of the present application uses a hardware FPGA component to complete the conversion of the received GNSS1PPS and ToD timing information and timing information to the frame number, time slot number and other information required by the system. It is simple to implement, requires fewer modules, has high system stability, and takes less time. The converted frame number and time slot number are directly placed in the memory through PCIe, and at the same time, the first module is informed through the flag bit. The transmission delay is short, the implementation is simple, and no additional network card support is required, which simplifies the implementation mechanism. At the same time, only when the content in the memory changes and the flag bit is set, it is defined as the arrival of new time slot information, and the definition standard is higher. In addition, in order to prevent the false reporting, over-reporting, omission and other time interval anomalies of the time slot boundary information from the FPGA component to the physical layer, the physical layer performs continuity checks and timeout checks to further ensure the stability and normality of the system timing. This solution has strong applicability, simple structure, and clear logic.
[0110] The embodiment of the present application also provides a time slot boundary processing device, which is applied to an FPGA component of a communication system, such as Figure 7 As shown, the device comprises:
[0111] The receiving module 701 is used to receive the timing information sent by the global navigation satellite system GNSS timing system;
[0112] A conversion module 702, configured to convert the timing information into time slot boundary information;
[0113] The writing module 703 is used to write the time slot boundary information into the memory of the first module of the communication system, and the first module is a module other than the FPGA component.
[0114] Optionally, the first module includes: one or more of: a physical layer, a media access control MAC layer, a driver module and an operation management OM module.
[0115] Optionally, the writing module 703 includes:
[0116] The writing submodule is used to write the time slot boundary information obtained by the current conversion into the memory of the first module using the high-speed serial computer bus PCIe with the time slot as a period.
[0117] Optionally, the writing submodule is specifically used to: write the time slot boundary information obtained by the current conversion into PCIe, so that the PCIe writes the time slot boundary information into the memory of the first module;
[0118] Receiving a write completion signal fed back by the PCIe;
[0119] After receiving the write completion signal, a first value representing a flag bit being in a set state is written into the PCIe, so that the PCIe writes the first value into a memory storing the state of the flag bit in the first module, wherein the state of the flag bit is related to the writing status of the time slot boundary information in the memory.
[0120] Furthermore, the device also includes:
[0121] A reading module is used to read a memory address from a register during the system initialization phase of the communication system, wherein the memory address is an address of a memory in the memory of the first module for storing the time slot boundary information.
[0122] It should be noted here that the above-mentioned time slot boundary processing device provided in the embodiment of the present application can implement all the method steps implemented in the above-mentioned time slot boundary processing method embodiment applied to FPGA components, and can achieve the same technical effect. The parts and beneficial effects of this embodiment that are the same as the method embodiment will not be described in detail here.
[0123] The embodiment of the present application also provides a time slot boundary processing device, which is applied to a first module of a communication system, such as Figure 8 As shown, the device comprises:
[0124] The checking module 801 is used to check the time slot boundary information in the memory of the first module; the time slot boundary information in the memory of the first module is written by the FPGA component;
[0125] The execution module 802 is used to execute the target operation when the time slot boundary information is checked and passed, and the target operation includes: sending the time slot boundary information to the second module, and / or performing data processing based on the time slot boundary information; wherein the second module is a module in the communication system other than the FPGA component and the first module.
[0126] Optionally, the first module includes: one or more of: a physical layer, a MAC layer, a driver module and an OM module.
[0127] Optionally, the device further comprises:
[0128] A first writing module is used to write the time slot boundary information transmitted by the FPGA component using PCIe into a memory storing the time slot boundary information; wherein the time slot boundary information is obtained by converting the timing information currently received by the FPGA component;
[0129] The second writing module is used to write the first value transmitted by the FPGA component using the PCIe into the memory storing the status of the flag bit in the first module, wherein the status of the flag bit is related to the writing status of the time slot boundary information in the memory.
[0130] Optionally, the checking module 801 is specifically used for: when it is detected through polling that the time slot boundary information in the memory has changed and the flag bit is set, checking the time slot boundary information in the memory of the first module.
[0131] Optionally, when the checking module 801 is used to check the time slot boundary information in the memory of the first module, it is specifically used to:
[0132] Check whether the time slot boundary information detected in this polling differs from the time slot boundary information detected in the previous polling by 1 time slot;
[0133] Check whether the difference between the first time and the second time is within a preset range, wherein the first time is the time when the time slot boundary information is detected in this polling, the second time is the time when the time slot boundary information is detected in the last polling, and the preset range is related to the duration of 1 time slot;
[0134] Among them, when the time slot boundary information detected in this polling differs by 1 time slot from the time slot boundary information detected in the previous polling, and the difference between the first time and the second time is within the preset range, it means that the time slot boundary information check has passed.
[0135] It should be noted here that the above-mentioned time slot boundary processing device provided in the embodiment of the present application can implement all the method steps implemented by the above-mentioned time slot boundary processing method embodiment applied to the first module, and can achieve the same technical effect. The parts and beneficial effects of this embodiment that are the same as the method embodiment will not be described in detail here.
[0136] An embodiment of the present application also provides a communication system, including a transceiver 910, a processor 900, a memory 920, and a program stored in the memory 920 and executable on the processor 900; wherein, when the processor 900 executes the program, it implements the time slot boundary processing method applied to the FPGA component as described above, or implements the time slot boundary processing method applied to the first module as described above.
[0137] The transceiver 910 is used to receive and send data under the control of the processor 900.
[0138] Among them, Fig. 9 In the embodiment, the bus architecture may include any number of interconnected buses and bridges, specifically linking various circuits of one or more processors represented by processor 900 and memory represented by memory 920. The bus architecture may also link various other circuits such as peripherals, voltage regulators, and power management circuits together, which are well known in the art and are therefore not further described herein. The bus interface provides an interface. The transceiver 910 may be a plurality of components, namely, a transmitter and a receiver, providing a unit for communicating with various other devices on a transmission medium. For different devices, the processor 900 is responsible for managing the bus architecture and general processing, and the memory 920 may store data used by the processor 900 when performing operations.
[0139] The embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by the processor, the time slot boundary processing method applied to the FPGA component as described above is implemented, or the time slot boundary processing method applied to the first module as described above is implemented, and the same technical effect can be achieved. To avoid repetition, it is not repeated here. Among them, the readable storage medium, such as a read-only memory (Read-Only Memory, referred to as ROM), a random access memory (Random Access Memory, referred to as RAM), a disk or an optical disk, etc.
[0140] An embodiment of the present application also provides a computer program product, including computer instructions, which, when executed by a processor, implement the time slot boundary processing method applied to the FPGA component as described above, or implement the time slot boundary processing method applied to the first module as described above, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.
[0141] In the embodiment of the present application, module can be implemented with software so that it can be executed by various types of processors. For example, an executable code module of an identification can include one or more physical or logical blocks of computer instructions, for example, it can be constructed as an object, process or function. Nevertheless, the executable code of the identified module does not need to be physically located together, but can include different instructions stored in different positions, and when these instructions are logically combined together, it constitutes a module and realizes the specified purpose of the module.
[0142] In fact, executable code module can be a single instruction or many instructions, and can even be distributed on a plurality of different code segments, distributed among different programs, and distributed across a plurality of memory devices. Similarly, operating data can be identified in the module, and can be implemented and organized in the data structure of any appropriate type according to any appropriate form. The operating data can be collected as a single data set, or can be distributed in different locations (including on different storage devices), and can only be present on a system or network as an electronic signal at least in part.
[0143] When a module can be implemented by software, considering the level of existing hardware technology, a person skilled in the art can build a corresponding hardware circuit to implement the corresponding function of the module that can be implemented by software without considering the cost. The hardware circuit includes a conventional very large scale integration (VLSI) circuit or gate array and existing semiconductors such as logic chips, transistors, or other discrete components. The module can also be implemented by a programmable hardware device, such as a field programmable gate array, a programmable array logic, a programmable logic device, etc.
[0144] The above exemplary embodiments are described with reference to the accompanying drawings, and many different forms and embodiments are feasible without departing from the spirit and teachings of the present application. Therefore, the present application should not be constructed as a limitation of the exemplary embodiments proposed herein. More specifically, these exemplary embodiments are provided so that the present application will be perfect and complete, and the scope of the present application will be conveyed to those who are familiar with the technology. In these figures, the component sizes and relative sizes may be exaggerated for clarity. The terms used here are only based on the purpose of describing specific exemplary embodiments and are not intended to be limiting. As used herein, unless the text clearly indicates otherwise, the singular forms "one", "an" and "the" are intended to include these multiple forms. It will be further understood that the terms "comprising" and / or "including" when used in this specification indicate the presence of the features, integers, steps, operations, components and / or components, but do not exclude the presence or increase of one or more other features, integers, steps, operations, components, components and / or their groups. Unless otherwise indicated, when stated, a range of values includes the upper and lower limits of that range and any subranges therebetween.
[0145] The above is a preferred embodiment of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.
Claims
1. A time slot boundary processing method, characterized in that: A field programmable gate array (FPGA) component applied to a communication system, the method comprising: Receive timing information sent by the Global Navigation Satellite System (GNSS) timing system; Converting the timing information into time slot boundary information; The time slot boundary information is written into the memory of the first module of the communication system, where the first module is a module other than the FPGA component.
2. The method according to claim 1, characterized in that The first module includes: one or more of: a physical layer, a media access control MAC layer, a driver module and an operation management OM module.
3. The method according to claim 1, characterized in that Writing the time slot boundary information into the memory of the first module of the communication system includes: Taking the time slot as a cycle, the time slot boundary information obtained by the current conversion is written into the memory of the first module by using the high-speed serial computer bus PCIe.
4. The method according to claim 3, characterized in that Taking the time slot as a cycle, using the high-speed serial computer bus PCIe, writing the time slot boundary information obtained by the current conversion into the memory of the first module, including: Writing the time slot boundary information obtained by the current conversion into PCIe, so that the PCIe writes the time slot boundary information into the memory of the first module; Receiving a write completion signal fed back by the PCIe; After receiving the write completion signal, a first value representing a flag bit being in a set state is written into the PCIe, so that the PCIe writes the first value into a memory storing the state of the flag bit in the first module, wherein the state of the flag bit is related to the writing status of the time slot boundary information in the memory.
5. The method according to claim 1, characterized in that The method further comprises: During the system initialization phase of the communication system, a memory address is read from a register, where the memory address is an address of a memory in the memory of the first module for storing the time slot boundary information.
6. A time slot boundary processing method, characterized in that: The first module applied to the communication system, the method comprising: Checking the time slot boundary information in the memory of the first module; the time slot boundary information in the memory of the first module is written by the FPGA component; When the time slot boundary information is checked and passed, the target operation is executed, and the target operation includes: sending the time slot boundary information to a second module, and / or performing data processing based on the time slot boundary information; wherein the second module is a module in the communication system other than the FPGA component and the first module.
7. The method according to claim 6, characterized in that The first module includes: one or more of: a physical layer, a MAC layer, a driver module and an OM module.
8. The method according to claim 6, characterized in that The method further comprises: Writing the time slot boundary information transmitted by the FPGA component using PCIe into a memory storing the time slot boundary information; wherein the time slot boundary information is obtained by converting the timing information currently received by the FPGA component; The first value transmitted by the FPGA component using the PCIe is written into the memory storing the status of the flag bit in the first module, wherein the status of the flag bit is related to the writing status of the time slot boundary information in the memory.
9. The method according to claim 8, characterized in that Checking the time slot boundary information in the memory of the first module includes: When it is detected through polling that the time slot boundary information in the memory changes and the flag bit is set, the time slot boundary information in the memory of the first module is checked.
10. The method according to claim 6 or 9, characterized in that: Checking the time slot boundary information in the memory of the first module includes: Check whether the time slot boundary information detected in this polling differs from the time slot boundary information detected in the previous polling by 1 time slot; Check whether the difference between the first time and the second time is within a preset range, wherein the first time is the time when the time slot boundary information is detected in this polling, the second time is the time when the time slot boundary information is detected in the last polling, and the preset range is related to the duration of 1 time slot; Among them, the time slot boundary information detected in this polling differs from the time slot boundary information detected in the previous polling by 1 time slot, and the difference between the first time and the second time is within the preset range, determining that the time slot boundary information check has passed.
11. A time slot boundary processing device, characterized in that: An FPGA component applied to a communication system, the device comprising: A receiving module is used to receive timing information sent by the global navigation satellite system GNSS timing system; A conversion module, used for converting the timing information into time slot boundary information; A writing module is used to write the time slot boundary information into the memory of the first module of the communication system, and the first module is a module other than the FPGA component.
12. A time slot boundary processing device, characterized in that: A first module applied to a communication system, the device comprising: A checking module, used for checking the time slot boundary information in the memory of the first module; the time slot boundary information in the memory of the first module is written by the FPGA component; An execution module is used to execute a target operation when the time slot boundary information is checked and passed, and the target operation includes: sending the time slot boundary information to a second module, and / or performing data processing based on the time slot boundary information; wherein the second module is a module in the communication system other than the FPGA component and the first module.
13. A communication system comprising a transceiver, a processor, a memory, and a program stored in the memory and executable on the processor; characterized in that: When the processor executes the program, the time slot boundary processing method according to any one of claims 1 to 5 is implemented, or the time slot boundary processing method according to any one of claims 6 to 10 is implemented.
14. A readable storage medium having a program or instruction stored thereon, characterized in that: When the program or instruction is executed by the processor, the time slot boundary processing method as described in any one of claims 1 to 5 is implemented, or the time slot boundary processing method as described in any one of claims 6 to 10 is implemented.
15. A computer program product, characterized in that The method comprises computer instructions, which, when executed by a processor, implement the time slot boundary processing method as claimed in any one of claims 1 to 5, or implement the time slot boundary processing method as claimed in any one of claims 6 to 10.