Pixel driving circuit and driving method thereof, display device, and signal processing method

Abstract

A pixel driving circuit and a driving method thereof, a display device, and a signal processing method, wherein the pixel driving circuit comprises: a third control subcircuit; the third control subcircuit is configured to adjust the signals of a third node (N3) and a fourth node (N4) under the control of the signals of at least one reset signal line (Reset) and at least one signal line among a dynamic signal line (Var) and an auxiliary signal line (Vx); in at least one display frame, the start time of at least one time period in which a first control unit provides a valid level signal to a second luminous signal line (EM2) is earlier than or equal to the start time of a second control unit providing an invalid level signal to at least one reset signal line (Reset).

Description

[0001] This application claims priority to PCT international application No. PCT / CN2023 / 113514, filed on August 17, 2023, with application number PCT / CN2023 / 113514 and invention name “Pixel driving circuit and driving method thereof, display device” and PCT international application No. PCT / CN2024 / 097840, filed on June 6, 2024, with invention name “Pixel driving circuit and driving method thereof, display device, signal processing method”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] The present disclosure relates to, but is not limited to, the field of display technology, and specifically to a pixel driving circuit and a driving method thereof, a display device, and a signal processing method. Background Art

[0003] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this application. This overview is not intended to limit the scope of protection of the claims.

[0005] In a first aspect, the present disclosure provides a pixel driving circuit, which is provided in a display device and includes: a driving subcircuit, a storage subcircuit, a first control subcircuit, a second control subcircuit, and a third control subcircuit;

[0006] The driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a driving current to the third node under the control of the signals of the first node and the second node;

[0007] The storage sub-circuit is electrically connected to the first node and the third node, respectively, and is configured to store a voltage difference of a signal between the first node and the third node;

[0008] The first control subcircuit is electrically connected to the first scan signal line, the second scan signal line, the data signal line, the reference signal line and the first node, and is configured to provide a signal of the data signal line or the reference signal line to the first node under the control of the signal of the first scan signal line and the second scan signal line;

[0009] The second control subcircuit is electrically connected to the first light emitting signal line, the second light emitting signal line, the first power line, the second node, the third node, and the fourth node, respectively, and is configured to provide a signal from the first power line to the second node and a signal from the third node to the fourth node under the control of signals from the first light emitting signal line and the second light emitting signal line;

[0010] The third control subcircuit is electrically connected to the third node, the fourth node, the at least one reset signal line, and at least one signal line among the dynamic signal line and the auxiliary signal line, respectively, and is configured to adjust the signals of the third node and the fourth node under the control of the signals of the at least one reset signal line and the at least one signal line among the dynamic signal line and the auxiliary signal line;

[0011] The display device includes: a first control unit, a second control unit, and a data unit, wherein the first control unit is electrically connected to the second light emitting signal line and configured to provide a signal to the second light emitting signal line, the second control unit is electrically connected to at least one reset signal line and configured to provide a signal to the at least one reset signal line, and the data unit is electrically connected to the dynamic signal line and configured to provide a signal to the dynamic signal line;

[0012] The content displayed by the display device includes at least one display frame. In at least one display frame, the start time of at least one time period in which the first control unit provides a valid level signal to the second light-emitting signal line is earlier than or equal to the start time in which the second control unit provides an invalid level signal to at least one reset signal line.

[0013] In an exemplary embodiment, the voltage value of the signal of the dynamic signal line includes: multiple voltage values, and at at least part of the time of at least one display frame, the voltage value of the dynamic signal provided by the data unit to the dynamic signal line is positively correlated with the temperature of the display device.

[0014] In an exemplary embodiment, the at least one reset signal line includes: a third reset signal line;

[0015] The third control subcircuit is electrically connected to the third node, the fourth node, the third reset signal line and the dynamic signal line respectively.

[0016] In an exemplary embodiment, the third control subcircuit includes: a second capacitor and an eighth transistor;

[0017] A first end of the second capacitor is electrically connected to the third node, and a second end of the second capacitor is electrically connected to the fourth node;

[0018] A control electrode of the eighth transistor is electrically connected to the third reset signal line, a first electrode of the eighth transistor is electrically connected to the dynamic signal line, and a second electrode of the eighth transistor is electrically connected to the fourth node.

[0019] In an exemplary embodiment, the display device further includes: a third control unit electrically connected to the first light emitting signal line and configured to provide a signal to the first light emitting signal line;

[0020] In at least one display frame, the start time of at least one time period in which the first control unit provides a valid level signal to the second luminous signal line is earlier than the start time in which the second control unit provides an invalid level signal to the third reset signal line, and the start time of at least one time period in which the third control unit provides a valid level signal to the first luminous signal line is later than the start time in which the second control unit provides an invalid level signal to the third reset signal line.

[0021] In an exemplary embodiment, the at least one reset signal line includes: a first reset signal line and a third reset signal line;

[0022] The third control subcircuit is electrically connected to the third node, the fourth node, the first reset signal line, the third reset signal line and the dynamic signal line respectively.

[0023] In an exemplary embodiment, the third control subcircuit includes: a second capacitor, a sixth transistor, and an eighth transistor;

[0024] A first end of the second capacitor is electrically connected to the third node, and a second end of the second capacitor is electrically connected to the fifth node;

[0025] a control electrode of the sixth transistor electrically connected to the first reset signal line, a first electrode of the sixth transistor electrically connected to the fifth node, and a second electrode of the sixth transistor electrically connected to the fourth node;

[0026] A control electrode of the eighth transistor is electrically connected to the third reset signal line, a first electrode of the eighth transistor is electrically connected to the dynamic signal line, and a second electrode of the eighth transistor is electrically connected to the fourth node.

[0027] In an exemplary embodiment, the third control subcircuit includes: a second capacitor, a third capacitor, a sixth transistor, and an eighth transistor;

[0028] A first end of the second capacitor is electrically connected to the third node, and a second end of the second capacitor is electrically connected to the fifth node;

[0029] A first end of the third capacitor is electrically connected to the fifth node, and a second end of the third capacitor is electrically connected to the fourth node;

[0030] The control electrode of the sixth transistor is electrically connected to the first reset signal line, the first electrode of the sixth transistor is electrically connected to the fifth node; and the second electrode of the sixth transistor is electrically connected to the fourth node.

[0031] A control electrode of the eighth transistor is electrically connected to the third reset signal line, a first electrode of the eighth transistor is electrically connected to the dynamic signal line, and a second electrode of the eighth transistor is electrically connected to the fourth node.

[0032] In an exemplary embodiment, the at least one reset signal line includes: a first reset signal line and a third reset signal line;

[0033] The third control subcircuit is electrically connected to the third node, the fourth node, the first reset signal line, the third reset signal line, the dynamic signal line and the auxiliary signal line respectively.

[0034] In an exemplary embodiment, the third control subcircuit includes: a second capacitor, a third capacitor, a sixth transistor, and an eighth transistor;

[0035] A first end of the second capacitor is electrically connected to the third node, and a second end of the second capacitor is electrically connected to the fifth node;

[0036] A first end of the third capacitor is electrically connected to the fifth node, and a second end of the third capacitor is electrically connected to the auxiliary signal line;

[0037] a control electrode of the sixth transistor electrically connected to the first reset signal line, a first electrode of the sixth transistor electrically connected to the fifth node, and a second electrode of the sixth transistor electrically connected to the fourth node;

[0038] A control electrode of the eighth transistor is electrically connected to the third reset signal line, a first electrode of the eighth transistor is electrically connected to the dynamic signal line, and a second electrode of the eighth transistor is electrically connected to the fourth node.

[0039] In an exemplary embodiment, the at least one reset signal line includes: a first reset signal line and a third reset signal line;

[0040] The third control sub-circuit is electrically connected to the third node, the fourth node, the first reset signal line, the third reset signal line and the auxiliary signal line respectively.

[0041] In an exemplary embodiment, the third control subcircuit includes: a second capacitor, a third capacitor, a sixth transistor, and a ninth transistor;

[0042] A first end of the second capacitor is electrically connected to the third node, and a second end of the second capacitor is electrically connected to the fifth node;

[0043] A first end of the third capacitor is electrically connected to the fifth node, and a second end of the third capacitor is electrically connected to the fourth node;

[0044] a control electrode of the sixth transistor electrically connected to the first reset signal line, a first electrode of the sixth transistor electrically connected to the fifth node, and a second electrode of the sixth transistor electrically connected to the fourth node;

[0045] A control electrode of the ninth transistor is electrically connected to the third reset signal line, a first electrode of the ninth transistor is electrically connected to the auxiliary signal line, and a second electrode of the ninth transistor is electrically connected to the fifth node.

[0046] In an exemplary embodiment, the display device further includes: a third control unit electrically connected to the first light emitting signal line and configured to provide a signal to the first light emitting signal line; the second control unit includes: a first sub-control unit electrically connected to the first reset signal line and configured to provide a signal to the first reset signal line; and a second sub-control unit electrically connected to the third reset signal line and configured to provide a signal to the third reset signal line.

[0047] In at least one display frame, at least one of the start time of the first sub-control unit providing an invalid level signal to the first reset signal line and the start time of the second sub-control unit providing an invalid level signal to the third reset signal line is later than the start time of at least one time period of the first control unit providing a valid level signal to the second luminous signal line, and earlier than the start time of at least one time period of the third control unit providing a valid level signal to the first luminous signal line, and the start time of the first sub-control unit providing an invalid level signal to the first reset signal line is earlier than the start time of the second sub-control unit providing an invalid level signal to the third reset signal line.

[0048] In an exemplary embodiment, the at least one reset signal line includes: a first reset signal line, a third reset signal line, and a fourth reset signal line;

[0049] The third control subcircuit is electrically connected to the third node, the fourth node, the first reset signal line, the third reset signal line, the fourth reset signal line, the dynamic signal line and the auxiliary signal line respectively.

[0050] In an exemplary embodiment, the third control subcircuit includes: a second capacitor, a third capacitor, a sixth transistor, an eighth transistor, and a ninth transistor;

[0051] A first end of the second capacitor is electrically connected to the third node, and a second end of the second capacitor is electrically connected to the fifth node;

[0052] A first end of the third capacitor is electrically connected to the fifth node, and a second end of the third capacitor is electrically connected to the fourth node;

[0053] a control electrode of the sixth transistor electrically connected to the first reset signal line, a first electrode of the sixth transistor electrically connected to the fifth node, and a second electrode of the sixth transistor electrically connected to the fourth node;

[0054] a control electrode of the eighth transistor electrically connected to the third reset signal line, a first electrode of the eighth transistor electrically connected to the dynamic signal line, and a second electrode of the eighth transistor electrically connected to the fourth node;

[0055] A control electrode of the ninth transistor is electrically connected to the fourth reset signal line, a first electrode of the ninth transistor is electrically connected to the auxiliary signal line, and a second electrode of the ninth transistor is electrically connected to the fifth node.

[0056] In an exemplary embodiment, the display device further includes: a third control unit electrically connected to the first light emitting signal line and configured to provide a signal to the first light emitting signal line; the second control unit includes: a first sub-control unit, a second sub-control unit, and a third sub-control unit; the first sub-control unit is electrically connected to the first reset signal line and configured to provide a signal to the first reset signal line; the second sub-control unit is electrically connected to the third reset signal line and configured to provide a signal to the third reset signal line; and the third sub-control unit is electrically connected to the fourth reset signal line and configured to provide a signal to the fourth reset signal line.

[0057] In at least one display frame, at least one of the start time of the first sub-control unit providing an invalid level signal to the first reset signal line, the start time of the second sub-control unit providing an invalid level signal to the third reset signal line, and the start time of the third sub-control unit providing an invalid level signal to the fourth reset signal line is later than the start time of at least one time period of the first control unit providing a valid level signal to the second light-emitting signal line, and earlier than the start time of at least one time period of the third control unit providing a valid level signal to the first light-emitting signal line, and the start time of the first sub-control unit providing an invalid level signal to the first reset signal line is earlier than at least one of the start time of the second sub-control unit providing an invalid level signal to the third reset signal line and the start time of the third sub-control unit providing an invalid level signal to the fourth reset signal line.

[0058] In an exemplary embodiment, the driving subcircuit includes: a third transistor, the first control subcircuit includes: a first transistor and a second transistor, the second control subcircuit includes: a fourth transistor and a fifth transistor, and the storage subcircuit includes: a first capacitor;

[0059] A control electrode of the first transistor is electrically connected to the first scan signal line, a first electrode of the first transistor is electrically connected to the data signal line, and a second electrode of the first transistor is electrically connected to the first node;

[0060] A control electrode of the second transistor is electrically connected to the second scan signal line, a first electrode of the second transistor is electrically connected to the reference signal line, and a second electrode of the second transistor is electrically connected to the first node;

[0061] The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node;

[0062] The control electrode of the fourth transistor is electrically connected to the first light emitting signal line, the first electrode of the fourth transistor is electrically connected to the first power supply line, and the second electrode of the fourth transistor is electrically connected to the second node;

[0063] a control electrode of the fifth transistor electrically connected to the second light emitting signal line, a first electrode of the fifth transistor electrically connected to the third node, and a second electrode of the fifth transistor electrically connected to the fourth node;

[0064] A first end of the first capacitor is electrically connected to the first power line, and a second end of the first capacitor is electrically connected to the first node;

[0065] The display device further includes: a fourth control unit and a fifth control unit, the fourth control unit being electrically connected to the first scan signal line and configured to provide a signal to the first scan signal line, and the fifth control unit being electrically connected to the second scan signal line and configured to provide a signal to the second scan signal line;

[0066] In at least one display frame, the end time of the fifth control unit providing the valid level signal to the second scan signal line is earlier than the start time of the fourth control unit providing the valid level signal to the first scan signal line, and the start time of the fourth control unit providing the valid level signal to the first scan signal line is earlier than the start time of at least one time period of the first control unit providing the valid level signal to the second light-emitting signal line.

[0067] In an exemplary embodiment, the dynamic signal line is an initial signal line;

[0068] The signal of the auxiliary signal line is a signal of at least one of a first power line, a reference signal line, and an initial signal line.

[0069] The signal of the auxiliary signal line is a signal of at least one of a first power line and a reference signal line.

[0070] In a second aspect, the present disclosure further provides a display device comprising: sub-pixels arranged in an array, at least one sub-pixel comprising: the above-mentioned pixel driving circuit.

[0071] In an exemplary embodiment, the present invention further comprises: a temperature sensor, a control chip, and a signal transmission component, wherein the signal transmission component comprises: a data unit, wherein the sub-pixel is electrically connected to a dynamic signal line;

[0072] The temperature sensor is configured to detect a first temperature signal of the display device;

[0073] The control chip is electrically connected to the temperature sensor and the signal transmission component, respectively, and is configured to obtain a first temperature signal detected by the temperature sensor, obtain a voltage offset corresponding to at least one sub-pixel based on the first temperature signal, obtain an adjusted dynamic signal corresponding to at least one sub-pixel based on the voltage offset corresponding to the at least one sub-pixel, and send the adjusted dynamic signal to the signal transmission component, and is further configured to send a control signal to the signal transmission component;

[0074] The signal transmission component is electrically connected to the dynamic signal line and is configured to provide the adjusted dynamic signal corresponding to the sub-pixel to the dynamic signal line connected to the sub-pixel under the control of the control signal.

[0075] In an exemplary embodiment, the control chip is further configured to acquire a first temperature signal detected by the temperature sensor within a preset time interval.

[0076] In an exemplary embodiment, a correspondence table between temperature and voltage offset is stored in the control chip. The control chip is further configured to obtain a second temperature signal based on the first temperature signal, and obtain a voltage offset corresponding to at least one sub-pixel by searching the correspondence table based on the second temperature signal. The first temperature signal is an analog signal, and the second temperature signal is a digital signal.

[0077] In an exemplary embodiment, the control chip is further configured to obtain a current dynamic signal of at least one sub-pixel, and obtain an adjusted dynamic signal corresponding to at least one sub-pixel based on the current dynamic signal of at least one sub-pixel and a voltage offset corresponding to at least one sub-pixel.

[0078] In an exemplary embodiment, at least two sub-pixels among the plurality of sub-pixels have the same voltage value of the dynamic signal at the same temperature.

[0079] In an exemplary embodiment, the signal transmission component is further configured to provide an adjusted dynamic signal corresponding to at least one sub-pixel to a dynamic signal line connected to at least one sub-pixel in at least one display frame under the control of the control signal.

[0080] In a third aspect, the present disclosure further provides a method for driving a pixel driving circuit, which is configured to drive the pixel driving circuit, the method comprising:

[0081] The driving subcircuit provides a driving current to the third node under the control of the signals of the first node and the second node;

[0082] The storage sub-circuit stores a voltage difference of a signal between the first node and the third node;

[0083] The first control subcircuit provides a signal of the data signal line or the reference signal line to the first node under the control of the signal of the first scan signal line and the second scan signal line;

[0084] The second control subcircuit provides the signal of the first power line to the second node and provides the signal of the third node to the fourth node under the control of the signals of the first light emitting signal line and the second light emitting signal line;

[0085] The third control subcircuit adjusts the signals of the third node and the fourth node under the control of the signals of at least one reset signal line and at least one signal line among the dynamic signal line and the auxiliary signal line;

[0086] In at least one display frame, at least one time period in which the first control unit provides an active level signal to the second lighting signal line starts earlier than or equal to a start time in which the second control unit provides an inactive level signal to at least one reset signal line.

[0087] In a fourth aspect, the present disclosure further provides a signal processing method, which is applied to the above-mentioned display device, and the method includes:

[0088] Acquire a first temperature signal detected by a temperature sensor;

[0089] obtaining a voltage offset corresponding to at least one sub-pixel according to the first temperature signal;

[0090] obtaining an adjusted dynamic signal corresponding to at least one sub-pixel based on a voltage offset corresponding to the at least one sub-pixel, and sending the adjusted dynamic signal to the signal transmission component, so that the signal transmission component provides the adjusted dynamic signal corresponding to the sub-pixel to a dynamic signal line connected to the sub-pixel under the control of the control signal;

[0091] The acquiring the first temperature signal detected by the temperature sensor comprises: acquiring the first temperature signal detected by the temperature sensor within a preset time interval;

[0092] Obtaining the voltage offset corresponding to at least one sub-pixel according to the first temperature signal includes: obtaining a second temperature signal according to the first temperature signal, and obtaining the voltage offset corresponding to the at least one sub-pixel by searching the corresponding relationship table according to the second temperature signal, wherein the first temperature signal is an analog signal and the second temperature signal is a digital signal;

[0093] The step of obtaining an adjusted dynamic signal corresponding to at least one sub-pixel based on a voltage offset corresponding to at least one sub-pixel includes: acquiring a current dynamic signal of at least one sub-pixel, and obtaining an adjusted dynamic signal corresponding to at least one sub-pixel based on the current dynamic signal of at least one sub-pixel and a voltage offset corresponding to at least one sub-pixel.

[0094] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0095] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0096] Figure 1 A schematic structural diagram of a pixel driving circuit provided in an embodiment of the present disclosure;

[0097] Figure 2 is the equivalent circuit of the third control subcircuit Figure 1 ;

[0098] Figure 3 is the equivalent circuit of the third control subcircuit Figure 2 ;

[0099] Figure 4 is the equivalent circuit of the third control subcircuit Figure 3 ;

[0100] Figure 5 is the equivalent circuit of the third control subcircuit Figure 4 ;

[0101] Figure 6 is the equivalent circuit of the third control subcircuit Figure 5 ;

[0102] Figure 7 is the equivalent circuit of the third control subcircuit Figure 6 ;

[0103] Figure 8 is a local equivalent circuit diagram of a pixel driving circuit;

[0104] Figure 9 The equivalent circuit of the pixel driving circuit is Figure 1 ;

[0105] Figure 10 The equivalent circuit of the pixel driving circuit Figure 2 ;

[0106] Figure 11 The equivalent circuit of the pixel driving circuit Figure 3 ;

[0107] Figure 12 The equivalent circuit of the pixel driving circuit is Figure 4 ;

[0108] Figure 13 The equivalent circuit of the pixel driving circuit Figure 5 ;

[0109] Figure 14 The equivalent circuit of the pixel driving circuit Figure 6 ;

[0110] Figure 15 for Figure 9 and Figure 10 The working timing diagram of the pixel driving circuit provided;

[0111] Figure 16 for Figure 11 The working timing diagram of the pixel driving circuit provided;

[0112] Figure 17 for Figure 12 The working timing diagram of the pixel driving circuit provided;

[0113] Figure 18 for Figure 13 and Figure 14 The working timing diagram of the pixel driving circuit provided;

[0114] Figure 19 A schematic structural diagram of another pixel driving circuit provided by an embodiment of the present disclosure;

[0115] Figure 20 is a schematic structural diagram of a display device;

[0116] Figure 21 for Figure 19 Schematic diagram of the structure of the pixel driving circuit provided Figure 1 ;

[0117] Figure 22A for Figure 21 The equivalent circuit of the pixel driving circuit provided Figure 1 ;

[0118] Figure 22B for Figure 21 The equivalent circuit of the pixel driving circuit provided Figure 2 ;

[0119] Figure 23 FIG22 is a schematic structural diagram of a display device in which a pixel driving circuit is provided;

[0120] Figure 24 for Figure 19 Schematic diagram of the structure of the pixel driving circuit provided Figure 2 ;

[0121] Figure 25A for Figure 24 The equivalent circuit of the pixel driving circuit provided Figure 1 ;

[0122] Figure 25B for Figure 24 The equivalent circuit of the pixel driving circuit provided Figure 2 ;

[0123] Figure 26A for Figure 24 The equivalent circuit of the pixel driving circuit provided Figure 3 ;

[0124] Figure 26B for Figure 24 The equivalent circuit of the pixel driving circuit provided Figure 4 ;

[0125] Figure 27 for Figure 19 Schematic diagram of the structure of the pixel driving circuit provided Figure 3 ;

[0126] Figure 28A for Figure 27 The equivalent circuit of the pixel driving circuit provided Figure 1 ;

[0127] Figure 28B for Figure 27 The equivalent circuit of the pixel driving circuit provided Figure 2 ;

[0128] Figure 29 for Figure 19 Schematic diagram of the structure of the pixel driving circuit provided Figure 4 ;

[0129] Figure 30A for Figure 29 The equivalent circuit of the pixel driving circuit provided Figure 1 ;

[0130] Figure 30B for Figure 29 The equivalent circuit of the pixel driving circuit provided Figure 2 ;

[0131] Figure 31 25 , 26 , 28 and 30 are schematic structural diagrams of a display device in which a pixel driving circuit is provided;

[0132] Figure 32 for Figure 19 Schematic diagram of the structure of the pixel driving circuit provided Figure 5 ;

[0133] Figure 33A for Figure 32 The equivalent circuit of the pixel driving circuit provided Figure 1 ;

[0134] Figure 33B for Figure 32 The equivalent circuit of the pixel driving circuit provided Figure 2 ;

[0135] Figure 34 FIG33 is a schematic structural diagram of a display device in which a pixel driving circuit is provided;

[0136] Figure 35A for Figure 22A The working timing of the pixel driving circuit provided Figure 1 ;

[0137] Figure 35B for Figure 22A The working timing of the pixel driving circuit provided Figure 2 ;

[0138] Figure 36A for Figure 22B The working timing of the pixel driving circuit provided Figure 1 ;

[0139] Figure 36B for Figure 22B The working timing of the pixel driving circuit provided Figure 2 ;

[0140] Figure 37A for Figure 25A 、 Figure 26A 、 Figure 28A and Figure 30A The working timing of the pixel driving circuit provided Figure 1 ;

[0141] Figure 37B for Figure 25A 、 Figure 26A 、 Figure 28A and Figure 30A The working timing of the pixel driving circuit provided Figure 2 ;

[0142] Figure 38A for Figure 25B 、 Figure 26B 、 Figure 28B and Figure 30B The working timing of the pixel driving circuit provided Figure 1 ;

[0143] Figure 38B for Figure 25B 、 Figure 26B 、 Figure 28B and Figure 30B The working timing of the pixel driving circuit provided Figure 2;

[0144] Figure 39A for Figure 33A The working timing of the pixel driving circuit provided Figure 1 ;

[0145] Figure 39B for Figure 33A The working timing of the pixel driving circuit provided Figure 2 ;

[0146] Figure 40A for Figure 33B The working timing of the pixel driving circuit provided Figure 1 ;

[0147] Figure 40B for Figure 33B The working timing of the pixel driving circuit provided Figure 2 ;

[0148] Figure 41 A schematic structural diagram of a display device provided in an embodiment of the present disclosure;

[0149] Figure 42 Schematic diagram of the voltage values ​​of dynamic signals of different sub-pixels at different temperatures Figure 1 ;

[0150] Figure 43 Schematic diagram of the voltage values ​​of dynamic signals of different sub-pixels at different temperatures Figure 2 ;

[0151] Figure 44 Schematic diagram showing how the brightness of a light-emitting device varies with grayscale in at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0152] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings below. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of some known functions and known components. The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0153] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0154] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0155] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0156] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0157] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0158] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0159] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0160] With the development of OLED display technology, oxide processes are often used in OLED display products due to their high uniformity. However, the coupling effect of some capacitors in pixel driver circuits made using oxide processes can introduce noise during the display phase, making the output drive current of the pixel driver circuit unstable and affecting its reliability.

[0161] Figure 1 This is a schematic diagram of the structure of the pixel driving circuit provided by the embodiment of the present disclosure. Figure 1 As shown, the pixel driving circuit provided by the embodiment of the present disclosure may include: a driving subcircuit, a first control subcircuit, a second control subcircuit, a third control subcircuit and a storage subcircuit.

[0162] like Figure 1 As shown, the driving sub-circuit is electrically connected to the first node N1, the second node N2 and the third node N3, respectively, and is configured to provide a driving current to the third node N3 under the control of the signals of the first node N1 and the second node N2; the first control sub-circuit is electrically connected to the first scan signal line G1, the second scan signal line G2, the data signal line Data, the reference signal line REF and the first node N1, respectively, and is configured to provide a signal of the data signal line Data or the reference signal line REF to the first node N1 under the control of the signals of the first scan signal line G1 and the second scan signal line G2; the second control sub-circuit is electrically connected to the first light-emitting signal line EM1, the second light-emitting signal line EM2, the first power line VDD, the second node The point N2, the third node N3 and the fourth node N4 are electrically connected, and are configured to provide the signal of the first power line VDD to the second node N2 and provide the signal of the third node N3 to the fourth node N4 under the control of the signal of the first light-emitting signal line EM1 and the second light-emitting signal line EM2; the third control sub-circuit is electrically connected to the first reset signal line Reset1, the auxiliary signal line VX and the third node N3, respectively, and is configured to control the signal of the third node N3 under the control of the signal of the first reset signal line Reset1 and the drive of the signal of the auxiliary signal line VX; the storage sub-circuit is electrically connected to the first node N1 and the third node N3, respectively, and is configured to store the voltage difference of the signal between the first node N1 and the third node N3.

[0163] In an exemplary embodiment, Figure 1As shown, the pixel driving circuit is electrically connected to the light emitting device L through the fourth node N4.

[0164] In an exemplary embodiment, the light emitting device L may include a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode). Exemplarily, the anode of the light emitting device L is electrically connected to the fourth node N4, and the cathode of the light emitting device L is electrically connected to the second power line VSS.

[0165] In an exemplary embodiment, the light-emitting device L may include a current-driven device, and may be a current-driven light-emitting diode, such as a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), an organic light-emitting diode (OLED), or a quantum dot light-emitting diode (QLED). A typical size (e.g., length) of a Micro LED may be less than 100 μm, for example, 10 μm to 50 μm. A typical size (e.g., length) of a Mini LED may be approximately 100 μm to 300 μm, for example, 120 μm to 260 μm.

[0166] In an exemplary embodiment, the organic light-emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, and the hole blocking layers of all sub-pixels may be a common layer connected together. The light-emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0167] In an exemplary embodiment, the first power line VDD continuously provides a high-level signal, and the signal of the first power line VDD is a DC signal.

[0168] In an exemplary embodiment, the second power line VSS continuously provides a low-level signal, and the signal of the second power line VSS is a DC signal.

[0169] In an exemplary embodiment, the reference signal line REF continuously provides a low-level signal. The signal of the reference signal line REF is a DC signal. Exemplarily, the voltage of the signal of the reference signal line REF may be 0V.

[0170] In an exemplary embodiment, the pixel driving circuit is located in a display substrate, and the content displayed by the display substrate includes multiple display frames. In any display frame, the signal of the first scanning signal line G1 is a pulse signal, and the signal of the second scanning signal line G2 is a pulse signal. The time period in which the second scanning signal line G2 is a valid level signal occurs before the time period in which the first scanning signal line G1 is a valid level signal.

[0171] The embodiment of the present disclosure provides a pixel driving circuit, comprising: a driving subcircuit, a first control subcircuit, a second control subcircuit, a third control subcircuit, and a storage subcircuit; the driving subcircuit is electrically connected to a first node, a second node, and a third node, respectively, and is configured to provide a driving current to the third node under the control of signals from the first node and the second node; the first control subcircuit is electrically connected to a first scan signal line, a second scan signal line, a data signal line, a reference signal line, and a first node, respectively, and is configured to provide a signal from a data signal line or a reference signal line to the first node under the control of signals from the first scan signal line and the second scan signal line; the second control subcircuit is electrically connected to a first scan signal line, a second scan signal line, a data signal line, a reference signal line, and a first node, respectively, and is configured to provide a signal from a data signal line or a reference signal line to the first node under the control of signals from the first scan signal line and the second scan signal line; The circuit is electrically connected to the first light-emitting signal line, the second light-emitting signal line, the first power line, the second node, the third node and the fourth node, respectively, and is configured to provide the signal of the first power line to the second node and the signal of the third node to the fourth node under the control of the signals of the first light-emitting signal line and the second light-emitting signal line; the third control subcircuit is electrically connected to the first reset signal line, the auxiliary signal line and the third node, respectively, and is configured to control the signal of the third node under the control of the signal of the first reset signal line and the drive of the signal of the auxiliary signal line; the storage subcircuit is electrically connected to the first node and the third node, respectively, and is configured to store the voltage difference of the signal between the first node and the third node. The present disclosure can control the signal of the third node through the signals of the first reset signal line and the auxiliary signal line by setting the third control subcircuit, thereby avoiding the introduction of noise in the display stage, maintaining the stability of the driving current output by the pixel driving circuit, and improving the reliability of the pixel driving circuit.

[0172] In an exemplary embodiment, the operation process of the pixel driving circuit includes a display phase, which includes a write phase and a light-emitting phase. The light-emitting phase occurs after the write phase, and the signal of the first scanning signal line G1 is an active-level signal during the write phase. The signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are both active-level signals during the light-emitting phase, and the time during which the write phase occurs is a write time period.

[0173] Figure 2 is the equivalent circuit of the third control subcircuit Figure 1 .like Figure 2 As shown, in an exemplary embodiment, the third control subcircuit may also be electrically connected to the third reset signal line Reset3 and the initial signal line INIT, respectively, and configured to provide a signal of the initial signal line to the fourth node N4 under the control of the signal of the third reset signal line Reset3. Exemplarily, the third control subcircuit may include: a sixth transistor T6, an eighth transistor T8, and a second capacitor C2. The control electrode of the sixth transistor T6 is electrically connected to the first reset signal line Reset1, the first electrode of the sixth transistor T6 is electrically connected to the auxiliary signal line VX, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5; the first end of the second capacitor C2 is electrically connected to the fifth node N5, and the second end of the second capacitor C2 is electrically connected to the third node N3; the first electrode of the eighth transistor T8 is electrically connected to the initial signal line INIT, and the second electrode of the eighth transistor T8 is electrically connected to the fourth node N4.

[0174] In an exemplary embodiment, Figure 2 As shown, the signal of the auxiliary signal line VX is a non-DC signal and is electrically connected to the fourth node N4.

[0175] In an exemplary embodiment, Figure 2 As shown, the present disclosure ensures that the third node N3 and the fourth node N4 are reset before the write period by ensuring that the signal of the second light-emitting signal line EM2 is at an active level during a portion of the time period when the signal of the third reset signal line Reset3 is at an active level. This ensures that the display uniformity of the pixel driving circuit is maintained. The present disclosure ensures that the signals of the first reset signal line Reset1 and the second light-emitting signal line EM2 are at an active level during at least a portion of the time period after the write period. This ensures that the voltage values ​​of the signals at both ends of the second capacitor C2 during the light-emitting phase are the same, thereby avoiding the influence of the second capacitor C2 on the third node N3 during the light-emitting phase and preventing the introduction of noise at the third node N3. This maintains the stability of the drive current output by the pixel driving circuit and improves the reliability of the pixel driving circuit.

[0176] Figure 3 is the equivalent circuit of the third control subcircuit Figure 2 .like Figure 3 As shown, in an exemplary embodiment, the third control subcircuit may also be electrically connected to the second reset signal line Reset2, and is further configured to provide a signal of the fifth node N5 to the third node N3 under the control of the signal of the second reset signal line Reset2. Exemplarily, the third control subcircuit may include: a sixth transistor T6, a seventh transistor T7, and a second capacitor C2. The first electrode of the sixth transistor T6 is electrically connected to the auxiliary signal line VX, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5; the control electrode of the seventh transistor T7 is electrically connected to the second reset signal line Reset3, the first electrode of the seventh transistor T7 is electrically connected to the fifth node N5, and the second electrode of the seventh transistor T7 is electrically connected to the third node N3; the first end of the second capacitor C2 is electrically connected to the fifth node N5, and the second end of the second capacitor C2 is electrically connected to the third node N3;

[0177] In an exemplary embodiment, Figure 3 As shown, the signal of the auxiliary signal line VX may be a DC signal, and may be the same as the signal of any one of the initial signal line INIT, the reference signal line REF, and the first power line VDD.

[0178] In an exemplary embodiment, Figure 3 As shown, the present disclosure ensures display uniformity of the pixel driving circuit by ensuring that the signals of the second reset signal line Reset2 and the second light-emitting signal line EM2 are valid level signals during a portion of the time period when the signal of the first reset signal line Reset1 is a valid level signal. This ensures that the third node N3 and the fourth node N4 are reset before the write period. By ensuring that the second reset signal line Reset2 is a valid level signal during at least a portion of the time period after the write period, the present disclosure ensures that the voltage values ​​of the signals at both ends of the second capacitor C2 during the light-emitting phase are the same, thereby avoiding the influence of the second capacitor C2 on the third node N3 during the light-emitting phase and the introduction of noise during the display phase. This maintains the stability of the drive current output by the pixel driving circuit and improves the reliability of the pixel driving circuit.

[0179] Figure 4 is the equivalent circuit of the third control subcircuit Figure 3 , Figure 5 is the equivalent circuit of the third control subcircuit Figure 4 In an exemplary embodiment, as Figure 4 and Figure 5As shown, the third control sub-circuit may be further electrically connected to the third reset signal line Reset3 and the initial signal line INIT, respectively, and configured to provide a signal of the initial signal line to the fourth node N4 under the control of a signal of the third reset signal line Reset3. Exemplarily, the third control sub-circuit may further include an eighth transistor T8, wherein a control electrode of the eighth transistor T8 is electrically connected to the third reset signal line Reset3, a first electrode of the eighth transistor T8 is electrically connected to the initial signal line, and a second electrode of the eighth transistor T8 is electrically connected to the fourth node N4.

[0180] In an exemplary embodiment, the signal of the auxiliary signal line VX is a DC signal, and the signal of the auxiliary signal line VX is the same as the signal of any one of the initial signal line INIT, the reference signal line REF, and the first power line VDD; alternatively, the signal of the auxiliary signal line VX is a non-DC signal, and the signal of the auxiliary signal line VX is electrically connected to the fourth node N4. Figure 4 The following is an example of a DC signal on the auxiliary signal line VX. Figure 5 The description is made by taking the case where the signal of the auxiliary signal line VX is a non-DC signal as an example.

[0181] In an exemplary embodiment, Figure 4 and Figure 5 As shown, when the signal of the first reset signal line Reset1 is a valid level signal, the signal of the third reset signal line is a valid level signal, and the signal of the second reset signal line is an invalid level signal. When the signal of the second reset signal line is a valid level signal, the signal of the first reset signal line is an invalid level signal. In the present disclosure, the signal of the second light-emitting signal line EM2 is a valid level signal during a portion of the time period when the signal of the third reset signal line Reset3 is a valid level signal. This can reset the third node N3 and the fourth node N4 before the write period, thereby ensuring display uniformity of the pixel driving circuit. In the present disclosure, by making the second reset signal line Reset2 a valid level signal during at least a portion of the time period after the write period, the voltage values ​​of the signals at both ends of the second capacitor C2 during the light-emitting phase are the same, thereby avoiding the influence of the second capacitor C2 on the third node N3 during the light-emitting phase, avoiding the introduction of noise during the display phase, maintaining the stability of the driving current output by the pixel driving circuit, and improving the reliability of the pixel driving circuit.

[0182] Figure 6 is the equivalent circuit of the third control subcircuit Figure 5 , Figure 7 is the equivalent circuit of the third control subcircuit Figure 6 In an exemplary embodiment, as Figure 6 and Figure 7As shown, the third control subcircuit may also be electrically connected to the third reset signal line Reset3 and the initial signal line INIT, respectively, and configured to provide the signal of the initial signal line to the fourth node N4 under the control of the signal of the third reset signal line Reset3. For example, the third control subcircuit may further include: a sixth transistor T6, an eighth transistor T8, and a second capacitor C2. The control electrode of the sixth transistor T6 is electrically connected to the first reset signal line Reset1, the first electrode of the sixth transistor T6 is electrically connected to the fifth node N5, and the second electrode of the sixth transistor T6 is electrically connected to the third node N3; the control electrode of the eighth transistor T8 is electrically connected to the third reset signal line Reset3, the first electrode of the eighth transistor T8 is electrically connected to the initial signal line INIT, and the second electrode of the eighth transistor T8 is electrically connected to the fourth node N4; the first end of the second capacitor C2 is electrically connected to the auxiliary signal line VX, and the second end of the second capacitor C2 is electrically connected to the fifth node N5.

[0183] In an exemplary embodiment, the signal of the auxiliary signal line VX is a DC signal, and the signal of the auxiliary signal line VX is the same as the signal of any one of the initial signal line, the reference signal line REF, and the first power line VDD; alternatively, the signal of the auxiliary signal line VX is a non-DC signal, and the signal of the auxiliary signal line VX is electrically connected to the fourth node N4. Figure 6 The following is an example of a DC signal on the auxiliary signal line VX. Figure 7 The description is made by taking the case where the signal of the auxiliary signal line VX is a non-DC signal as an example.

[0184] In an exemplary embodiment, Figure 6 and Figure 7 As shown, the present disclosure resets the third node N3 and the fourth node N4 before the write period by setting the signal of the second light-emitting signal line EM2 to a valid level during a portion of the time period when the signal of the third reset signal line Reset3 is a valid level signal, thereby ensuring display uniformity of the pixel driving circuit. The present disclosure sets the first reset signal line Reset1 to an invalid level signal during the time period after the write period, thereby preventing the second capacitor C2 from affecting the third node N3, avoiding the introduction of noise during the display phase, maintaining the stability of the drive current output by the pixel driving circuit, and improving the reliability of the pixel driving circuit.

[0185] In an exemplary embodiment, the initial signal line INIT continuously provides a low-level signal, and the signal of the initial signal line INIT is a DC signal.

[0186] In an exemplary embodiment, the voltage value of the signal of the initial signal line INIT may be lower than the voltage value of the signal of the second power line VSS, which may prevent the light emitting device L from emitting light inadvertently and improve the reliability of the pixel driving circuit.

[0187] Figures 2 to 7 Only six exemplary structures of the third control sub-circuit are shown. It is easy for those skilled in the art to understand that the implementation of the third control sub-circuit is not limited thereto.

[0188] Figure 8 is the local equivalent circuit diagram of the pixel driving circuit. Figure 8 As shown, in an exemplary embodiment, the first control subcircuit may include: a first transistor T1 and a second transistor T2, the driving subcircuit may include: a third transistor T3, the second control subcircuit may include: a fourth transistor T4 and a fifth transistor T5, and the storage subcircuit may include: a first capacitor C1. The control electrode of the first transistor T1 is electrically connected to the first scan signal line G1, the first electrode of the first transistor T1 is electrically connected to the data signal line Data, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the second scan signal line G2, the first electrode of the second transistor T2 is electrically connected to the reference signal line REF, and the second electrode of the second transistor T2 is electrically connected to the first node N1; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the The second electrode is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first light-emitting signal line EM1, the first electrode of the fourth transistor T4 is electrically connected to the first power supply line VDD, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the second light-emitting signal line EM2, the first electrode of the fifth transistor T5 is electrically connected to the third node N3, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4; the first end of the first capacitor C1 is electrically connected to the first node N1, and the second end of the first capacitor C1 is electrically connected to the third node N3.

[0189] Figure 8 Only an exemplary structure of the driving sub-circuit, the first control sub-circuit, the second control sub-circuit and the storage sub-circuit is shown. It is easy for those skilled in the art to understand that the implementation of the driving sub-circuit, the first control sub-circuit, the second control sub-circuit and the storage sub-circuit is not limited to this.

[0190] In an exemplary embodiment, Figure 9 The equivalent circuit of the pixel driving circuit Figure 1 , Figure 10 The equivalent circuit of the pixel driving circuit Figure 2 , Figure 11 The equivalent circuit of the pixel driving circuit Figure 3 , Figure 12 The equivalent circuit of the pixel driving circuit Figure 4 .like Figures 9 to 12As shown, in an exemplary embodiment, the first control subcircuit in the pixel driving circuit includes: a first transistor T1 and a second transistor T2, the driving subcircuit includes: a third transistor T3, the second control subcircuit includes: a fourth transistor T4 and a fifth transistor T5, the storage subcircuit includes: a first capacitor C1, the third control subcircuit includes: a second capacitor C2 and a sixth transistor T6, and the third control subcircuit further includes: at least one transistor of a seventh transistor T7 and an eighth transistor T8. Among them, the control electrode of the first transistor T1 is electrically connected to the first scan signal line G1, the first electrode of the first transistor T1 is electrically connected to the data signal line Data, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the second scan signal line G2, the first electrode of the second transistor T2 is electrically connected to the reference signal line REF, and the second electrode of the second transistor T2 is electrically connected to the first node N1; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first light-emitting signal line EM1, the first electrode of the fourth transistor T4 is electrically connected to the first power supply line VDD, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the second light-emitting signal line EM2, and the first electrode of the fifth transistor T5 is electrically connected to the third node N3 a first terminal of the first capacitor C1 is electrically connected to the first node N1, and a second terminal of the first capacitor C1 is electrically connected to the third node N3; a first terminal of the second capacitor C2 is electrically connected to the fifth node N5, and a second terminal of the second capacitor C2 is electrically connected to the third node N3; a second terminal of the second capacitor C2 is electrically connected to the fifth node N5, and a second terminal of the second capacitor C2 is electrically connected to the third node N3; a second terminal of the second capacitor C2 is electrically connected to the fifth node N5, and a second terminal of the second capacitor C2 is electrically connected to the third node N3; a first terminal of the second capacitor C2 is electrically connected to the fifth node N5, and a second terminal of the second capacitor C2 is electrically connected to the third node N3. Figure 9 and Figure 10 The third control sub-circuit further includes a seventh transistor T7 and an eighth transistor T8. Figure 11 The third control sub-circuit further includes a seventh transistor T7. Figure 12 The description is made by taking the example that the third control sub-circuit further includes: an eighth transistor T8.

[0191] In an exemplary embodiment, Figure 9 and Figure 10 As shown, the third control sub-circuit further includes: the signal of the auxiliary signal line VX in the pixel driving circuit of the seventh transistor T7 and the eighth transistor T8 can be a DC signal, or can be a non-DC signal, Figure 9 The following description is made by taking the case where the signal of the auxiliary signal line VX in the pixel driving circuit is a DC signal and is the same as the signal of any one of the initial signal line INIT, the reference signal line REF and the first power line VDD. Figure 10 The description is made by taking an example in which the signal of the auxiliary signal line VX in the pixel driving circuit is a non-DC signal and is electrically connected to the fourth node N4.

[0192] In an exemplary embodiment, Figure 11 As shown, the third control sub-circuit further includes a pixel driving circuit in which the signal of the auxiliary signal line VX in the seventh transistor T7 is a DC signal and is the same as the signal of any one of the initial signal line, the reference signal line and the first power line.

[0193] In an exemplary embodiment, Figure 12 As shown, the signal of the auxiliary signal line VX in the pixel driving circuit of the third control sub-circuit further includes the eighth transistor T8 is a non-DC signal and is electrically connected to the fourth node N4.

[0194] Transistors can be divided into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages).

[0195] In an exemplary embodiment, any of the first to eighth transistors T1 to T8 may be an oxide thin film transistor, the active layer of which is made of an oxide semiconductor (Oxide), which has advantages such as low leakage current.

[0196] In an exemplary embodiment, any one of the first to eighth transistors T1 to T8 is an N-type transistor.

[0197] In an exemplary embodiment, Figure 13 The equivalent circuit of the pixel driving circuit Figure 5 , Figure 14 The equivalent circuit of the pixel driving circuit Figure 6 .like Figure 13 and Figure 14 As shown, the first control subcircuit in the pixel driving circuit may include: a first transistor T1 and a second transistor T2, the driving subcircuit may include: a third transistor T3, the second control subcircuit may include: a fourth transistor T4 and a fifth transistor T5, the storage subcircuit may include: a first capacitor C1, and the third control subcircuit may include: a second capacitor C2, a sixth transistor T6 and an eighth transistor T8. Among them, the control electrode of the first transistor T1 is electrically connected to the first scan signal line G1, the first electrode of the first transistor T1 is electrically connected to the data signal line Data, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the second scan signal line G2, the first electrode of the second transistor T2 is electrically connected to the reference signal line REF, and the second electrode of the second transistor T2 is electrically connected to the first node N1; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first light emitting signal line EM1, the first electrode of the fourth transistor T4 is electrically connected to the first power supply line VDD, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The control electrode of the sixth transistor T6 is electrically connected to the first reset signal line Reset1, the first electrode of the sixth transistor T6 is electrically connected to the fifth node N5, and the second electrode of the sixth transistor T6 is electrically connected to the third node N3; the control electrode of the eighth transistor T8 is electrically connected to the third reset signal line Reset3, the first electrode of the eighth transistor T8 is electrically connected to the initial signal line INIT, and the second electrode of the eighth transistor T8 is electrically connected to the fourth node N4; the first end of the first capacitor C1 is electrically connected to the first node N1, and the second end of the first capacitor C1 is electrically connected to the third node N3; the first end of the second capacitor C2 is electrically connected to the auxiliary signal line VX, and the second end of the second capacitor C2 is electrically connected to the fifth node N5.

[0198] In an exemplary embodiment, Figure 13 and Figure 14 As shown, the third control subcircuit includes: a sixth transistor T6, an eighth transistor T8 and a second capacitor C2. The signal of the auxiliary signal line VX in the pixel driving circuit can be a DC signal or a non-DC signal. Figure 13 The following description is made by taking the case where the signal of the auxiliary signal line VX in the pixel driving circuit is a DC signal and is the same as the signal of any one of the initial signal line INIT, the reference signal line REF and the first power line VDD. Figure 14The description is made by taking an example in which the signal of the auxiliary signal line VX in the pixel driving circuit is a non-DC signal and is electrically connected to the fourth node N4.

[0199] In an exemplary embodiment, any of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 may be an oxide thin film transistor. The active layer of the oxide thin film transistor is made of an oxide semiconductor. Oxide thin film transistors have advantages such as low leakage current.

[0200] In an exemplary embodiment, any one of the first transistor T1 , the second transistor T2 , the fourth transistor T4 , the fifth transistor T5 , the sixth transistor T6 , and the eighth transistor T8 is an N-type transistor.

[0201] In an exemplary embodiment, Figures 9 to 14 In the provided pixel driving circuit, the number of the first transistor T1 , the second transistor T2 , and the fourth transistor T4 may be at least one.

[0202] In an exemplary embodiment, when the number of the first transistors T1 may be at least two, the control electrodes of all the first transistors are electrically connected to the first scan signal line, at least two first transistors are arranged in series, the first electrode of the first first transistor is electrically connected to the data signal line, and the second electrode of the last first transistor is electrically connected to the first node N1.

[0203] In an exemplary embodiment, when the number of the second transistors T2 may be at least two, the control electrodes of all the second transistors T2 are electrically connected to the second scan signal line, at least two second transistors are arranged in series, the first electrode of the first second transistor is electrically connected to the reference signal line, and the second electrode of the last second transistor is electrically connected to the second node N2.

[0204] Figure 15 for Figure 9 and Figure 10 The working timing diagram of the pixel driving circuit provided is as follows. Figure 9 and Figure 10 The operation process of the pixel driving circuit of the example illustrates an exemplary embodiment of the present disclosure. Figure 9 and Figure 10 The pixel driving circuit includes eight transistors (a first transistor T1 to an eighth transistor T8) and two capacitors (a first capacitor C1 and a second capacitor C2), and all of the eight transistors are N-type transistors.

[0205] In an exemplary embodiment, Figure 9 and Figure 10 The working process of the provided pixel driving circuit may include:

[0206] The first phase P1 is called the first reset phase. The signals on the second scan signal line G2, the second luminescence signal line EM2, the first reset signal line Reset1, and the third reset signal line Reset3 are high-level signals, while the signals on the first scan signal line G1, the first luminescence signal line EM1, and the second reset signal line Reset2 are low-level signals. The signal on the second scan signal line G2 is high-level, the second transistor T2 is turned on, and the signal on the reference signal line REF is written to the first node N1, initializing (resetting) the signal on the first node N1 and clearing the existing charge on the first node N1. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the signal on the auxiliary signal line VX is written to the fifth node N5, initializing (resetting) the signal on the fifth node N5 and clearing the existing charge on the fifth node N5. The signals on the second light-emitting signal line EM2 and the third reset signal line Reset3 are high-level signals, the fifth transistor T5 and the eighth transistor T8 are turned on, and the signal on the initial signal line INIT is written to the third node N3 and the fourth node N4, respectively. Since the voltage values ​​of the signals on the first node N1 and the third node N3 are greater than the threshold voltage of the third transistor T3, the third transistor T3 is turned on, and the signal on the initial signal line INIT is written to the second node N2, initializing (resetting) the signals on the second node N2, the third node N3, and the fourth node N4, clearing the existing charges on the second node N2, the third node N3, and the fourth node N4. The signals on the first scanning signal line G1, the first light-emitting signal line EM1, and the second reset signal line Reset2 are low-level signals, and the first transistor T1, the fourth transistor T4, and the seventh transistor T7 are turned off. At this stage, the light-emitting device L does not emit light.

[0207] In the second phase P2, i.e., the threshold compensation phase, the signals on the first reset signal line Reset1, the third reset signal line Reset3, the second scan signal line G2, and the first light-emitting signal line EM1 are high-level signals, while the signals on the second reset signal line Reset2, the first scan signal line G1, and the second light-emitting signal line EM2 are low-level signals. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the signal on the auxiliary signal line VX is continuously written to the fifth node N5, continuously initializing (resetting) the signal on the fifth node N5. The signal on the third reset signal line Reset3 is high-level, the eighth transistor T8 is turned on, and the signal on the initialization signal line INIT is continuously written to the fourth node N4, continuously initializing (resetting) the signal on the fourth node N4. The signal on the second scan signal line G2 is high, the second transistor T2 is turned on, the signal on the reference signal line REF is continuously supplied to the first node N1, the signal on the first emission signal line EM1 is high, and the fourth transistor T4 is turned on. The signal on the first power line VDD is written to the third node N3 via the turned-on fourth transistor T4, the second node N2, and the turned-on third transistor T3, until the voltage V3 of the signal on the third node N3 reaches Vref - Vth, where Vref is the voltage value of the signal on the initial signal line REF and Vth is the threshold voltage of the third transistor T3. At this point, the first capacitor C1 stores the voltage difference Vth between the signals on the first node N1 and the third node N3. The signals on the second reset signal line Reset2, the first scan signal line G1, and the second emission signal line EM2 are low, and the first transistor T1, the fifth transistor T5, and the seventh transistor are turned off. During this stage, the light-emitting device L does not emit light.

[0208] In the third phase P3, the data writing phase, the signals on the first reset signal line Reset1, the third reset signal line Reset3, and the first scan signal line G1 are high-level signals, while the signals on the second reset signal line Reset2, the second scan signal line G2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are low-level signals. The data signal line Data outputs a data voltage. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the signal on the auxiliary signal line VX is continuously written to the fifth node N5, continuously initializing (resetting) the signal on the fifth node N5. The signal on the third reset signal line Reset3 is high-level, the eighth transistor T8 is turned on, and the signal on the initialization signal line INIT is continuously written to the fourth node N4, continuously initializing (resetting) the signal on the fourth node N4. The signal on the first scan signal line G1 is high, turning on the first transistor T1. The data voltage on the data signal line Data is written to the first node N1. At this point, the voltage V1 of the first node N1 equals Vdata, where Vdata is the data voltage on the data signal line. The signal on the first node N1 changes from its current voltage value to its previous voltage value. Therefore, under the action of the first capacitor C1 and the second capacitor C2, the signal on the third node N3 also changes. At this point, the voltage V3 of the signal on the third node N3 equals Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2), where C1 is the capacitance of the first capacitor and C2 is the capacitance of the second capacitor. The signals on the second reset signal line Reset2, the second scan signal line G2, the first emission signal line EM1, and the second emission signal line EM2 are low. The second transistor T2, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are turned off. In this stage, the light-emitting device L does not emit light.

[0209] In the fourth phase P4, referred to as the second reset phase, the second reset signal line Reset2, the third reset signal line Reset3, and the second light-emitting signal line EM2 are high-level signals, while the signals on the first reset signal line Reset1, the first light-emitting signal line EM1, the first scanning signal line G1, and the second scanning signal line G2 are low-level signals. The signal on the third reset signal line Reset3 is high-level, the eighth transistor T8 is turned on, and the signal on the initialization signal line INIT is continuously written to the fourth node N4, continuously initializing (resetting) the signal on the fourth node N4. The signal on the second light-emitting signal line EM2 is high, the fifth transistor T5 is turned on, and the voltage V3 of the signal on the third node N3 is equal to Vinit, where Vinit is the voltage value of the signal on the initial signal line. At this time, the first node N1 is pulled low by the first capacitor C1, so that the voltage V1 of the signal on the first node N1 is equal to Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]+Vinit. The signal on the second reset signal line Reset2 is high, the seventh transistor T7 is turned on, and the voltages of the signals on the third node N3 and the fifth node N5 remain consistent. The signals on the first reset signal line Reset1, the first light-emitting signal line EM1, the first scan signal line G1, and the second scan signal line G2 are low, and the first transistor T1, the second transistor T2, the fourth transistor T4, and the sixth transistor T6 are turned off. In this stage, the light-emitting device L does not emit light.

[0210] In the fifth phase P5, i.e., the light-emitting phase, the signals on the second reset signal line Reset2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals, while the signals on the first reset signal line Reset1, the third reset signal line Reset3, and the first scan signal line G1 and the second scan signal line G2 are low-level signals. The signals on the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are high-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, and the power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fourth transistor T4, third transistor T3, and fifth transistor T5, driving the light-emitting device L to emit light. The signal on the second reset signal line Reset2 is high-level, the seventh transistor T7 is turned on, and the voltages of the signals on the third node N3 and the fifth node N5 remain consistent. The signals on the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals. The first transistor T1, the second transistor T2, the sixth transistor T6, and the eighth transistor T8 are turned off. In this phase, the light-emitting device L emits light.

[0211] During the pixel driving circuit's driving process, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its control electrode (also the first node N1) and the second electrode (also the third node N3). Since the voltage value of the signal at the first node V1 = Vdata - [Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2)] + Vinit, and the voltage value of the signal at the third node N3 V3 = Vinit, the driving current of the third transistor T3 is:

[0212] I=K*(Vgs-Vth) 2

[0213] =K*[Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]-Vth] 2

[0214] =K*[(C2 / (C1+C2))*(Vdata-Vref)] 2 .

[0215] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the control electrode and the second electrode of the third transistor T3.

[0216] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0217] Figure 16 for Figure 11 The working timing diagram of the pixel driving circuit provided is as follows. Figure 11 The operation process of the pixel driving circuit of the example illustrates an exemplary embodiment of the present disclosure. Figure 11 The pixel driving circuit includes 7 transistors (a first transistor T1 to a seventh transistor T7) and two capacitors (a first capacitor C1 and a second capacitor C2), and all of the 7 transistors are N-type transistors.

[0218] In an exemplary embodiment, Figure 11 The working process of the provided pixel driving circuit may include:

[0219] In the first phase P1, referred to as the first reset phase, the signals on the second scan signal line G2, the second light-emitting signal line EM2, the first reset signal line Reset1, and the second reset signal line Reset2 are high-level signals, while the signals on the first scan signal line G1 and the first light-emitting signal line EM1 are low-level signals. The signal on the second scan signal line G2 is high-level, the second transistor T2 is turned on, and the signal on the reference signal line REF is written to the first node N1, initializing (resetting) the signal on the first node N1 and clearing the existing charge in the first node N1. The signals on the first reset signal line Reset1, the second reset signal line Reset2, and the second light-emitting signal line EM2 are high-level signals. The fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned on, and the signal on the auxiliary signal line VX is sequentially written to the fifth node N5, the third node N3, and the fourth node N4, initializing (resetting) the signals on the third node N3, the fourth node N4, and the fifth node N5, clearing the existing charge on the third node N3, the fourth node N4, and the fifth node N5. The signals of the first scanning signal line G1 and the first light emitting signal line EM1 are low level signals, and the first transistor T1 and the fourth transistor T4 are turned off. In this stage, the light emitting device L does not emit light.

[0220] In the second phase P2, i.e., the threshold compensation phase, the signals on the first reset signal line Reset1, the second scan signal line G2, and the first light-emitting signal line EM1 are high-level signals, while the signals on the second reset signal line Reset2, the first scan signal line G1, and the second light-emitting signal line EM2 are low-level signals. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the signal on the auxiliary signal line VX is continuously written to the fifth node N5, continuously initializing (resetting) the signal on the fifth node N5. The signal on the second scan signal line G2 is high, the second transistor T2 is turned on, the signal on the reference signal line REF is continuously supplied to the first node N1, the signal on the first emission signal line EM1 is high, and the fourth transistor T4 is turned on. The signal on the first power line VDD is written to the third node N3 via the turned-on fourth transistor T4, the second node N2, and the turned-on third transistor T3, until the voltage V3 of the signal on the third node N3 reaches Vref - Vth, where Vref is the voltage value of the signal on the initial signal line REF and Vth is the threshold voltage of the third transistor T3. At this point, the first capacitor C1 stores the voltage difference Vth between the signals on the first node N1 and the third node N3. The signals on the second reset signal line Reset2, the first scan signal line G1, and the second emission signal line EM2 are low, and the first transistor T1, the fifth transistor T5, and the seventh transistor are turned off. During this stage, the light-emitting device L does not emit light.

[0221] In the third phase P3, the data writing phase, the signals on the first reset signal line Reset1 and the first scan signal line G1 are high-level signals, the signals on the second reset signal line Reset2, the second scan signal line G2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are low-level signals, and the data signal line Data outputs a data voltage. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the signal on the auxiliary signal line VX is continuously written to the fifth node N5, continuously initializing (resetting) the signal on the fifth node N5. The signal on the first scan signal line G1 is high, turning on the first transistor T1. The data voltage on the data signal line Data is written to the first node N1. At this point, the voltage V1 of the first node N1 equals Vdata, where Vdata is the data voltage on the data signal line. The signal on the first node N1 changes from its current voltage value to its previous voltage value. Therefore, under the action of the first capacitor C1 and the second capacitor C2, the signal on the third node N3 also changes. At this point, the voltage V3 of the signal on the third node N3 equals Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2), where C1 is the capacitance of the first capacitor and C2 is the capacitance of the second capacitor. The signals on the second reset signal line Reset2, the second scan signal line G2, the first emission signal line EM1, and the second emission signal line EM2 are low. The second transistor T2, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are turned off. In this stage, the light-emitting device L does not emit light.

[0222] In the fourth phase P4, referred to as the second reset phase, the second reset signal line Reset2 and the second light-emitting signal line EM2 are high-level signals, while the signals on the first reset signal line Reset1, the first light-emitting signal line EM1, the first scanning signal line G1, and the second scanning signal line G2 are low-level signals. The signal on the second light-emitting signal line EM2 is high-level, the fifth transistor T5 is turned on, and the voltage V3 of the signal on the third node N3 is equal to Vinit, where Vinit is the voltage value of the signal on the initial signal line. At this time, the first node N1 is pulled down by the first capacitor C1, such that the voltage V1 of the signal on the first node N1 is equal to Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]+Vinit. The signal on the second reset signal line Reset2 is high-level, the seventh transistor T7 is turned on, and the voltages of the signals on the third node N3 and the fifth node N5 remain consistent. The signals of the first reset signal line Reset1, the first light emitting signal line EM1, the first scanning signal line G1 and the second scanning signal line G2 are low level signals, and the first transistor T1, the second transistor T2, the fourth transistor T4 and the sixth transistor T6 are turned off. In this stage, the light emitting device L does not emit light.

[0223] In the fifth phase P5, i.e., the light-emitting phase, the signals on the second reset signal line Reset2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals, while the signals on the first reset signal line Reset1, the first scan signal line G1, and the second scan signal line G2 are low-level signals. The signals on the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are high-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, and the power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fourth transistor T4, the third transistor T3, and the fifth transistor T5, driving the light-emitting device L to emit light. The signal on the second reset signal line Reset2 is high-level, the seventh transistor T7 is turned on, and the voltages of the signals on the third node N3 and the fifth node N5 remain consistent. The signals on the first reset signal line Reset1, the first scan signal line G1, and the second scan signal line G2 are low-level signals, and the first transistor T1, the second transistor T2, and the sixth transistor T6 are turned off. In this phase, the light-emitting device L emits light.

[0224] During the pixel driving circuit's driving process, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its control electrode (also the first node N1) and the second electrode (also the third node N3). Since the voltage value of the signal at the first node V1 = Vdata - [Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2)] + Vinit, and the voltage value of the signal at the third node N3 V3 = Vinit, the driving current of the third transistor T3 is:

[0225] I=K*(Vgs-Vth) 2

[0226] =K*[Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]-Vth] 2

[0227] =K*[(C2 / (C1+C2))*(Vdata-Vref)] 2 .

[0228] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the control electrode and the second electrode of the third transistor T3.

[0229] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0230] Figure 17 for Figure 12 The working timing diagram of the pixel driving circuit provided is as follows. Figure 12 The operation process of the pixel driving circuit of the example illustrates an exemplary embodiment of the present disclosure. Figure 12 The pixel driving circuit includes 7 transistors (a first transistor T1 to a sixth transistor T6 and an eighth transistor T8) and two capacitors (a first capacitor C1 and a second capacitor C2), and all of the 7 transistors are N-type transistors.

[0231] In an exemplary embodiment, Figure 12 The working process of the provided pixel driving circuit may include:

[0232] The first phase P1 is called the first reset phase. The signals on the second scan signal line G2, the second light-emitting signal line EM2, the first reset signal line Reset1, and the third reset signal line Reset3 are high-level signals, while the signals on the first scan signal line G1 and the first light-emitting signal line EM1 are low-level signals. The signal on the second scan signal line G2 is high-level, the second transistor T2 is turned on, and the signal on the reference signal line REF is written to the first node N1, initializing (resetting) the signal on the first node N1 and clearing the existing charge on the first node N1. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the signal on the auxiliary signal line VX is written to the fifth node N5, initializing (resetting) the signal on the fifth node N5 and clearing the existing charge on the fifth node N5. The signals on the second light-emitting signal line EM2 and the third reset signal line Reset3 are high-level signals, the fifth transistor T5 and the eighth transistor T8 are turned on, and the signal on the initial signal line INIT is written to the third node N3 and the fourth node N4, respectively. Since the voltage values ​​of the signals on the first node N1 and the third node N3 are greater than the threshold voltage of the third transistor T3, the third transistor T3 is turned on, and the signal on the initial signal line INIT is written to the second node N2, initializing (resetting) the signals on the second node N2, the third node N3, and the fourth node N4, clearing the existing charges on the second node N2, the third node N3, and the fourth node N4. The signals on the first scanning signal line G1 and the first light-emitting signal line EM1 are low-level signals, and the first transistor T1 and the fourth transistor T4 are turned off. At this stage, the light-emitting device L does not emit light.

[0233] In the second phase P2, i.e., the threshold compensation phase, the signals on the first reset signal line Reset1, the third reset signal line Reset3, the second scan signal line G2, and the first light-emitting signal line EM1 are high-level signals, while the signals on the first scan signal line G1 and the second light-emitting signal line EM2 are low-level signals. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the signal on the auxiliary signal line VX is continuously written to the fifth node N5, continuously initializing (resetting) the signal on the fifth node N5. The signal on the third reset signal line Reset3 is high-level, the eighth transistor T8 is turned on, and the signal on the initialization signal line INIT is continuously written to the fourth node N4, continuously initializing (resetting) the signal on the fourth node N4. The signal on the second scan signal line G2 is high, the second transistor T2 is turned on, the signal on the reference signal line REF is continuously supplied to the first node N1, the signal on the first emission signal line EM1 is high, the fourth transistor T4 is turned on, and the signal on the first power line VDD is written to the third node N3 via the turned-on fourth transistor T4, the second node N2, and the turned-on third transistor T3, until the voltage V3 of the signal on the third node N3 reaches Vref - Vth, where Vref is the voltage value of the signal on the initial signal line REF and Vth is the threshold voltage of the third transistor T3. At this point, the first capacitor C1 stores the voltage difference Vth between the signals on the first node N1 and the third node N3. The signals on the first scan signal line G1 and the second emission signal line EM2 are low, and the first transistor T1 and the fifth transistor T5 are turned off. During this stage, the light-emitting device L does not emit light.

[0234] In the third phase P3, the data writing phase, the signals on the first reset signal line Reset1, the third reset signal line Reset3, and the first scan signal line G1 are high-level signals, the signals on the second scan signal line G2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are low-level signals, and the data signal line Data outputs a data voltage. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the signal on the auxiliary signal line VX is continuously written to the fifth node N5, continuously initializing (resetting) the signal on the fifth node N5. The signal on the third reset signal line Reset3 is high-level, the eighth transistor T8 is turned on, and the signal on the initialization signal line INIT is continuously written to the fourth node N4, continuously initializing (resetting) the signal on the fourth node N4. The signal on the first scan signal line G1 is high, turning on the first transistor T1. The data voltage on the data signal line Data is written to the first node N1. At this point, the voltage V1 of the first node N1 equals Vdata, where Vdata is the data voltage on the data signal line. The signal on the first node N1 changes from its current voltage value to its previous voltage value. Therefore, under the action of the first capacitor C1 and the second capacitor C2, the signal on the third node N3 also changes. At this point, the voltage V3 of the signal on the third node N3 equals Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2), where C1 is the capacitance of the first capacitor and C2 is the capacitance of the second capacitor. The signals on the second scan signal line G2, the first emission signal line EM1, and the second emission signal line EM2 are low, turning off the second transistor T2, the fourth transistor T4, and the fifth transistor T5. In this stage, the light-emitting device L does not emit light.

[0235] In the fourth phase P4, referred to as the second reset phase, the first reset signal line Reset1, the third reset signal line Reset3, and the second light-emitting signal line EM2 are high-level signals, while the signals on the first light-emitting signal line EM1, the first scanning signal line G1, and the second scanning signal line G2 are low-level signals. The signal on the third reset signal line Reset3 is high-level, the eighth transistor T8 is turned on, and the signal on the initialization signal line INIT is continuously written to the fourth node N4, continuously initializing (resetting) the signal on the fourth node N4. The signal on the second light-emitting signal line EM2 is high-level, the fifth transistor T5 is turned on, and the voltage V3 of the signal on the third node N3 is equal to Vinit, where Vinit is the voltage value of the signal on the initialization signal line. At this time, the first node N1 is pulled down by the first capacitor C1, so that the voltage V1 of the signal on the first node N1 is equal to Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]+Vinit. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the voltages of the signals on the third node N3 and the fifth node N5 are kept consistent. The signals of the first reset signal line Reset1, the first light emitting signal line EM1, the first scanning signal line G1 and the second scanning signal line G2 are low level signals, and the first transistor T1, the second transistor T2 and the fourth transistor T4 are turned off. In this stage, the light emitting device L does not emit light.

[0236] In the fifth phase P5, i.e., the light-emitting phase, the signals on the first reset signal line Reset1, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals, while the signals on the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals. The signals on the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are high-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, and the power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fourth transistor T4, third transistor T3, and fifth transistor T5, driving the light-emitting device L to emit light. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the voltages of the signals on the third node N3 and the fifth node N5 remain consistent. The signals on the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals, and the first transistor T1, the second transistor T2, and the eighth transistor T8 are turned off. In this phase, the light-emitting device L emits light.

[0237] During the pixel driving circuit's driving process, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its control electrode (also the first node N1) and the second electrode (also the third node N3). Since the voltage value of the signal at the first node V1 = Vdata - [Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2)] + Vinit, and the voltage value of the signal at the third node N3 V3 = Vinit, the driving current of the third transistor T3 is:

[0238] I=K*(Vgs-Vth) 2

[0239] =K*[Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]-Vth] 2

[0240] =K*[(C2 / (C1+C2))*(Vdata-Vref)] 2 .

[0241] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the control electrode and the second electrode of the third transistor T3.

[0242] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0243] for Figures 9 to 12 In the fourth and fifth stages of the provided pixel driving circuit, the signals of the third node N3 and the fifth node N5 at both ends of the second capacitor C2 remain consistent, so that the third node of the pixel driving circuit will not be affected by the coupling effect of the second capacitor C2 in the fifth stage, which can improve the stability of the driving current of the pixel driving circuit and improve the reliability of the pixel driving circuit.

[0244] Figure 18 for Figure 13 and Figure 14 The working timing diagram of the pixel driving circuit provided is as follows. Figure 13 and Figure 14 The operation process of the pixel driving circuit of the example illustrates an exemplary embodiment of the present disclosure. Figure 13 and Figure 14The pixel driving circuit includes 7 transistors (a first transistor T1 to a sixth transistor T6 and an eighth transistor T8) and two capacitors (a first capacitor C1 and a second capacitor C2), and all of the 7 transistors are N-type transistors.

[0245] In an exemplary embodiment, Figure 13 and Figure 14 The working process of the provided pixel driving circuit may include:

[0246] The first phase P1 is called the first reset phase. The signals on the second scan signal line G2, the second light-emitting signal line EM2, the first reset signal line Reset1, and the third reset signal line Reset3 are high-level signals, while the signals on the first scan signal line G1 and the first light-emitting signal line EM1 are low-level signals. The signal on the second scan signal line G2 is high-level, the second transistor T2 is turned on, and the signal on the reference signal line REF is written to the first node N1, initializing (resetting) the signal on the first node N1 and clearing the existing charge on the first node N1. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the signal on the auxiliary signal line VX is written to the fifth node N5, initializing (resetting) the signal on the fifth node N5 and clearing the existing charge on the fifth node N5. The signals on the second light-emitting signal line EM2 and the third reset signal line Reset3 are high-level signals, the fifth transistor T5 and the eighth transistor T8 are turned on, and the signal on the initial signal line INIT is written to the third node N3 and the fourth node N4, respectively. Since the voltage values ​​of the signals on the first node N1 and the third node N3 are greater than the threshold voltage of the third transistor T3, the third transistor T3 is turned on, and the signal on the initial signal line INIT is written to the second node N2, initializing (resetting) the signals on the second node N2, the third node N3, and the fourth node N4, clearing the existing charges on the second node N2, the third node N3, and the fourth node N4. The signals on the first scanning signal line G1 and the first light-emitting signal line EM1 are low-level signals, and the first transistor T1 and the fourth transistor T4 are turned off. At this stage, the light-emitting device L does not emit light.

[0247] In the second phase P2, i.e., the threshold compensation phase, the signals on the first reset signal line Reset1, the third reset signal line Reset3, the second scan signal line G2, and the first light-emitting signal line EM1 are high-level signals, while the signals on the first scan signal line G1 and the second light-emitting signal line EM2 are low-level signals. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the signal on the auxiliary signal line VX is continuously written to the fifth node N5, continuously initializing (resetting) the signal on the fifth node N5. The signal on the third reset signal line Reset3 is high-level, the eighth transistor T8 is turned on, and the signal on the initialization signal line INIT is continuously written to the fourth node N4, continuously initializing (resetting) the signal on the fourth node N4. The signal on the second scan signal line G2 is high, the second transistor T2 is turned on, the signal on the reference signal line REF is continuously supplied to the first node N1, the signal on the first emission signal line EM1 is high, the fourth transistor T4 is turned on, and the signal on the first power line VDD is written to the third node N3 via the turned-on fourth transistor T4, the second node N2, and the turned-on third transistor T3, until the voltage V3 of the signal on the third node N3 reaches Vref - Vth, where Vref is the voltage value of the signal on the initial signal line REF and Vth is the threshold voltage of the third transistor T3. At this point, the first capacitor C1 stores the voltage difference Vth between the signals on the first node N1 and the third node N3. The signals on the first scan signal line G1 and the second emission signal line EM2 are low, and the first transistor T1 and the fifth transistor T5 are turned off. During this stage, the light-emitting device L does not emit light.

[0248] In the third phase P3, the data writing phase, the signals on the first reset signal line Reset1, the third reset signal line Reset3, and the first scan signal line G1 are high-level signals, the signals on the second scan signal line G2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are low-level signals, and the data signal line Data outputs a data voltage. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the signal on the auxiliary signal line VX is continuously written to the fifth node N5, continuously initializing (resetting) the signal on the fifth node N5. The signal on the third reset signal line Reset3 is high-level, the eighth transistor T8 is turned on, and the signal on the initialization signal line INIT is continuously written to the fourth node N4, continuously initializing (resetting) the signal on the fourth node N4. The signal on the first scan signal line G1 is high, turning on the first transistor T1. The data voltage on the data signal line Data is written to the first node N1. At this point, the voltage V1 of the first node N1 equals Vdata, where Vdata is the data voltage on the data signal line. The signal on the first node N1 changes from its current voltage value to its previous voltage value. Therefore, under the action of the first capacitor C1 and the second capacitor C2, the signal on the third node N3 also changes. At this point, the voltage V3 of the signal on the third node N3 equals Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2), where C1 is the capacitance of the first capacitor and C2 is the capacitance of the second capacitor. The signals on the second scan signal line G2, the first emission signal line EM1, and the second emission signal line EM2 are low, turning off the second transistor T2, the fourth transistor T4, and the fifth transistor T5. In this stage, the light-emitting device L does not emit light.

[0249] The fourth phase P4, referred to as the second reset phase, is characterized by the high-level signals of the third reset signal line Reset3 and the second light-emitting signal line EM2, while the signals of the first reset signal line Reset1, the first light-emitting signal line EM1, the first scanning signal line G1, and the second scanning signal line G2 are low-level signals. The signal of the third reset signal line Reset3 is high-level, the eighth transistor T8 is turned on, and the signal of the initialization signal line INIT is continuously written to the fourth node N4, continuously initializing (resetting) the signal of the fourth node N4. The signal of the second light-emitting signal line EM2 is high-level, the fifth transistor T5 is turned on, and the voltage V3 of the signal at the third node N3 is equal to Vinit, where Vinit is the voltage value of the signal of the initialization signal line. At this time, the first node N1 is pulled low by the action of the first capacitor C1, so that the voltage V1 of the signal at the first node N1 is equal to Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]+Vinit. The signals of the first reset signal line Reset1, the first light emitting signal line EM1, the first scanning signal line G1 and the second scanning signal line G2 are low level signals, and the first transistor T1, the second transistor T2, the fourth transistor T4 and the sixth transistor T6 are turned off. In this stage, the light emitting device L does not emit light.

[0250] In the fifth phase P5, i.e., the light-emitting phase, the signals on the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are high-level signals, while the signals on the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals. The signals on the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are high-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, and the power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fourth transistor T4, the third transistor T3, and the fifth transistor T5, driving the light-emitting device L to emit light. The signal on the first reset signal line Reset1 is high-level, the sixth transistor T6 is turned on, and the voltages of the signals on the third node N3 and the fifth node N5 remain consistent. The signals on the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals. The first transistor T1, the second transistor T2, the sixth transistor T6, and the eighth transistor T8 are turned off. In this phase, the light-emitting device L emits light.

[0251] During the pixel driving circuit's driving process, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its control electrode (also the first node N1) and the second electrode (also the third node N3). Since the voltage value of the signal at the first node V1 = Vdata - [Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2)] + Vinit, and the voltage value of the signal at the third node N3 V3 = Vinit, the driving current of the third transistor T3 is:

[0252] I=K*(Vgs-Vth) 2

[0253] =K*[Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]-Vth] 2

[0254] =K*[(C2 / (C1+C2))*(Vdata-Vref)] 2 .

[0255] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the control electrode and the second electrode of the third transistor T3.

[0256] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0257] for Figure 13 and Figure 14 In the fourth and fifth stages of the provided pixel driving circuit, the sixth transistor T6, in which the second capacitor C2 and the third node N3 are disconnected, is disconnected, so that the third node of the pixel driving circuit is not affected by the coupling effect of the second capacitor C2 in the fifth stage, thereby improving the stability of the driving current of the pixel driving circuit and improving the reliability of the pixel driving circuit.

[0258] Figure 19 FIG. 1 is a structural diagram of another pixel driving circuit provided by an embodiment of the present disclosure. Figure 19 As shown, the pixel driving circuit provided by the embodiment of the present disclosure is arranged in a display device, and includes: a driving subcircuit, a storage subcircuit, a first control subcircuit, a second control subcircuit and a third control subcircuit.

[0259] like Figure 19As shown, the driving sub-circuit is electrically connected to the first node N1, the second node N2 and the third node N3, respectively, and is configured to provide a driving current to the third node N3 under the control of the signals of the first node N1 and the second node N2; the storage sub-circuit is electrically connected to the first node N1 and the third node N3, respectively, and is configured to store the voltage difference of the signal between the first node N1 and the third node N3; the first control sub-circuit is electrically connected to the first scan signal line G1, the second scan signal line G2, the data signal line Data, the reference signal line REF and the first node N1, respectively, and is configured to provide the signal of the data signal line Data or the reference signal line REF to the first node N1 under the control of the signals of the first scan signal line G1 and the second scan signal line G2; the second control sub-circuit is electrically connected to the first light emitting signal line G1, the second scan signal line G2, the data signal line Data, the reference signal line REF and the first node N1, respectively, and is configured to provide the signal of the data signal line Data or the reference signal line REF to the first node N1 under the control of the signals of the first scan signal line G1 and the second scan signal line G2; The first control sub-circuit is electrically connected to the first light-emitting signal line EM1, the second light-emitting signal line EM2, the first power line VDD, the second node N2, the third node N3 and the fourth node N4, and is configured to provide the signal of the first power line VDD to the second node N2 and the signal of the third node N3 to the fourth node N4 under the control of the signal of the first light-emitting signal line EM1 and the second light-emitting signal line EM2; the third control sub-circuit is electrically connected to the third node N3, the fourth node N4, at least one reset signal line Reset and at least one signal line among the dynamic signal line Var and the auxiliary signal line VX, respectively, and is configured to adjust the signals of the third node N3 and the fourth node N4 under the control of the signal of the at least one reset signal line Reset and at least one signal line among the dynamic signal line Var and the auxiliary signal line VX.

[0260] Figure 20 is a schematic diagram of the structure of the display device, such as Figure 20 As shown, the display device includes: a first control unit, a second control unit and a data unit, the first control unit is electrically connected to the second light-emitting signal line EM2, and is configured to provide a signal to the second light-emitting signal line EM2, the second control unit is electrically connected to at least one reset signal line Reset, and is configured to provide a signal to at least one reset signal line Reset, and the data unit is electrically connected to the dynamic signal line Var, and is configured to provide a signal to the dynamic signal line Var.

[0261] In an exemplary embodiment, the content displayed by the display device includes at least one display frame, and in the at least one display frame, the start time of at least one time period in which the first control unit provides a valid level signal to the second light emitting signal line EM2 is earlier than or equal to the start time in which the second control unit provides an invalid level signal to the at least one reset signal line.

[0262] In an exemplary embodiment, Figure 19 As shown, the pixel driving circuit is electrically connected to the light emitting device L through the fourth node N4. The light emitting device L is also electrically connected to the second power line VSS.

[0263] In an exemplary embodiment, the first power line VDD continuously provides a high-level signal, and the signal of the first power line VDD is a DC signal.

[0264] In an exemplary embodiment, the second power line VSS continuously provides a low-level signal, and the signal of the second power line VSS is a DC signal.

[0265] In an exemplary embodiment, the reference signal line REF continuously provides a low-level signal. The signal of the reference signal line REF is a DC signal. Exemplarily, the voltage of the signal of the reference signal line REF may be 0V.

[0266] The mobility of the oxide thin-film transistors in the pixel drive circuit varies with the temperature of the display device. As the temperature of the display device increases, the change in the mobility of the oxide thin-film transistors and the change in the voltage across the OLED will cause the brightness of the display substrate to increase, resulting in uneven brightness of the display substrate at different temperatures, affecting the display effect of the display device. However, the present disclosure uses a third control subcircuit to adjust the signals of the third node and the fourth node under the control of the signals of at least one reset signal line and at least one of the dynamic signal line and the auxiliary signal line. By adjusting the signal of the dynamic signal line, the temperature of the display device is reduced, thereby reducing the impact of the temperature change of the display device on the display brightness, improving the brightness uniformity of the display device at different temperatures, and ensuring the display effect of the display device.

[0267] In an exemplary embodiment, the voltage value of the signal of the dynamic signal line Var includes: a plurality of voltage values, and during at least a portion of at least one display frame, the voltage value of the dynamic signal provided by the data unit to the dynamic signal line Var is positively correlated with the temperature of the display device.

[0268] In an exemplary embodiment, the dynamic signal line Var may be an initial signal line.

[0269] Figure 21 for Figure 19 Schematic diagram of the structure of the pixel driving circuit provided Figure 1 .like Figure 21 As shown, the at least one reset signal line may include a third reset signal line Reset3. The third control sub-circuit may be electrically connected to the third node N3, the fourth node N4, the third reset signal line Reset3 and the dynamic signal line Var respectively.

[0270] Figure 22A for Figure 21 The equivalent circuit diagram of the pixel driving circuit provided, Figure 22B for Figure 21 The equivalent circuit of the pixel driving circuit provided Figure 2 .like Figure 22A and Figure 22B As shown, the driving subcircuit includes: a third transistor T3, the first control subcircuit includes: a first transistor T1 and a second transistor T2, the second control subcircuit includes: a fourth transistor T4 and a fifth transistor T5, the storage subcircuit includes: a first capacitor C1; the third control subcircuit includes: a second capacitor C2 and an eighth transistor T8. The control electrode of the first transistor T1 is electrically connected to the first scan signal line G1, the first electrode of the first transistor T1 is electrically connected to the data signal line Data, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the second scan signal line G2, the first electrode of the second transistor T2 is electrically connected to the reference signal line REF, and the second electrode of the second transistor T2 is electrically connected to the first node N1; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first light emitting signal line EM1, and the first electrode of the fourth transistor T4 is electrically connected to the first power line VD D is electrically connected, the second electrode of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the second light-emitting signal line EM2, the first electrode of the fifth transistor T5 is electrically connected to the third node N3, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4; the control electrode of the eighth transistor T8 is electrically connected to the third reset signal line Reset3, the first electrode of the eighth transistor T8 is electrically connected to the dynamic signal line Var, and the second electrode of the eighth transistor T8 is electrically connected to the fourth node N4; the first end of the first capacitor C1 is electrically connected to the first power supply line VDD, and the second end of the first capacitor C1 is electrically connected to the first node N1; the first end of the second capacitor C2 is electrically connected to the third node N3, and the second end of the second capacitor C2 is electrically connected to the fourth node N4.

[0271] In an exemplary embodiment, Figure 22A and Figure 22B Any of the first to fifth transistors T1 to T5 and the eighth transistor T8 in the pixel driving circuit may be an N-type transistor or a P-type transistor. The first to fifth transistors T1 to T5 and the eighth transistor T8 may all be N-type transistors, or the first to fifth transistors T1 to T5 and the eighth transistor T8 may all be P-type transistors. Using transistors of the same type in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield. In some possible implementations, the first to fifth transistors T1 to T5 and the eighth transistor T8 may include P-type transistors and N-type transistors.

[0272] Figure 22AThe following description is made by taking as an example any transistor among the first transistor T1 to the fifth transistor T5 and the eighth transistor T8 as an N-type transistor. Figure 22B The description is made by taking as an example that the first transistor T1 , the second transistor T2 , the third transistor T3 and the eighth transistor T8 are N-type transistors, and the fourth transistor T4 and the fifth transistor T5 are P-type transistors.

[0273] In an exemplary embodiment, according to actual needs, one of the fourth transistor T4 and the fifth transistor T5 may be a P-type transistor. For example, the fourth transistor T4 is a P-type transistor, or the fifth transistor T5 is a P-type transistor.

[0274] In an exemplary embodiment, the P-type transistor may be a low temperature polysilicon (LTPS) thin film transistor, and the N-type transistor may be an oxide thin film transistor.

[0275] Figure 22B The pixel driving circuit provided is Figure 22A Compared with the pixel driving circuit provided, the fourth transistor T4 and the fifth transistor T5 are of different transistor types. Figure 22B In the provided pixel driving circuit, the fourth transistor T4 and the fifth transistor T5 are P-type transistors, which can reduce the width-to-length ratio of the channel region of at least one of the fourth transistor T4 and the fifth transistor T5, improve the mobility of at least one of the fourth transistor T4 and the fifth transistor T5, and thereby reduce the switching power consumption of at least one of the fourth transistor T4 and the fifth transistor T5, thereby reducing the power consumption of the display device in which the pixel driving circuit is located.

[0276] Figure 23 FIG22 is a schematic diagram of the structure of the display device where the pixel driving circuit is provided. Figure 23 As shown, in an exemplary embodiment, the display device further includes: a third control unit, the third control unit being electrically connected to the first light emitting signal line EM1 and configured to provide a signal to the first light emitting signal line EM1, wherein, in at least one display frame, a start time of at least one time period in which the first control unit provides a valid level signal to the second light emitting signal line EM2 is earlier than a start time in which the second control unit provides an invalid level signal to the third reset signal line Reset3, and a start time of at least one time period in which the third control unit provides a valid level signal to the first light emitting signal line EM1 is later than a start time in which the second control unit provides an invalid level signal to the third reset signal line Reset3.

[0277] Figure 24 for Figure 19 Schematic diagram of the structure of the pixel driving circuit provided Figure 2.like Figure 24 As shown, at least one reset signal line includes: a first reset signal line Reset1 and a third reset signal line Reset3. The third control subcircuit is electrically connected to the third node N3, the fourth node N4, the first reset signal line Reset1, the third reset signal line Reset3 and the dynamic signal line Var respectively.

[0278] Figure 25A for Figure 24 The equivalent circuit of the pixel driving circuit provided Figure 1 , Figure 25B for Figure 24 The equivalent circuit of the pixel driving circuit provided Figure 2 .like Figure 25A and Figure 25B As shown, the driving subcircuit includes: a third transistor T3, the first control subcircuit includes: a first transistor T1 and a second transistor T2, the second control subcircuit includes: a fourth transistor T4 and a fifth transistor T5, the storage subcircuit includes: a first capacitor C1, and the third control subcircuit includes: a second capacitor C2, a sixth transistor T6 and an eighth transistor T8. Among them, the control electrode of the first transistor T1 is electrically connected to the first scan signal line G1, the first electrode of the first transistor T1 is electrically connected to the data signal line Data, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the second scan signal line G2, the first electrode of the second transistor T2 is electrically connected to the reference signal line REF, and the second electrode of the second transistor T2 is electrically connected to the first node N1; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first light emitting signal line EM1, the first electrode of the fourth transistor T4 is electrically connected to the first power supply line VDD, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The control electrode of the sixth transistor T6 is electrically connected to the first reset signal line Reset1, the first electrode of the sixth transistor T6 is electrically connected to the fifth node N5, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4; the control electrode of the eighth transistor T8 is electrically connected to the third reset signal line Reset3, the first electrode of the eighth transistor T8 is electrically connected to the dynamic signal line Var, and the second electrode of the eighth transistor T8 is electrically connected to the fourth node N4; the first end of the first capacitor C1 is electrically connected to the first power supply line VDD, and the second end of the first capacitor C1 is electrically connected to the first node N1; the first end of the second capacitor C2 is electrically connected to the third node N3, and the second end of the second capacitor C2 is electrically connected to the fifth node N5.

[0279] Figure 26A for Figure 24 The equivalent circuit of the pixel driving circuit provided Figure 3 , Figure 26B for Figure 24 The equivalent circuit of the pixel driving circuit provided Figure 4 .like Figure 26A and Figure 26B As shown, the driving subcircuit includes: a third transistor T3, the first control subcircuit includes: a first transistor T1 and a second transistor T2, the second control subcircuit includes: a fourth transistor T4 and a fifth transistor T5, the storage subcircuit includes: a first capacitor C1, and the third control subcircuit includes: a second capacitor C2, a third capacitor C3, a sixth transistor T6 and an eighth transistor T8. Among them, the control electrode of the first transistor T1 is electrically connected to the first scan signal line G1, the first electrode of the first transistor T1 is electrically connected to the data signal line Data, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the second scan signal line G2, the first electrode of the second transistor T2 is electrically connected to the reference signal line REF, and the second electrode of the second transistor T2 is electrically connected to the first node N1; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first light-emitting signal line EM1, the first electrode of the fourth transistor T4 is electrically connected to the first power supply line VDD, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the second light-emitting signal line EM2, and the fifth transistor T5 is electrically connected to the second light-emitting signal line EM2. A first electrode of T5 is electrically connected to the third node N3, and a second electrode of the fifth transistor T5 is electrically connected to the fourth node N4; a control electrode of the sixth transistor T6 is electrically connected to the first reset signal line Reset1, and a first electrode of the sixth transistor T6 is electrically connected to the fifth node N5; a second electrode of the sixth transistor T6 is electrically connected to the fourth node N4; a control electrode of the eighth transistor T8 is electrically connected to the third reset signal line Reset3, a first electrode of the eighth transistor T8 is electrically connected to the dynamic signal line Var, and a second electrode of the eighth transistor T8 is electrically connected to the fourth node N4; a first end of the first capacitor C1 is electrically connected to the first power supply line VDD, and a second end of the first capacitor C1 is electrically connected to the first node N1; a first end of the second capacitor C2 is electrically connected to the third node N3, and a second end of the second capacitor C2 is electrically connected to the fifth node N5; a first end of the third capacitor C3 is electrically connected to the fifth node N5, and a second end of the third capacitor C3 is electrically connected to the fourth node N4.

[0280] In an exemplary embodiment, Figure 25A 、 Figure 25B 、 Figure 26A and Figure 26B Any of the first to fifth transistors T1 to T5, the sixth transistor T6, and the eighth transistor T8 may be an N-type transistor or a P-type transistor. The first to fifth transistors T1 to T5, the sixth transistor T6, and the eighth transistor T8 may all be N-type transistors, or the first to fifth transistors T1 to T5, the sixth transistor T6, and the eighth transistor T8 may all be P-type transistors. Using transistors of the same type in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield. In some possible implementations, the first to fifth transistors T1 to T5, the sixth transistor T6, and the eighth transistor T8 may include P-type transistors and N-type transistors.

[0281] Figure 25A and Figure 26A The following description is made by taking as an example any transistor among the first transistor T1 to the fifth transistor T5, the sixth transistor T6 and the eighth transistor T8 as an N-type transistor. Figure 25B and Figure 26B The description is made by taking the example that the first transistor T1 , the second transistor T2 , the third transistor T3 , the sixth transistor T6 and the eighth transistor T8 are N-type transistors, and the fourth transistor T4 and the fifth transistor T5 are P-type transistors.

[0282] In an exemplary embodiment, according to actual needs, one of the fourth transistor T4 and the fifth transistor T5 may be a P-type transistor. For example, the fourth transistor T4 is a P-type transistor, or the fifth transistor T5 is a P-type transistor.

[0283] In an exemplary embodiment, the P-type transistor may be a low temperature polysilicon (LTPS) thin film transistor, and the N-type transistor may be an oxide thin film transistor.

[0284] Figure 25B The pixel driving circuit provided is Figure 25A Compared with the pixel driving circuit provided, the fourth transistor T4 and the fifth transistor T5 are of different transistor types. Figure 25B In the provided pixel driving circuit, the fourth transistor T4 and the fifth transistor T5 are P-type transistors, which can reduce the width-to-length ratio of the channel region of at least one of the fourth transistor T4 and the fifth transistor T5, improve the mobility of at least one of the fourth transistor T4 and the fifth transistor T5, and thereby reduce the switching power consumption of at least one of the fourth transistor T4 and the fifth transistor T5, thereby reducing the power consumption of the display device in which the pixel driving circuit is located.

[0285] Figure 26B The pixel driving circuit provided is Figure 26A Compared with the pixel driving circuit provided, the fourth transistor T4 and the fifth transistor T5 are of different transistor types. Figure 26B In the provided pixel driving circuit, the fourth transistor T4 and the fifth transistor T5 are P-type transistors, which can reduce the width-to-length ratio of the channel region of at least one of the fourth transistor T4 and the fifth transistor T5, improve the mobility of at least one of the fourth transistor T4 and the fifth transistor T5, and thereby reduce the switching power consumption of at least one of the fourth transistor T4 and the fifth transistor T5, thereby reducing the power consumption of the display device in which the pixel driving circuit is located.

[0286] Figure 27 for Figure 19 Schematic diagram of the structure of the pixel driving circuit provided Figure 3 .like Figure 27 As shown, at least one reset signal line includes: a first reset signal line Reset1 and a third reset signal line Reset3. The third control sub-circuit is electrically connected to the third node N3, the fourth node N4, the first reset signal line Reset1, the third reset signal line Reset3, the dynamic signal line Var, and the auxiliary signal line VX.

[0287] Figure 28A for Figure 27 The equivalent circuit of the pixel driving circuit provided Figure 1 , Figure 28B for Figure 27 The equivalent circuit of the pixel driving circuit provided Figure 2 .like Figure 28A and Figure 28BAs shown, the driving subcircuit includes: a third transistor T3, the first control subcircuit includes: a first transistor T1 and a second transistor T2, the second control subcircuit includes: a fourth transistor T4 and a fifth transistor T5, the storage subcircuit includes: a first capacitor C1; the third control subcircuit includes: a second capacitor C2, a third capacitor C3, a sixth transistor T6 and an eighth transistor T8. Among them, the control electrode of the first transistor T1 is electrically connected to the first scan signal line G1, the first electrode of the first transistor T1 is electrically connected to the data signal line Data, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the second scan signal line G2, the first electrode of the second transistor T2 is electrically connected to the reference signal line REF, and the second electrode of the second transistor T2 is electrically connected to the first node N1; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first light-emitting signal line EM1, the first electrode of the fourth transistor T4 is electrically connected to the first power supply line VDD, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the second light-emitting signal line EM2, and the fifth transistor T5 is electrically connected to the second light-emitting signal line EM2. A first electrode of T5 is electrically connected to the third node N3, and a second electrode of the fifth transistor T5 is electrically connected to the fourth node N4; a control electrode of the sixth transistor T6 is electrically connected to the first reset signal line Reset1, a first electrode of the sixth transistor T6 is electrically connected to the fifth node N5, and a second electrode of the sixth transistor T6 is electrically connected to the fourth node N4; a control electrode of the eighth transistor T8 is electrically connected to the third reset signal line Reset3, a first electrode of the eighth transistor T8 is electrically connected to the dynamic signal line Var, and a second electrode of the eighth transistor T8 is electrically connected to the fourth node N4; a first end of the first capacitor C1 is electrically connected to the first power supply line VDD, and a second end of the first capacitor C1 is electrically connected to the first node N1; a first end of the second capacitor C2 is electrically connected to the third node N3, and a second end of the second capacitor C2 is electrically connected to the fifth node N5; a first end of the third capacitor C3 is electrically connected to the fifth node N5, and a second end of the third capacitor C3 is electrically connected to the auxiliary signal line VX.

[0288] In an exemplary embodiment, Figure 28A and Figure 28BAny of the first to fifth transistors T1 to T5, the sixth transistor T6, and the eighth transistor T8 may be an N-type transistor or a P-type transistor. The first to fifth transistors T1 to T5, the sixth transistor T6, and the eighth transistor T8 may all be N-type transistors, or the first to fifth transistors T1 to T5, the sixth transistor T6, and the eighth transistor T8 may all be P-type transistors. Using transistors of the same type in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield. In some possible implementations, the first to fifth transistors T1 to T5, the sixth transistor T6, and the eighth transistor T8 may include P-type transistors and N-type transistors.

[0289] Figure 28A The following description is made by taking as an example any transistor among the first transistor T1 to the fifth transistor T5, the sixth transistor T6 and the eighth transistor T8 as an N-type transistor. Figure 28B The description is made by taking the example that the first transistor T1 , the second transistor T2 , the third transistor T3 , the sixth transistor T6 and the eighth transistor T8 are N-type transistors, and the fourth transistor T4 and the fifth transistor T5 are P-type transistors.

[0290] In an exemplary embodiment, according to actual needs, one of the fourth transistor T4 and the fifth transistor T5 may be a P-type transistor. For example, the fourth transistor T4 is a P-type transistor, or the fifth transistor T5 is a P-type transistor.

[0291] In an exemplary embodiment, the P-type transistor may be a low temperature polysilicon (LTPS) thin film transistor, and the N-type transistor may be an oxide thin film transistor.

[0292] Figure 28B The pixel driving circuit provided is Figure 28A Compared with the pixel driving circuit provided, the fourth transistor T4 and the fifth transistor T5 are of different transistor types. Figure 28B In the provided pixel driving circuit, the fourth transistor T4 and the fifth transistor T5 are P-type transistors, which can reduce the width-to-length ratio of the channel region of at least one of the fourth transistor T4 and the fifth transistor T5, improve the mobility of at least one of the fourth transistor T4 and the fifth transistor T5, and thereby reduce the switching power consumption of at least one of the fourth transistor T4 and the fifth transistor T5, thereby reducing the power consumption of the display device in which the pixel driving circuit is located.

[0293] Figure 29 for Figure 19 Schematic diagram of the structure of the pixel driving circuit provided Figure 4 .like Figure 29 As shown, at least one reset signal line includes: a first reset signal line Reset1 and a third reset signal line Reset3. The third control sub-circuit is electrically connected to the third node N3, the fourth node N4, the first reset signal line Reset1, the third reset signal line Reset3 and the auxiliary signal line VX respectively.

[0294] Figure 30A for Figure 29 The equivalent circuit of the pixel driving circuit provided Figure 1 , Figure 30B for Figure 29 The equivalent circuit of the pixel driving circuit provided Figure 2 .like Figure 30A and Figure 30BAs shown, the driving subcircuit includes: a third transistor T3, the first control subcircuit includes: a first transistor T1 and a second transistor T2, the second control subcircuit includes: a fourth transistor T4 and a fifth transistor T5, the storage subcircuit includes: a first capacitor C1; the third control subcircuit includes: a second capacitor C2, a third capacitor C3, a sixth transistor T6 and a ninth transistor T9. Among them, the control electrode of the first transistor T1 is electrically connected to the first scan signal line G1, the first electrode of the first transistor T1 is electrically connected to the data signal line Data, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the second scan signal line G2, the first electrode of the second transistor T2 is electrically connected to the reference signal line REF, and the second electrode of the second transistor T2 is electrically connected to the first node N1; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first light-emitting signal line EM1, the first electrode of the fourth transistor T4 is electrically connected to the first power line VDD, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the second light-emitting signal line EM2, and the fifth transistor T5 is electrically connected to the second light-emitting signal line EM2. A first electrode of the transistor T5 is electrically connected to the third node N3, and a second electrode of the fifth transistor T5 is electrically connected to the fourth node N4; a control electrode of the sixth transistor T6 is electrically connected to the first reset signal line Reset1, a first electrode of the sixth transistor T6 is electrically connected to the fifth node N5, and a second electrode of the sixth transistor T6 is electrically connected to the fourth node N4; a control electrode of the ninth transistor T9 is electrically connected to the third reset signal line Reset3, a first electrode of the ninth transistor T9 is electrically connected to the auxiliary signal line VX, and a second electrode of the ninth transistor T9 is electrically connected to the fifth node N5; a first end of the first capacitor C1 is electrically connected to the first power supply line VDD, and a second end of the first capacitor C1 is electrically connected to the first node N1; a first end of the second capacitor C2 is electrically connected to the third node N3, and a second end of the second capacitor C2 is electrically connected to the fifth node N5; a first end of the third capacitor C3 is electrically connected to the fifth node N5, and a second end of the third capacitor C3 is electrically connected to the fourth node N4.

[0295] In an exemplary embodiment, Figure 30A and Figure 30BAny of the first to fifth transistors T1 to T5, the sixth transistor T6, and the ninth transistor T9 in the pixel driving circuit may be an N-type transistor or a P-type transistor. The first to fifth transistors T1 to T5, the sixth transistor T6, and the ninth transistor T9 may all be N-type transistors, or the first to fifth transistors T1 to T5, the sixth transistor T6, and the ninth transistor T9 may all be P-type transistors. Using transistors of the same type in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield. In some possible implementations, the first to fifth transistors T1 to T5, the sixth transistor T6, and the ninth transistor T9 may include P-type transistors and N-type transistors.

[0296] Figure 30A The following description is made by taking as an example any transistor among the first transistor T1 to the fifth transistor T5, the sixth transistor T6 and the ninth transistor T9 as an N-type transistor. Figure 30B The description is made by taking the example that the first transistor T1 , the second transistor T2 , the third transistor T3 , the sixth transistor T6 and the ninth transistor T9 are N-type transistors, and the fourth transistor T4 and the fifth transistor T5 are P-type transistors.

[0297] In an exemplary embodiment, according to actual needs, one of the fourth transistor T4 and the fifth transistor T5 may be a P-type transistor. For example, the fourth transistor T4 is a P-type transistor, or the fifth transistor T5 is a P-type transistor.

[0298] In an exemplary embodiment, the P-type transistor may be a low temperature polysilicon (LTPS) thin film transistor, and the N-type transistor may be an oxide thin film transistor. Figure 30B The pixel driving circuit provided is Figure 30A Compared with the pixel driving circuit provided, the fourth transistor T4 and the fifth transistor T5 are of different transistor types. Figure 30B In the provided pixel driving circuit, the fourth transistor T4 and the fifth transistor T5 are P-type transistors, which can reduce the width-to-length ratio of the channel region of at least one of the fourth transistor T4 and the fifth transistor T5, improve the mobility of at least one of the fourth transistor T4 and the fifth transistor T5, and thereby reduce the switching power consumption of at least one of the fourth transistor T4 and the fifth transistor T5, thereby reducing the power consumption of the display device in which the pixel driving circuit is located.

[0299] Figure 31 25, 26, 28 and 30 provide schematic structural diagrams of display devices where pixel driving circuits are located. Figure 31As shown, the display device may further include: a third control unit, the third control unit being electrically connected to the first light emitting signal line EM1 and configured to provide a signal to the first light emitting signal line EM1; the second control unit including: a first sub-control unit and a second sub-control unit, the first sub-control unit being electrically connected to the first reset signal line Reset1 and configured to provide a signal to the first reset signal line Reset1; and the second sub-control unit being electrically connected to the third reset signal line Reset3 and configured to provide a signal to the third reset signal line Reset3, wherein, in at least one display frame, at least one of a start time of the first sub-control unit providing the invalid level signal to the first reset signal line Reset1 and a start time of the second sub-control unit providing the invalid level signal to the third reset signal line Reset3 is later than a start time of at least one time period in which the first control unit provides the valid level signal to the second light emitting signal line EM2, and is earlier than a start time of at least one time period in which the third control unit provides the valid level signal to the first light emitting signal line EM1, and a start time of the first sub-control unit providing the invalid level signal to the first reset signal line Reset1 is earlier than a start time of the second sub-control unit providing the invalid level signal to the third reset signal line Reset3.

[0300] Figure 32 for Figure 19 Schematic diagram of the structure of the pixel driving circuit provided Figure 5 .like Figure 32 As shown, the at least one reset signal line includes: a first reset signal line Reset1, a third reset signal line Reset3, and a fourth reset signal line Reset4. The third control sub-circuit is electrically connected to the third node N3, the fourth node N4, the first reset signal line Reset1, the third reset signal line Reset3, the fourth reset signal line Reset4, the dynamic signal line Var, and the auxiliary signal line VX, respectively.

[0301] Figure 33A for Figure 32 The equivalent circuit of the pixel driving circuit provided Figure 1 , Figure 33B for Figure 32 The equivalent circuit of the pixel driving circuit provided Figure 2 .like Figure 33A and Figure 33BAs shown, the driving subcircuit includes: a third transistor T3, the first control subcircuit includes: a first transistor T1 and a second transistor T2, the second control subcircuit includes: a fourth transistor T4 and a fifth transistor T5, the storage subcircuit includes: a first capacitor C1, and the third control subcircuit includes: a second capacitor C2, a third capacitor C3, a sixth transistor T6, an eighth transistor T8 and a ninth transistor T9. Among them, the control electrode of the first transistor T1 is electrically connected to the first scan signal line G1, the first electrode of the first transistor T1 is electrically connected to the data signal line Data, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the second scan signal line G2, the first electrode of the second transistor T2 is electrically connected to the reference signal line REF, and the second electrode of the second transistor T2 is electrically connected to the first node N1; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first light-emitting signal line EM1, the first electrode of the fourth transistor T4 is electrically connected to the first power supply line VDD, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the second light-emitting signal line EM2, the first electrode of the fifth transistor T5 is electrically connected to the third node N3, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4 a control electrode of the sixth transistor T6 electrically connected to the first reset signal line Reset1, a first electrode of the sixth transistor T6 electrically connected to the fifth node N5, and a second electrode of the sixth transistor T6 electrically connected to the fourth node N4; a control electrode of the eighth transistor T8 electrically connected to the third reset signal line Reset3, a first electrode of the eighth transistor T8 electrically connected to the dynamic signal line Var, and a second electrode of the eighth transistor T8 electrically connected to the fourth node N4; a control electrode of the ninth transistor T9 electrically connected to the fourth reset signal line Reset4, a first electrode of the ninth transistor T9 electrically connected to the auxiliary signal line VX, and a second electrode of the ninth transistor T9 electrically connected to the fifth node N5; a first end of the first capacitor C1 electrically connected to the first power supply line VDD, and a second end of the first capacitor C1 electrically connected to the first node N1; a first end of the second capacitor C2 electrically connected to the third node N3, and a second end of the second capacitor C2 electrically connected to the fifth node N5; a first end of the third capacitor C3 electrically connected to the fifth node N5, and a second end of the third capacitor C3 electrically connected to the fourth node N4.

[0302] In an exemplary embodiment, Figure 33A and Figure 33BAny of the first transistor T1 to the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 in the pixel driving circuit can be an N-type transistor or a P-type transistor. The first transistor T1 to the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 can all be N-type transistors, or the first transistor T1 to the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 can all be P-type transistors. Using transistors of the same type in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 can include P-type transistors and N-type transistors.

[0303] Figure 33A The following description is made by taking as an example any transistor among the first transistor T1 to the fifth transistor T5, the sixth transistor T6, the eighth transistor T8 and the ninth transistor T9 as an N-type transistor. Figure 33B The description is made by taking the example that the first transistor T1 , the second transistor T2 , the third transistor T3 , the sixth transistor T6 , the eighth transistor T8 and the ninth transistor T9 are N-type transistors, and the fourth transistor T4 and the fifth transistor T5 are P-type transistors.

[0304] In an exemplary embodiment, according to actual needs, one of the fourth transistor T4 and the fifth transistor T5 may be a P-type transistor. For example, the fourth transistor T4 is a P-type transistor, or the fifth transistor T5 is a P-type transistor.

[0305] In an exemplary embodiment, the P-type transistor may be a low temperature polysilicon (LTPS) thin film transistor, and the N-type transistor may be an oxide thin film transistor. Figure 33B The pixel driving circuit provided is Figure 33A Compared with the pixel driving circuit provided, the fourth transistor T4 and the fifth transistor T5 are of different transistor types. Figure 33B In the provided pixel driving circuit, the fourth transistor T4 and the fifth transistor T5 are P-type transistors, which can reduce the width-to-length ratio of the channel region of at least one of the fourth transistor T4 and the fifth transistor T5, improve the mobility of at least one of the fourth transistor T4 and the fifth transistor T5, and thereby reduce the switching power consumption of at least one of the fourth transistor T4 and the fifth transistor T5, thereby reducing the power consumption of the display device in which the pixel driving circuit is located.

[0306] Figure 34 FIG33 is a schematic diagram of the structure of the display device where the pixel driving circuit is provided. Figure 34 As shown, the display device may further include: a third control unit, the third control unit is electrically connected to the first light-emitting signal line EM1, and is configured to provide a signal to the first light-emitting signal line EM1, the second control unit includes: a first sub-control unit, a second sub-control unit and a third sub-control unit, the first sub-control unit is electrically connected to the first reset signal line Reset1, and is configured to provide a signal to the first reset signal line Reset1, the second sub-control unit is electrically connected to the third reset signal line Reset3, and is configured to provide a signal to the third reset signal line Reset3, the third sub-control unit is electrically connected to the fourth reset signal line Reset4, and is configured to provide a signal to the fourth reset signal line Reset4; in at least one display frame, the first sub-control unit provides an invalid level to the first reset signal line Reset1 At least one of the start time of the signal, the start time of the second sub-control unit providing the invalid level signal to the third reset signal line Reset3 and the start time of the third sub-control unit providing the invalid level signal to the fourth reset signal line Reset4 is later than the start time of at least one time period in which the first control unit provides the valid level signal to the second light-emitting signal line EM2, and earlier than the start time of at least one time period in which the third control unit provides the valid level signal to the first light-emitting signal line EM1, and the start time of the first sub-control unit providing the invalid level signal to the first reset signal line Reset1 is earlier than at least one of the start time of the second sub-control unit providing the invalid level signal to the third reset signal line Reset3 and the start time of the third sub-control unit providing the invalid level signal to the fourth reset signal line Reset4.

[0307] In an exemplary embodiment, Figure 23 、 Figure 31 and Figure 34 As shown, the display device may further include: a fourth control unit and a fifth control unit, the fourth control unit being electrically connected to the first scan signal line G1 and configured to provide a signal to the first scan signal line G1, and the fifth control unit being electrically connected to the second scan signal line G2 and configured to provide a signal to the second scan signal line G2. In at least one display frame, the end time of the fifth control unit providing the active-level signal to the second scan signal line G2 is earlier than the start time of the fourth control unit providing the active-level signal to the first scan signal line G1, and the start time of the fourth control unit providing the active-level signal to the first scan signal line G1 is earlier than the start time of at least one time period in which the first control unit provides the active-level signal to the second light-emitting signal line EM2.

[0308] In an exemplary embodiment, the signal of the auxiliary signal line VX is a direct current signal, and may be a constant voltage signal.

[0309] In an exemplary embodiment, the signal of the auxiliary signal line VX may be a signal of at least one of the first power line VDD, the reference signal line REF, and the initial signal line INIT.

[0310] In an exemplary embodiment, the signal of the initial signal line is a direct current signal, and may be a constant voltage signal.

[0311] In an exemplary embodiment, a change in the voltage value of the dynamic signal provided by the dynamic signal line Var affects the voltage of the third node N3, thereby affecting the voltage difference between the control electrode (that is, the first node N1) and the second electrode (that is, the third node N3) of the third transistor T3 (that is, the driving transistor), and ultimately affecting the magnitude of the light-emitting current. When the temperature of the display device rises, the voltage value of the dynamic signal provided by the dynamic signal line Var is adjusted to reduce the light-emitting current, and ultimately reduce the temperature of the display device, thereby ensuring the brightness uniformity of the display device.

[0312] Figure 35A for Figure 22A The working timing of the pixel driving circuit provided Figure 1 , combined with Figure 22A and Figure 35A The pixel driving circuit provided by the present disclosure is further described.

[0313] In the first phase P11, referred to as the reset phase, the signals on the second scan signal line G2, the second light-emitting signal line EM2, and the third reset signal line Reset3 are high-level signals, while the signals on the first scan signal line G1 and the first light-emitting signal line EM1 are low-level signals. The signal on the second scan signal line G2 is high-level, turning on the second transistor T2. The signal on the reference signal line REF is written to the first node N1, initializing (resetting) the signal on the first node N1 and clearing the existing charge in the first node N1. The signals on the second light-emitting signal line EM2 and the third reset signal line Reset3 are high-level signals, the fifth transistor T5 and the eighth transistor T8 are turned on, and the signal on the dynamic signal line Var is written to the third node N3 and the fourth node N4, respectively. Because the voltage values ​​of the signals on the first node N1 and the third node N3 are greater than the threshold voltage of the third transistor T3, the third transistor T3 is turned on, and the signal on the dynamic signal line Var is written to the second node N2, initializing (resetting) the signals on the second node N2, the third node N3, and the fourth node N4, clearing the existing charge in the second node N2, the third node N3, and the fourth node N4. The signals on the first scanning signal line G1 and the first light-emitting signal line EM1 are low-level signals, and the first transistor T1 and the fourth transistor T4 are turned off. At this stage, the light-emitting device L does not emit light.

[0314] In the second phase P12, i.e., the threshold compensation phase, the signals on the third reset signal line Reset3, the second scan signal line G2, and the first light-emitting signal line EM1 are high-level signals, while the signals on the first scan signal line G1 and the second light-emitting signal line EM2 are low-level signals. The signal on the third reset signal line Reset3 is high-level, the eighth transistor T8 is turned on, and the signal on the dynamic signal line Var is continuously written to the fourth node N4, continuously initializing (resetting) the signal on the fourth node N4. The signal on the second scan signal line G2 is high, the second transistor T2 is turned on, the signal on the reference signal line REF is continuously supplied to the first node N1, the signal on the first emission signal line EM1 is high, the fourth transistor T4 is turned on, and the signal on the first power line VDD is written to the third node N3 via the turned-on fourth transistor T4, the second node N2, and the turned-on third transistor T3, until the voltage V3 of the signal on the third node N3 reaches Vref - Vth, where Vref is the voltage of the signal on the reference signal line REF and Vth is the threshold voltage of the third transistor T3. At this point, the first capacitor C1 stores the voltage difference Vth between the signals on the first node N1 and the third node N3. The signals on the first scan signal line G1 and the second emission signal line EM2 are low, and the first transistor T1 and the fifth transistor T5 are turned off. During this stage, the light-emitting device L does not emit light.

[0315] In the third phase P13, the data writing phase, the signal on the third reset signal line Reset is high, the signals on the second scan signal line G2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are low, the first scan signal line G1 is high for a portion of the time, and the data signal line Data outputs a data voltage. The signal on the third reset signal line Reset3 is high, the eighth transistor T8 is turned on, and the signal on the dynamic signal line Var is continuously written to the fourth node N4, continuously initializing (resetting) the signal on the fourth node N4. The signal on the first scan signal line G1 is high, turning on the first transistor T1. The data voltage on the data signal line Data is written to the first node N1. At this point, the voltage V1 of the first node N1 equals Vdata, where Vdata is the data voltage on the data signal line. The signal on the first node N1 changes from its current voltage value to its previous voltage value. Therefore, under the action of the first capacitor C1 and the second capacitor C2, the signal on the third node N3 also changes. At this point, the voltage V3 of the signal on the third node N3 equals Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2), where C1 is the capacitance of the first capacitor and C2 is the capacitance of the second capacitor. The signals on the second scan signal line G2, the first emission signal line EM1, and the second emission signal line EM2 are low, turning off the second transistor T2, the fourth transistor T4, and the fifth transistor T5. In this stage, the light-emitting device L does not emit light.

[0316] In the fourth phase P14, i.e., the light-emitting phase, the signals on the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are high-level signals, while the signals on the third reset signal line Reset3 and the first scan signal line G1 and the second scan signal line G2 are low-level signals. The signals on the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are high-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fourth transistor T4, third transistor T3, and fifth transistor T5, driving the light-emitting device L to emit light. The signals on the third reset signal line Reset3 and the first scan signal line G1 and the second scan signal line G2 are low-level signals, and the first transistor T1, the second transistor T2, and the eighth transistor T8 are turned off. In this phase, the light-emitting device L emits light.

[0317] During the pixel driving circuit's driving process, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its control electrode (also the first node N1) and the second electrode (also the third node N3). Since the voltage value of the signal at the first node V1 = Vdata - [Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2)] + Vinit, and the voltage value of the signal at the third node N3 V3 = Vinit, the driving current of the third transistor T3 is:

[0318] I=K*(Vgs-Vth) 2

[0319] =K*[Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]-Vth] 2

[0320] =K*[(C2 / (C1+C2))*(Vdata-Vref)] 2 .

[0321] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the control electrode and the second electrode of the third transistor T3.

[0322] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0323] Figure 35B for Figure 22A The working timing of the pixel driving circuit provided Figure 2 , combined with Figure 22A and Figure 35B The pixel driving circuit provided by the present disclosure is further described.

[0324] In the first phase P21, referred to as the reset phase, the signals on the second scan signal line G2, the second light-emitting signal line EM2, and the third reset signal line Reset3 are high-level signals, while the signals on the first scan signal line G1 and the first light-emitting signal line EM1 are low-level signals. The signal on the second scan signal line G2 is high-level, turning on the second transistor T2. The signal on the reference signal line REF is written to the first node N1, initializing (resetting) the signal on the first node N1 and clearing the existing charge in the first node N1. The signals on the second light-emitting signal line EM2 and the third reset signal line Reset3 are high-level signals, the fifth transistor T5 and the eighth transistor T8 are turned on, and the signal on the dynamic signal line Var is written to the third node N3 and the fourth node N4, respectively. Because the voltage values ​​of the signals on the first node N1 and the third node N3 are greater than the threshold voltage of the third transistor T3, the third transistor T3 is turned on, and the signal on the dynamic signal line Var is written to the second node N2, initializing (resetting) the signals on the second node N2, the third node N3, and the fourth node N4, clearing the existing charge in the second node N2, the third node N3, and the fourth node N4. The signals on the first scanning signal line G1 and the first light-emitting signal line EM1 are low-level signals, and the first transistor T1 and the fourth transistor T4 are turned off. At this stage, the light-emitting device L does not emit light.

[0325] In the second phase P22, i.e., the threshold compensation phase, the signals on the third reset signal line Reset3, the second scan signal line G2, and the first light-emitting signal line EM1 are high-level signals, while the signals on the first scan signal line G1 and the second light-emitting signal line EM2 are low-level signals. The signal on the third reset signal line Reset3 is high-level, the eighth transistor T8 is turned on, and the signal on the dynamic signal line Var is continuously written to the fourth node N4, continuously initializing (resetting) the signal on the fourth node N4. The signal on the second scan signal line G2 is high, the second transistor T2 is turned on, the signal on the reference signal line REF is continuously supplied to the first node N1, the signal on the first emission signal line EM1 is high, the fourth transistor T4 is turned on, and the signal on the first power line VDD is written to the third node N3 via the turned-on fourth transistor T4, the second node N2, and the turned-on third transistor T3, until the voltage V3 of the signal on the third node N3 reaches Vref - Vth, where Vref is the voltage of the signal on the reference signal line REF and Vth is the threshold voltage of the third transistor T3. At this point, the first capacitor C1 stores the voltage difference Vth between the signals on the first node N1 and the third node N3. The signals on the first scan signal line G1 and the second emission signal line EM2 are low, and the first transistor T1 and the fifth transistor T5 are turned off. During this stage, the light-emitting device L does not emit light.

[0326] In the third phase P23, the data writing phase, the signal on the third reset signal line Reset is high, the signals on the second scan signal line G2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are low, the first scan signal line G1 is high for a portion of the time, and the data signal line Data outputs a data voltage. The signal on the third reset signal line Reset3 is high, the eighth transistor T8 is turned on, and the signal on the dynamic signal line Var is continuously written to the fourth node N4, continuously initializing (resetting) the signal on the fourth node N4. The signal on the first scan signal line G1 is high, turning on the first transistor T1. The data voltage on the data signal line Data is written to the first node N1. At this point, the voltage V1 of the first node N1 equals Vdata, where Vdata is the data voltage on the data signal line. The signal on the first node N1 changes from its current voltage value to its previous voltage value. Therefore, under the action of the first capacitor C1 and the second capacitor C2, the signal on the third node N3 also changes. At this point, the voltage V3 of the signal on the third node N3 equals Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2), where C1 is the capacitance of the first capacitor and C2 is the capacitance of the second capacitor. The signals on the second scan signal line G2, the first emission signal line EM1, and the second emission signal line EM2 are low, turning off the second transistor T2, the fourth transistor T4, and the fifth transistor T5. In this stage, the light-emitting device L does not emit light.

[0327] In the fourth phase P24, the second reset phase, the signal on the second light-emitting signal line EM2 is high, while the signals on the first scan signal line G1, the second scan signal line G2, and the first light-emitting signal line EM1 are low. The signal on the third reset signal line Reset3 is high for some periods of time and low for some periods of time. The high period of the third reset signal line Reset3 occurs before the low period of the third reset signal line Reset3. The signal on the second light-emitting signal line EM2 is high, the fifth transistor T5 turns on, and then the eighth transistor T8 turns off. Although the signal on the third node N3 changes to the signal on the dynamic signal line Var, the voltage difference between the signals on the first node N1 and the third node N3 remains unchanged. The signals on the first scan signal line G1, the second scan signal line G2, and the first light-emitting signal line EM1 are low, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are off. During this phase, the light-emitting device L does not emit light.

[0328] In the fifth phase P25, i.e., the light-emitting phase, the signals on the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are high-level signals, and the signals on the third reset signal line Reset3 and the first scan signal line G1 and the second scan signal line G2 are low-level signals. The signals on the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are high-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fourth transistor T4, third transistor T3, and fifth transistor T5, driving the light-emitting device L to emit light. The signals on the third reset signal line Reset3 and the first scan signal line G1 and the second scan signal line G2 are low-level signals, and the first transistor T1, the second transistor T2, and the eighth transistor T8 are turned off. In this phase, the light-emitting device L emits light.

[0329] During the pixel driving circuit's driving process, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its control electrode (also the first node N1) and the second electrode (also the third node N3). Since the voltage value of the signal at the first node V1 = Vdata - [Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2)] + Vinit, and the voltage value of the signal at the third node N3 V3 = Vinit, the driving current of the third transistor T3 is:

[0330] I=K*(Vgs-Vth) 2

[0331] =K*[Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]-Vth] 2

[0332] =K*[(C2 / (C1+C2))*(Vdata-Vref)] 2 .

[0333] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the control electrode and the second electrode of the third transistor T3.

[0334] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0335] Figure 36A for Figure 22B The working timing of the pixel driving circuit provided Figure 1 , combined with Figure 22B and Figure 36A The pixel driving circuit provided by the present disclosure is further described.

[0336] In the first phase P11, referred to as the reset phase, the signals on the second scan signal line G2, the first light-emitting signal line EM1, and the third reset signal line Reset3 are high-level signals, while the signals on the first scan signal line G1 and the second light-emitting signal line EM2 are low-level signals. The signal on the second scan signal line G2 is high-level, turning on the second transistor T2. The signal on the reference signal line REF is written to the first node N1, initializing (resetting) the signal on the first node N1 and clearing the existing charge in the first node N1. The signal on the second light-emitting signal line EM2 is low, the signal on the third reset signal line Reset3 is high, the fifth transistor T5 and the eighth transistor T8 are turned on, and the signal on the dynamic signal line Var is written to the third node N3 and the fourth node N4, respectively. Because the voltage values ​​of the signals on the first node N1 and the third node N3 are greater than the threshold voltage of the third transistor T3, the third transistor T3 is turned on, and the signal on the dynamic signal line Var is written to the second node N2, initializing (resetting) the signals on the second node N2, the third node N3, and the fourth node N4, clearing the existing charge on the second node N2, the third node N3, and the fourth node N4. The signal on the first scanning signal line G1 is low, the signal on the first light-emitting signal line EM1 is high, and the first transistor T1 and the fourth transistor T4 are turned off. At this stage, the light-emitting device L does not emit light.

[0337] In the second phase P12, i.e., the threshold compensation phase, the signals on the third reset signal line Reset3, the second scan signal line G2, and the second light-emitting signal line EM2 are high-level signals, while the signals on the first scan signal line G1 and the first light-emitting signal line EM1 are low-level signals. The signal on the third reset signal line Reset3 is high-level, the eighth transistor T8 is turned on, and the signal on the dynamic signal line Var is continuously written to the fourth node N4, continuously initializing (resetting) the signal on the fourth node N4. The signal on the second scan signal line G2 is high, the second transistor T2 is turned on, the signal on the reference signal line REF is continuously supplied to the first node N1, the signal on the first light-emitting signal line EM1 is low, and the fourth transistor T4 is turned on. The signal on the first power line VDD is written to the third node N3 via the turned-on fourth transistor T4, the second node N2, and the turned-on third transistor T3, until the voltage V3 of the signal on the third node N3 reaches Vref - Vth, where Vref is the voltage of the signal on the reference signal line REF and Vth is the threshold voltage of the third transistor T3. At this point, the first capacitor C1 stores the voltage difference Vth between the signals on the first node N1 and the third node N3. The signal on the first scan signal line G1 is low, the signal on the second light-emitting signal line EM2 is high, and the first transistor T1 and the fifth transistor T5 are turned off. During this stage, the light-emitting device L does not emit light.

[0338] In the third phase P13, the data writing phase, the signals on the first emitting signal line EM1, the second emitting signal line EM2, and the third reset signal line Reset are high-level signals, the signal on the second scanning signal line G2 is low-level, the first scanning signal line G1 is high-level for a portion of the time period, and the data signal line Data outputs a data voltage. The signal on the third reset signal line Reset3 is high-level, the eighth transistor T8 is turned on, and the signal on the dynamic signal line Var is continuously written to the fourth node N4, continuously initializing (resetting) the signal on the fourth node N4. The signal on the first scan signal line G1 is high, turning on the first transistor T1. The data voltage on the data signal line Data is written to the first node N1. At this point, the voltage V1 of the first node N1 equals Vdata, where Vdata is the data voltage of the data signal line. The signal on the first node N1 changes from its current voltage value to its previous voltage value. Therefore, under the action of the first capacitor C1 and the second capacitor C2, the signal on the third node N3 also changes. At this point, the voltage V3 of the signal on the third node N3 equals Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2), where C1 is the capacitance of the first capacitor and C2 is the capacitance of the second capacitor. The signal on the second scan signal line G2 is low, and the signals on the first and second emission signal lines EM1 and EM2 are high. The second transistor T2, the fourth transistor T4, and the fifth transistor T5 are off. In this stage, the light-emitting device L does not emit light.

[0339] In the fourth phase P14, i.e., the light-emitting phase, the signals on the first light-emitting signal line EM1, the second light-emitting signal line EM2, the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals. The signals on the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are low-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fourth transistor T4, third transistor T3, and fifth transistor T5, driving the light-emitting device L to emit light. The signals on the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals, and the first transistor T1, the second transistor T2, and the eighth transistor T8 are turned off. In this phase, the light-emitting device L emits light.

[0340] During the pixel driving circuit's driving process, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its control electrode (also the first node N1) and the second electrode (also the third node N3). Since the voltage value of the signal at the first node V1 = Vdata - [Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2)] + Vinit, and the voltage value of the signal at the third node N3 V3 = Vinit, the driving current of the third transistor T3 is:

[0341] I=K*(Vgs-Vth) 2

[0342] =K*[Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]-Vth] 2

[0343] =K*[(C2 / (C1+C2))*(Vdata-Vref)] 2 .

[0344] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the control electrode and the second electrode of the third transistor T3.

[0345] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0346] Figure 36B for Figure 22B The working timing of the pixel driving circuit provided Figure 2 , combined with Figure 22B and Figure 36B The pixel driving circuit provided by the present disclosure is further described.

[0347] In the first phase P21, referred to as the reset phase, the signals on the second scan signal line G2, the first light-emitting signal line EM1, and the third reset signal line Reset3 are high-level signals, while the signals on the first scan signal line G1 and the second light-emitting signal line EM2 are low-level signals. The signal on the second scan signal line G2 is high-level, turning on the second transistor T2. The signal on the reference signal line REF is written to the first node N1, initializing (resetting) the signal on the first node N1 and clearing the existing charge in the first node N1. The signal on the second light-emitting signal line EM2 is low, the signal on the third reset signal line Reset3 is high, the fifth transistor T5 and the eighth transistor T8 are turned on, and the signal on the dynamic signal line Var is written to the third node N3 and the fourth node N4, respectively. Because the voltage values ​​of the signals on the first node N1 and the third node N3 are greater than the threshold voltage of the third transistor T3, the third transistor T3 is turned on, and the signal on the dynamic signal line Var is written to the second node N2, initializing (resetting) the signals on the second node N2, the third node N3, and the fourth node N4, clearing the existing charge on the second node N2, the third node N3, and the fourth node N4. The signal on the first scanning signal line G1 is low, the signal on the first light-emitting signal line EM1 is high, and the first transistor T1 and the fourth transistor T4 are turned off. At this stage, the light-emitting device L does not emit light.

[0348] In the second phase P22, i.e., the threshold compensation phase, the signals on the third reset signal line Reset3, the second scan signal line G2, and the second light-emitting signal line EM2 are high-level signals, while the signals on the first scan signal line G1 and the first light-emitting signal line EM1 are low-level signals. The signal on the third reset signal line Reset3 is high-level, the eighth transistor T8 is turned on, and the signal on the dynamic signal line Var is continuously written to the fourth node N4, continuously initializing (resetting) the signal on the fourth node N4. The signal on the second scan signal line G2 is high, the second transistor T2 is turned on, the signal on the reference signal line REF is continuously supplied to the first node N1, the signal on the first light-emitting signal line EM1 is low, and the fourth transistor T4 is turned on. The signal on the first power line VDD is written to the third node N3 via the turned-on fourth transistor T4, the second node N2, and the turned-on third transistor T3, until the voltage V3 of the signal on the third node N3 reaches Vref - Vth, where Vref is the voltage of the signal on the reference signal line REF and Vth is the threshold voltage of the third transistor T3. At this point, the first capacitor C1 stores the voltage difference Vth between the signals on the first node N1 and the third node N3. The signal on the first scan signal line G1 is low, the signal on the second light-emitting signal line EM2 is high, and the first transistor T1 and the fifth transistor T5 are turned off. During this stage, the light-emitting device L does not emit light.

[0349] In the third phase P23, the data writing phase, the signals on the third reset signal line Reset, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals, the signal on the second scan signal line G2 is low-level, the first scan signal line G1 is high-level during a portion of the time period, and the data signal line Data outputs a data voltage. The signal on the third reset signal line Reset3 is high-level, the eighth transistor T8 is turned on, and the signal on the dynamic signal line Var is continuously written to the fourth node N4, continuously initializing (resetting) the signal on the fourth node N4. The signal on the first scan signal line G1 is high, turning on the first transistor T1. The data voltage on the data signal line Data is written to the first node N1. At this point, the voltage V1 of the first node N1 equals Vdata, where Vdata is the data voltage of the data signal line. The signal on the first node N1 changes from its current voltage value to its previous voltage value. Therefore, under the action of the first capacitor C1 and the second capacitor C2, the signal on the third node N3 also changes. At this point, the voltage V3 of the signal on the third node N3 equals Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2), where C1 is the capacitance of the first capacitor and C2 is the capacitance of the second capacitor. The signal on the second scan signal line G2 is low, and the signals on the first and second emission signal lines EM1 and EM2 are high. The second transistor T2, the fourth transistor T4, and the fifth transistor T5 are off. In this stage, the light-emitting device L does not emit light.

[0350] In the fourth phase P24, the second reset phase, the signal on the first light-emitting signal line EM1 is high, while the signals on the first scan signal line G1, the second scan signal line G2, and the second light-emitting signal line EM2 are low. The signal on the third reset signal line Reset3 is high for some periods of time and low for some periods of time. The high period of the third reset signal line Reset3 occurs before the low period of the third reset signal line Reset3. The signal on the second light-emitting signal line EM2 is low, the fifth transistor T5 is turned on, and then the eighth transistor T8 is turned off. Although the signal on the third node N3 changes to the signal on the dynamic signal line Var, the voltage difference between the signals on the first node N1 and the third node N3 remains unchanged. The signals on the first scan signal line G1 and the second scan signal line G2 are low, the signal on the first light-emitting signal line EM1 is high, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off. During this phase, the light-emitting device L does not emit light.

[0351] In the fifth phase P25, i.e., the light-emitting phase, the signals on the first light-emitting signal line EM1, the second light-emitting signal line EM2, the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals. The signals on the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are low-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fourth transistor T4, the third transistor T3, and the fifth transistor T5, driving the light-emitting device L to emit light. The signals on the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals, and the first transistor T1, the second transistor T2, and the eighth transistor T8 are turned off. In this phase, the light-emitting device L emits light.

[0352] During the pixel driving circuit's driving process, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its control electrode (also the first node N1) and the second electrode (also the third node N3). Since the voltage value of the signal at the first node V1 = Vdata - [Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2)] + Vinit, and the voltage value of the signal at the third node N3 V3 = Vinit, the driving current of the third transistor T3 is:

[0353] I=K*(Vgs-Vth) 2

[0354] =K*[Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]-Vth] 2

[0355] =K*[(C2 / (C1+C2))*(Vdata-Vref)] 2 .

[0356] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the control electrode and the second electrode of the third transistor T3.

[0357] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0358] Figure 37A for Figure 25A 、 Figure 26A 、 Figure 28A and Figure 30A The working timing of the pixel driving circuit provided Figure 1 , combined with Figure 25A and Figure 37A The pixel driving circuit provided by the present disclosure is further described.

[0359] In the first phase P31, referred to as the reset phase, the signals on the second scan signal line G2, the second light-emitting signal line EM2, the first reset signal line Reset1, and the third reset signal line Reset3 are high-level signals, while the signals on the first scan signal line G1 and the first light-emitting signal line EM1 are low-level signals. The signal on the second scan signal line G2 is high-level, turning on the second transistor T2. The signal on the reference signal line REF is written to the first node N1, initializing (resetting) the signal on the first node N1 and clearing the existing charge in the first node N1. The signals on the second light-emitting signal line EM2, the first reset signal line Reset1, and the third reset signal line Reset3 are high-level signals. The fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are turned on. The signal on the dynamic signal line Var is written to the third node N3, the fourth node N4, and the fifth node N5, respectively. Because the voltage values ​​of the signals on the first node N1 and the third node N3 are greater than the threshold voltage of the third transistor T3, the third transistor T3 is turned on. The signal on the dynamic signal line Var is written to the second node N2, initializing (resetting) the signals on the second node N2, the third node N3, the fourth node N4, and the fifth node N5, clearing the existing charges on the second node N2, the third node N3, the fourth node N4, and the fifth node N5. The signals on the first scanning signal line G1 and the first light-emitting signal line EM1 are low-level signals. The first transistor T1 and the fourth transistor T4 are turned off. At this stage, the light-emitting device L does not emit light.

[0360] In the second phase P32, i.e., the threshold compensation phase, the signals on the first reset signal line Reset1, the third reset signal line Reset3, the second scan signal line G2, and the first light-emitting signal line EM1 are high-level signals, while the signals on the first scan signal line G1 and the second light-emitting signal line EM2 are low-level signals. The signals on the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, the sixth transistor T6 and the eighth transistor T8 are turned on, and the signal on the dynamic signal line Var is continuously written to the fourth node N4 and the fifth node N5, continuously initializing (resetting) the signals on the fourth node N4 and the fifth node N5. The signal on the second scan signal line G2 is high, the second transistor T2 is turned on, the signal on the reference signal line REF is continuously supplied to the first node N1, the signal on the first emission signal line EM1 is high, the fourth transistor T4 is turned on, and the signal on the first power line VDD is written to the third node N3 via the turned-on fourth transistor T4, the second node N2, and the turned-on third transistor T3, until the voltage V3 of the signal on the third node N3 reaches Vref - Vth, where Vref is the voltage of the signal on the reference signal line REF and Vth is the threshold voltage of the third transistor T3. At this point, the first capacitor C1 stores the voltage difference Vth between the signals on the first node N1 and the third node N3. The signals on the first scan signal line G1 and the second emission signal line EM2 are low, and the first transistor T1 and the fifth transistor T5 are turned off. During this stage, the light-emitting device L does not emit light.

[0361] In the third phase P33, the data writing phase, the signals on the first reset signal line Reset1 and the third reset signal line Reset are high-level signals, the signals on the second scan signal line G2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are low-level signals, the first scan signal line G1 is high-level during a portion of the time period, and the data signal line Data outputs a data voltage. The signals on the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, the sixth transistor T6 and the eighth transistor T8 are turned on, and the signal on the dynamic signal line Var is continuously written to the fourth node N4 and the fifth node N5, continuously initializing (resetting) the signals on the fourth node N4 and the fifth node N5. The signal on the first scan signal line G1 is high, turning on the first transistor T1. The data voltage on the data signal line Data is written to the first node N1. At this point, the voltage V1 of the first node N1 equals Vdata, where Vdata is the data voltage on the data signal line. The signal on the first node N1 changes from its current voltage value to its previous voltage value. Therefore, under the action of the first capacitor C1 and the second capacitor C2, the signal on the third node N3 also changes. At this point, the voltage V3 of the signal on the third node N3 equals Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2), where C1 is the capacitance of the first capacitor and C2 is the capacitance of the second capacitor. The signals on the second scan signal line G2, the first emission signal line EM1, and the second emission signal line EM2 are low, turning off the second transistor T2, the fourth transistor T4, and the fifth transistor T5. In this stage, the light-emitting device L does not emit light.

[0362] In the fourth phase P34, i.e., the light-emitting phase, the signals on the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are high-level signals, while the signals on the first reset signal line Reset1, the third reset signal line Reset3, and the first scan signal line G1 and the second scan signal line G2 are low-level signals. The signals on the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are high-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fourth transistor T4, the third transistor T3, and the fifth transistor T5, driving the light-emitting device L to emit light. The signals on the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals, and the first transistor T1, the second transistor T2, the sixth transistor T6, and the eighth transistor T8 are turned off. In this phase, the light-emitting device L emits light.

[0363] During the pixel driving circuit's driving process, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its control electrode (also the first node N1) and the second electrode (also the third node N3). Since the voltage value of the signal at the first node V1 = Vdata - [Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2)] + Vinit, and the voltage value of the signal at the third node N3 V3 = Vinit, the driving current of the third transistor T3 is:

[0364] I=K*(Vgs-Vth) 2

[0365] =K*[Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]-Vth] 2

[0366] =K*[(C2 / (C1+C2))*(Vdata-Vref)] 2 .

[0367] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the control electrode and the second electrode of the third transistor T3.

[0368] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0369] Figure 37B for Figure 25A 、 Figure 26A 、 Figure 28A and Figure 30A The working timing of the pixel driving circuit provided Figure 2 , combined with Figure 25A and Figure 37B The pixel driving circuit provided by the present disclosure is further described.

[0370] The first phase P41 is called the reset phase. The signals on the first reset signal line Reset1, the second scan signal line G2, the second light-emitting signal line EM2, and the third reset signal line Reset3 are high-level signals, while the signals on the first scan signal line G1 and the first light-emitting signal line EM1 are low-level signals. The signal on the second scan signal line G2 is high-level, the second transistor T2 is turned on, and the signal on the reference signal line REF is written to the first node N1, initializing (resetting) the signal on the first node N1 and clearing the existing charge in the first node N1. The signals on the first reset signal line Reset1, the second emission signal line EM2, and the third reset signal line Reset3 are high-level signals. The fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are turned on, and the signal on the dynamic signal line Var is written to the third node N3, the fourth node N4, and the fifth node N5, respectively. Because the voltage values ​​of the signals on the first node N1 and the third node N3 are greater than the threshold voltage of the third transistor T3, the third transistor T3 is turned on, and the signal on the dynamic signal line Var is written to the second node N2, initializing (resetting) the signals on the second node N2, the third node N3, the fourth node N4, and the fifth node N5, clearing the existing charges on the second node N2, the third node N3, the fourth node N4, and the fifth node N5. The signals on the first scan signal line G1 and the first emission signal line EM1 are low-level signals, and the first transistor T1 and the fourth transistor T4 are turned off. At this stage, the light-emitting device L does not emit light.

[0371] In the second phase P42, i.e., the threshold compensation phase, the signals on the first reset signal line Reset1, the third reset signal line Reset3, the second scan signal line G2, and the first light-emitting signal line EM1 are high-level signals, while the signals on the first scan signal line G1 and the second light-emitting signal line EM2 are low-level signals. The signals on the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, the sixth transistor T6 and the eighth transistor T8 are turned on, and the signal on the dynamic signal line Var is continuously written to the fourth node N4 and the fifth node N5, continuously initializing (resetting) the signals on the fourth node N4 and the fifth node N5. The signal on the second scan signal line G2 is high, the second transistor T2 is turned on, the signal on the reference signal line REF is continuously supplied to the first node N1, the signal on the first emission signal line EM1 is high, the fourth transistor T4 is turned on, and the signal on the first power line VDD is written to the third node N3 via the turned-on fourth transistor T4, the second node N2, and the turned-on third transistor T3, until the voltage V3 of the signal on the third node N3 reaches Vref - Vth, where Vref is the voltage of the signal on the reference signal line REF and Vth is the threshold voltage of the third transistor T3. At this point, the first capacitor C1 stores the voltage difference Vth between the signals on the first node N1 and the third node N3. The signals on the first scan signal line G1 and the second emission signal line EM2 are low, and the first transistor T1 and the fifth transistor T5 are turned off. During this stage, the light-emitting device L does not emit light.

[0372] In the third phase P43, the data writing phase, the signals on the first reset signal line Reset1 and the third reset signal line Reset are high-level signals, the signals on the second scan signal line G2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are low-level signals, the first scan signal line G1 is high-level during a portion of the time period, and the data signal line Data outputs a data voltage. The signals on the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, the eighth transistor T8 is turned on, and the signal on the dynamic signal line Var is continuously written to the fourth node N4 and the fifth node N5, continuously initializing (resetting) the signals on the fourth node N4 and the fifth node N5. The signal on the first scan signal line G1 is high, turning on the first transistor T1. The data voltage on the data signal line Data is written to the first node N1. At this point, the voltage V1 of the first node N1 equals Vdata, where Vdata is the data voltage on the data signal line. The signal on the first node N1 changes from its current voltage value to its previous voltage value. Therefore, under the action of the first capacitor C1 and the second capacitor C2, the signal on the third node N3 also changes. At this point, the voltage V3 of the signal on the third node N3 equals Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2), where C1 is the capacitance of the first capacitor and C2 is the capacitance of the second capacitor. The signals on the second scan signal line G2, the first emission signal line EM1, and the second emission signal line EM2 are low, turning off the second transistor T2, the fourth transistor T4, and the fifth transistor T5. In this stage, the light-emitting device L does not emit light.

[0373] In the fourth phase P44, the second reset phase, the signal on the second emission signal line EM2 is high, while the signals on the first scan signal line G1, the second scan signal line G2, and the first emission signal line EM1 are low. The signals on the third reset signal line Reset3 and the first reset signal line Reset1 are high for some periods of time and low for some periods of time. The period during which either the third reset signal line Reset3 or the first reset signal line Reset1 is high precedes the period during which it is low. The signal on the second emission signal line EM2 is high, the fifth transistor T5 is turned on, and then the sixth transistor T6 and the eighth transistor T8 are turned off in sequence. Although the signal on the third node N3 becomes the signal on the dynamic signal line Var, the voltage difference between the signals on the first node N1 and the third node N3 remains unchanged. The signals on the first scan signal line G1, the second scan signal line G2, and the first emission signal line EM1 are low, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off. In this phase, the light-emitting device L does not emit light.

[0374] In the fifth phase P45, i.e., the light-emitting phase, the signals on the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are high-level signals, while the signals on the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals. The signals on the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are high-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fourth transistor T4, the third transistor T3, and the fifth transistor T5, driving the light-emitting device L to emit light. The signals on the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals, and the first transistor T1, the second transistor T2, the sixth transistor T6, and the eighth transistor T8 are turned off. In this phase, the light-emitting device L emits light.

[0375] During the pixel driving circuit's driving process, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its control electrode (also the first node N1) and the second electrode (also the third node N3). Since the voltage value of the signal at the first node V1 = Vdata - [Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2)] + Vinit, and the voltage value of the signal at the third node N3 V3 = Vinit, the driving current of the third transistor T3 is:

[0376] I=K*(Vgs-Vth) 2

[0377] =K*[Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]-Vth] 2

[0378] =K*[(C2 / (C1+C2))*(Vdata-Vref)] 2 .

[0379] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the control electrode and the second electrode of the third transistor T3.

[0380] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0381] Figure 25A、 Figure 26A and Figure 28A The transistors included in the circuit are the same, and the only difference is the connection relationship and number of capacitors. The capacitors do not affect the timing, so Figure 26A and Figure 28A The working process of the provided pixel driving circuit is exactly the same as the working process of Figure 25, and the present disclosure does not limit this.

[0382] Combine Figure 30A and Figure 37A The pixel driving circuit provided by the present disclosure is further described.

[0383] In the first phase P31, referred to as the reset phase, the signals on the second scan signal line G2, the second light-emitting signal line EM2, the first reset signal line Reset1, and the third reset signal line Reset3 are high-level signals, while the signals on the first scan signal line G1 and the first light-emitting signal line EM1 are low-level signals. The signal on the second scan signal line G2 is high-level, turning on the second transistor T2. The signal on the reference signal line REF is written to the first node N1, initializing (resetting) the signal on the first node N1 and clearing the existing charge in the first node N1. The signals on the second light-emitting signal line EM2, the first reset signal line Reset1, and the third reset signal line Reset3 are high-level signals. The fifth transistor T5, the sixth transistor T6, and the ninth transistor T9 are turned on. The signal on the auxiliary signal line VX is written to the third node N3, the fourth node N4, and the fifth node N5, respectively. Because the voltage values ​​of the signals on the first node N1 and the third node N3 are greater than the threshold voltage of the third transistor T3, the third transistor T3 is turned on. The signal on the auxiliary signal line VX is written to the second node N2, initializing (resetting) the signals on the second node N2, the third node N3, the fourth node N4, and the fifth node N5, clearing the existing charges on the second node N2, the third node N3, the fourth node N4, and the fifth node N5. The signals on the first scanning signal line G1 and the first light-emitting signal line EM1 are low-level signals. The first transistor T1 and the fourth transistor T4 are turned off. At this stage, the light-emitting device L does not emit light.

[0384] In the second phase P32, i.e., the threshold compensation phase, the signals on the first reset signal line Reset1, the third reset signal line Reset3, the second scan signal line G2, and the first light-emitting signal line EM1 are high-level signals, while the signals on the first scan signal line G1 and the second light-emitting signal line EM2 are low-level signals. The signals on the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, the sixth transistor T6 and the ninth transistor T9 are turned on, and the signal on the auxiliary signal line VX is continuously written to the fourth node N4 and the fifth node N5, continuously initializing (resetting) the signals on the fourth node N4 and the fifth node N5. The signal on the second scan signal line G2 is high, the second transistor T2 is turned on, the signal on the reference signal line REF is continuously supplied to the first node N1, the signal on the first emission signal line EM1 is high, the fourth transistor T4 is turned on, and the signal on the first power line VDD is written to the third node N3 via the turned-on fourth transistor T4, the second node N2, and the turned-on third transistor T3, until the voltage V3 of the signal on the third node N3 reaches Vref - Vth, where Vref is the voltage of the signal on the reference signal line REF and Vth is the threshold voltage of the third transistor T3. At this point, the first capacitor C1 stores the voltage difference Vth between the signals on the first node N1 and the third node N3. The signals on the first scan signal line G1 and the second emission signal line EM2 are low, and the first transistor T1 and the fifth transistor T5 are turned off. During this stage, the light-emitting device L does not emit light.

[0385] In the third phase P33, the data writing phase, the signals on the first reset signal line Reset1 and the third reset signal line Reset are high-level signals, the signals on the second scan signal line G2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are low-level signals, the first scan signal line G1 is high-level during a portion of the time period, and the data signal line Data outputs a data voltage. The signals on the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, the sixth transistor T6 and the ninth transistor T9 are turned on, and the signal on the auxiliary signal line VX is continuously written into the fourth node N4 and the fifth node N5, continuously initializing (resetting) the signals on the fourth node N4 and the fifth node N5. The signal on the first scan signal line G1 is high, turning on the first transistor T1. The data voltage on the data signal line Data is written to the first node N1. At this point, the voltage V1 of the first node N1 equals Vdata, where Vdata is the data voltage on the data signal line. The signal on the first node N1 changes from its current voltage value to its previous voltage value. Therefore, under the action of the first capacitor C1 and the second capacitor C2, the signal on the third node N3 also changes. At this point, the voltage V3 of the signal on the third node N3 equals Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2), where C1 is the capacitance of the first capacitor and C2 is the capacitance of the second capacitor. The signals on the second scan signal line G2, the first emission signal line EM1, and the second emission signal line EM2 are low, turning off the second transistor T2, the fourth transistor T4, and the fifth transistor T5. In this stage, the light-emitting device L does not emit light.

[0386] In the fourth phase P34, i.e., the light-emitting phase, the signals on the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are high-level signals, while the signals on the first reset signal line Reset1, the third reset signal line Reset3, and the first scan signal line G1 and the second scan signal line G2 are low-level signals. The signals on the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are high-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fourth transistor T4, the third transistor T3, and the fifth transistor T5, driving the light-emitting device L to emit light. The signals on the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals, and the first transistor T1, the second transistor T2, the sixth transistor T6, and the ninth transistor T9 are turned off. In this phase, the light-emitting device L emits light.

[0387] During the pixel driving circuit's driving process, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its control electrode (also the first node N1) and the second electrode (also the third node N3). Since the voltage value of the signal at the first node V1 = Vdata - [Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2)] + Vinit, and the voltage value of the signal at the third node N3 V3 = Vinit, the driving current of the third transistor T3 is:

[0388] I=K*(Vgs-Vth) 2

[0389] =K*[Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]-Vth] 2

[0390] =K*[(C2 / (C1+C2))*(Vdata-Vref)] 2 .

[0391] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the control electrode and the second electrode of the third transistor T3.

[0392] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0393] Combine Figure 30A and Figure 37B The pixel driving circuit provided by the present disclosure is further described.

[0394] The first phase P41 is called the reset phase. The signals on the first reset signal line Reset1, the second scan signal line G2, the second light-emitting signal line EM2, and the third reset signal line Reset3 are high-level signals, while the signals on the first scan signal line G1 and the first light-emitting signal line EM1 are low-level signals. The signal on the second scan signal line G2 is high-level, the second transistor T2 is turned on, and the signal on the reference signal line REF is written to the first node N1, initializing (resetting) the signal on the first node N1 and clearing the existing charge in the first node N1. The signals on the first reset signal line Reset1, the second emission signal line EM2, and the third reset signal line Reset3 are high-level signals. The fifth transistor T5, the sixth transistor T6, and the ninth transistor T9 are turned on. The signal on the auxiliary signal line VX is written to the third node N3, the fourth node N4, and the fifth node N5, respectively. Because the voltage values ​​of the signals on the first node N1 and the third node N3 are greater than the threshold voltage of the third transistor T3, the third transistor T3 is turned on. The signal on the auxiliary signal line VX is written to the second node N2, initializing (resetting) the signals on the second node N2, the third node N3, the fourth node N4, and the fifth node N5, clearing the existing charges on the second node N2, the third node N3, the fourth node N4, and the fifth node N5. The signals on the first scan signal line G1 and the first emission signal line EM1 are low-level signals. The first transistor T1 and the fourth transistor T4 are turned off. At this stage, the light-emitting device L does not emit light.

[0395] In the second phase P42, i.e., the threshold compensation phase, the signals on the first reset signal line Reset1, the third reset signal line Reset3, the second scan signal line G2, and the first light-emitting signal line EM1 are high-level signals, while the signals on the first scan signal line G1 and the second light-emitting signal line EM2 are low-level signals. The signals on the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, the sixth transistor T6 and the ninth transistor T9 are turned on, and the signal on the auxiliary signal line VX is continuously written to the fourth node N4 and the fifth node N5, continuously initializing (resetting) the signals on the fourth node N4 and the fifth node N5. The signal on the second scan signal line G2 is high, the second transistor T2 is turned on, the signal on the reference signal line REF is continuously supplied to the first node N1, the signal on the first emission signal line EM1 is high, the fourth transistor T4 is turned on, and the signal on the first power line VDD is written to the third node N3 via the turned-on fourth transistor T4, the second node N2, and the turned-on third transistor T3, until the voltage V3 of the signal on the third node N3 reaches Vref - Vth, where Vref is the voltage of the signal on the reference signal line REF and Vth is the threshold voltage of the third transistor T3. At this point, the first capacitor C1 stores the voltage difference Vth between the signals on the first node N1 and the third node N3. The signals on the first scan signal line G1 and the second emission signal line EM2 are low, and the first transistor T1 and the fifth transistor T5 are turned off. During this stage, the light-emitting device L does not emit light.

[0396] In the third phase P43, the data writing phase, the signals on the first reset signal line Reset1 and the third reset signal line Reset are high-level signals, the signals on the second scan signal line G2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are low-level signals, the first scan signal line G1 is high-level during a portion of the time period, and the data signal line Data outputs a data voltage. The signals on the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, the ninth transistor T9 is turned on, and the signal on the auxiliary signal line VX is continuously written to the fourth node N4 and the fifth node N5, continuously initializing (resetting) the signals on the fourth node N4 and the fifth node N5. The signal on the first scan signal line G1 is high, turning on the first transistor T1. The data voltage on the data signal line Data is written to the first node N1. At this point, the voltage V1 of the first node N1 equals Vdata, where Vdata is the data voltage on the data signal line. The signal on the first node N1 changes from its current voltage value to its previous voltage value. Therefore, under the action of the first capacitor C1 and the second capacitor C2, the signal on the third node N3 also changes. At this point, the voltage V3 of the signal on the third node N3 equals Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2), where C1 is the capacitance of the first capacitor and C2 is the capacitance of the second capacitor. The signals on the second scan signal line G2, the first emission signal line EM1, and the second emission signal line EM2 are low, turning off the second transistor T2, the fourth transistor T4, and the fifth transistor T5. In this stage, the light-emitting device L does not emit light.

[0397] In the fourth phase P44, the second reset phase, the signal on the second emission signal line EM2 is high, while the signals on the first scan signal line G1, the second scan signal line G2, and the first emission signal line EM1 are low. The signals on the third reset signal line Reset3 and the first reset signal line Reset1 are high for some periods of time and low for some periods of time. The period during which either the third reset signal line Reset3 or the first reset signal line Reset1 is high precedes the period during which it is low. The signal on the second emission signal line EM2 is high, the fifth transistor T5 is turned on, and then the sixth transistor T6 and the ninth transistor T9 are turned off in sequence. Although the signal on the third node N3 becomes the signal on the dynamic signal line Var, the voltage difference between the signals on the first node N1 and the third node N3 remains unchanged. The signals on the first scan signal line G1, the second scan signal line G2, and the first emission signal line EM1 are low, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off. In this phase, the light-emitting device L does not emit light.

[0398] In the fifth phase P45, i.e., the light-emitting phase, the signals on the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are high-level signals, and the signals on the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals. The signals on the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are high-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fourth transistor T4, the third transistor T3, and the fifth transistor T5, driving the light-emitting device L to emit light. The signals on the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals, and the first transistor T1, the second transistor T2, the sixth transistor T6, and the ninth transistor T9 are turned off. In this phase, the light-emitting device L emits light.

[0399] During the pixel driving circuit's driving process, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its control electrode (also the first node N1) and the second electrode (also the third node N3). Since the voltage value of the signal at the first node V1 = Vdata - [Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2)] + Vinit, and the voltage value of the signal at the third node N3 V3 = Vinit, the driving current of the third transistor T3 is:

[0400] I=K*(Vgs-Vth) 2

[0401] =K*[Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]-Vth] 2

[0402] =K*[(C2 / (C1+C2))*(Vdata-Vref)] 2 .

[0403] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the control electrode and the second electrode of the third transistor T3.

[0404] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0405] Figure 38Afor Figure 25B 、 Figure 26B 、 Figure 28B and Figure 30B The working timing of the pixel driving circuit provided Figure 1 , combined with Figure 25B and Figure 38A The pixel driving circuit provided by the present disclosure is further described.

[0406] In the first phase P31, referred to as the reset phase, the signals on the second scan signal line G2, the first emission signal line EM1, the first reset signal line Reset1, and the third reset signal line Reset3 are high-level signals, while the signals on the first scan signal line G1 and the second emission signal line EM2 are low-level signals. The signal on the second scan signal line G2 is high-level, turning on the second transistor T2. The signal on the reference signal line REF is written to the first node N1, initializing (resetting) the signal on the first node N1 and clearing the existing charge in the first node N1. The signal on the second light-emitting signal line EM2 is low, the signals on the first reset signal line Reset1 and the third reset signal line Reset3 are high, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are turned on, and the signal on the dynamic signal line Var is written to the third node N3, the fourth node N4, and the fifth node N5, respectively. Because the voltage values ​​of the signals on the first node N1 and the third node N3 are greater than the threshold voltage of the third transistor T3, the third transistor T3 is turned on, and the signal on the dynamic signal line Var is written to the second node N2, initializing (resetting) the signals on the second node N2, the third node N3, the fourth node N4, and the fifth node N5, clearing the existing charge on the second node N2, the third node N3, the fourth node N4, and the fifth node N5. The signal on the first scanning signal line G1 is low, the signal on the first light-emitting signal line EM1 is high, and the first transistor T1 and the fourth transistor T4 are turned off. At this stage, the light-emitting device L does not emit light.

[0407] In the second phase P32, i.e., the threshold compensation phase, the signals on the first reset signal line Reset1, the third reset signal line Reset3, the second scan signal line G2, and the second light-emitting signal line EM2 are high-level signals, while the signals on the first scan signal line G1 and the first light-emitting signal line EM1 are low-level signals. The signals on the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, the sixth transistor T6 and the eighth transistor T8 are turned on, and the signal on the dynamic signal line Var is continuously written to the fourth node N4 and the fifth node N5, continuously initializing (resetting) the signals on the fourth node N4 and the fifth node N5. The signal on the second scan signal line G2 is high, the second transistor T2 is turned on, the signal on the reference signal line REF is continuously supplied to the first node N1, the signal on the first light-emitting signal line EM1 is low, and the fourth transistor T4 is turned on. The signal on the first power line VDD is written to the third node N3 via the turned-on fourth transistor T4, the second node N2, and the turned-on third transistor T3, until the voltage V3 of the signal on the third node N3 reaches Vref - Vth, where Vref is the voltage of the signal on the reference signal line REF and Vth is the threshold voltage of the third transistor T3. At this point, the first capacitor C1 stores the voltage difference Vth between the signals on the first node N1 and the third node N3. The signal on the first scan signal line G1 is low, the signal on the second light-emitting signal line EM2 is high, and the first transistor T1 and the fifth transistor T5 are turned off. During this stage, the light-emitting device L does not emit light.

[0408] In the third phase P33, the data writing phase, the signals on the first reset signal line Reset1, the third reset signal line Reset, the first luminescence signal line EM1, and the second luminescence signal line EM2 are high-level signals. The signal on the second scan signal line G2 is low-level. The first scan signal line G1 is high-level during a portion of the time period. The data signal line Data outputs a data voltage. The signals on the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals. The sixth transistor T6 and the eighth transistor T8 are turned on. The signal on the dynamic signal line Var is continuously written to the fourth node N4 and the fifth node N5, continuously initializing (resetting) the signals on the fourth node N4 and the fifth node N5. The signal on the first scan signal line G1 is high, turning on the first transistor T1. The data voltage on the data signal line Data is written to the first node N1. At this point, the voltage V1 of the first node N1 equals Vdata, where Vdata is the data voltage of the data signal line. The signal on the first node N1 changes from its current voltage value to its previous voltage value. Therefore, under the action of the first capacitor C1 and the second capacitor C2, the signal on the third node N3 also changes. At this point, the voltage V3 of the signal on the third node N3 equals Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2), where C1 is the capacitance of the first capacitor and C2 is the capacitance of the second capacitor. The signal on the second scan signal line G2 is low, and the signals on the first and second emission signal lines EM1 and EM2 are high. The second transistor T2, the fourth transistor T4, and the fifth transistor T5 are off. In this stage, the light-emitting device L does not emit light.

[0409] In the fourth phase P34, i.e., the light-emitting phase, the signals on the first light-emitting signal line EM1, the second light-emitting signal line EM2, the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals. The signals on the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are low-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fourth transistor T4, third transistor T3, and fifth transistor T5, driving the light-emitting device L to emit light. The signals on the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals, and the first transistor T1, the second transistor T2, the sixth transistor T6, and the eighth transistor T8 are turned off. In this phase, the light-emitting device L emits light.

[0410] During the pixel driving circuit's driving process, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its control electrode (also the first node N1) and the second electrode (also the third node N3). Since the voltage value of the signal at the first node V1 = Vdata - [Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2)] + Vinit, and the voltage value of the signal at the third node N3 V3 = Vinit, the driving current of the third transistor T3 is:

[0411] I=K*(Vgs-Vth) 2

[0412] =K*[Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]-Vth] 2

[0413] =K*[(C2 / (C1+C2))*(Vdata-Vref)] 2 .

[0414] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the control electrode and the second electrode of the third transistor T3.

[0415] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0416] Figure 38B for Figure 25B 、 Figure 26B 、 Figure 28B and Figure 30B The working timing of the pixel driving circuit provided Figure 2 , combined with Figure 25B and Figure 38B The pixel driving circuit provided by the present disclosure is further described.

[0417] The first phase P41 is called the reset phase. The signals on the first reset signal line Reset1, the second scan signal line G2, the first light-emitting signal line EM1, and the third reset signal line Reset3 are high-level signals, while the signals on the first scan signal line G1 and the second light-emitting signal line EM2 are low-level signals. The signal on the second scan signal line G2 is high-level, turning on the second transistor T2. The signal on the reference signal line REF is written to the first node N1, initializing (resetting) the signal on the first node N1 and clearing the existing charge in the first node N1. The signals on the first reset signal line Reset1 and the third reset signal line Reset3 are high, the signal on the second light-emitting signal line EM2 is low, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are turned on, and the signal on the dynamic signal line Var is written to the third node N3, the fourth node N4, and the fifth node N5, respectively. Because the voltage values ​​of the signals on the first node N1 and the third node N3 are greater than the threshold voltage of the third transistor T3, the third transistor T3 is turned on, and the signal on the dynamic signal line Var is written to the second node N2, initializing (resetting) the signals on the second node N2, the third node N3, the fourth node N4, and the fifth node N5, clearing the existing charges on the second node N2, the third node N3, the fourth node N4, and the fifth node N5. The signal on the first scan signal line G1 is low, the signal on the first light-emitting signal line EM1 is high, and the first transistor T1 and the fourth transistor T4 are turned off. At this stage, the light-emitting device L does not emit light.

[0418] In the second phase P42, i.e., the threshold compensation phase, the signals on the first reset signal line Reset1, the third reset signal line Reset3, the second scan signal line G2, and the second light-emitting signal line EM2 are high-level signals, while the signals on the first scan signal line G1 and the first light-emitting signal line EM1 are low-level signals. The signals on the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, the sixth transistor T6 and the eighth transistor T8 are turned on, and the signal on the dynamic signal line Var is continuously written to the fourth node N4 and the fifth node N5, continuously initializing (resetting) the signals on the fourth node N4 and the fifth node N5. The signal on the second scan signal line G2 is high, the second transistor T2 is turned on, the signal on the reference signal line REF is continuously supplied to the first node N1, the signal on the first light-emitting signal line EM1 is low, and the fourth transistor T4 is turned on. The signal on the first power line VDD is written to the third node N3 via the turned-on fourth transistor T4, the second node N2, and the turned-on third transistor T3, until the voltage V3 of the signal on the third node N3 reaches Vref - Vth, where Vref is the voltage of the signal on the reference signal line REF and Vth is the threshold voltage of the third transistor T3. At this point, the first capacitor C1 stores the voltage difference Vth between the signals on the first node N1 and the third node N3. The signal on the first scan signal line G1 is low, the signal on the second light-emitting signal line EM2 is high, and the first transistor T1 and the fifth transistor T5 are turned off. During this stage, the light-emitting device L does not emit light.

[0419] In the third phase P43, the data writing phase, the signals on the first reset signal line Reset1, the third reset signal line Reset, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals. The signal on the second scan signal line G2 is low-level. The first scan signal line G1 is high-level during a portion of the time period. The data signal line Data outputs a data voltage. The signals on the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals. The eighth transistor T8 is turned on, and the signal on the dynamic signal line Var is continuously written to the fourth node N4 and the fifth node N5, continuously initializing (resetting) the signals on the fourth node N4 and the fifth node N5. The signal on the first scan signal line G1 is high, turning on the first transistor T1. The data voltage on the data signal line Data is written to the first node N1. At this point, the voltage V1 of the first node N1 equals Vdata, where Vdata is the data voltage of the data signal line. The signal on the first node N1 changes from its current voltage value to its previous voltage value. Therefore, under the action of the first capacitor C1 and the second capacitor C2, the signal on the third node N3 also changes. At this point, the voltage V3 of the signal on the third node N3 equals Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2), where C1 is the capacitance of the first capacitor and C2 is the capacitance of the second capacitor. The signal on the second scan signal line G2 is low, and the signals on the first and second emission signal lines EM1 and EM2 are high. The second transistor T2, the fourth transistor T4, and the fifth transistor T5 are off. In this stage, the light-emitting device L does not emit light.

[0420] In the fourth phase P44, the second reset phase, the signal on the first emission signal line EM1 is high, while the signals on the first scan signal line G1, the second scan signal line G2, and the second emission signal line EM2 are low. The signals on the third reset signal line Reset3 and the first reset signal line Reset1 are high for some periods of time and low for some periods of time. The period during which either the third reset signal line Reset3 or the first reset signal line Reset1 is high precedes the period during which it is low. The signal on the second emission signal line EM2 is low, and the fifth transistor T5 is turned on. Then, the sixth transistor T6 and the eighth transistor T8 are turned off in sequence. Although the signal on the third node N3 changes to the signal on the dynamic signal line Var, the voltage difference between the signals on the first node N1 and the third node N3 remains unchanged. The signals on the first scan signal line G1 and the second scan signal line G2 are low, while the signal on the first emission signal line EM1 is high. The second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off. In this phase, the light-emitting device L does not emit light.

[0421] In the fifth phase P45, i.e., the light-emitting phase, the signals on the first light-emitting signal line EM1, the second light-emitting signal line EM2, the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals. The signals on the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are low-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fourth transistor T4, third transistor T3, and fifth transistor T5, driving the light-emitting device L to emit light. The signals on the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals, and the first transistor T1, the second transistor T2, the sixth transistor T6, and the eighth transistor T8 are turned off. In this phase, the light-emitting device L emits light.

[0422] During the pixel driving circuit's driving process, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its control electrode (also the first node N1) and the second electrode (also the third node N3). Since the voltage value of the signal at the first node V1 = Vdata - [Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2)] + Vinit, and the voltage value of the signal at the third node N3 V3 = Vinit, the driving current of the third transistor T3 is:

[0423] I=K*(Vgs-Vth) 2

[0424] =K*[Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]-Vth] 2

[0425] =K*[(C2 / (C1+C2))*(Vdata-Vref)] 2 .

[0426] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the control electrode and the second electrode of the third transistor T3.

[0427] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0428] Figure 25B 、 Figure 26B and Figure 28B The transistors included in the circuit are the same, and the only difference is the connection relationship and number of capacitors. The capacitors do not affect the timing, so Figure 26B and Figure 28B The working process of the provided pixel driving circuit is exactly the same as the working process of Figure 25, and the present disclosure does not limit this.

[0429] Combine Figure 30B and Figure 38A The pixel driving circuit provided by the present disclosure is further described.

[0430] In the first phase P31, referred to as the reset phase, the signals on the second scan signal line G2, the first emission signal line EM1, the first reset signal line Reset1, and the third reset signal line Reset3 are high-level signals, while the signals on the first scan signal line G1 and the second emission signal line EM2 are low-level signals. The signal on the second scan signal line G2 is high-level, turning on the second transistor T2. The signal on the reference signal line REF is written to the first node N1, initializing (resetting) the signal on the first node N1 and clearing the existing charge in the first node N1. The signal on the second light-emitting signal line EM2 is low, the signals on the first reset signal line Reset1 and the third reset signal line Reset3 are high, the fifth transistor T5, the sixth transistor T6, and the ninth transistor T9 are turned on, and the signal on the auxiliary signal line VX is written to the third node N3, the fourth node N4, and the fifth node N5, respectively. Because the voltage values ​​of the signals on the first node N1 and the third node N3 are greater than the threshold voltage of the third transistor T3, the third transistor T3 is turned on, and the signal on the auxiliary signal line VX is written to the second node N2, initializing (resetting) the signals on the second node N2, the third node N3, the fourth node N4, and the fifth node N5, clearing the existing charge in the second node N2, the third node N3, the fourth node N4, and the fifth node N5. The signal on the first scanning signal line G1 is low, the signal on the first light-emitting signal line EM1 is high, and the first transistor T1 and the fourth transistor T4 are turned off. At this stage, the light-emitting device L does not emit light.

[0431] In the second phase P32, i.e., the threshold compensation phase, the signals on the first reset signal line Reset1, the third reset signal line Reset3, the second scan signal line G2, and the second light-emitting signal line EM2 are high-level signals, while the signals on the first scan signal line G1 and the first light-emitting signal line EM1 are low-level signals. The signals on the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, the sixth transistor T6 and the ninth transistor T9 are turned on, and the signal on the auxiliary signal line VX is continuously written to the fourth node N4 and the fifth node N5, continuously initializing (resetting) the signals on the fourth node N4 and the fifth node N5. The signal on the second scan signal line G2 is high, the second transistor T2 is turned on, the signal on the reference signal line REF is continuously supplied to the first node N1, the signal on the first light-emitting signal line EM1 is low, and the fourth transistor T4 is turned on. The signal on the first power line VDD is written to the third node N3 via the turned-on fourth transistor T4, the second node N2, and the turned-on third transistor T3, until the voltage V3 of the signal on the third node N3 reaches Vref - Vth, where Vref is the voltage of the signal on the reference signal line REF and Vth is the threshold voltage of the third transistor T3. At this point, the first capacitor C1 stores the voltage difference Vth between the signals on the first node N1 and the third node N3. The signal on the first scan signal line G1 is low, the signal on the second light-emitting signal line EM2 is high, and the first transistor T1 and the fifth transistor T5 are turned off. During this stage, the light-emitting device L does not emit light.

[0432] In the third phase P33, the data writing phase, the signals on the first reset signal line Reset1, the third reset signal line Reset2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals. The signal on the second scan signal line G is low-level. The first scan signal line G1 is high-level during a portion of the time period. The data signal line Data outputs a data voltage. The signals on the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals. The sixth transistor T6 and the ninth transistor T9 are turned on. The signal on the auxiliary signal line VX is continuously written into the fourth node N4 and the fifth node N5, continuously initializing (resetting) the signals on the fourth node N4 and the fifth node N5. The signal on the first scan signal line G1 is high, turning on the first transistor T1. The data voltage on the data signal line Data is written to the first node N1. At this point, the voltage V1 of the first node N1 equals Vdata, where Vdata is the data voltage of the data signal line. The signal on the first node N1 changes from its current voltage value to its previous voltage value. Therefore, under the action of the first capacitor C1 and the second capacitor C2, the signal on the third node N3 also changes. At this point, the voltage V3 of the signal on the third node N3 equals Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2), where C1 is the capacitance of the first capacitor and C2 is the capacitance of the second capacitor. The signal on the second scan signal line G2 is low, and the signals on the first and second emission signal lines EM1 and EM2 are high. The second transistor T2, the fourth transistor T4, and the fifth transistor T5 are off. In this stage, the light-emitting device L does not emit light.

[0433] In the fourth phase P34, i.e., the light-emitting phase, the signals on the first light-emitting signal line EM1, the second light-emitting signal line EM2, the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals. The signals on the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are low-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fourth transistor T4, third transistor T3, and fifth transistor T5, driving the light-emitting device L to emit light. The signals on the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals, and the first transistor T1, the second transistor T2, the sixth transistor T6, and the ninth transistor T9 are turned off. In this phase, the light-emitting device L emits light.

[0434] During the pixel driving circuit's driving process, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its control electrode (also the first node N1) and the second electrode (also the third node N3). Since the voltage value of the signal at the first node V1 = Vdata - [Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2)] + Vinit, and the voltage value of the signal at the third node N3 V3 = Vinit, the driving current of the third transistor T3 is:

[0435] I=K*(Vgs-Vth) 2

[0436] =K*[Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]-Vth] 2

[0437] =K*[(C2 / (C1+C2))*(Vdata-Vref)] 2 .

[0438] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the control electrode and the second electrode of the third transistor T3.

[0439] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0440] Combine Figure 30B and Figure 38B The pixel driving circuit provided by the present disclosure is further described.

[0441] The first phase P41 is called the reset phase. The signals on the first reset signal line Reset1, the second scan signal line G2, the first light-emitting signal line EM1, and the third reset signal line Reset3 are high-level signals, while the signals on the first scan signal line G1 and the second light-emitting signal line EM2 are low-level signals. The signal on the second scan signal line G2 is high-level, turning on the second transistor T2. The signal on the reference signal line REF is written to the first node N1, initializing (resetting) the signal on the first node N1 and clearing the existing charge in the first node N1. The signals on the first reset signal line Reset1 and the third reset signal line Reset3 are high, the signal on the second light-emitting signal line EM2 is low, the fifth transistor T5, the sixth transistor T6, and the ninth transistor T9 are turned on, and the signal on the auxiliary signal line VX is written to the third node N3, the fourth node N4, and the fifth node N5, respectively. Because the voltage values ​​of the signals on the first node N1 and the third node N3 are greater than the threshold voltage of the third transistor T3, the third transistor T3 is turned on, and the signal on the auxiliary signal line VX is written to the second node N2, initializing (resetting) the signals on the second node N2, the third node N3, the fourth node N4, and the fifth node N5, clearing the existing charge on the second node N2, the third node N3, the fourth node N4, and the fifth node N5. The signal on the first scan signal line G1 is low, the signal on the first light-emitting signal line EM1 is high, and the first transistor T1 and the fourth transistor T4 are turned off. At this stage, the light-emitting device L does not emit light.

[0442] In the second phase P42, i.e., the threshold compensation phase, the signals on the first reset signal line Reset1, the third reset signal line Reset3, the second scan signal line G2, and the second light-emitting signal line EM2 are high-level signals, while the signals on the first scan signal line G1 and the first light-emitting signal line EM1 are low-level signals. The signals on the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals, the sixth transistor T6 and the ninth transistor T9 are turned on, and the signal on the auxiliary signal line VX is continuously written to the fourth node N4 and the fifth node N5, continuously initializing (resetting) the signals on the fourth node N4 and the fifth node N5. The signal on the second scan signal line G2 is high, the second transistor T2 is turned on, the signal on the reference signal line REF is continuously supplied to the first node N1, the signal on the first light-emitting signal line EM1 is low, and the fourth transistor T4 is turned on. The signal on the first power line VDD is written to the third node N3 via the turned-on fourth transistor T4, the second node N2, and the turned-on third transistor T3, until the voltage V3 of the signal on the third node N3 reaches Vref - Vth, where Vref is the voltage of the signal on the reference signal line REF and Vth is the threshold voltage of the third transistor T3. At this point, the first capacitor C1 stores the voltage difference Vth between the signals on the first node N1 and the third node N3. The signal on the first scan signal line G1 is low, the signal on the second light-emitting signal line EM2 is high, and the first transistor T1 and the fifth transistor T5 are turned off. During this stage, the light-emitting device L does not emit light.

[0443] In the third phase P43, the data writing phase, the signals on the first reset signal line Reset1, the third reset signal line Reset, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals. The signal on the second scan signal line G2 is low-level. The first scan signal line G1 is high-level during a portion of the time period. The data signal line Data outputs a data voltage. The signals on the first reset signal line Reset1 and the third reset signal line Reset3 are high-level signals. The ninth transistor T9 is turned on. The signal on the auxiliary signal line VX is continuously written into the fourth node N4 and the fifth node N5, continuously initializing (resetting) the signals on the fourth node N4 and the fifth node N5. The signal on the first scan signal line G1 is high, turning on the first transistor T1. The data voltage on the data signal line Data is written to the first node N1. At this point, the voltage V1 of the first node N1 equals Vdata, where Vdata is the data voltage of the data signal line. The signal on the first node N1 changes from its current voltage value to its previous voltage value. Therefore, under the action of the first capacitor C1 and the second capacitor C2, the signal on the third node N3 also changes. At this point, the voltage V3 of the signal on the third node N3 equals Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2), where C1 is the capacitance of the first capacitor and C2 is the capacitance of the second capacitor. The signal on the second scan signal line G2 is low, and the signals on the first and second emission signal lines EM1 and EM2 are high. The second transistor T2, the fourth transistor T4, and the fifth transistor T5 are off. In this stage, the light-emitting device L does not emit light.

[0444] In the fourth phase P44, the second reset phase, the signal on the first emission signal line EM1 is high, while the signals on the first scan signal line G1, the second scan signal line G2, and the second emission signal line EM2 are low. The signals on the third reset signal line Reset3 and the first reset signal line Reset1 are high for some periods of time and low for some periods of time. The period during which either the third reset signal line Reset3 or the first reset signal line Reset1 is high precedes the period during which it is low. The signal on the second emission signal line EM2 is low, and the fifth transistor T5 is turned on. Then, the sixth transistor T6 and the ninth transistor T9 are turned off in sequence. Although the signal on the third node N3 changes to the signal on the dynamic signal line Var, the voltage difference between the signals on the first node N1 and the third node N3 remains unchanged. The signals on the first scan signal line G1 and the second scan signal line G2 are low, while the signal on the first emission signal line EM1 is high. The second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned off. In this phase, the light-emitting device L does not emit light.

[0445] In the fifth phase P45, i.e., the light-emitting phase, the signals on the first light-emitting signal line EM1, the second light-emitting signal line EM2, the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals. The signals on the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are low-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fourth transistor T4, the third transistor T3, and the fifth transistor T5, driving the light-emitting device L to emit light. The signals on the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1, and the second scan signal line G2 are low-level signals, and the first transistor T1, the second transistor T2, the sixth transistor T6, and the ninth transistor T9 are turned off. In this phase, the light-emitting device L emits light.

[0446] During the pixel driving circuit's driving process, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its control electrode (also the first node N1) and the second electrode (also the third node N3). Since the voltage value of the signal at the first node V1 = Vdata - [Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2)] + Vinit, and the voltage value of the signal at the third node N3 V3 = Vinit, the driving current of the third transistor T3 is:

[0447] I=K*(Vgs-Vth) 2

[0448] =K*[Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]-Vth] 2

[0449] =K*[(C2 / (C1+C2))*(Vdata-Vref)] 2 .

[0450] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the control electrode and the second electrode of the third transistor T3.

[0451] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0452] Figure 39A for Figure 33A The working timing of the pixel driving circuit provided Figure 1 , combined with Figure 33A and Figure 39A The pixel driving circuit provided by the present disclosure is further described.

[0453] In the first phase P51, referred to as the reset phase, the signals on the second scan signal line G2, the second light-emitting signal line EM2, the first reset signal line Reset1, the third reset signal line Reset3, and the fourth reset signal line Reset4 are high-level signals, while the signals on the first scan signal line G1 and the first light-emitting signal line EM1 are low-level signals. The signal on the second scan signal line G2 is high-level, turning on the second transistor T2. The signal on the reference signal line REF is written to the first node N1, initializing (resetting) the signal on the first node N1 and clearing the existing charge in the first node N1. The signals on the second light-emitting signal line EM2, the first reset signal line Reset1, the third reset signal line Reset3, and the fourth reset signal line Reset4 are high-level signals. The fifth transistor T5, the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 are turned on. The signal on the dynamic signal line Var is written to the third node N3, the fourth node N4, and the fifth node N5, respectively. Because the voltage values ​​of the signals on the first node N1 and the third node N3 are greater than the threshold voltage of the third transistor T3, the third transistor T3 is turned on. The signal on the dynamic signal line Var is written to the second node N2, initializing (resetting) the signals on the second node N2, the third node N3, the fourth node N4, and the fifth node N5, clearing the existing charges on the second node N2, the third node N3, the fourth node N4, and the fifth node N5. The signals on the first scanning signal line G1 and the first light-emitting signal line EM1 are low-level signals. The first transistor T1 and the fourth transistor T4 are turned off. At this stage, the light-emitting device L does not emit light.

[0454] In the second phase P52, i.e., the threshold compensation phase, the signals on the first reset signal line Reset1, the third reset signal line Reset3, the fourth reset signal line Reset4, the second scan signal line G2, and the first light-emitting signal line EM1 are high-level signals, while the signals on the first scan signal line G1 and the second light-emitting signal line EM2 are low-level signals. The signals on the first reset signal line Reset1, the third reset signal line Reset3, and the fourth reset signal line Reset4 are high-level signals, the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 are turned on, and the signal on the dynamic signal line Var or the auxiliary signal line VX is continuously written into the fourth node N4 and the fifth node N5, continuously initializing (resetting) the signals on the fourth node N4 and the fifth node N5. The signal on the second scan signal line G2 is high, the second transistor T2 is turned on, the signal on the reference signal line REF is continuously supplied to the first node N1, the signal on the first emission signal line EM1 is high, the fourth transistor T4 is turned on, and the signal on the first power line VDD is written to the third node N3 via the turned-on fourth transistor T4, the second node N2, and the turned-on third transistor T3, until the voltage V3 of the signal on the third node N3 reaches Vref - Vth, where Vref is the voltage of the signal on the reference signal line REF and Vth is the threshold voltage of the third transistor T3. At this point, the first capacitor C1 stores the voltage difference Vth between the signals on the first node N1 and the third node N3. The signals on the first scan signal line G1 and the second emission signal line EM2 are low, and the first transistor T1 and the fifth transistor T5 are turned off. During this stage, the light-emitting device L does not emit light.

[0455] In the third phase P53, the data writing phase, the signals on the first reset signal line Reset1, the third reset signal line Reset3, and the fourth reset signal line Reset4 are high-level signals. The signals on the second scan signal line G2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are low-level signals. The first scan signal line G1 is high-level during a portion of the time period, and the data signal line Data outputs a data voltage. The signals on the first reset signal line Reset1, the third reset signal line Reset3, and the fourth reset signal line Reset4 are high-level signals. The sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 are turned on. The signal on the dynamic signal line Var is continuously written to the fourth node N4 and the fifth node N5, continuously initializing (resetting) the signals on the fourth node N4 and the fifth node N5. The signal on the first scan signal line G1 is high, turning on the first transistor T1. The data voltage on the data signal line Data is written to the first node N1. At this point, the voltage V1 of the first node N1 equals Vdata, where Vdata is the data voltage on the data signal line. The signal on the first node N1 changes from its current voltage value to its previous voltage value. Therefore, under the action of the first capacitor C1 and the second capacitor C2, the signal on the third node N3 also changes. At this point, the voltage V3 of the signal on the third node N3 equals Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2), where C1 is the capacitance of the first capacitor and C2 is the capacitance of the second capacitor. The signals on the second scan signal line G2, the first emission signal line EM1, and the second emission signal line EM2 are low, turning off the second transistor T2, the fourth transistor T4, and the fifth transistor T5. In this stage, the light-emitting device L does not emit light.

[0456] In the fourth phase P54, i.e., the light-emitting phase, the signals on the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are high-level signals, while the signals on the first reset signal line Reset1, the third reset signal line Reset3, the fourth reset signal line Reset4, the first scan signal line G1, and the second scan signal line G2 are low-level signals. The signals on the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are high-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, and the power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fourth transistor T4, the third transistor T3, and the fifth transistor T5, driving the light-emitting device L to emit light. The signals on the first reset signal line Reset1, the third reset signal line Reset3, the fourth reset signal line Reset4, the first scan signal line G1, and the second scan signal line G2 are low-level signals, and the first transistor T1, the second transistor T2, the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 are turned off. In this phase, the light-emitting device L emits light.

[0457] During the pixel driving circuit's driving process, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its control electrode (also the first node N1) and the second electrode (also the third node N3). Since the voltage value of the signal at the first node V1 = Vdata - [Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2)] + Vinit, and the voltage value of the signal at the third node N3 V3 = Vinit, the driving current of the third transistor T3 is:

[0458] I=K*(Vgs-Vth) 2

[0459] =K*[Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]-Vth] 2

[0460] =K*[(C2 / (C1+C2))*(Vdata-Vref)] 2 .

[0461] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the control electrode and the second electrode of the third transistor T3.

[0462] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0463] Figure 39B for Figure 33A The working timing of the pixel driving circuit provided Figure 2 , combined with Figure 33A and Figure 39B The pixel driving circuit provided by the present disclosure is further described.

[0464] The first phase P61 is called the reset phase. The signals on the first reset signal line Reset1, the second scan signal line G2, the second light-emitting signal line EM2, the third reset signal line Reset3, and the fourth reset signal line Reset4 are high-level signals, while the signals on the first scan signal line G1 and the first light-emitting signal line EM1 are low-level signals. The signal on the second scan signal line G2 is high-level, turning on the second transistor T2. The signal on the reference signal line REF is written to the first node N1, initializing (resetting) the signal on the first node N1 and clearing the existing charge in the first node N1. The signals on the first reset signal line Reset1, the second emission signal line EM2, the third reset signal line Reset3, and the fourth reset signal line Reset4 are high-level signals. The fifth transistor T5, the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 are turned on. The signal on the dynamic signal line Var is written to the third node N3, the fourth node N4, and the fifth node N5, respectively. Because the voltage values ​​of the signals on the first node N1 and the third node N3 are greater than the threshold voltage of the third transistor T3, the third transistor T3 is turned on. The signal on the dynamic signal line Var is written to the second node N2, initializing (resetting) the signals on the second node N2, the third node N3, the fourth node N4, and the fifth node N5, clearing the existing charges in the second node N2, the third node N3, the fourth node N4, and the fifth node N5. The signals on the first scan signal line G1 and the first emission signal line EM1 are low-level signals. The first transistor T1 and the fourth transistor T4 are turned off. At this stage, the light-emitting device L does not emit light.

[0465] In the second phase P62, i.e., the threshold compensation phase, the signals on the first reset signal line Reset1, the third reset signal line Reset3, the fourth reset signal line Reset4, the second scan signal line G2, and the first light-emitting signal line EM1 are high-level signals, while the signals on the first scan signal line G1 and the second light-emitting signal line EM2 are low-level signals. The signals on the first reset signal line Reset1, the third reset signal line Reset3, and the fourth reset signal line Reset4 are high-level signals, the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 are turned on, and the signal on the dynamic signal line Var or the auxiliary signal line VX is continuously written into the fourth node N4 and the fifth node N5, continuously initializing (resetting) the signals on the fourth node N4 and the fifth node N5. The signal on the second scan signal line G2 is high, the second transistor T2 is turned on, the signal on the reference signal line REF is continuously supplied to the first node N1, the signal on the first emission signal line EM1 is high, the fourth transistor T4 is turned on, and the signal on the first power line VDD is written to the third node N3 via the turned-on fourth transistor T4, the second node N2, and the turned-on third transistor T3, until the voltage V3 of the signal on the third node N3 reaches Vref - Vth, where Vref is the voltage of the signal on the reference signal line REF and Vth is the threshold voltage of the third transistor T3. At this point, the first capacitor C1 stores the voltage difference Vth between the signals on the first node N1 and the third node N3. The signals on the first scan signal line G1 and the second emission signal line EM2 are low, and the first transistor T1 and the fifth transistor T5 are turned off. During this stage, the light-emitting device L does not emit light.

[0466] In the third phase P63, the data writing phase, the signals on the first reset signal line Reset1, the third reset signal line Reset3, and the fourth reset signal line Reset4 are high-level signals. The signals on the second scan signal line G2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are low-level signals. The first scan signal line G1 is high-level during a portion of the time period, and the data signal line Data outputs a data voltage. The signals on the first reset signal line Reset1, the third reset signal line Reset3, and the fourth reset signal line Reset4 are high-level signals. The eighth transistor T8 and the ninth transistor T9 are turned on. The signal on the dynamic signal line Var is continuously written to the fourth node N4 and the fifth node N5, continuously initializing (resetting) the signals on the fourth node N4 and the fifth node N5. The signal on the first scan signal line G1 is high, turning on the first transistor T1. The data voltage on the data signal line Data is written to the first node N1. At this point, the voltage V1 of the first node N1 equals Vdata, where Vdata is the data voltage on the data signal line. The signal on the first node N1 changes from its current voltage value to its previous voltage value. Therefore, under the action of the first capacitor C1 and the second capacitor C2, the signal on the third node N3 also changes. At this point, the voltage V3 of the signal on the third node N3 equals Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2), where C1 is the capacitance of the first capacitor and C2 is the capacitance of the second capacitor. The signals on the second scan signal line G2, the first emission signal line EM1, and the second emission signal line EM2 are low, turning off the second transistor T2, the fourth transistor T4, and the fifth transistor T5. In this stage, the light-emitting device L does not emit light.

[0467] In the fourth phase P64, the second reset phase, the signal on the second light-emitting signal line EM2 is high, the signals on the first scan signal line G1, the second scan signal line G2, and the first light-emitting signal line EM1 are low, and the signals on the third reset signal line Reset3, the fourth reset signal line Reset4, and the first reset signal line Reset1 are high for part of the time period and low for part of the time period. The time period during which any of the signals on the third reset signal line Reset3, the fourth reset signal line Reset4, and the first reset signal line Reset1 is high is earlier than the time period during which the signals are low. The time during which the third reset signal line Reset3 and the fourth reset signal line Reset4 are high is shorter than the time during which the signal on the first reset signal line Reset1 is high. The signal on the second light-emitting signal line EM2 is high, the fifth transistor T5 is turned on, the sixth transistor T6 is turned off first, and then the eighth transistor T8 and the ninth transistor T9 are turned off. Although the signal on the third node N3 changes to the signal on the dynamic signal line Var, the voltage difference between the signals on the first node N1 and the third node N3 remains unchanged. The signals of the first scanning signal line G1, the second scanning signal line G2 and the first light emitting signal line EM1 are low level signals, and the second transistor T2, the fourth transistor T4 and the fifth transistor T5 are turned off. In this stage, the light emitting device L does not emit light.

[0468] In the fifth stage P65, i.e., the light-emitting stage, the signals on the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are high-level signals, and the signals on the first reset signal line Reset1, the third reset signal line Reset3, the fourth reset signal line Reset4, the first scan signal line G1, and the second scan signal line G2 are low-level signals. The signals on the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are high-level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fourth transistor T4, the third transistor T3, and the fifth transistor T5, driving the light-emitting device L to emit light. The signals on the first reset signal line Reset1, the third reset signal line Reset3, the fourth reset signal line Reset4, the first scan signal line G1, and the second scan signal line G2 are low-level signals, and the first transistor T1, the second transistor T2, the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 are turned off. In this stage, the light-emitting device L emits light.

[0469] During the pixel driving circuit's driving process, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its control electrode (also the first node N1) and the second electrode (also the third node N3). Since the voltage value of the signal at the first node V1 = Vdata - [Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2)] + Vinit, and the voltage value of the signal at the third node N3 V3 = Vinit, the driving current of the third transistor T3 is:

[0470] I=K*(Vgs-Vth)2

[0471] =K*[Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]-Vth]2

[0472] =K*[(C2 / (C1+C2))*(Vdata-Vref)]2.

[0473] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the control electrode and the second electrode of the third transistor T3.

[0474] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0475] Figure 40A for Figure 33B The working timing of the pixel driving circuit provided Figure 1 , combined with Figure 33B and Figure 40A The pixel driving circuit provided by the present disclosure is further described.

[0476] In the first phase P51, referred to as the reset phase, the signals on the second scan signal line G2, the first light-emitting signal line EM1, the first reset signal line Reset1, the third reset signal line Reset3, and the fourth reset signal line Reset4 are high-level signals, while the signals on the first scan signal line G1 and the second light-emitting signal line EM2 are low-level signals. The signal on the second scan signal line G2 is high-level, turning on the second transistor T2. The signal on the reference signal line REF is written to the first node N1, initializing (resetting) the signal on the first node N1 and clearing the existing charge in the first node N1. The signal on the second light-emitting signal line EM2 is low, the signals on the first, third, and fourth reset signal lines Reset1, Reset3, and Reset4 are high, the fifth, sixth, eighth, and ninth transistors T5, T6, T8, and T9 are turned on, and the signal on the dynamic signal line Var is written to the third, fourth, and fifth nodes N3, N4, and N5, respectively. Because the voltages of the signals on the first and third nodes N1 and N3 are greater than the threshold voltage of the third transistor T3, the third transistor T3 is turned on, and the signal on the dynamic signal line Var is written to the second node N2. This initializes (resets) the signals on the second, third, fourth, and fifth nodes N5, clearing the existing charges on the second, third, fourth, and fifth nodes N2, N3, and N4. The signal on the first scanning signal line G1 is low, the signal on the first light-emitting signal line EM1 is high, and the first and fourth transistors T1 and T4 are turned off. At this stage, the light-emitting device L does not emit light.

[0477] In the second phase P52, i.e., the threshold compensation phase, the signals on the first reset signal line Reset1, the third reset signal line Reset3, the fourth reset signal line Reset4, the second scan signal line G2, and the second light-emitting signal line EM2 are high-level signals, while the signals on the first scan signal line G1 and the first light-emitting signal line EM1 are low-level signals. The signals on the first reset signal line Reset1, the third reset signal line Reset3, and the fourth reset signal line Reset4 are high-level signals, the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 are turned on, and the signal on the dynamic signal line Var or the auxiliary signal line VX is continuously written into the fourth node N4 and the fifth node N5, continuously initializing (resetting) the signals on the fourth node N4 and the fifth node N5. The signal on the second scan signal line G2 is high, the second transistor T2 is turned on, the signal on the reference signal line REF is continuously supplied to the first node N1, the signal on the first light-emitting signal line EM1 is low, and the fourth transistor T4 is turned on. The signal on the first power line VDD is written to the third node N3 via the turned-on fourth transistor T4, the second node N2, and the turned-on third transistor T3, until the voltage V3 of the signal on the third node N3 reaches Vref - Vth, where Vref is the voltage of the signal on the reference signal line REF and Vth is the threshold voltage of the third transistor T3. At this point, the first capacitor C1 stores the voltage difference Vth between the signals on the first node N1 and the third node N3. The signal on the first scan signal line G1 is low, the signal on the second light-emitting signal line EM2 is high, and the first transistor T1 and the fifth transistor T5 are turned off. During this stage, the light-emitting device L does not emit light.

[0478] In the third phase P53, the data writing phase, the signals on the first reset signal line Reset1, the third reset signal line Reset3, the fourth reset signal line Reset4, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals. The signal on the second scan signal line G2 is low-level. The first scan signal line G1 is high-level during a portion of the time period. The data signal line Data outputs a data voltage. The signals on the first reset signal line Reset1, the third reset signal line Reset3, and the fourth reset signal line Reset4 are high-level signals. The sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 are turned on. The signal on the dynamic signal line Var is continuously written to the fourth node N4 and the fifth node N5, continuously initializing (resetting) the signals on the fourth node N4 and the fifth node N5. The signal on the first scan signal line G1 is high, turning on the first transistor T1. The data voltage on the data signal line Data is written to the first node N1. At this point, the voltage V1 of the first node N1 equals Vdata, where Vdata is the data voltage of the data signal line. The signal on the first node N1 changes from its current voltage value to its previous voltage value. Therefore, under the action of the first capacitor C1 and the second capacitor C2, the signal on the third node N3 also changes. At this point, the voltage V3 of the signa...

Claims

1. A pixel driving circuit, provided in a display device, comprising: a driving sub-circuit, a storage sub-circuit, a first control sub-circuit, a second control sub-circuit, and a third control sub-circuit; The driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a driving current to the third node under the control of the signals of the first node and the second node; The storage sub-circuit is electrically connected to the first node and the third node, respectively, and is configured to store a voltage difference of a signal between the first node and the third node; The first control subcircuit is electrically connected to the first scan signal line, the second scan signal line, the data signal line, the reference signal line and the first node, and is configured to provide a signal of the data signal line or the reference signal line to the first node under the control of the signal of the first scan signal line and the second scan signal line; The second control subcircuit is electrically connected to the first light emitting signal line, the second light emitting signal line, the first power line, the second node, the third node, and the fourth node, respectively, and is configured to provide a signal from the first power line to the second node and a signal from the third node to the fourth node under the control of signals from the first light emitting signal line and the second light emitting signal line; The third control subcircuit is electrically connected to the third node, the fourth node, the at least one reset signal line, and at least one signal line among the dynamic signal line and the auxiliary signal line, respectively, and is configured to adjust the signals of the third node and the fourth node under the control of the signals of the at least one reset signal line and the at least one signal line among the dynamic signal line and the auxiliary signal line; The display device includes: a first control unit, a second control unit, and a data unit, wherein the first control unit is electrically connected to the second light emitting signal line and configured to provide a signal to the second light emitting signal line, the second control unit is electrically connected to at least one reset signal line and configured to provide a signal to the at least one reset signal line, and the data unit is electrically connected to the dynamic signal line and configured to provide a signal to the dynamic signal line; The content displayed by the display device includes at least one display frame. In at least one display frame, the start time of at least one time period in which the first control unit provides a valid level signal to the second light-emitting signal line is earlier than or equal to the start time in which the second control unit provides an invalid level signal to at least one reset signal line.

2. The pixel driving circuit according to claim 1, wherein: The voltage value of the signal of the dynamic signal line includes: a plurality of voltage values. During at least a portion of at least one display frame, the voltage value of the dynamic signal provided by the data unit to the dynamic signal line is positively correlated with the temperature of the display device.

3. The pixel driving circuit according to claim 1, wherein: The at least one reset signal line includes: a third reset signal line; The third control subcircuit is electrically connected to the third node, the fourth node, the third reset signal line and the dynamic signal line respectively.

4. The pixel driving circuit according to claim 3, wherein: The third control subcircuit includes: a second capacitor and an eighth transistor; A first end of the second capacitor is electrically connected to the third node, and a second end of the second capacitor is electrically connected to the fourth node; A control electrode of the eighth transistor is electrically connected to the third reset signal line, a first electrode of the eighth transistor is electrically connected to the dynamic signal line, and a second electrode of the eighth transistor is electrically connected to the fourth node.

5. The pixel driving circuit according to claim 3 or 4, wherein: The display device further includes: a third control unit, the third control unit being electrically connected to the first light emitting signal line and configured to provide a signal to the first light emitting signal line; In at least one display frame, the start time of at least one time period in which the first control unit provides a valid level signal to the second luminous signal line is earlier than the start time in which the second control unit provides an invalid level signal to the third reset signal line, and the start time of at least one time period in which the third control unit provides a valid level signal to the first luminous signal line is later than the start time in which the second control unit provides an invalid level signal to the third reset signal line.

6. The pixel driving circuit according to claim 1, wherein: The at least one reset signal line includes: a first reset signal line and a third reset signal line; The third control subcircuit is electrically connected to the third node, the fourth node, the first reset signal line, the third reset signal line and the dynamic signal line respectively.

7. The pixel driving circuit according to claim 6, wherein: The third control subcircuit includes: a second capacitor, a sixth transistor and an eighth transistor; A first end of the second capacitor is electrically connected to the third node, and a second end of the second capacitor is electrically connected to the fifth node; a control electrode of the sixth transistor electrically connected to the first reset signal line, a first electrode of the sixth transistor electrically connected to the fifth node, and a second electrode of the sixth transistor electrically connected to the fourth node; A control electrode of the eighth transistor is electrically connected to the third reset signal line, a first electrode of the eighth transistor is electrically connected to the dynamic signal line, and a second electrode of the eighth transistor is electrically connected to the fourth node.

8. The pixel driving circuit according to claim 6, wherein: The third control subcircuit includes: a second capacitor, a third capacitor, a sixth transistor and an eighth transistor; A first end of the second capacitor is electrically connected to the third node, and a second end of the second capacitor is electrically connected to the fifth node; A first end of the third capacitor is electrically connected to the fifth node, and a second end of the third capacitor is electrically connected to the fourth node; The control electrode of the sixth transistor is electrically connected to the first reset signal line, the first electrode of the sixth transistor is electrically connected to the fifth node; and the second electrode of the sixth transistor is electrically connected to the fourth node. A control electrode of the eighth transistor is electrically connected to the third reset signal line, a first electrode of the eighth transistor is electrically connected to the dynamic signal line, and a second electrode of the eighth transistor is electrically connected to the fourth node.

9. The pixel driving circuit according to claim 1, wherein: The at least one reset signal line includes: a first reset signal line and a third reset signal line; The third control subcircuit is electrically connected to the third node, the fourth node, the first reset signal line, the third reset signal line, the dynamic signal line and the auxiliary signal line respectively.

10. The pixel driving circuit according to claim 9, wherein: The third control subcircuit includes: a second capacitor, a third capacitor, a sixth transistor and an eighth transistor; A first end of the second capacitor is electrically connected to the third node, and a second end of the second capacitor is electrically connected to the fifth node; A first end of the third capacitor is electrically connected to the fifth node, and a second end of the third capacitor is electrically connected to the auxiliary signal line; a control electrode of the sixth transistor electrically connected to the first reset signal line, a first electrode of the sixth transistor electrically connected to the fifth node, and a second electrode of the sixth transistor electrically connected to the fourth node; A control electrode of the eighth transistor is electrically connected to the third reset signal line, a first electrode of the eighth transistor is electrically connected to the dynamic signal line, and a second electrode of the eighth transistor is electrically connected to the fourth node.

11. The pixel driving circuit according to claim 1, wherein: The at least one reset signal line includes: a first reset signal line and a third reset signal line; The third control sub-circuit is electrically connected to the third node, the fourth node, the first reset signal line, the third reset signal line and the auxiliary signal line respectively.

12. The pixel driving circuit according to claim 11, wherein: The third control subcircuit includes: a second capacitor, a third capacitor, a sixth transistor and a ninth transistor; A first end of the second capacitor is electrically connected to the third node, and a second end of the second capacitor is electrically connected to the fifth node; A first end of the third capacitor is electrically connected to the fifth node, and a second end of the third capacitor is electrically connected to the fourth node; a control electrode of the sixth transistor electrically connected to the first reset signal line, a first electrode of the sixth transistor electrically connected to the fifth node, and a second electrode of the sixth transistor electrically connected to the fourth node; A control electrode of the ninth transistor is electrically connected to the third reset signal line, a first electrode of the ninth transistor is electrically connected to the auxiliary signal line, and a second electrode of the ninth transistor is electrically connected to the fifth node.

13. The pixel driving circuit according to any one of claims 6 to 12, wherein: The display device further includes: a third control unit electrically connected to the first light emitting signal line and configured to provide a signal to the first light emitting signal line; the second control unit includes: a first sub-control unit and a second sub-control unit, the first sub-control unit electrically connected to the first reset signal line and configured to provide a signal to the first reset signal line; the second sub-control unit electrically connected to the third reset signal line and configured to provide a signal to the third reset signal line; In at least one display frame, at least one of the start time of the first sub-control unit providing an invalid level signal to the first reset signal line and the start time of the second sub-control unit providing an invalid level signal to the third reset signal line is later than the start time of at least one time period of the first control unit providing a valid level signal to the second luminous signal line, and earlier than the start time of at least one time period of the third control unit providing a valid level signal to the first luminous signal line, and the start time of the first sub-control unit providing an invalid level signal to the first reset signal line is earlier than the start time of the second sub-control unit providing an invalid level signal to the third reset signal line.

14. The pixel driving circuit according to claim 1, wherein: The at least one reset signal line includes: a first reset signal line, a third reset signal line, and a fourth reset signal line; The third control subcircuit is electrically connected to the third node, the fourth node, the first reset signal line, the third reset signal line, the fourth reset signal line, the dynamic signal line and the auxiliary signal line respectively.

15. The pixel driving circuit according to claim 14, wherein: The third control subcircuit includes: a second capacitor, a third capacitor, a sixth transistor, an eighth transistor and a ninth transistor; A first end of the second capacitor is electrically connected to the third node, and a second end of the second capacitor is electrically connected to the fifth node; A first end of the third capacitor is electrically connected to the fifth node, and a second end of the third capacitor is electrically connected to the fourth node; a control electrode of the sixth transistor electrically connected to the first reset signal line, a first electrode of the sixth transistor electrically connected to the fifth node, and a second electrode of the sixth transistor electrically connected to the fourth node; a control electrode of the eighth transistor electrically connected to the third reset signal line, a first electrode of the eighth transistor electrically connected to the dynamic signal line, and a second electrode of the eighth transistor electrically connected to the fourth node; A control electrode of the ninth transistor is electrically connected to the fourth reset signal line, a first electrode of the ninth transistor is electrically connected to the auxiliary signal line, and a second electrode of the ninth transistor is electrically connected to the fifth node.

16. The pixel driving circuit according to claim 14 or 15, wherein: The display device further includes: a third control unit electrically connected to the first light emitting signal line and configured to provide a signal to the first light emitting signal line; the second control unit includes: a first sub-control unit, a second sub-control unit, and a third sub-control unit; the first sub-control unit is electrically connected to the first reset signal line and configured to provide a signal to the first reset signal line; the second sub-control unit is electrically connected to the third reset signal line and configured to provide a signal to the third reset signal line; and the third sub-control unit is electrically connected to the fourth reset signal line and configured to provide a signal to the fourth reset signal line; In at least one display frame, at least one of the start time of the first sub-control unit providing an invalid level signal to the first reset signal line, the start time of the second sub-control unit providing an invalid level signal to the third reset signal line, and the start time of the third sub-control unit providing an invalid level signal to the fourth reset signal line is later than the start time of at least one time period of the first control unit providing a valid level signal to the second light-emitting signal line, and earlier than the start time of at least one time period of the third control unit providing a valid level signal to the first light-emitting signal line, and the start time of the first sub-control unit providing an invalid level signal to the first reset signal line is earlier than at least one of the start time of the second sub-control unit providing an invalid level signal to the third reset signal line and the start time of the third sub-control unit providing an invalid level signal to the fourth reset signal line.

17. The pixel driving circuit according to claim 1, wherein: The driving subcircuit includes: a third transistor, the first control subcircuit includes: a first transistor and a second transistor, the second control subcircuit includes: a fourth transistor and a fifth transistor, and the storage subcircuit includes: a first capacitor; A control electrode of the first transistor is electrically connected to the first scan signal line, a first electrode of the first transistor is electrically connected to the data signal line, and a second electrode of the first transistor is electrically connected to the first node; A control electrode of the second transistor is electrically connected to the second scan signal line, a first electrode of the second transistor is electrically connected to the reference signal line, and a second electrode of the second transistor is electrically connected to the first node; The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node; The control electrode of the fourth transistor is electrically connected to the first light emitting signal line, the first electrode of the fourth transistor is electrically connected to the first power supply line, and the second electrode of the fourth transistor is electrically connected to the second node; a control electrode of the fifth transistor electrically connected to the second light emitting signal line, a first electrode of the fifth transistor electrically connected to the third node, and a second electrode of the fifth transistor electrically connected to the fourth node; A first end of the first capacitor is electrically connected to the first power line, and a second end of the first capacitor is electrically connected to the first node; The display device further includes: a fourth control unit and a fifth control unit, the fourth control unit being electrically connected to the first scan signal line and configured to provide a signal to the first scan signal line, and the fifth control unit being electrically connected to the second scan signal line and configured to provide a signal to the second scan signal line; In at least one display frame, the end time of the fifth control unit providing the valid level signal to the second scan signal line is earlier than the start time of the fourth control unit providing the valid level signal to the first scan signal line, and the start time of the fourth control unit providing the valid level signal to the first scan signal line is earlier than the start time of at least one time period of the first control unit providing the valid level signal to the second light-emitting signal line.

18. The display device according to claim 1, wherein The dynamic signal line is an initial signal line; The signal of the auxiliary signal line is a signal of at least one of a first power line, a reference signal line, and an initial signal line.

19. A display device comprising: Sub-pixels are arranged in an array, and at least one sub-pixel comprises: a pixel driving circuit as claimed in any one of claims 1 to 18.

20. The display device according to claim 19, further comprising: A temperature sensor, a control chip, and a signal transmission component, wherein the signal transmission component includes: a data unit, wherein the sub-pixel is electrically connected to a dynamic signal line; The temperature sensor is configured to detect a first temperature signal of the display device; The control chip is electrically connected to the temperature sensor and the signal transmission component, respectively, and is configured to obtain a first temperature signal detected by the temperature sensor, obtain a voltage offset corresponding to at least one sub-pixel based on the first temperature signal, obtain an adjusted dynamic signal corresponding to at least one sub-pixel based on the voltage offset corresponding to the at least one sub-pixel, and send the adjusted dynamic signal to the signal transmission component, and is further configured to send a control signal to the signal transmission component; The signal transmission component is electrically connected to the dynamic signal line and is configured to provide the adjusted dynamic signal corresponding to the sub-pixel to the dynamic signal line connected to the sub-pixel under the control of the control signal.

21. The display device according to claim 20, wherein The control chip is further configured to acquire a first temperature signal detected by the temperature sensor within a preset time interval.

22. The display device according to claim 20, wherein The control chip stores a correspondence table between temperature and voltage offset. The control chip is also configured to obtain a second temperature signal based on the first temperature signal, and obtain a voltage offset corresponding to at least one sub-pixel by searching the correspondence table based on the second temperature signal. The first temperature signal is an analog signal, and the second temperature signal is a digital signal.

23. The display device according to claim 20, wherein The control chip is further configured to obtain a current dynamic signal of at least one sub-pixel, and obtain an adjusted dynamic signal corresponding to at least one sub-pixel according to the current dynamic signal of at least one sub-pixel and a voltage offset corresponding to at least one sub-pixel.

24. The display device according to claim 20, wherein At least two sub-pixels among the plurality of sub-pixels have the same voltage value of the dynamic signal at the same temperature.

25. The display device according to claim 20, wherein The signal transmission component is further configured to provide an adjusted dynamic signal corresponding to at least one sub-pixel to a dynamic signal line connected to at least one sub-pixel in at least one display frame under the control of the control signal.

26. A method for driving a pixel driving circuit, configured to drive the pixel driving circuit according to any one of claims 1 to 18, the method comprising: The driving subcircuit provides a driving current to the third node under the control of the signals of the first node and the second node; The storage sub-circuit stores a voltage difference of a signal between the first node and the third node; The first control subcircuit provides a signal of the data signal line or the reference signal line to the first node under the control of the signal of the first scan signal line and the second scan signal line; The second control subcircuit provides the signal of the first power line to the second node and provides the signal of the third node to the fourth node under the control of the signals of the first light emitting signal line and the second light emitting signal line; The third control subcircuit adjusts the signals of the third node and the fourth node under the control of the signals of at least one reset signal line and at least one signal line among the dynamic signal line and the auxiliary signal line; In at least one display frame, at least one time period in which the first control unit provides an active level signal to the second lighting signal line starts earlier than or equal to a start time in which the second control unit provides an inactive level signal to at least one reset signal line.

27. A signal processing method, applied to the display device according to any one of claims 19 to 25, the method comprising: Acquire a first temperature signal detected by a temperature sensor; obtaining a voltage offset corresponding to at least one sub-pixel according to the first temperature signal; Obtaining an adjusted dynamic signal corresponding to at least one sub-pixel based on a voltage offset corresponding to the at least one sub-pixel, and sending the adjusted dynamic signal to a signal transmission component, so that the signal transmission component provides the adjusted dynamic signal corresponding to the sub-pixel to a dynamic signal line connected to the sub-pixel under the control of a control signal; The acquiring the first temperature signal detected by the temperature sensor comprises: acquiring the first temperature signal detected by the temperature sensor within a preset time interval; Obtaining the voltage offset corresponding to at least one sub-pixel according to the first temperature signal includes: obtaining a second temperature signal according to the first temperature signal, and obtaining the voltage offset corresponding to the at least one sub-pixel by searching a corresponding relationship table according to the second temperature signal, wherein the first temperature signal is an analog signal and the second temperature signal is a digital signal; The step of obtaining an adjusted dynamic signal corresponding to at least one sub-pixel based on a voltage offset corresponding to at least one sub-pixel includes: acquiring a current dynamic signal of at least one sub-pixel, and obtaining an adjusted dynamic signal corresponding to at least one sub-pixel based on the current dynamic signal of at least one sub-pixel and a voltage offset corresponding to at least one sub-pixel.

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